DRIVER WITH 112-CHANNEL OUTPUTS GENERAL DESCRIPTION SPLD112A, ver

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DRIVER WITH 112-CHANNEL OUTPUTS GENERAL DESCRIPTION SPLD112A, ver

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SPLD112A
DRIVER WITH 112-CHANNEL OUTPUTS
GENERAL DESCRIPTION SPLD112A, versatile matrix driver with power CMOS technology from Sunplus, capable providing varieties common/segment combinations application development. Ease use, high
performance cost make SPLD112A ideal most related products. This includes four primary blocks: 112-bit Shift Register, 112-bit Data Latch, 112-bit Level Driver Charge Pump. 112-bit Shift Register allows users select different common/segment types well data shifting. 112-bit Data Latch basically responsible loading data from Shift Register 112-bit Level Driver generate corresponding voltage level. block Charge Pump capable raising voltage level double triple (negative voltage level) original voltage level. Moreover, SPLD112A also converts serial data parallel data outputs waveform LCD.
FEATURES Operating voltage: 2.4V 6.0V driver voltage:
BLOCK DIAGRAM
D[112:1] 4-level Driver X112(seg/com) CUP2 charge Level shift selector pump CUP1 VSS2 112-bit Latch
Bias voltage supplied externally Built-in voltage converter( double triple) Serial data input Chain function (only segment) 1/48, 1/32 1/16 duty
DO112 112-bit shift register MODE0 MODE1
Segment common driver, combinations provided Mode Mode0 Mode1 Common Segment
Sunplus Technology Co., Ltd.
Rev.:
2000.02.15
SPLD112A
BLOCK FUNCTION DESCRIPTION 112-bit Shift Register Basically, this block data shift register. needs cooperate with Mode0 Mode1 select mode that defines various segment common ranges. example, when Mode0=1 Mode1=1, mode defined ModeB. ModeB, segments D112 commons. data segment enters from data common enters from DO112. Furthermore, according signal, data segment will enter into Shift Register continuously shifting after another until Shift Register. other hand, data common will enter into 81th Shift Register continuously shifting until Shift Register.
112-bit-latch will load data Register from Shift Register when LD=1 hold data when LD=0.
Level Shift Selector Block uses DF(Frame Signal) data 112-bit-latch decode types voltage level control signals.
functionality level Driver *112 block process control signal from Level Shift turns certain order corresponding voltage level.
purpose Charge Pump Block generate double triple voltage level. signal control signal. When MEN=1, Charge Pump will enabled generate double/triple voltage. When MEN=0, Charge Pump will disabled voltage level VSS2 grounded. clock signal Charge Pump whose frequency suggested from 50KHz 300KHz.
FUNCTION DESCRIPTION Four combinations provided different applications Mode Mode0 Mode1 Segment Common D[112:65] COM[48:1] D[80:1] SEG[80:1] D[112:81] COM[32:1] D[96:1] SEG[96:1] D[112:97] COM[16:1] D[112:1] SEG[112:1] Note D[64:1] SEG[64:1]
Sunplus Technology Co., Ltd.
Rev.:
2000.02.15
SPLD112A
COM/SEG
Data
Display Output Level
COMMON
SEGMENT
Mode
Mode0
Mode1
D[64:1]
D[80:65]
D[96:81]
D[112:97]
Mode
D112
BIT1
BIT2
BIT3
BIT4
BIT64
BIT65
BIT66
BIT112
DO112
Mode
D112
BIT1
BIT2
BIT3
BIT4
BIT80
BIT81
BIT82
BIT112
DO112
Sunplus Technology Co., Ltd.
Rev.:
2000.02.15
SPLD112A
Mode
D112
BIT1
BIT2
BIT3
BIT4
BIT96
BIT97
BIT98
BIT112
DO112
Mode
D112 DO112
BIT1
BIT2
BIT3
BIT4
BIT80
BIT81
BIT82
BIT112
DESCRIPTION Mnemonic D112 data shift clock; also used clock double/triple voltage generator. data shifted 112-bit latch falling edge `CP'. data setup time data hold time required between `DIN' `CP'. alternate signal data load. When `LOAD' `HIGH', shift register contents transferred driver through level shifter. When `LOAD' `LOW', last display data which transferred when `LOAD' high, held. Segment data input. transferred driver. DO112 When `Mode-D' selected, content 112th Shift Register output from DO112. When Mode-A, Mode-B Mode-C selected, data applied this shifted Type Segment/Common output Description
data applied `DO112' will shifted -65, bit-81 bit- MODE0 MODE1 VDD, CUP1, CUP2 Power input Coupling capacitor change pump Mode-A, Mode-B, Mode-C Mode-D selector
Sunplus Technology Co., Ltd.
Rev.:
2000.02.15
SPLD112A
Mnemonic Master enable: generate voltage tripler disable This should controlled CPU. Before entering standby mode, `MEN' must programmed `LOW' turn double/triple voltage generator. VSS2 Double voltage output Triple voltage output, `MEM' assigned `LOW', VSS2 will keep same voltage ground. This clock needed double/triple voltage generator. frequency suggested between 50kHz 300kHz depending loading between VEE. Type Description reference voltage input; highest V1-lowest
ABSOLUTE MAXIMUM RATINGS Characteristics supply Voltage supply Voltage input Voltage Range Symbol |VEE| Ratings -0.5V VDD+0.5V
Note: Stresses beyond those given Absolute Maximum Rating table cause operational errors damage device. normal operational conditions AC/DC Electrical Characteristics.
Sunplus Technology Co., Ltd.
Rev.:
2000.02.15
SPLD112A
ELECTRICAL CHARACTERISTICS Limit Characteristics Operating voltage Standby current Consumption current Input high level (CP, DIN, MODE0, MODE1, MEN, CKV) Input level Output high level Output level resister Note resister 100K VDD-0.5 -VEE Symbol Min. ISTYB IGND Typ. Max. Note 100KHz Unit Test Condition
between
Sunplus Technology Co., Ltd.
Rev.:
2000.02.15
SPLD112A
VSS2
Doubler short VSS2 Tripler short LCDEN DO112 D[80:1] RESBP SEG[80:1] COM[32:1] MODE0 RESBP D[112:1] MODE1 D[112:81]
SPL512A
CUP2 VSS2
SPLD112A
CUP1
APPLICATION NOTES
Application Circuit
PANEL
Figure SPLD112A, 1/32 duty, segments APPLICATION CIRCUIT
Sunplus Technology Co., Ltd.
Rev.:
2000.02.15
SPLD112A
VSS2
Doubler short VSS2 Tripler short
LCDEN
VSS2 CUP1 CUP2
VSS2
VSS2
RESBP
O[64:1]
CUP2 MODE0 MODE1 DO112 O[112:1]
MODE0 MODE1 DO112 O[112:1]
O[112:65]
Sunplus Technology Co., Ltd.
RESBP ROSC
SEG[112:1]
SEG[176:113] COM[48:1]
PANEL
Figure SPLD112A, 1/48 duty, segments, APPLICATION CIRCUIT
SPL512A
SPLD112A
SPLD112A CUP1
Rev.:
2000.02.15
SPLD112A
VSS2
Doubler short VSS2 Tripler short
LCDEN
VSS2
VSS2
VSS2
RESBP
CUP2 MODE DO80
CUP2 MODE0 MODE1 DO112 D[112:1]
SPL512A
SPLD80A
CUP1
SPLD112A
CUP1
O[80:1]
D[80:1]
D[112:81] COM[32:1]
RESBP ROSC
SEG[80:1]
SEG[160:81]
PANEL
Figure Application circuit SPLD80A SPLD112A driver panel
Sunplus Technology Co., Ltd.
Rev.:
2000.02.15
SPLD112A
VSS2
Doubler short VSS2 Tripler short
LCDEN
VSS2
VSS2
SPL512A
VSS2
SPLD80A
CUP1 CUP2 MODE
SPLD80A
CUP1 CUP2 MODE
SPLD112A
CUP1 CUP2
RESBP
MODE1 MODE0
DO80 O[80:1] O[80:1]
DO80
D[112:1]
DO112
RESBP ROSC
SEG[80:1] SEG[160:81] SEG[256:161] COM[16:1]
PANEL
Figure Application circuit SPLD80A SPLD112A driver panel
Sunplus Technology Co., Ltd.
Rev.:
2000.02.15
SPLD112A
application circuit Figure uses SPL512A control SPLD112A. Connect substrate floating depending type panel used. example, panel with bias, must adjustment `LCDEN' SPLD512A connected `MEN' SPLD112A enabling disabling display avoid path current sleep mode. `CP' shift register clock data shifting. `CKV' source supplying Charge Pump generate double/triple voltage level (The range between 50KHz 300KHZ; value depended loading between VEE). frequency range closed CKV, possible short together. respectively. That is,R1/(4R1+R2) should 1/7; contrast
Figure Timing Charts Application Example segment Driver Operation
DO112
Figure Timing Charts Application Example Common Driver Operation
Sunplus Technology Co., Ltd.
Rev.:
2000.02.15
SPLD112A
Followed recommended frequency range. Rload Range(Depend Panel Size) 120K Rload 300K Rload 120K Rload Note: Rload Better Range(Hz) 150K 100K 200K 200K 300K Available Range 200K 100K 300K 200K 400K
Timing Panel Dimension Segments Commons) Assignments: DO112 Mode[1,0] [High, High] SEGMENTS[80.1] O[80.1] COMMONS[32.1] O[112.81]
Voltage Define: DF=1 COMMON-Selection Alternative Voltage COMMON-NonSelection Alternative Voltage SEGMENTS Turn Voltage SEGMENTS Turn Voltage Pixel Turn Differential Voltage (VDD DF=0
Note: Data COM1 Should shifted SPLD112 before Change High (which indicate Start Frame).
Sunplus Technology Co., Ltd.
Rev.:
2000.02.15
SPLD112A
Frame Duty
COM1 Selected Period COM2 Selected Period
COM1
COM2
Sunplus Technology Co., Ltd.
Rev.:
2000.02.15
SPLD112A
Timing Characteristic Operation (Operation Condition: Voltage Frequency 5MHz Parameter Data Latch Setup Time Data Latch Hold Time High High Width Common-Outputs High Segment-Outputs transition High (Hold Time) Symbol TWLD TLCOM TLSEG TDFFP TLDFP Min. Max. Unit
Depend Load Depend Load
Note that Signal must "NonOverlap"
TWCP CP80
TWLD
TLSEG
TLCOM
SEGMENTS
COMMONS
TLDFP
TDFFP
Sunplus Technology Co., Ltd.
Rev.:
2000.02.15
SPLD112A
ASSIGNMENT LOCATIONS Assignment
Chip Size: 6480 3889 This substrate should connected
Note: ensure that functions properly, please bond VDD, VSS, AVDD AVSS pins.
Ordering Information Product Number SPLD112A-nnnnV-C Note1: Code number (nnnnV) assigned customer. Note2: Code number (nnnn 0000 9999); version Package Type Chip form
NOTE: SUNPLUS TECHNOLOGY CO., reserves right make changes time without notice order improve design performance supply best possible product.
Sunplus Technology Co., Ltd.
Rev.:
2000.02.15
SPLD112A
Locations Name -3076 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -3075 -2913 -2751 -2607 -2463 -2323 -2188 -2047 -1912 1786 1417 1272 1127 -229 -369 -510 -651 -786 -926 -1070 -1214 -1376 -1538 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 Name D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 -1772 -1631 -1490 -1355 -1215 -1080 -940 -805 -664 -529 -389 -254 -113 1122 1263 1398 1538 1673 1808 1943 2078 2213 2354 2502 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787 -1787
Sunplus Technology Co., Ltd.
Rev.:
2000.02.15
SPLD112A
Name D110 D111 D112 MODE0 MODE1 DO112 CUP2 CUP1 VSS2 2649 2795 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 3073 2810 2654 2503 2348 2213 2078 1943 1808 -1787 -1787 -1671 -1510 -1349 -1192 -1041 -889 -754 -615 -480 -340 -205 1029 1174 1318 1471 1645 1786 1786 1786 1786 1786 1786 1786 1786 Name 1673 1538 1398 1263 1122 -113 -254 -389 -529 -664 -805 -940 -1080 -1215 -1355 -1490 -1631 -1772 -1912 -2047 -2188 -2323 -2463 -2607 -2751 -2913 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786 1786
Sunplus Technology Co., Ltd.
Rev.:
2000.02.15
SPLD112A
DISCLAIMER information appearing this publication believed accurate. Integrated circuits sold Sunplus Technology covered warranty patent indemnification provisions stipulated terms sale only. SUNPLUS makes warranty, express, statutory implied description regarding information this publication regarding freedom described chip(s) from patent infringement. FURTHER, SUNPLUS MAKES WARRANTY MERCHANTABILITY FITNESS PURPOSE. SUNPLUS reserves right halt production alter specifications prices time without notice. Accordingly, reader cautioned verify that data sheets other information this publication current before placing orders. Products described herein intended normal commercial applications. Applications involving unusual environmental reliability requirements, e.g. military equipment medical life support equipment, specifically recommended without additional processing SUNPLUS such applications. reference purposes only. Please note that application circuits illustrated this document
Sunplus Technology Co., Ltd.
Rev.:
2000.02.15

DRIVER WITH 112-CHANNEL OUTPUTS GENERAL DESCRIPTION SPLD112A, ver

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