High Precision, High Speed ADC:16 Bits, 625kSPS DRVDD AVDD AVDD A

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High Precision, High Speed ADC:16 Bits, 625kSPS DRVDD AVDD AVDD A

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AK2702
High Precision, High Speed ADC:16 Bits, 625kSPS
DRVDD AVDD AVDD AVDD AVSS AVSS RESET/ SYNC DRVSS AVSS
Monolithic 16-Bit, Oversampled Convertor Oversampling Mode, Clock output Word Rate VINA Specifications Signal Passband VINB Signal-to-Noise: 90dB Total Harmonic Distortion: -96dB Spurious Free Dynamic range: 100dB Digital Filter Stopband Attentuation: Passband Ripple: 0.004dB Linear Phase BOTTOM COMMON Power Dissipation MODE Power Supply VREF Analog Supply SENSE Digital Supply Twos-Complement Output Data REFCOM 44-Lead LQFP
DVSS
DVDD
MULTIBIT DELTA SIGMA MODULATOR
DIGITAL DEMODULATOR
AK2702
OUTPUT REGISTER
STAGE 1:2X DECIMATION FILTER
OUTPUT MODE MULTIPLEXER
BIT1 BIT16
STAGE 2:2X DECIMATION FILTER REFERENCE BUFFER STAGE 3:2X DECIMATION FILTER
BANDGAP REFERENCE MODE REGISTER READ
BIAS CIRCUIT
CLOCK BUFFER
BIAS ADJUST
MODE
Description
AK2702 16-bit, high speed oversampled analog-to-digital converter (ADC) that offers high dynamic range over wideband kHz. AK2702 manufactured advanced submicron analog CMOS process. High dynamic range achieved with oversampling through proprietary multi delta sigma techniques. AK2702 switched-capacitor with nominal full scale input range offers differential input with 60dB common-mode rejection. signal range each differential input centered common-mode level. on-chip decimation filter consists three halfband filter stages that provide decimation filtering with 85dB stopband attenuation 0.004 passband ripple.
Block Diagram
on-chip reference reference buffer amplifier configured maximum accuracy flexibility. AK2702 operates single analog supply, digital supply typically consuming power. AK2702 available 44-lead LQFP package specified operate range 85C.
PERFORMANCE SPECIFICATION
SPECIFICATION
5.0V, 3.0V, AGND DGND fCLOCK MSPS, 2.5V, Input 2.5V TMAX=85C TMIN=-40C Parameter Conditions/Comments Min. Typ. Max. Units Resolution Input Referred Noise (Typical) Reference Accuracy Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Missing Codes Offset Error Gain Error Temperature Drift Offset Error Gain Error Power Supply Rejection Supply Rejection Supply Rejection Analog Input Input Span Input Range Common Mode Rejection Input Capacitance Internal Voltage Reference Output Voltage Power Supplies AVDD SVDD DVDD Supply Currents I(AVDD SVDD) I(DVDD RVDD) Power Consumption Power 100kHz Input, -2.2dBFS2 100kHz Input, -2.2dBFS2 100kHz Input, -2.2dBFS
0.69 Note Note Bits Guaranteed2 Note Note 0.064 50mV (p-p) 100kHz VREF 2.5V 100kHz, 1.2Vp-p input -61.5 Note 2.350 4.75 2.500 2.650 5.25 5.25 -61.5 AVDD-0.5 +0.75 +0.50
Bits Bits ppm/C ppm/C FSR/V Vp-p Diff
12/1999
ASAHI KASEI
AK2702
PERFORMANCE SPECIFICATION (continued)
SPECIFICATION
AVDD +5V, DVDD= +3V, fCLOCK MSPS, 2.5V, Input 2.5V, TMAX=85C TMIN=-40C Parameter DYNAMIC PERFORMANCE Input Test Frequency: Signal Noise (SNR) Distortion (SINAD) Total Harmonic Distortion (THD) Spurious Free Dynamic Range (SFDR) Input Test Frequency: Signal Noise (SNR) Distortion (SINAD) Total Harmonic Distortion (THD) Spurious Free Dynamic Range (SFDR) Input Amplitude: -0.5dBFS Input Amplitude: dBFS Input Amplitude: -0.5 dBFS Input Amplitude: dBFS Input Amplitude: -0.5 dBFS Input Amplitude: dBFS Input Amplitude: -0.5 dBFS Input Amplitude: dBFS 89.5 -94.5 -104 94.5 Input Amplitude: -0.5dBFS2 Input Amplitude: dBFS Input Amplitude: -0.5 dBFS Input Amplitude: dBFS Input Amplitude: -0.5 dBFS2 Input Amplitude: dBFS Input Amplitude: -0.5 dBFS Input Amplitude: dBFS
Conditions/Comments
Min.
Typ.
Max.
Units
89.5 84.5 84.5 -101
DIGITAL FILTER CHARACTERISTICS
Parameter Digital Filter Decimation) Passband Stopband Passband Ripple Stopband Attenuation Group Delay Group Delay Variation Settling Time 0.0007%) 85.5 0.372 4.625 ±0.004 Conditions/Comments Min. Typ. Max. Units
12/1999
PERFORMANCE SPECIFICATION (continued)
DIGITAL SPECIFICATION
AVDD +5V, DVDD +3V, MAX=85C TMIN=-40C Parameter Conditions/Comments High Level Input Voltage Level Input Voltage High Level Input Voltage Level Input Voltage High Level Output Voltage Level Output Voltage Input Leakage Current Clock Clock Read, CSB, RSTB Pins Read, CSB, RSTB Pins Iout Iout RVDD-0.4 +0.1 0.7*DVDD 0.3*DVDD Min. 0.7*AVDD 0.3*AVDD Typical Units
Notes Conventional measurements really apply delta sigma converters: looks continually better longer data records taken. AK2700, numbers given representative. 100% production tested sample tested specified temperatures
Absolute Maximum Ratings
AGND, SGND,RGND DGND voltages with respect ground.
Parameter
Power Supplies VINA VIND Temperature Tstg Ambient Operating Temperature (Power Applied) Storage Temperature Analog Power Supply Digital Power Supply Difference between AGND, SGND, RGND DGND Input Current-All pins except supply pins Analog Input Voltage Digital Input Voltage
Min. -0.3 -0.3
Max.
Units
-0.3 -0.3
Recommended Operation Conditions
AGND, SGND, RGND, DGND voltages with respect ground.
Parameter
Power Supplies
Min. Analog Power Supply (AVDD SVDD) Digital Power Supply (DVDD RVDD) 4.75
Typ.
Max. 5.25
Units
12/1999
ASAHI KASEI
AK2702
Description
9-24 Name DVSS SVSS DVDD SVDD RVSS RVDD READ D15-D0 Function Description Digital Ground, DGND=0V Digital Ground. SGND=0V Digital Power Supply. DVDD 3/5V Digital Power Supply. DVDD Digital Ground. RGND=0V Digital Supply RVDD=3/5V Master Clock. Referenced AVDD Output Enable Active high Data Output (MSB Pin9 Data Range Flag when converter filter overflows Data Valid Flag Data Available Chip Select Active Analog Supply. AVDD Analog Ground. AGND Reset Active Connected Connected Connected Connected Bias Resistance ohms Negative Reference Positive Reference Analog Ground. AGND Common Mode Reference Connect Positive Analog Input Negative Analog Input Connect Analog Supply. AVDD
AVDD AVSS RSTB TST1 TST2 TST3 MODE BIAS VREFL VREFH AVSS VINP VINN AVDD
Layout
12/1999
VREFH
VREFL
MODE
AVDD
AVSS
VINN
VINP
BIAS
DVSS SVSS DVDD SVDD RVSS RVDD
TST3 TST2 TST1 RSTB
LQFP AK2702
AVSS AVDD
READ
Digital Switching Characteristics
AVDD +5V, DVDD=3V, CL=20pF, TMAX=85C TMIN=-40C Parameter tCLK tDAV Clock Period Data Available Period Data Invalid Data Setup time Clock Pulse Width High Clock Pulse Width Data Hold Time Three-State Output Disable Time Three-State Output Enable Time tDAV-tH-tDI 15.2 Conditions/Comments Min. tCLKx8 0.43 tDAV Typ. Max. Units
12/1999
ASAHI KASEI
AK2702
Timing Diagrams
Analog Input
Clock
Data
tDAV READ
Figure Switching Characteristics
12/1999
AK2702
ASAHI KASEI
Device Operation
THEORY OPERATION
AK2702 bit, 625kSPS Analog Digital converter intended high speed instrumentation, medical imaging high resolution, high speed data acquisition. novel delta-sigma modulator operating 5Mhz employing multibit quantization dynamic element matching techniques achieves 90dB signal noise performance, with 100dB spurious free dynamic range power dissipation 150mW. on-chip decimation filter provides excellent stopband rejection suppress stray signal between 0.745MHz 9.25Mhz, substantially easing requirements anti-aliasing filter analog input path. AK2702 features READ pins allow easy interfacing. digital supply 5.25 2.7V used, though supply recommended minimize digital noise board. Data available (DAV) allows user easily synchronize converter's decimated output data rate. indicates overflow condition within modulator digital filters. RSTB provided synchronize converter's decimated data clear overflow conditions. on-chip reference reference buffer included AK2702. 2.5V reference provides pk-pk differential input full scale. range operation AVSS AVDD where AVSS AVDD nominally +5V.
INPUT DRIVER CONSIDERATION
optimum noise distortion performance AK2702 achieved when device driven differentially with input span. Since applications have signal preconditioned differential operation, there often need perform single-endedto-differential conversion. This best realized using differential driver. SINGLE-ENDED DIFFERENTIAL DRIVER
-VIN VINA
100pF
AK2702
100pF
VINB
ohms
kohms 0.01
Analog Input Reference Overview
value defines maximum input voltage AK2702. internal reference buffer scales 2.5V create VREFH VREFL. scale factor these buffers 0.8. Thus maximum input voltage defined +0.8 -0.8 -2V.
Figure Coupled Differential Driver with Level Shifting
INPUT SPAN
AK2702 implemented with differential input structure. This allows common mode input voltage varied independent input span converter. input core difference voltages applied VINA VINB input pins. This difference must less than pk-pk.
INPUT RANGE
analog input structure bounds valid operating
There particular single-ended-to-differential driver circuits useful driving AK2702. first circuit shown figure optimized coupling applications requiring optimum distortion performance. This circuit converts level shifts Vp-p single-ended, ground referenced signal 4Vp-p differential signal centered common-mode level AK2702. circuit based amps which configured matched unity gain difference amplifiers. single ended input signal applied opposing inputs difference amplifiers, thus providing differential outputs. common mode offset voltage applied non-inverting resistor each difference amplifier, thus providing differential outputs. offset voltage derived from AK2702 output impedance buffer amplifier capable driving capacitive load
12/1999
ASAHI KASEI
AK2702
protect AK2702 from undervoltage fault condition from amps specified operation, series resistors diode AGND inserted between each output AK2702 inputs. AK2702 will inherently protected against over voltage conditions amps share same positive power supply AK2702. gain accuracy common mode rejection each difference amplifiers enhanced using matched thin-film resistor network amps. These values should less than ohms maintain lowest possible noise. noise gain reduced adding shunt capacitor, across each amp's feedback resistor. This will essentially establish pass filter that will reduce noise gain beyond cutoff while simultaneously band limiting input signal. lowest possible noise performance while maintaining excellent distortion performance, unity gain OP642 should considered.
internal analog bias point used internally AK2702. This must decoupled analog ground with atleast 10uF capacitor. This voltage (2.5V) should buffered used external biasing.
REFERENCE OPERATION
AK2702 contains integrated bandgap reference internal reference buffer amplifier. This reference generates 2.5V. actual voltages used internal circuitry AK2702 appear VREFH VREFL pins. proper operation, necessary capacitive network decoupled pins. digital switching lines must drawn away from these pins.
DIGITAL INPUTS OUTPUTS
DATA OUTPUT AK2702 output data presented two's complement format. READ These pins control state output data pins AK2702. active READ active high. When both pins active data driven output data pins, otherwise output data pins high impedance (Hi-Z) state. indicates when output data valid. Digital output data updated rising edge DAV. duty cycle approximately remains independent READ. RSTB RSTB asynchronous digital input that active low. assertion, clocks decimation filter disabled, goes data output pins invalid. addition, analog modulator clocks also reset long RSTB maintained low. RSTB must remain atleast clock period ensure dividers modulators reset. RSTB used synchronized multiple AK2702 clocked with same clock. order synchronize necessary that clock dividers each AK2702s reset same state. next rising edge following rising edge RSTB, input sampled synchronously. synchronous output that updated each
0.1µF
VINA
100pF
10µF 0.1µF
AK2702
ohms
100pF
VINB
100pF
0.1µF
Figure3: Coupled Noise Differential Driver
lowest possible noise distortion performance achieved using coupled circuit, shown figure. circuit consists noise, high speed amps configured inverting gain unity gain buffer. this configuration, noise performance dominated inverting topology it's noise gain two. Excellent distortion achieved amps centered around AGND. outputs each coupled small series resistor capacitor respective inputs AK2702. Further band noise reduction realized with addition 100pF single ended differential capacitors. lower cutoff frequency this coupled circuit determined OP642 provides overall noise distortion performance.
12/1999
AK2702
ASAHI KASEI
period. indicates that overrange conditions occur within AK2702. Ideally, should latched falling edge ensure proper setup hold time. typically remains high more than clock cycle AK2702 used systems that incorporate automatic gain control. signal used indicate that signal amplitude should reduced. MODE Mode must connected gnd, only mode supported AK2702. BIAS connected 7.8k ohms. This sets bias currents analog circuitry. Minimization capacitance this recommended order prevent instability bias amplifier.
parallel with input signal traces should routed away from input circuitry. While AK2702 features separate analog digital pins, should treated analog component.
Analog Digital Supply Decoupling
analog digital supplies should decoupled close chip physically possible. combination 0.1uF 10uF should connected between each pair power supplies: AVDD AVSS, DVDD DVSS, SVDD SVSS, RVDD RVSS. external decoupling bias network shown figure
0.1uF 10uF
0.1uF
0.1uF 10uF
VREFH
VREFL
kohms
DIGITAL OUTPUT CONSIDERATION
AK2702 output drivers onfigured interface with logic families setting RVDD large drive currents tend cause glitches RVDD power rail. This effect SINAD performance. Applications requiring AK2702 drive large loads large fannout require additional decoupling capacitors RVDD. addition external buffers latches reduce output loading while providing effective isolation.
0.1uF 0.01uF
MODE TST3 TST2 TST1 RSTB AVSS
0.1uF 10uF
AVDD
AVSS VINN VINP
DVDD DVSS SVDD SVSS RVDD RVSS READ DATA DATA
0.01uF 0.1uF 0.01uF 0.1uF
AK2702
BIAS
AVDD DATA
CLOCK INPUT CONSIDERATION
clock input should treated analog signal cases where aperture jitter affect dynamic range AK2702. input buffer powered analog supply requires high levels 3.5V respectively. Supplies clock buffers should separated from output driver supplies avoid modulating clock signal with digital noise. jitter crystal controlled oscillators make best clock source
Figure4: Decoupling Bias Connection AK2702
GROUNDING DECOUPLING
Analog Digital Grounding Multi layer printed circuit boards (PCBs) recommended provide optimal grounding power schemes. ground power planes results both reduction electromagnetic interference (EMI) overall improvement performance. important design layout that prevents noise from coupling onto input signal. Digital signals should
12/1999
ASAHI KASEI
AK2702
MARKINGS
Marking Spec
AK2702 XXXXXXX JAPAN
XXXXXXX Date Production Code JAPAN Country Origin
12/1999
AK2702
ASAHI KASEI
OUTLINE DIMENSIONS
10.0
12.8+
10.0
0.6+0.2 0.37
0.1+0.1
44-Lead LQFP
1.7MAX
0.17
Dimensions shown millimeters
Important Notice These products their specifications subject change without notice. Before considering application, consult Asahi Kasei Microsystems Co., Ltd. (AKM) sales office authorized distributor concerning their current status. assumes liability infringement patent, intellectual property, other right application information contained herein. export these products, devices systems containing them, require export license other official approval under regulations country export pertaining customs tariffs, currency exchange, strategic materials. products neither intended authorized critical components safety, life support, other hazard related device system, assumes responsibility relating such use, except with express written consent Representative Director AKM. used here: hazard related device system designed intended life support maintenance safety applications medicine, aerospace, nuclear energy, other fields, which failure function perform reasonable expected result loss life significant injury damage person property. critical component whose failure function perform reasonably expected result, whether directly indirectly, loss safety effectiveness device system containing which must therefore meet very high standards performance reliability. responsibility buyer distributor product contributes, disposes otherwise places product with third party notify that party advance above content conditions, buyer distributor agrees assume responsibility liability hold harmless from claims arising from said product absence such notification.
0~10
12/1999

High Precision, High Speed ADC:16 Bits, 625kSPS DRVDD AVDD AVDD A

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