Designer's Guide (Preliminary) Order 1104 Rev. October 1996

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Designer's Guide (Preliminary) Order 1104 Rev. October 1996

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WaveArtist100 WaveArtist300 Audio System Devices
Designer's Guide (Preliminary)
Order 1104 Rev. October 1996
WaveArtist100/300 Audio System Devices Designer's Guide
NOTICE
Information furnished Rockwell International Corporation believed accurate reliable. However, responsibility assumed Rockwell International use, infringement patents other rights third parties which result from use. license granted implication otherwise under patent rights Rockwell International other than circuitry embodied Rockwell products. Rockwell International reserves right change circuitry time without notice. This document subject change without notice.
WaveArtist trademark Rockwell International. Microsoft MS-DOS registered trademarks Microsoft Corporation. Windows, Windows Windows Sound System, DirectSound trademarks Microsoft Corporation. Sound Blaster trademark Creative Technology Ltd.
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WaveArtist100/300 Audio System Devices Designer's Guide
Table Contents
INTRODUCTION .1-1 Summary. .1-1 Features.1-2 DESCRIPTION .2-1 RWA100/RWA300 Description.2-1 2.1.1 Sample Rate Conversion .2-1 Synthesis .2-1 Stereo Codec/Mixer.2-1 Host Software .2-1 Music Processor (RWA300 Only) .2-1 2.1.2 Hardware Signal Interfaces .2-1 2.1.3 Host Software .2-1 RWA035 Description .2-2 2.2.1 Host Interface .2-2 2.2.2 DRAM Interface .2-2 Specifications .2-3 HARDWARE INTERFACE. Interface Signals, Assignments, Signal Descriptions.3-1 Hardware Interface Circuits 3-15 3.2.1 Host Plug Play (PnP) Interface. .3-15 3.2.2 Serial EEPROM Interface .3-15 3.2.3 Audio Interface 3-15 .3-16 Line In.3-16 Input .3-17 Input .3-17 Mono In.3-17 Line .3-18 Mono .3-19 3.2.4 Enhanced CD-ROM Interface. .3-19 3.2.5 Joystick/MIDI Interface .3-20 Joystick Interface .3-21 MIDI Interface .3-21 3.2.6 Modem Interface.3-22 3.2.7 Crystal Interface Circuit.3-22 3.2.8 RWA300 External Memory Bus. .3-24 Interface. .3-24 DRAM Interface.3-24 RWA035 Interface .3-24 INTERFACE TIMING WAVEFORMS.4-1 Timing.4-1 Serial EEPROM Interface Timing .4-5 MIDI Serial Interface Timing .4-6 Memory Interface Timing (RWA300) .4-7 DRAM Interface.4-7 Interface. .4-7 HOST SOFTWARE INTERFACE.5-1 Interface Register Map.5-1 PLUG-AND-PLAY INTERFACE.6-1 Resource Data .6-1 1104
WaveArtist100/300 Audio System Devices Designer's Guide
DESIGN CONSIDERATIONS .7-1 BOARD LAYOUT GUIDELINES .7-1 7.1.1 General Principles.7-1 7.1.2 Component Placement.7-1 7.1.3 Signal Routing .7-2 7.1.4 Power .7-3 7.1.5 Ground Planes.7-3 7.1.6 Crystal Circuit .7-3 CRYSTAL/OSCILLATOR SPECIFICATIONS .7-5 PACKAGE DIMENSIONS .7-6
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WaveArtist100/300 Audio System Devices Designer's Guide
List Figures
Figure 1-1. RWA100/RWA300 Block Diagram.1-4 Figure 3-1. RWA100 Interface Signals Figure 3-2. RWA300 Interface Signals Figure 3-3. 208-Pin Package .3-4 Figure 3-4. RWA035 Signals 80-Pin PQFP 3-10 Figure 3-5. Typical EEPROM Interface Connection 3-15 Figure 3-6. Typical Microphone Interface Circuit. 3-16 Figure 3-7. Typical Line Interface Circuit 3-16 Figure 3-8. Typical Input Interface Circuit 3-17 Figure 3-9. Typical Input Interface Circuit 3-17 Figure 3-10. Typical Mono Interface Circuit 3-18 Figure 3-11. Typical Line Interface Circuit 3-18 Figure 3-12. Typical Mono Interface Circuit 3-19 Figure 3-13. Typical CD-ROM Interface Circuit 3-20 Figure 3-14. Typical Joystick/MIDI Interface Circuit 3-21 Figure 3-15. Typical Modem Interface Circuit 3-22 Figure 3-16. Typical Crystal Interface Circuit 3-23 Figure 3-17. Typical RWA300 Memory RWA035 Interface Circuit. 3-24 Figure 4-1. Waveforms Timing System Write. .4-2 Figure 4-2. Waveforms Timing System Read.4-2 Figure 4-3. Waveforms Timing ~Chip Select Throughput Delay .4-3 Figure 4-4. Waveforms Timing Throughput Delay .4-3 Figure 4-5. Waveforms Timing Throughput Delay.4-4 Figure 4-6. Waveforms Timing DACK Throughput Delay .4-4 Figure 4-7. Waveforms Timing Serial EEPROM Interface. .4-5 Figure 4-8. Waveforms Timing Serial EEPROM Interface. .4-6 Figure 4-9. Waveforms Timing MIDI Interface .4-6 Figure 4-10. Waveforms: Read Cycle .4-7 Figure 7-1. Package Dimensions 208-Pin .7-7 Figure 7-2. Package Dimensions 80-Pin PQFP.7-8 Figure 7-3. Package Dimensions 44-Pin SOP.7-9
List Tables
Table 1-1. Models Functions .1-3 Table 2-2. Current Power Requirements .2-3 Table 2-3. Recommended Operating Conditions .2-3 Table 2-4. Absolute Maximum Ratings. Table 3-1. RWA100/RWA300 Assignments 208-Pin .3-5 Table 3-2. RWA100/RWA300 Hardware Interface Signal Definitions .3-7 Table 3-3. RWA035 Hardware Interface Signal Definitions 3-11 Table 3-4. Input/Output Type Descriptions 3-12 Table 3-5. Digital Electrical Characteristics. 3-13 Table 3-6. Analog Performance 3-14 Table 3-7. Analog Performance 3-14 Table 4-1. Timing Serial EEPROM Interface .4-5 Table 4-2. Timing: DRAM Interface. .4-7 Table 4-3. Timing: Interface.4-7 Table 5-1. Interface Register .5-1 Table 7-1. RWA300 Device Noise Characteristics .7-4 Table 7-2. Crystal Specifications 50.8032 .7-5
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INTRODUCTION
Summary
Rockwell WaveArtist100 (RWA100) WaveArtist300 (RWA300) complete audio system devices, each packaged profile, small footprint, 208-pin ball grid array (BGA). These pin-compatible devices support single design providing increasing level functionality from synthesis (RWA100) high quality music wavetable synthesis with optional effects processor upgrade (RWA300). (See Table 1-1.) models support synthesis, 16-bit stereo audio with simultaneous record playback Plug-and-Play (PnP) interface cost effective, expandable audio audio/modem system designs. They also compatible with applications that Sound Blaster Pro, Yamaha OPL3, AdLib, MPU-401 interfaces. Also supported game port with internal timers enhanced CD-ROM interface. (See Figure 1-1.) RWA100/RWA300, when used with Rockwell modem, provides seamless integration high speed data/fax modem, voice/audio, AudioSpan simultaneous voice data, speakerphone functions. RWA100 supports low-end sound applications lowest component cost. RWA300 with internal music processor, features Audio Kurzweil special audio effects best high quality sound designs. RWA300 also connects external wavetable ROM, optional downloadable sound sample DRAM 8MB), optional RWA035 Effects Processor Upgrade. RWA035 Effects Processor Upgrade, 80-pin PQFP, adds professional quality sound processing such concert hall other spatial features RWA300. RWA035 connects external DRAM. Host software, compatible with Windows Sound System (WSS), provided Windows Windows 3.1x, Windows DirectSound environments. software utility also available configure interface MS-DOS environment. part part approved reference hardware designs available.
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WaveArtist100/300 Audio System Devices Designer's Guide Features
RWA100/RWA300 common features 16-bit stereo audio single mixed-signal device 16-bit delta sigma codec with Sound Blaster compatible Simultaneous (full-duplex) record playback 8-bit 16-bit sample record playback from 44.1 Digital sample rate conversion with resolution Integrated OPL3/OPL2 AdLib compatible synthesis with external required external analog input channels stereo, mono) Independent left right channel mixers each with external inputs internal input (digitally summed optional wavetable, signals) external analog output channels stereo, mono) Uses single crystal oscillator Integrated hardware interfaces MPU-401 MIDI UART compatible Enhanced CD-ROM compatible Joystick with internal timers (game port compatible) interface Programmable resource data RWA300 with internal Music Processor General MIDI compatible wavetable synthesis supports voices 44.1 Audio Kurzweil Basic effects reverb, chorus, spatialization Treble bass equalization Interface wavetable Interface sound sample DRAM 8MB) Interface RWA035 Effects Processor Upgrade RWA035 Effects Processor Upgrade 80-pin PQFP Full effects reverb, chorus delay Spatial placement effects Interface DRAM profile, small footprint packages RWA100 RWA300: 208-pin RWA035: 80-pin PQFP Power management Applications Integrated audio/telephony cards Motherboards, notebooks, add-on cards audio/games Windows Sound System (WSS) DirectSound
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Table 1-1. Models Functions
Required Devices Function RWA100 RWA300 RWA031/RWA032 ROM2 RWA300, RWA031/RWA032 ROM2, RWA035
Synthesis High Quality Wavetable Synthesis Spatialization Effects (Reverb Chorus) Equalization (Treble Bass) Professional Quality Effects Processing (Reverb, Chorus, Delay, Concert, Auditorium, etc.)
Notes: RWA031/RWA032 optional 1MB/2MB wavetable RWA300.
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CONTROL, ADDRESS, DATA
ROCKWELL MODEM (e.g., RC336ACF/SP) TYPICAL MODEM CONNECTION
TELEPHONE LINE INTERFACE
TELEPHONE LINE
DATA
CONTROL ENHANCED CD-ROM INTERFACE
CD-ROM
CONTROL
MONOIN MONOOUT CONTROL, ADDRESS, DATA MICROPHONE (LMIC, RMIC) LINE (LLINE, RLINE) LINEOUT (LOUT, ROUT) (LAUX1, RAUX1) (LAUX2, RAUX2)
GAME/MIDI PORT
EEPROM (256B)
RWA100/ RWA300, (208-PIN BGA)
RWA300 INTERFACE
WAVETABLE (2MB 1MB)
OPTIONAL DRAM 8MB)
OPTIONAL RWA035 EFFECTS PROCESSOR UPGRADE
DRAM (512KB)
MD151F1 RWA300
Figure 1-1. RWA100/RWA300 Block Diagram
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DESCRIPTION
RWA100/RWA300 Description
2.1.1 Sample Rate Conversion Analog inputs outputs sampled 44.1 kHz. internal sample rate converter converts samples sample rates ranging from 44.1 kHz. sample rate converter eliminates need external synthesis. also allows single crystal support sample rates. Synthesis internal OPL3 OPL2 compatible synthesis engine operate either 2-operator 4-operator mode. Address, data, status registers provided compatibility with AdLib/Sound Blaster interfaces. Stereo Codec/Mixer integrated 16-bit delta sigma stereo codec simultaneously mixes, records, plays with high fidelity. record multiplexer stereo input selects from four external stereo inputs, external mono input, internal mixer. mixer combines external inputs into stereo input record multiplexer. playback, separate stereo mono outputs provided. samples digitally mixed with wavetable synthesizer samples, then converted analog outputs. Volume controls provided input output paths. Host Software Windows Sound System (WSS) compatible recording playback 16-bit 8-bit audio supported Rockwellprovided host driver software which controls WaveArtist using WaveArtist command/status registers. Music Processor (RWA300 Only) RWA300 supports 32-voice polyphony General MIDI wavetable synthesis 44.1 kHz. provides several basic audio effects, including reverb, chorus, sound spatialization (reverb chorus available during wavetable synthesis operation). Additionally, treble/bass equalization PCM, wavetable synthesis signals. external used store wavetable sounds. Sound samples loaded into optional external DRAM played back with internal synthesis engine. This interface also supports multiple hardware static buffers, allowing games written DirectSound playback sounds more efficiently more than sample mixed same time. additional high quality effects, interface provided RWA035 Effects Processor Upgrade device. RWA035 programmed with additional sound delay processing algorithms such concert hall other spatial effects. 2.1.2 Hardware Signal Interfaces Section 3.2. 2.1.3 Host Software Host software provided Windows Windows 3.1x (WSS), Windows Windows Windows 3.11, Hardware Installation Module (HIM) assists installation Ring driver (MIDI/FM I/O, wave I/O, mixer/volume control, wave sample download), Ring (virtual device driver allocation physical resources). Windows .INF file works conjunction with install Ring driver (wave I/O, mixer/volume control, wave sample download), Ring (resource management). DirectSound also supported Windows utility available configure interface MS-DOS environment.
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WaveArtist100/300 Audio System Devices Designer's Guide RWA035 Description
RWA035 self-contained effects device that provides downloadable delay effects (such reverberation chorus) digital audio stream. RWA035 receives audio words from RWA300 returns audio words RWA300 altered achieve desired effect. External DRAM 256k used effects processing. 2.2.1 Host Interface supported signals address inputs (SMA[8:1], bidirectional data lines (SMD[15:0], control inputs Chip Enable input (CE#), Write (WR#) Clock (CLK) Period (TOPI#). RWA035 receives digital audio data from RWA300 over Serial Input Data (KISI) input sends digital audio data RWA300 over Serial Output Data (KISO) output. 2.2.2 DRAM Interface RWA035 connects DRAM using address outputs (RMA[8:0]), bidirectional data lines(RMD[11:0]), control outputs Strobe (RMRAS#), Column Strobe [RMCAS#), read/write output (RMR/W#). DRAM must have maximum access time example, Mosel V53C664HK70 compatible DRAM used size.
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WaveArtist100/300 Audio System Devices Designer's Guide Specifications
power requirements listed Table 2-2. recommended operating conditions listed Table 2-3. absolute maximum ratings listed Table 2-4.
Table 2-2. Current Power Requirements
Current Model RWA100 Normal Mode Power Down Mode RWA300 Normal Mode Power Down Mode RWA035 Normal Mode Power Down Mode 1350 1575 50.8032 Typical Current (mA) Maximum Current (mA) Power Typical Power (mW) Maximum Power (mW) Notes 50.8032
Notes: Test conditions: typical values; 5.25 maximum values.
Table 2-3. Recommended Operating Conditions
Rating Supply Voltage Units
Table 2-4. Absolute Maximum Ratings
Parameter Supply Voltage Input Voltage Operating Temperature Range Storage Temperature Range Analog Inputs Voltage Applied Outputs High Impedance (Off) State Input Clamp Current Output Clamp Current Static Discharge Voltage (25°C) Latch-up Current (25°C) Symbol TRIG Limits -0.5 +7.0 -0.5 (+5VD +0.5) +125 -0.3 (+5VA 0.3) -0.5 (+5VD 0.5) ±2500 ±200 Units
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HARDWARE INTERFACE
Interface Signals, Assignments, Signal Descriptions
RWA100 signal interface shown Figure 3-1. RWA300 signal interface shown Figure 3-2. 208-pin package shown Figure 3-3. RWA100/RWA300 assignments listed Table 3-1. RWA100/RWA300 signals described Table 3-2. RWA035 assignments 80-pin PQFP shown Figure 3-4. RWA035 signals described Table 3-3. hardware input/output interface circuit types described Table 3-3. digital interface signal characteristics described Table 3-5. analog-to-digital (ADC) interface signal characteristics described Table 3-6. digital-to-analog (DAC) interface signal characteristics described Table 3-7.
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WaveArtist100/300 Audio System Devices Designer's Guide
XTALI XTALO
GAME PORT (JOYSTICK MIDI) INTERFACE
CRYSTAL CIRCUIT
MIDI_RX MIDI_TX
MIRQ SD[15:0] SA[15:0] IOR# IOW# RESET IRQ3 IRQ4 IRQ5 IRQ7 IRQ9 IRQ10 CDIRQ CDDRQ CDDACK# CDSEL# CDSEL0# CDSEL1# CDHI# MSEL# RESET#
MODEM INTERFACE
CD-ROM INTERFACE
INTERFACE
IRQ11 IRQ15 DRQ1 DRQ5 DRQ6 DRQ7 DACK1# DACK5# DACK6# DACK7# IOCS16# SBHE# IOCHRDY
RWA100 WaveArtist
RLINE LLINE RAUX1 LAUX1 RAUX2 LAUX2 RMIC LMIC MONOIN ROUT LOUT MONOOUT VREF
AUDIO INTERFACE
SERIAL EEPROM (256B)
RMIXOUT0 RMIXOUT1 LMIXOUT0 LMIXOUT 0.47 0.47
MD151F2 RWA200
Figure 3-1. RWA100 Interface Signals
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WaveArtist100/300 Audio System Devices Designer's Guide
XTALI XTALO
GAME PORT (JOYSTICK MIDI) INTERFACE
CRYSTAL CIRCUIT
MIDI_RX MIDI_TX
MIRQ SD[15:0] SA[15:0] IOR# IOW# RESET IRQ3 IRQ4 IRQ5 IRQ7 IRQ9 CDIRQ CDDRQ CDDACK# CDSEL# CDSEL0# CDSEL1# CDHI# MSEL# RESET#
MODEM INTERFACE
CD-ROM INTERFACE
INTERFACE
IRQ10 IRQ11 IRQ15 DRQ1 DRQ5 DRQ6 DRQ7 DACK1# DACK5# DACK6# DACK7# IO16# SBHE# RLINE LLINE RAUX1 LAUX1 RAUX2 LAUX2 RMIC LMIC MONOIN
AUDIO INTERFACE
RWA300 WaveArtist
ROUT LOUT MONOOUT VREF
SERIAL EEPROM (256B)
RMIXOUT0 RMIXOUT1 LMIXOUT0 LMIXOUT MA[22:0] MD[15:0] RAS# SMAV# SMROE0# SMROE1# SMMCS# MA[19:0] MD[15:0] SMROE0# A[19:0] D[15:0] 0.47 MA[20,18,16,7:0] MD[15:0] RAS# SMAV# A[10:0] D[15:0] R/W# RAS# UCAS# LCAS# 0.47
DRAM 8MB)
(2MB 1MB)
MA[7:0] MD[15:0] WRST# SMMCS YCLKM TOPO# KISOB KISIB
RWA135 (OPTIONAL)
MA[8:1] MD[15:0] RESET# TOPI KISI KISO RMA[8:0] RMD[11:0] RMRAS# RMCAS# RMR/W#
DRAM 256K
A[8:0] D[11:0] RAS# CAS#
MD151F3 RWA300
Figure 3-2. RWA300 Interface Signals 1104
WaveArtist100/300 Audio System Devices Designer's Guide
CORNER
VIEW
BOTTOM VIEW
MD151F4 208BGA
Figure 3-3. 208-Pin Package
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WaveArtist100/300 Audio System Devices Designer's Guide
Table 3-1. RWA100/RWA300 Assignments 208-Pin
Location SOUT SCLK RLINE LLINE MONOIN AVSS RWA100 Signal RESET# TXSIN AVSS AVDD AVDD VREF LAUX2 LAUX1 MA14 MA12 SMROE0# KISOB TOPO# RWA300 Signal MA13 MA11 VR5V SMAV# SMROE1# TOPI Location RMIC AVSS AVDD MA21 MA22 RWA100 Signal RWA300 Signal STROBE RAUX2 RAUX1 MONOOUT ROUT LOUT LMIC MA17 MA18 RMIXOUT0 RMIXOUT1 LMIXOUT1 LMIXOUT0 MA19 MA20 MA15 MA16 MA10 VREG YCLKM SMMCS# KISIB Location MD12 MD13 MD10 MD11 MIDI_TX MIDI_RX RWA100 Signal RWA300 Signal DVSS AVSS DVDD MODE1 MODE0 TEST_EN
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WaveArtist100/300 Audio System Devices Designer's Guide
Table 3-1. RWA100/RWA300 Assignments 208-Pin (Cont'd)
Location IRQ10 IRQ11 XTALO CDDRQ IRQ7 IRQ9 XTALI IRQ3 IRQ4 IRQ5 MSEL# MIRQ IRQ15 TEST CDIRQ CDHI# RWA100 Signal WRST# RWA300 Signal MD14 MD15 RAS# Location RWA100 Signal RWA300 Signal CDSEL0# CDSEL1# CDDACK# DACK7# DACK1# SA13 RESET SD14 SD12 SD10 CDSEL# DRQ1 DACK5# SA10 SA12 SA15 IOW# SD15 SD13 SD11 Location RWA100 Signal RWA300 Signal IOCS16# DRQ7 DRQ6 DRQ5 DACK6# SBHE# SA11 SA14 IOR#
Notes: Boxed cells show signals unique RWA100 RWA300 listed respective column. external connection permitted (this connected internal circuitry). applicable (pin does exist).
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Table 3-2. RWA100/RWA300 Hardware Interface Signal Definitions
Label Type General XTALI, XTALO VDD, DVDD AVDD GND, DVSS AVSS TEST Ixtl, Oxtl Itpd Crystal Input, Crystal Output. Connect 50.8032 crystal circuit. Digital Power. Connect VDC. Digital Power Analog Device Digital Circuits. Connect through filter. Analog Power. Connect Digital Ground. Connect digital ground. Digital Ground Internal Codec. Connect digital ground. Analog Ground. Connect analog ground. Test. Connect GND. Host Interface Host Address Enable. Active high input asserted during cycle. logic responds host address command signal lines (IOR# IOW#) when low. Host Address Lines. Host address lines used ADDRESS, WRITE_DATA, READ_DATA ports Port Base decoding. Host Data Lines. Host bidirectional data lines used transfer data between host WaveArtist. Host Read. Active input asserted strobe read data onto host data bus. Host Write. Active input asserted strobe write data from host data Interrupt Request. Active high output asserted indicate interrupt request. Request. Active high output asserted request data transfer. Request Acknowledge. Active input asserted acknowledge corresponding request. Host Reset. Active high input asserted reset RWA100/RWA300. When asserted, internal registers reset their hardware default states. must asserted least before being deasserted. While reset state, host activity ignored. Active open collector output asserted during read write operation. System High Enable. Active input asserted when high-order byte host accessed. Serial EEPROM Interface MSEL# It/Otod2 Serial EEPROM Clock. clock timing output 24C02 serial EEPROM. Serial EEPROM Address/Data I/O. Bidirectional data from 24C02 serial EEPROM. Connect this external pull-up resistor (e.g., VCC. Serial EEPROM Write Control. Active output allow writing into EEPROM memory. Modem Controller Interface Modem Chip Select. Active output modem controller asserted whenever valid address present host address bus, i.e., address which falls within range written host Space Configuration Register. Modem Interrupt Request. Active high input from modem's HINT pin. Modem Reset. Active output; inverse RESET from host bus. This signal used reset modem controller CD-ROM interface. Signal/Definition RWA100/RWA300 COMMON
SA[15:0] SD[15:0] IOR# IOW# IRQ[15, DRQ1, DRQ5, DRQ6, DRQ7 DACK1#, DACK5#, DACK6#, DACK7# RESET
It/Ot12 Itst Itst Otts8 Otts8 Itst
IOCS16# SBHE#
Otod12
MIRQ RESET#
Itpd
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WaveArtist100/300 Audio System Devices Designer's Guide
Table 2-2. RWA100/RWA300 Device Hardware Interface Signal Definitions (Cont'd)
Label Type Signal/Definition RWA100/RWA300 COMMON (CONTINUED) Game Port MIDI Port Interface JA1, JA2, JAX, JB1, JBX, MIDI_RX MIDI_TX LAUX1, RAUX1 LAUX2, RAUX2 LLINE, RLINE LMIC, RMIC LOUT, ROUT MONOIN MONOOUT VREF LMIXOUT0, LMIXOUT1 RMIXOUT0, RMIXOUT1 CDSEL# CDSEL0# CDSEL1# CDIRQ CDDRQ CDDACK# CDHI# TXSIN SOUT SCLK STROBE Itpu1k Ia/Ocod12 Itpu1k Ia/Ocod12 Itpu Joystick Switch Inputs Binary inputs used determine state Joystick switches These ports each have built-in pull-up resistor. Joystick Position. Analog inputs used determine position Joystick potentiometer. Joystick Switch Inputs Binary inputs used determine state Joystick switches These ports each have built-in pull-up resistor. Joystick Position. Analog inputs used determine position Joystick potentiometer. MIDI Receive. MIDI serial input data from MPU-401 UART compatible interface. This built-in pull-up resistor. MIDI Transmit. MIDI serial output data MPU-401 UART compatible interface. Audio Interface Auxiliary Input Left Right. Normally connected CD-ROM left right channels, respectively. Auxiliary Input Left Right. Line-Level Input Left Right. Microphone Input Left Right. Line-Level Output Left Right. Monaural Input. Monaural Output. Audio Interconnect Reference Voltage Centerpoint Voltage. Connect analog ground through capacitor capacitor parallel. Reference Voltage. Connect analog ground through parallel. Mixer Coupling Left. Connect LMIXOUT0 LMIXOUT1 though external 0.47 capacitor. Mixer Coupling Right. Connect RMIXOUT0 RMIXOUT1 though external 0.47 capacitor. CD-ROM Interface Itpd Itpd CD-ROM Chip Select. Active low, asserted enable interface. CD-ROM Chip Select CD-ROM Chip Select CD-ROM Interrupt Request. CD-ROM Request. CD-ROM Request Acknowledge. CD-ROM High. Active output used enable high byte CD-ROM data. Reserved/No External Connection Reserved. external connection, leave open (this connected internal circuitry). Reserved. external connection, leave open (this connected internal circuitry). Reserved. external connection, leave open (this connected internal circuitry). Reserved. external connection, leave open (this connected internal circuitry).
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Table 2-2. RWA100/RWA300 Device Hardware Interface Signal Definitions (Cont'd)
Label Type RWA300 ONLY General VR5V VREG TEST_EN MODE0 MODE1 MA[22:0] Digital Power. Connect VDC. Regulator Core Voltage DSP. Connect digital ground through 1000 capacitor. Test. Connect VCC. Used. Leave open. Memory Interface Memory Address Lines. MA[22:0] address (512K external wavetable optional sound sample DRAM 8MB). DRAM addressing RWA300 Address Line MA[7:0] MA16 MA18 MA20 MD[15:0] SMROE0# SMROE1# RAS# SMAV# WRST# SMMCS# YCLKM TOPO# TOPI KISOB KISIB Notes: Type: Input, Output, Device Interconnect. connection (NC) means external connection allowed (pin connected internal circuitry). IA/OB DRAM Address LineSupported DRAM Size A[7:0] (128KB) 256K (512KB) (2MB) (8MB) Signal/Definition
Memory Data Lines. MD[15:0] transfer 16-bit data from external wavetable RWA300 between RWA300 optional sound sample DRAM. Output Enable Active output, asserted enable output wavetable ROM. Output Enable used; leave open. DRAM Write Enable. Active low, asserted when writing optional DRAM. DRAM Strobe. Active output, asserted strobe DRAM address. DRAM Address Lines Valid. Active output, asserted strobe DRAM column address. RWA035 Interface Reset. Active output, asserted reset RWA035. RWA035 used, connect WRST# RWA035 RESET# pin. RWA035 used, leave this open. Chip Select. Active output, asserted select RWA035 device. RWA035 used, connect this RWA035 pin. RWA035 used, leave this open. Clock. RWA035 used, connect YCLKM RWA035 pin. RWA035 used, leave this open. Period Out. RWA035 used, connect TOPO# RWA035 TOPI pin. RWA035 used, connect TOPO# RWA300 TOPI pin. Period Connect this RWA300 TOPO# pin. Serial Output Data. RWA035 used, connect KISOB RWA035 KISI pin. RWA035 used, leave this open. Serial Input Data. RWA035 used, connect KISIB RWA035 KISO pin. RWA035 used, leave this open.
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MD12 MD11 MD10
MD13 MD14 MD15 RESET# TOPI KISO KISI RMCAS# RMR/W# RMRAS# RMA0 RMA1 RMA2 RMA3
RMA4 RMA5 RMA6 RMA7 RMA8 RMD0 RMD1 RMD2 RMD3 RMA4 RMD5 RMD6 RMD7 RMD8
DTACK# RMD11 RMD10 RMD9
MD152F7 RWA035
Figure 3-4. RWA035 Signals 80-Pin PQFP
3-10
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WaveArtist100/300 Audio System Devices Designer's Guide
Table 3-3. RWA035 Hardware Interface Signal Definitions
Label Type Power Ground 20-28 78-80, 1-3, 6-9, 12-13, 16-19 Digital Power. Connect through filter. Signal/Definition
Digital Ground. Connect digital ground.
RWA030 Interface MA[8:0] MD[15:0] It/Ot4 Clock. Connect RWA030 YCLKM pin. Write. Connect RWA030 pin. Chip Select. Active input, asserted select RWA035 device. Connect RWA030 SMMCS pin. Memory Address. Connect ground. Connect MA[8:1] RWA030 MA[7:0], respectively. Memory Data. Connect MD[15:0] RWA030 MD[15:0], respectively.
KISI KISO TOPI RESET#
Itst
Serial Input Data. Connect RWA030 KISOB pin. Serial Output Data. Connect RWA030 KISIB pin. Period Connect TOPI RWA030 TOPO pin. Reset. Active input, asserted reset RWA035. Connect RESET# RWA030 WRST# pin. Memory Interface Memory Address. DRAM, connect RMA[7:0] DRAM pins A[7:0], respectively; leave RMA8 open. Memory Data. Connect RMD[11:0] DRAM pins D[11:0], respectively. Connect DRAM pins D[12-15] through individual pull-up resistors. Memory Read/Write. High when reading from DRAM; when writing DRAM. Connect RMR/W# DRAM pins UW#. Memory Address Select. Active output, asserted when DRAM address valid RMD[11:0]. Connect RMRAS# DRAM RAS#. Memory Column Address Select. Active output, asserted when DRAM column address valid RMD[11:0]. Connect RMCAS# DRAM CAS#. Other Data Transfer Acknowledge. used; leave DTACK# open. Read. used; leave this open. This internal pullup resistor.
RMA[8:0] RMD[11:0] RMR/W# RMRAS# RMCAS#
56-62, 6566 38-42, 4549, 52-53
It/Ot2
DTACK#
It/Ot4 Itpu
Notes: Type type (see Table 3-5).
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Table 3-4. Input/Output Type Descriptions
Type Itpd Itpu Itst Itstpu Itts I/Ot12 Ot12 Otoc16 Otod2 Otpu4 Otpu12 Otts8 Description Device interconnect, electrical characteristics stated. Analog input, signal analog characteristics. Digital input, CMOS compatible. Digital input, compatible. Digital input, compatible, internal pull-down resistor ground. input externally driven, assumes state. Digital input, compatible, internal pull-up resistor VDD. input externally driven, assumes high state. Digital input, compatible, schmitt trigger. Digital input, compatible, schmitt trigger, internal pull-up resistor (50K) VDD. Digital input, compatible, tri-state. Digital input, compatible. Digital input, switches between VDD. Crystal Input, centered around VDD/2 volts swings approximately volts about VDD/2. Digital input/output, compatible, Analog output, signal analog characteristics. Digital output, drive. Digital output, CMOS compatible, Digital output, compatible, Digital output, compatible, Digital output, compatible, Digital output, compatible, open collector, Digital output, compatible, open drain, Digital output, compatible, internal pull-up resistor (50K) VDD, drive. Digital output, compatible, internal pull-up resistor (50K) VDD, high drive, max. load. Digital output compatible, tristate, Digital output, will drive logic level 3.5V greater while sourcing will drive logic zero level volts less while sinking Digital output, drives between VDD. Digital output, open drain driver. drive output zero level volts less while sinking Internal pull-up resistor VDD. output will assume high state driver turned off. external connection allowed (pin connected internal circuitry).
Notes: electrical characteristics Table (digital signals), Table (analog input signals), Table (analog output signals). compatible inputs will accept voltage volts logic level voltage volts logic zero level.
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Table 3-5. Digital Electrical Characteristics
Parameter Input High Voltage Input Voltage Input High Current Input Current Input Leakage Current Output High Voltage Output Voltage Table LOAD ±2.5 LOAD -0.3 µADC 0.8V (VDD-1V) 5.25V, 5.25V, 5.25V Symbol Min. Typ. Max. Units Test Conditions1
Notes: Test Conditions: 70°C, (unless otherwise stated).
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Table 3-6. Analog Performance
Parameter Symbol Resolution bits Instantaneous Dynamic Range LINE Input (typ.) Input (typ.) Total Harmonic Distortion (THD) LINE Input (typ.) Input (typ.) Channel Isolation LINE-to-LINE (min.) LINE-to-MIC, LINE-to-AUX LINE-to-AUX (min.) Channel Gain Mismatch LINE input ±0.5 (max.) input ±0.5 (max.) Input Gain 22.5 (typ.) steps] Path Offset Voltage (typ.) Gain Error (max.) Gain Drift ppm/°C Full Scale Input LINE, MONOIN Vp-p (max.) input Vp-p (max.) input (±20 mVp-p (max.) Input Resistance (min.), (max) Input Capacitance (typ.) Test Conditions: 25°C; Input: sine wave; Conversion rate 44.1 kHz; measurement bandwidth kHz; 16-bit linear coding; dynamic range measured input; measured Vrms input; nominal gain
Table 3-7. Analog Performance
Symbol Resolution bits Differential Non-linearity (max.) Total Dynamic Range (typ.) Total Harmonic Distortion (THD) Bypassing Mixer (typ.) Channel Isolation LOUT ROUT >-90 Reference Voltage Voltage (reference (Typ.) 4.0V 2.5V) Load Current (max.) Offset Voltage (typ.), (max.) Full Scale Output Voltage Vp-p (max.) Gain Drift 3000 ppm/°C Deviation from Linear Phase (max.) Output Load Resistance LOUT ROUT (min.) MONOOUT (min.) Mute Attenuation (min.) [for signal level] Pass-band Ripple ±0.1 (max.) Out-of-Band Energy (0.6*FS MHz) (max.) Audible Out-of-Band Level (0.6*FS kHz) (max.) Test Conditions: 25°C; Output: sine wave; Conversion rate 44.1 kHz; measurement bandwidth kHz; 16-bit linear coding; dynamic range measured input; measured Vrms output; nominal gain Parameter
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WaveArtist100/300 Audio System Devices Designer's Guide Hardware Interface Circuits
This section describes typical WaveArtist interface circuits connections. Consult following AccelerATor Kits reference designs full schematics typical applications: AK28-D640: ACFSP RWA100/RWA300 Audio/Telephony Internal Card 3.2.1 Host Plug Play (PnP) Interface interface supports logical devices with programmable base address assignments logical devices typically assigned WaveArtist command/status registers, Sound Blaster Pro, MPU-401, modem, CD-ROM, game port. address assignment, IRQ, DRQ, DACK signal routing established software driver writing configuration registers after successful isolation. Control lines supported are: Read (IOR#), Write (IOW#), Address Enable (AEN), Reset (RESET), System High (SBHE#) inputs, (IOCS16#) output. Interrupt servicing supported eight Interrupt Request outputs (IRQ[15, 3]). Direct memory access (DMA) supported four Request outputs (DMA[7, four Acknowledge inputs (DACK#[7,6,5,1]). RWA100/RWA300 address, data, control signals connect directly host without need external glue logic. 3.2.2 Serial EEPROM Interface 3-line serial interface XICOR X24C02 compatible serial EEPROM supported. interface signals Data Clock (SCK) Write Control (WC#) outputs bidirectional Serial Data (SDA) line. Since interface open collector, external pullup resistor required. utility available programming EEPROM from host bus. typical EEPROM interface connection shown Figure 3-5.
WAVEARTIST
Figure 3-5. Typical EEPROM Interface Connection 3.2.3 Audio Interface Stereophonic signals supported are: Microphone (RMIC, LMIC), Line (RLINE, LLINE), Audio (RAUX1, LAUX1), Auxiliary (RAUX2, LAUX2) inputs Audio (ROUT, LOUT) outputs. Monophonic signals supported are: Mono (MONOIN) input Mono (MONOOUT) output.
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microphone input signals (LMIC RMIC) supported. typical microphone interface shown Figure 3-6. Figure 3-6, signal from microphone receptacle coupled capacitor LMIC RMIC pins provide input both channels. signal LMIC RMIC optionally routed modem voice input (MIC_V) through isolation capacitor C136. This configuration supports both electret microphone Plantronics headset. external amplifier needed boosting microphone level since provided codec. enabled software control. bias electret microphone provided R123, R124, C143, C144 circuit. side R124 provides filtered bias microphone C143 C144 provide decoupling. bias current should less than 0.65 Plantronics headsets. High frequency noise filtered microphone receptacle capacitor noise suppression provided ferrite inductor
WAVEARTIST
Figure 3-6. Typical Microphone Interface Circuit Line line-level input signals (LLINE RLINE) supported. typical Line interface circuit shown Figure 3-7. Figure 3-7, left channel input voltage divided resistors R114 reduce input voltage VRMS (2.0 VP-P) maximum input level then coupled capacitor LLINE input pin. Similarly, right channel input voltage divided resistors R115 then coupled RLINE input pin. High frequency noise filtered Line receptacle capacitors C117 C118. noise suppression provided ferrite inductors L21.
WAVEARTIST
Figure 3-7. Typical Line Interface Circuit
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Input auxiliary input signals (LAUX1 RAUX1) supported. typical Input interface circuit CD-ROM shown Figure 3-8. Figure 3-8, left channel input voltage divided resistors reduce input voltage VRMS maximum input level then coupled capacitor LAUX1 input pin. Similarly, right channel input voltage divided then coupled RAUX1 input pin.
WAVEARTIST
Figure 3-8. Typical Input Interface Circuit Input auxiliary input signals (LAUX2 RAUX2) supported. typical Input interface circuit modem/telephone line/telephone handset interface shown Figure 3-9. Figure 3-9, left channel input from modem output coupled capacitor LAUX2 input pin. Similarly, right channel input from modem voice speaker output (SPK_V) coupled RAUX2 input pin.
WAVEARTIST
Figure 3-9. Typical Input Interface Circuit Mono monaural input (MONOIN) supported. typical Mono interface circuit shown Figure 3-10. modem voice application, Mono input typically coupled through modem voice speaker output. speaker application, Mono input typically coupled speaker output from motherboard. speaker output signal from motherboard disconnected from speaker connected through voltage divider MONOIN pin. this application, MONOOUT then routed speaker connector, MONOOUT description).
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WAVEARTIST
Modem Voice Speaker Interface
WAVEARTIST
Speaker Interface
Figure 3-10. Typical Mono Interface Circuit Line line-level output signals (LOUT ROUT) supported. typical Line interface circuit shown Figure 3-11. Figure 3-11., LOUT output coupled through capacitor left channel line receptacle left channel headset receptacle through attenuator resistor Likewise, ROUT output coupled through right channel line receptacle headset receptacle through attenuator resistor signals routed through ferrite inductors suppression filtered output receptacle capacitors chassis ground.
WAVEARTIST
Figure 3-11. Typical Line Interface Circuit 3-18 1104
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Mono monaural output (MONOOUT) supported. MONOOUT signal left right line channels independently muted. Typical Mono interface circuits supporting connection speaker input modem music input shown Figure 3-12. modem music hold application, MONOOUT coupled through music hold circuit. speaker connection, MONOOUT signal coupled through amplifier circuit which drives speaker through 4-pin header motherboard connection speaker lines. this application, MONOIN connected speaker output signal from motherboard, MONOIN description).
WAVEARTIST
Music Hold Interface
WAVEARTIST
Speaker Interface
Figure 3-12. Typical Mono Interface Circuit
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3.2.4 Enhanced CD-ROM Interface supported signals CD-ROM Select output (CDSEL#), programmable address chip select outputs (CDSEL0# CDSEL1#), CD-ROM Interrupt Request output (CDIRQ), CD-ROM Request output (CDDRQ), CD-ROM Request Acknowledge input (CDDACK#), CD-ROM Enable High Byte output (CDHI#). address base signal assignments established setup. typical CD-ROM interface circuit 40-pin CD-ROM header shown Figure 3-13. CD-ROM data lines (CD15:0]) routed from header host data (SD[15:0]) through transceivers (lower bits [7:0]) (upper bits [15:8]). lower data byte from CD-ROM enabled onto host through transceiver when CDSEL# DIOR# (buffered host read, IOR#, through buffer U1). upper data byte from CD-ROM enabled onto host through transceiver when ENHI# DIOR# low. CDSEL0#, CDSEL1#, CDIRQ, CDDACK# RESET#, CDDRQ routed directly header. Pull down resistor connected CDDRQ.
WAVEARTIST
Figure 3-13. Typical CD-ROM Interface Circuit
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3.2.5 Joystick/MIDI Interface Eight joystick MIDI signals supported. These signals typically routed standard 15-pin DB-15 game port connector. Only external passive components required complete game port interface circuit. Joystick Interface four timer input pins (JAX, JAY, JBX, JBY) support joysticks four paddles. four button input pins (JA1, JA2, JB1, JB2) support buttons joystick. external timer device required. typical joystick/MIDI interface shown Figure 3-14. Figure 3-14, timer input signal, provide timer debounce period time constant. provide high frequency noise suppression, needed. JAY, JBX, signal interface circuits operate identically. When host writes game port, timer pins discharge external capacitors internal flip-flop output When capacitor charges internal threshold voltage (0.63 time constant), internal flip-flop reset capacitor charging time constant determined joystick potentiometer value external circuit. timer output discharge 0.1µF capacitor from falling edge internal decoded game write signal within host will periodically read game port address push button status calculate coordinate based duration timer flip-flop output being high. switch input routed directly from DB-15 connector, i.e., external pullup resistors required. Capacitor provides switch overshoot protection. JB1, JA2, signal interface circuits operate identically.
WAVEARTIST
Figure 3-14. Typical Joystick/MIDI Interface Circuit
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MIDI Interface MIDI serial interface receive transmit serial data logic levels. External hardware required connect signals, MIDI Receive (MIDI_RX) input MIDI Transmit (MIDI_TX) output, interface with other MIDI compatible components. serial data character format consists start (logical eight data bits (LSB shifted first), stop (logical data rate complies with standard MIDI specification. Figure 3-14, MIDI_TX MIDI_RX signals routed directly DB-15 game connector. ferrite inductor each line needed suppression. Each line must connected chassis ground through 1200 capacitor. 3.2.6 Modem Interface Only three signals needed connect WaveArtist Rockwell modem: Modem Reset (RESET#) Modem Chip Select (MSEL#) outputs Modem Interrupt Request (MIRQ) input. typical modem connection shown Figure 3-15. RESET# output connects Modem ~RESET input, MSEL# output connects modem ~HCS input modem data transceiver (U1) input, MIRQ input connects modem HINT output. MSEL# output pulled deselect modem disconnect (provide high impedance) modem data lines from host through transceiver (U1) when WaveArtist active. external pulldown resistor needed MIRQ input. Note that modem data lines normally connected directly data transceiver (U1), however, series resistor required each modem data line some computers reduce signal reflections/switching transients data lines. modem host address inputs (HA2:0], host read (~HRD), host write (~HWT) connect directly host connector. address lines connected through capacitors noise suppression.
MODEM
WAVEARTIST
Figure 3-15. Typical Modem Interface Circuit
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3.2.7 Crystal Interface Circuit Figure 3-16.
WAVEARTIST
Figure 3-16. Typical Crystal Interface Circuit
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3.2.8 RWA300 External Memory RWA300 external memory supports address outputs (MA[22:0]), bidirectional data lines (MD[15:0]), associated control lines connect external wavetable ROM, optional downloadable sound sample DRAM, optional RWA035 Effects Processor Upgrade. typical memory connection shown Figure 3-17. Interface RWA300 connects external wavetable ROM. organized bits 512k bits with maximum access time wavetable sound available file form programming into ROM. Alternatively, Rockwell RWA031 (1MB) RWA032 (2MB) masked 44-pin containing wavetable sound available. DRAM Interface RWA300 optionally connects DRAM 8MB) allow sound samples downloaded through RWA300. DRAM must have maximum access time RWA035 Interface RWA300 optionally connects RWA035 Effects Processor Upgrade professional quality sound processing such concert hall other spatial features RWA300. RWA035 connects external DRAM. DRAM must have maximum access time
WAVEARTIST RWA300 RWA030
Figure 3-17. Typical RWA300 Memory RWA035 Interface Circuit
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Interface Timing Waveforms
Timing
system interface timing shown Figure (host write) Figure (host read). chip select signal throughput timing shown Figure 4-3. signal throughput timing shown Figure 4-4. signal throughput timing shown Figure 4-5. DACK signal throughput timing shown Figure 4-6.
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IOW# tsas taens Timing Requirements IOW# pulse width setup hold setup hold setup hold tsas tsah taens taenh
1104F4-1
tsah
taenh
data input
Figure 4-1. Waveforms Timing System Write
IOR# tsas taens tsrd Timing Requirements IOR# pulse width setup hold setup hold delay hold tsas tsah taens taenh tsrd tsrh @150 loading data output tsrh taenh tsah
1104F4-2-HRD
Figure 4-2. Waveforms Timing System Read 1104
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valid address
tcsd MSEL# CDSEL# CDSEL0# CDSEL1# Timing Requirements MSEL# delay CDSEL# delay CDSEL0# delay CDSEL1# delay tcsd
tcsd
loading
1104F4-3-HCS
Figure 4-3. Waveforms Timing ~Chip Select Throughput Delay
MIRQ CDIRQ tirqd IRQn tirqd
Timing Requirements IRQn delay tirqd @150 loading
1104F4-4
Figure 4-4. Waveforms Timing Throughput Delay
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CDDRQ tdrqd DRQn tdrqd
Timing Requirements DRQn delay tdrqd @150 loading
1104F4-5
Figure 4-5. Waveforms Timing Throughput Delay
~DACKn tdackd CDDACK# tdackd
Timing Requirements CDDACK# delay tdackd @150 loading
1104F4-6 CDDACK
Figure 4-6. Waveforms Timing DACK Throughput Delay
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WaveArtist100/300 Audio System Devices Designer's Guide Serial EEPROM Interface Timing
serial EEPROM interface timing shown Figure Table 4-1. Serial EEPROM format shown Figure 4-8.
SCLK
Output
Input
Notes Numbers refer timing requirements listed associated timing table. load: Device EEPROM
1104F4-7 EEPROM
Figure 4-7. Waveforms Timing Serial EEPROM Interface
Table 4-1. Timing Serial EEPROM Interface
Item Definition SCLK time SCLK high time SCLK clock period Start hold after SCLK Data output delay (rising) Data output delay (falling) Stop hold after SCLK Data setup SCLK Data hold after SCLK Min. 1260 1260 2520 Max. Units Figure 4-7, Note Figure 4-7, Note Notes Max. load Max. load Max. load
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ACTIVITY: MASTER
START
SLAVE ADDRESS
STOP
LINE
DATA
ACTIVITY: EEPROM
Current Address Read
ACTIVITY: MASTER
START
SLAVE ADDRESS
WORD ADDRESS
START
SLAVE ADDRESS
STOP
LINE
DATA
ACTIVITY: EEPROM
Random Read 1104F4-8 EEPROM
Figure 4-8. Waveforms Timing Serial EEPROM Interface
MIDI Serial Interface Timing
MIDI interface waveforms timing shown Figure 4-9.
MIDI_RX MIDI_TX START
STOP
11581F4-9
Figure 4-9. Waveforms Timing MIDI Interface
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WaveArtist100/300 Audio System Devices Designer's Guide Memory Interface Timing (RWA300)
DRAM Interface DRAM interface timing conforms Fujitsu MB814260-70 256K 16-bit dynamic compatible. DRAM interface timing parameters listed Table 4-2.
Table 4-2. Timing: DRAM Interface
Parameter RAS# Access Time CAS# Access Time Address Access Time Random Cycle Time Value max. max. max. max.
Interface timing listed Table illustrated Figure 4-10.
Table 4-3. Timing: Interface
Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Output Chip Disable Output High Output Hold from Address Change tACF Symbol Min. Value Max. Value
MA0-MA19
ADD1
ADD2
SMROE0# (CE#)
tACE
(OE#)
VALI DATA VALI DATA
MD0-MD7 MD8-MD15
1103F3-3
Figure 4-10. Waveforms: Read Cycle
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HOST SOFTWARE INTERFACE
This section describes, from orientation interfaces their relative functions,. These interfaces categorized according registers shown Table Sound Blaster Pro, MPU-401, (OPL3), WaveArtist. Each category described separate section within this document.
Interface Register
Table 5-1. Interface Register
Address (Hex) SB+0, SB+8, SB+0, SB+8, SB+1, SB+9, SB+2, SB+8, SB+3, SB+8, SB+4 SB+5 SB+6 SB+A SB+C SB+C SB+E MB+0 MB+1 MB+1 WB+0, WB+2, WB+4 WB+5 WB+6 WB+7 WB+8,9 WB+A,B 3F8-3FF 2F8-2FF 3E8-3EF 2E8-2EF Bits Game Port Music Address Music Status Music Data Music Address Music Data Sound Blaster Mixer Address Sound Blaster Mixer Data Sound Blaster Reset Sound Blaster Data Sound Blaster Data Sound Blaster Write Status Sound Blaster Read Status Data Register Command Register Status Register WaveArtist Command Register Byte WaveArtist Command Register High Byte WaveArtist Data Register Byte WaveArtist Data Register High Byte WaveArtist Control Register (CTRLR) WaveArtist Status Register (STATR) WaveArtist Expansion Control Register WaveArtist Expansion Control Register WaveArtist Expansion Data Register WaveArtist Expansion Data Register Communications Port (COM1) Communications Port (COM2) Communications Port (COM3) Communications Port (COM4) Function
Notes: Sound Blaster interface base register (typically assigned setup). MPU-401 interface base register (typically assigned setup). WaveArtist interface base register (typically between 0250 03F0 assigned setup).
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PLUG-AND-PLAY INTERFACE
interface supported with logical devices. IRQ3 programmable base address assignments available logical devices. Address assignment, IRQ, DRQ, DACK signal routing done software driver writing configuration registers after successful isolation. Plug-and-Play specification.
Resource Data
example resource data shown below.
Address (Dec.) Data (Dec.) Data (Hex.) Description Vendor Name Vendor Product Number 5000 Serial Number: 00000001
Checksum (LFSR) Version Card String Rockwell Identifier string ANSI length length Logical Device Logical Device Wave Artist Wave Audio 5000 Range Check Enabled boot Dependent Function Port Descriptor address decode base base high (0250) base base high (03F0) Alignment base address Range length Format Channel bit, count word
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Dependent Function Logical Device Logical Device Sound Blaster 5001 Range Check Enabled boot Dependent Function Format Channel bit, count byte Port Descriptor address decode base base high (0220) base base high (0240) Alignment base address Range length Port Descriptor address decode base base high (0388) base base high (0388) Alignment base address Range length Format Dependent Function Logical Device Logical Device MPU401 5002 Range Check Enabled boot Dependent Function Preferred Configuration Port Descriptor address decode address base base high (0330) base base high (0330) Alignment base address Range length Format Dependent Function Acceptable Configuration Port Descriptor address decode address base base high (0300) base base high (0300) Alignment base address Range length Format Dependent Function Suboptimal Configuration Port Descriptor address decode address
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base base high (0300) base base high (0330) Alignment base address Range length Format Dependent Function Logical Device Logical Device Modem RC288ACF/SP 0160 Range Check Enabled boot Compatible device ID:PNPC11E
Dependent Function COM3 more Most preferred Port Descriptor address decode base base high (03E8) base base high (03E8) Alignment base address Range length Format 5,7,10,11,15 Dependent Function COM4 more Most preferred Port Descriptor address decode base base high (02E8) base base high (02E8) Alignment base address Range length Format 5,7,10,11,15 Dependent Function COM1 Acceptable Port Descriptor address decode base base high (03F8) base base high (03F8) Alignment base address Range length Format 4,5,7,10,11,15 Dependent Function COM2 Acceptable Port Descriptor address decode base base high (02F8)
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13933 base base high (02F8) Alignment base address Range length Format 3,5,7,10,11,15 Dependent Function COM3 Acceptable Port Descriptor address decode base base high (03E8) base base high (03E8) Alignment base address Range length Format 4,5,7,10,11,15 Dependent Function COM4 Acceptable Port Descriptor address decode base base high (02E8) base base high (02E8) Alignment base address Range length Format 3,5,7,10,11,15 Dependent Function Logical Device Logical Device CDROM Dummy placer with resource requested 5003 Range Check Enabled boot Dependent Function real resources Format Dependent Function Logical Device Logical Device Game Port 5004 Range Check Enabled boot Port Descriptor address decode base base high (0201) base base high (0201) Alignment base address Range length Check
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DESIGN CONSIDERATIONS
Good engineering practices must followed when designing printed circuit board (PCB) containing audio device. This especially important considering record/play analog speech music audio. Suppression noise essential proper operation performance audio device interfacing audio circuits. aspects noise board design containing audio device must considered: on-board/off-board generated noise that affect analog signal levels analog-to-digital conversion (ADC)/digital-to-analog conversion (DAC), on-board generated noise that radiate off-board. Both on-board off-board generated noise that coupled on-board affect interfacing signal levels quality, especially level analog signals. particular concern noise frequency ranges affecting audio circuit performance. On-board generated electromagnetic interference (EMI) noise that radiated conducted off-board separate, equally important, concern. This noise affect operation surrounding equipment. Most local governing agencies have stringent certification requirements that must specific environments. order minimize contribution circuit design layout EMI, designer must understand major sources reduce them acceptable levels. Proper board layout (component placement orientation, signal routing, trace thickness geometry, etc.), component selection (composition, value, tolerance), interface connections, shielding required board design achieve desired audio performance attain certification. aspects proper engineering practices beyond scope this designer's guide. designer should consult noise suppression techniques described technical publications journals, electronics electrical engineering text books, component supplier application notes. Seminars addressing noise suppression techniques often offered technical professional associations well component suppliers. following guidelines offered specifically help achieve stated audio device performance minimize generation.
BOARD LAYOUT GUIDELINES
7.1.1 General Principles Provide separate digital analog sections board. Keep digital analog components their corresponding traces separate possible minimum) confined defined sections. Keep high speed digital traces short possible. Keep sensitive analog traces short possible. Provide proper power supply distribution, grounding, decoupling. Provide separate filtered/regulated analog power supply. Provide separate digital ground, analog ground, chassis ground appropriate) planes. Provide wide traces power critical signals. Position interface circuits near corresponding off-board connectors.
7.1.2 Component Placement From system circuit schematic, Identify digital analog circuits their components, well external signal power connections. Identify digital, analog, mixed digital/analog components within their respective circuits. Note location power signals pins each device (IC).
Roughly position digital analog circuits separate sections board. Keep digital analog components their corresponding traces separate possible confined their respective sections board. Typically, digital circuits will cover one-half board, analog circuits will cover one-half board. Once sections have been roughly defined, place components starting with connectors jacks.
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Allow sufficient clearance around connectors jacks mating connectors plugs. Allow sufficient clearance around components power ground traces. Allow sufficient clearance around sockets allow component extractors.
First, place mixed analog/digital components (e.g., converter, converter). Orient components pins carrying digital signals extend onto digital section pins carrying analog signals extend onto analog section much possible. Position components straddle border between analog digital sections.
Place analog components. Place analog circuitry same area PCB. Place analog components close side board containing RLINE, LLINE, RAUX1, LAUX1, RAUX2, LAUX2, RMIC, LMIC, MONOIN, MONOOUT signals. Avoid placing noisy components traces near RLINE, LLINE, RAUX1, LAUX1, RAUX2, LAUX2, RMIC, LMIC, MONOIN, MONOOUT lines.
Place active digital components/circuits decoupling capacitors. Place digital components close together order minimize signal trace length. Place decoupling (bypass) capacitors close pins (usually power ground) they decoupling. Make smallest loop area possible between capacitor power/ground pins reduce EMI. Place host interface components close edge connector accordance with applicable interface standard, e.g., 2.5-in maximum trace length bus. Place crystal circuit close possible audio device
Provide "connector" component, usually zero resistor ferrite bead more points connect section's ground another.
7.1.3 Signal Routing Route audio signals provide maximum isolation between noise sources noise sensitive inputs. When layout requirements necessitate routing these signals together, they should separated neutral signals. noise source, neutral, noise sensitive pins listed Table 7-1. Keep digital signals within digital section analog signals within analog section. (Previous placement isolation traces should prevent these traces from straying outside their respective sections.) Route digital traces perpendicular analog traces minimize signal cross coupling. Provide isolation traces (usually ground traces) ensure that analog signals confined analog section digital traces remain analog section. trace have narrowed route though mixed analog/digital keep trace continuous. Route analog isolation ground trace, least wide. Route digital isolation ground trace, least wide.
Keep host control signals (e.g., IOR#, IOW#, RESET) traces least thick (preferably mil). Keep analog signal (e.g., RMIC, LMIC, LLINE, RLINE) traces least thick (preferably mil) short possible. Keep other signal traces wide possible, least (preferably mil).Route signals between components shortest possible path (the components should have been previously placed allow this). Route traces between bypass capacitors pins, least wide; avoid vias possible. Gather signals that pass between sections (typically speed control status signals) together route them between sections through path isolation ground traces (preferred) points only. path made side only, then isolation trace kept contiguous briefly passing other side jump over signal traces. Avoid right angle degree) turns high frequency traces. smoothed radiuses degree corners. 1104
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Minimize number through-hole connections (feedthroughs/vias) traces carrying high frequency signals. Keep signal traces away from crystal circuit. Distribute high frequency signals continuously single trace rather than several traces radiating from point. Eliminate ground loops, which unexpected current return paths power source. 7.1.4 Power Identify digital power (VDD) analog power (AVDD) supply connections. Where main power enters (edge connector power connector), place electrolytic tantalum capacitor parallel with ceramic capacitor between power ground. These capacitors help supply current surge demands prevent those surges from generating noise power lines that affect other circuits. Provide voltage regulator supply clean analog power (+5VA) AVDD pins. Generally, route power traces before signal traces.
7.1.5 Ground Planes 2-layer design, provide digital analog ground plane areas unused space around under digital analog circuit components, respectively, both sides board, connect them such manner avoid small islands. Connect each ground plane area like ground plane areas same side several points like ground plane areas opposite side through board several points. Connect DGND pins digital ground plane area AGND pins analog ground plane area. Typically, separate collective digital ground plane area from collective analog ground plane area fairly straight gap. There should inroads digital ground plane area extending into analog ground plane area visa versa. 4-layer design, provide separate digital analog ground planes covering corresponding digital analog circuits, respectively. Connect DGND pins digital ground plane AGND pins analog ground plane. Typically, separate digital ground plane from analog ground plane fairly straight gap. design which needs filtering, define additional "chassis" section adjacent bracket plug-in card. Most components (usually ferrite beads/capacitor combinations) positioned this section. Fill unused space with chassis ground plane, connect metal card bracket connector shields/grounds. Keep current paths separate board functions isolated, thereby reducing current's travel distance. Separate board functions are: host interface, audio interface, CD-ROM interface, game port/MIDI interface, modem interface, memory (e.g., DRAM). Power ground each these functions should separate islands connected together power ground source points only. Connect grounds together only point, possible, using ferrite bead. Allow other points grounds connected together necessary suppression. Keep ground traces wide possible, least mil. Keep traces connecting decoupling capacitors power ground their respective short direct (i.e., going through vias) possible.
7.1.6 Crystal Circuit Keep traces component leads connected crystal input output pins (i.e., XTLI XTLO) short order reduce induced noise levels minimize stray capacitance that could affect crystal oscillator. Keep XTLO trace extremely short with bends greater than degrees containing vias since XTLO connected fast rise time, high current driver. Where ground plane available, such 2-layer design, crystal capacitors ground paths using separate short traces wide possible) with minimum angles vias directly corresponding device digital ground nearest crystal pins. Connect crystal cases(s) ground applicable). Connect crystal capacitor ground connections directly audio device. common ground plane ground trace route capacitor corresponding pin.
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Table 7-1. RWA300 Device Noise Characteristics
Device Function VDD, AVDD GND, AGND Crystal Interface RWA300 EEPROM CD-ROM Game port/MIDI Interface Audio Interface External Memory Connection (NC) Noise Source Added Neutral Noise Sensitive
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WaveArtist100/300 Audio System Devices Designer's Guide CRYSTAL/OSCILLATOR SPECIFICATIONS
specifications recommended suppliers crystal listed Table 7-2.
Table 7-2. Crystal Specifications 50.8032
Characteristic Rockwell Part Electrical Frequency Frequency Tolerance Frequency Stability Temperature Aging Oscillation Mode Calibration Mode Load Capacitance, Shunt Capacitance, Series Resistance, Drive Level Operating Temperature Storage Temperature Mechanical Dimensions Mounting Holder Suggested Suppliers Dimensions Mounting Holder 333R45-005 50.8032 nom. 11.5 (0°C 70°C) over years Third overtone Parallel resonant nom. max. max. Drive Level correlation; max. 70°C -40°C 85°C 11.05 4.65 13.46 Through Hole HC-49/U America, Inc. Toyocom U.S.A., Inc. Hy-Q International (USA), Inc. Value
Notes: Characteristics 25°C unless otherwise noted. Supplier Information: Hy-Q International (USA), Inc. Enlanger, (606) 283-5000 America, Inc. Fountain Valley, (714) 557-7833 Toyocom U.S.A., Inc. Costa Mesa, (714) 668-9081
1104
WaveArtist100/300 Audio System Devices Designer's Guide PACKAGE DIMENSIONS
package dimensions RWA100/RWA300 208-pin shown Figure 7-1. package dimensions RWA035 80-pin PQFP shown Figure 7-2. package dimensions RWA031/RWA032 44-pin shown Figure 7-3.
1104
WaveArtist100/300 Audio System Devices Designer's Guide
27.000 0.200 24.000 0.100 R.500
MARK 24.000 0.200 1.414 27.000 0.100
VIEW
SIDE VIEW
24.130 12.065 1.270
SEATING PLANE
0.150 0.75 0.15
0.600 .100 BEFORE REFLOW 0.480 AFTER REFLOW
24.130
12.065 1.270
2.220 0.220 BEFORE REFLOW 2.100 AFTER REFLOW
BOTTOM VIEW
NOTES: REFLOW APPLIES SOLDERING HOST BOARD. DIMENSIONS MILLIMETERS (MM).
SIDE VIEW DETAIL
1104F11-X PD-208BGA
Figure 7-1. Package Dimensions 208-Pin
1104
WaveArtist100/300 Audio System Devices Designer's Guide
CHAM (4X) detail
VIEW
SIDE VIEW
Dim. Coplanarity
Millimeters Max. Min. 0.35 0.05 17.45 16.95 14.0 12.35 1.03 0.73 0.65 0.25 0.45 0.19 0.13
Inches* Max. Min. 0.0945 0.0020 0.6673 0.0138 0.6870 0.0787 0.5512 0.4862 0.0287 0.0406 0.0630 0.0256 0.0098 0.0051 0.0177 0.0075
0.004
Ref: 80-PIN PQFP (GP00-D227)
DETAIL
Metric values (millimeters) should used layout. English values (inches) converted from metric values include round-off errors.
PD-PQFP-80 (040695)
Figure 7-2. Package Dimensions 80-Pin PQFP
1104
WaveArtist100/300 Audio System Devices Designer's Guide
Figure 7-3. Package Dimensions 44-Pin
1104
WaveArtist100/300 Audio System Devices Designer's Guide
This page intentionally blank.
7-10
1104
INSIDE BACK COVER NOTES
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more information: Call 1-800-854-8099 International information: Call 1-714-833-6996 Address: http://www.nb.rockwell.com E-Mail Address: literature@nb.rockwell.com
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©1996, Rockwell International Corporation Printed U.S.A. Rights Reserved

Designer's Guide (Preliminary) Order 1104 Rev. October 1996

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