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SWITI Switching 20450 20470 24470 Version MTSI MTSI-L MTSI-XL
Wired Communications
Edition 2001-01-01 Published Infineon Technologies St.-Martin-Strasse D-81541 Germany
Infineon Technologies 2001.
Rights Reserved. Attention please! information herein given describe certain components shall considered warranted characteristics. Terms delivery rights technical change reserved. hereby disclaim warranties, including limited warranties non-infringement, regarding circuits, descriptions charts stated herein. Infineon Technologies approved CECC manufacturer. Information further information technology, delivery terms conditions prices please contact your nearest Infineon Technologies Office Germany Infineon Technologies Representatives worldwide (see address list). Warnings technical requirements components contain dangerous substances. information types question please contact your nearest Infineon Technologies Office. Infineon Technologies Components only used life-support devices systems with express written approval Infineon Technologies, failure such components reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain and/or protect human life. they fail, reasonable assume that health user other persons endangered.
SWITI Switching 20450 20470 24470 Version MTSI
Wired Communications
MTSI-L
MTSI-XL
PRELIMINARY Revision History: Previous Version: Page
2001-01-01 03.00
Subjects (major changes since last revision) chapter sub-channel broadcast Change memory dump: software reset must issued instead memory dump disable. chapter 4.5.2: Analog Disconnect Part Broadcast Command: ITSA register. Update Timing Electrical Characteristics
questions technology, delivery prices please contact Infineon Technologies Offices Germany Infineon Technologies Companies Representatives worldwide: webpage http://www.infineon.com
20450 20470 24470
Table Contents 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 3.3.1 3.3.1.1 3.3.1.2 3.3.1.3 3.3.1.4 3.3.1.5 3.3.2 3.3.3 3.3.4 3.4.1 3.4.2 3.4.2.1 3.4.2.2 3.4.3 3.4.4 3.7.1 3.7.2
Page
Overview Overview Features Features Detail Logic Symbol Standard Application Description Diagrams Definitions Functions Local Interface (PCM) General Purpose Port Clock Signals JTAG Interface Microprocessor Interface Power Supply Architectural Description Functional Block Diagram Overview Functional Blocks Switching Factory Switching Modes Minimum Constant Delay Sub-Channel Switching Multipoint Switching Broadcast Switching Bidirectional Switching Parallel Mode Local (PCM) Switching Block Error Handling Analyze Connection Data Memory Clock Generator General Overview Analog (APLL) Functional Description Jittertransferfunction Phase Alignment Synchronization Loops Read SWITI Configuration with Indirect Register Addressing Power-On Reset Behavior Hardware Reset Software Reset
Description Interfaces Local Interface (PCM)
2001-01-01
Preliminary Data Sheet
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Table Contents 4.3.1 4.3.2 4.5.1 4.5.2 4.6.1 4.6.2 4.6.3 6.7.1 6.7.2 6.7.3 6.7.3.1 6.7.3.2 6.8.1 6.10 6.10.1 6.10.2 6.10.2.1 6.10.2.2 6.10.2.3 6.10.3 6.10.4
Page
Data Rate Microprocessor Interface Intel/Siemens Motorola Mode De-multiplexed Multiplexed Mode General Purpose Port (GPIO) General Purpose Clocks Frame Group Outputs GPCLK Clock Outputs JTAG (Boundary Scan) Boundary Scan Test-Access-Port (TAP) Controller Identification Code Read Access Register Description Register Overview 8-Bit Interface Detailed Register Description 8-bit Interface Register Overview 16-Bit Interface Detailed Register Description 16-Bit Interface Programming Device Read Write Access Interrupt Handling Command Register Overview Indirect Configuration Register Access Initialization Procedure Clocking Unit Local (PCM) Line Interface Standby Command Determining Clock Rates Performing Shifting Input Shifting Output Shifting Global Clock Signals Framing Groups Read Time Slot Value Establish Connections Establish 8-bit Connections Sub-Channel Switching Establish 4-bit Connections Establish 2-bit Connections Establish 1-bit Connections Establish Broadcast Connections Establish Sub-Channel Broadcast Connection
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Table Contents 6.10.5 6.11 6.12 6.12.1 6.12.2 6.12.3 6.12.4 6.12.5 6.12.6 6.12.7 6.13 7.3.1 7.3.2 7.3.3
Page
Establish Multipoint Connection Send Messages Release Connections Release 8-bit Connections Release 4-bit Connections Release 2-bit Connections Release 1-bit Connections Release Broadcast Connection Release Sub-Channel Broadcast Connection Release Multipoint Connection Stop Sending Messages
Timing Diagrams Interface Timing Parallel Mode Timing Microprocessor Interface Timing Infineon/Intel Timing De-Multiplexed Mode Infineon/Intel Timing Multiplexed Mode Motorola Microprocessor Timing JTAG Interface Timing Electrical Characteristics Absolute Maximum Ratings Operating Range Crystal Oscillator Characteristics Capacitances Characteristics
Package Outlines
Preliminary Data Sheet
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List Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Page
Logic Symbol Standard Application Configuration Block Diagram Bidirectional Mode SWITI Clock Generator Block Diagram APLL APLL Jitter Transfer Function Interface Configurations Shifting Multiplexed De-multiplexed Mode GPIO Port Configuration Example Frame Signal Example. Order Register Access 8-bit Access Interrupt Structure 16-bit Access Interrupt Structure Initialization Procedure after Reset Example: Input Shifting Example: Output Shifting Example Framing Groups Example: 8-bit Connection Sub-channel Address Time-Slot Example: 4-bit Connection Example: 2-bit Connection Example: 1-bit Connection Example: Broadcast Connection Example: Sub-Channel Broadcast Connection Example: Multipoint Connection Example: Send Message Timing Parallel Mode Timing Infineon/Intel Read Cycle De-Multiplexed Mode Infineon/Intel Write Cycle De-Multiplexed Mode Infineon/Intel Read Cycle Multiplexed Mode Infineon/Intel Write Cycle Multiplexed Mode Motorola Read Cycle Motorola Write Cycle Boundary Scan Timing. External Crystal Wave Form AC-Test Outlines P-MQFP-100-2
Preliminary Data Sheet
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List Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
Page should read what? SWITI Family Tree Local Interface GPIO Clock Pins JTAG Interface. Microprocessor Interface Power Supply Pins. Controller Instructions Boundary Scan IDCODE IDCODE Read Access Register Overview 8-Bit Interface Value Range SPA/DPA Value Range ITSA/OTSA Value Range SCA. Register Overview 16-Bit Interface Affected Registers Connection Commands Affected Registers Configuration Commands. Connection Command Parameter Codes Configuration Command Parameter Codes. Configuration Command Parameter Code. Timing Parallel Mode Timing Infineon/Intel Timing De-Multiplexed Mode Infineon/Intel Timing Multiplexed Mode Motorola Timing JTAG Interface Timing Absolute Maximum Ratings Operating Range External Capacitances Crystal (Recommendation) Characteristics Input/Output Capacitances
Preliminary Data Sheet
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PRELIMINARY
Preface
Switching (SWITI) family switching devices wide area telecommunication data communication applications. This document provides complete reference information according chip interfaces, programming, internal architecture applications. Organization this Document This Preliminary Data Sheet divided into chapters. organized follows: Chapter Overview Gives general description product family, lists features, presents some typical applications. Chapter Description Lists locations with associated signals, categorizes signals according function, describes signals. Chapter Description Interfaces Rough overview internal architecture clock fallback feature. Chapter Description Interfaces Short introduction used interfaces. Chapter Register Description Gives information about registers accessible microprocessor interface according address, short name, access, reset value value range. Chapter Programming Device Gives variety examples programm device, lists available command parameter values. Chapter Timing Diagrams Contains timing diagrams. Chapter Electrical Characteristics Specification electrical parameters. Chapter Package Outlines Outlines available packages (P-MQFP-100-2).
Preliminary Data Sheet
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PRELIMINARY
Table Programmer
should read what? Relevant Chapters
Addressed Person Board Designer
Preliminary Data Sheet
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PRELIMINARY Overview
Overview
switching family, called SWITI, provides complete cost-effective solution switching systems. family divided sub-families, MTSI family HTSI family. Preliminary Data Sheet describes functionality characteristic MTSI devices. devices used today's switching applications, e.g. conventional PBXs central offices, well H.100/H.110 applications (only HTSI family), which high performing CTI- Voice-over-IP-applications, most important future technologies telecommunications. main requirements today's switching applications following features: Constant delay e.g. support wide band data switching, channel bundling switching/subchannel switching support applications such mobile base stations, DECT, computer telephony addition, SWITI family provides features ensure broad range configurations make possible adapt device switching applications: compliant H.100/H.110 interface (HTSI) 8-channel stream-to-stream switching capability (HTSI) Message mode, which allows assign preset value output time-slot GPIO (General Purpose I/O) port, which controlled from external
SWITI family. SWITI family consists with different switching capacities. possible configurations shown Table HTSI versions provide additional H.100 H.110 interface, while MTSIs standard switching devices. devices programmed easily, thus helping designer/programmer integrate device into application comfortably. Table Name HTSI-XL (H-Mode) HTSI-XL (M-Mode) HTSI-L (H-Mode) HTSI-L (M-Mode) P-BGA-217-1 SWITI Family Tree Package P-BGA-217-1 Ordering Number 24471 HTSI-XL 24471 HTSI-XL 20471 HTSI-L 20471 HTSI-L 1024 Connec- Local-Bus tions IN/OUT 2048 16/16 32/32 16/16 32/32 H-Bus
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PRELIMINARY Table Name HTSI (H-Mode) HTSI (M-Mode) MTSI-XL MTSI-L MTSI SWITI Family Tree (cont'd) Package P-BGA-217-1 Ordering Number 20451 HTSI 20451 HTSI P-MQFP-100-2 24470 MTSI-XL P-MQFP-100-2 20470 MTSI-L P-MQFP-100-2 20450 MTSI 2048 1024 Connec- Local-Bus tions IN/OUT 16/16 32/32 16/16 16/16 16/16 H-Bus Overview
Preliminary Data Sheet
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PRELIMINARY
Switching SWITI
20450 20470 24470
Version
CMOS
General
Overview Features
Switching capacity 512, 1024, 2048 connections different types between different buses Programmable data rates 2.048 Mbit/s, P-MQFP-100-2 4.096 Mbit/s, 8.192 Mbit/s, 16.384 Mbit/s stream basis Highways (IN/OUT) Constant delay minimum delay programmable connection basis Sub-channel switching ability 1-bit, 2-bit, 4-bit wide time-slots Programmable clock shift local Automatic data rate adaption Optional 8-bit parallel input and/or 8-bit parallel output first lines local Broadcast capabilities Multipoint switching ability Read write access time-slots Message mode (time-slot write access) Programmable framing group GPIO port 8-bit µP-interface supports both Intel Motorola mode Optional 16-bit interface mode (instead GPIO port) chip clock operation (master/slave) JTAG interface Boundary scan according IEEE 1149.1 power supply tolerant inputs/outputs
Type 20450 20470 24470
Preliminary Data Sheet
Package P-MQFP-100-2
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PRELIMINARY Overview
Features Detail
Flexible Data Rates Each input each output line local programmable operate different data rates. possible data rates 2.048 Mbit/s, 4.096 Mbit/s, 8.192 Mbit/s, 16.384 Mbit/s. Constant Minimum Delay Each connection independent addressed buses determined constant delay minimum delay connection. Constant delay means that input timeslot sub-channel available programmed output after frames. Minimum delay means that time-slot sub-channel appears output soon possible. minimum delay depends chosen connections possible range between frames. Sub-Channel Switching Each connection 1-bit, 2-bit, 4-bit, 8-bit connection. Sub-Channel switching constant delay frames. Programmable Clock Shift position time-slot each local input line programmed within time-slot before after rising edge half clock steps. Also position time-slot local output lines programmed within first time-slot after rising edge. Automatic Data Rate Adaption Connections also possible between lines operating different data rates. programmer just specifies input output line, time-slot, necessary, subchannel. Parallel Mode first local input output lines configured parallel input output port respectively. serial mode time-slot determined consecutive data clock cycles according each line. parallel mode time-slot determined data clock cycle according first lines. Broadcast With this feature possible distribute incoming time-slot different output timeslots.
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PRELIMINARY Multipoint Multipoint connections seen opposite broadcast connections. Here possible generate output time-slot consisting several input time-slots. specified input time-slots logically connected (selectable) have constant delay frames. Read Access programmer access input time-slot. After issuing appropriate command arrival time-slot will reported interrupt. value read from dedicated register. every read request command issued again. Message Mode (Write Access) This feature allows constant value sent given output time-slot. Framing Group possible specify different framing signals kHz. position rising edge pulse width programmed each signal. reference frame determined signal. pulse parameters programmed half step resolution according 16.384 clock. General Purpose Clocks GPCLK lines configured individual clock outputs with kHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 test purposes with internal frequency input frequency analog (APLL). GPIO Port Each line general purpose input/output port configured either input output. According input edge causes interrupt. outputs influenced write access microprocessor interface. Thus user possibility observe influence additional signals application. Microprocessor Interface devices provide standard 8-bit microprocessor interface operating either Intel Motorola mode. Optionally possible configure GPIO port additional data lines provide 16-bit microprocessor interface. 16-bit interface reduces number write cycles required configure connection from case 8-bit interface) write cycles. Overview
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PRELIMINARY Input/Output Tolerance MTSI used environment. Inputs outputs tolerant. outputs have level driving capability. Overview
Logic Symbol
MTSI pure switch provides input lines output lines.
IN[15:0]
UT[15:0]
TRST
20450/20470/24470
eneral Purpose Clocks
isc.
[7:0]
A[4:0]
IREQ
RESET
DE16
iti_035.em
Figure
Logic Symbol
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PRELIMINARY Overview
Standard Application
MTSI HTSI M-Mode used, just MTSC MTSL, standard private branch exchange central office applications (Figure e.g. switching network.
Line Unit EPIC/ DELIC Switching Network MTSI/ HTSI
SLMD Subscriber Line Modul Digital EPIC/ DELIC MTSI/ HTSI HDLC
Coordination Processor
switi_014.emf
Figure
Standard Application
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PRELIMINARY Description
Description
description gives overview numbers, names, direction, position function ordered different interfaces. Note: unused input pins should connected avoid leakage current.
Diagrams
P-MQFP-100-2
IN10 IN11 IN12 IN13 IN14 IN15
GPCLK0 GPCLK1 GPCLK2 GPCLK3 GPCLK4 GPCLK5 GPCLK6 GPCLK7 VDDA VSSA ECLKO ECLKI Reserved NTWK_1 NTWK_2 IREQ/IREQ Reset Mode16 TRST
MTSI
OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7
View
switi_047.emf
Figure
Configuration
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Preliminary Data Sheet
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PRELIMINARY Description
2.2.1
Table
100-97, 94-83 31-37, 40-48
Definitions Functions Local Interface (PCM)
Local Interface
Symbol IN[15:0]1) OUT[15:0]2) Function Frame Synchronization Clock Reset Behavior High
Data Clock 2.048 Mbit/s, 4.096 Mbit/s, 8.192 Mbit/ High 16.384 Mbit/s Receive Data Port Transmit Data Port High
IN15, IN14, IN13. OUT15, OUT14, OUT13.
2.2.2
Table
28-21
General Purpose Port
GPIO
Symbol GPIO[7:0]1) Function General Purpose port (only 8-bit interface used) Reset Behavior Input
D[15:8]
Upper 16-bit interface
GPIO7, GPIO6, GPIO5.
2.2.3
Table
73-80
Clock Signals
Clock Pins
Symbol ECLKI ECLKO
Function External Crystal Input 16.384 MHz, 32.768 External Oscillator Input 16.384 MHz, 32.768 External Crystal Output 16.384 MHz, 32.768 General Purpose Clock Output (Framing Signals)
Reset Behavior
Output Output
GPCLK[7:0]
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PRELIMINARY Table
Description
Clock Pins (cont'd)
Symbol NTWK_1 Function Primary Network Timing Reference Input Optionally synchronized this input which kHz, kHz, 1.536 MHz, 1.544 MHz, 2.048 Secondary Network Timing Reference Input Optionally synchronized this input which kHz, kHz, 1.536 MHz, 1.544 MHz, 2.048 Reset Behavior
NTWK_2
GPCLK7, GPCLK6, GPCLK5.
2.2.4
Table
JTAG Interface
JTAG Interface
Symbol Function Test Clock Single rate test data clock. Test Mode Select transition this required step through controller state machine. Test Reset Resets controller state machine (asynchronous reset). Test Data appropriate controller state test data instruction shifted this line. Test Data Input appropriate controller state test data instruction shifted this line. High Reset Behavior
TRST
2.2.5
Table
Microprocessor Interface
Microprocessor Interface
Symbol Function Chip Select Active low. "low" this line selects registers read/ write operations. Read (Intel/Infineon Mode) Indicates read access. Data Strobe (Motorola Mode) During read cycle, indicates that device should place valid data bus. During write access, indicates that valid data bus. Reset Behavior
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PRELIMINARY Table
Description
Microprocessor Interface (cont'd)
Symbol Function Write (Intel/Infineon Mode) Indicates write access. Read/Write (Motorola Mode) Indicates direction data transfer bus. Address Latch Enable Controls on-chip address latch multiplexed mode. While 'high', latch transparent. falling edge latches current address. also evaluated determine mode (ALE 'low' Motorola, 'high' Intel/Infineon) Microprocessor 8/16-Bit Interface Selection ('low' bit, 'high' bit) Interrupt Request This programmable push/pull (active high low) open-drain. This signal activated when SWITI requests interrupt. When operated open drain mode, multiple interrupt sources connected. Address When operated address/data multiplex mode, address pins externally connected bus. Data System Reset SWITI forced into reset state. Input High Reset Behavior
MODE16 IREQ/ IREQ
10-6
A[4:0]1)
20-17, 14-11
D[7:0]2) RESET
2.2.6
Table
Power Supply
Power Supply Pins
Symbol VDDA VSSA Function Power Supply Digital Ground Power Supply Analog Logic Used Analog Ground Reserved. Must connected ground
1,15, 29,39, 50,59, 65,81, 2,16, 30,38, 49,58, 64,82,
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PRELIMINARY Architectural Description
Architectural Description
following sections give short overview functionality SWITI.
Functional Block Diagram
Programming
GPIOs
JTAG
µP-Interface
Clocks
Switching Factory
Constant Delay Channel
Line,
Line,
Control
Input Handler
Input Data Memory
Control
Output Handler
Control
Output Data Memory
Minimum Delay
Block Automatic Data Rate Adaption
Local
iti_ 8.em
Local I/Os
Figure
Block Diagram
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PRELIMINARY Architectural Description
Overview Functional Blocks
Switching Factory switching factory responsible transferring handling incoming data streams assigned output channels time-slots. block includes 512, 1024, 2048 byte input output data memory well input output connection memory. Local-Bus Block block designed handle conversion data provided switching block external local (PCM) interface. performs timing, data rate selection tristate control. Microprocessor Interface Block standard 8-bit multiplexed de-multiplexed interface provided, compatible Intel/Infineon Tech. (e.g. 80386EX, C166) Motorola (e.g. 68040, 68340, 68360, 801) systems. GPIO port needed used provide 16-bit interface. GPIO Block This block supports external port lines each configurable input output. change input line cause interrupt masked). user access port configuration information appropriate registers interface. Clock Block generates frequencies supporting local (PCM). internal phaselocked loop (PLL) generates frequencies synchronized selected reference signal. output frequency tolerance equal input frequency tolerance. operates from 16.384 MHz, 32.768 external crystal, oscillator.
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PRELIMINARY Architectural Description
Switching Factory
shown Figure switching factory comprises input/output data memory input/output data handler with programmed connections. controller handles lines operating same different data rate. establish connection user must only program source line with time-slot destination line with time-slot. internal controller (data handler) writes connection connection descriptor list stores this list connection data handler. programming procedure described Chapter incoming time-slot will stored input data memory controlled input handler. output handler controls constant, minimum delay sub-channel switching.
3.3.1
Switching Modes
SWITI family supports various number switching modes. modes described following chapters.
3.3.1.1
Minimum Constant Delay
Each connection independent addressed buses determined constant delay minimum delay connection. Constant delay means that input timeslot sub-channel available programmed output after frames. Minimum delay means that time-slot sub-channel appears output soon possible. minimum delay depends chosen connections possible range between frames. application note which describes possible connection minimum delays available.
3.3.1.2
Sub-Channel Switching
Sub-Channel switching constant delay frames. Every connection 1-bit, 2-bit, 4-bit, normal 8-bit connection. possible combine every kind subchannel connection, e.g. 1-bit time-slots with 4-bit time-slot output timeslot. Please refer Chapter 6.10.2 detailed description about programming.
3.3.1.3
Multipoint Switching
described overview multipoint-switching allows switch several input timeslots output time-slot. input data logical connected. This mode selectable with multipoint connection command. setup (logical last connection determines other previous programmed multipoint connections. Multipoint switching always constant delay. Subchannel switching supported.
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PRELIMINARY Architectural Description
3.3.1.4
Broadcast Switching
Broadcast switching allows distribute incoming time-slot different output timeslots. input output mechanism same normal constant delay connection mode with sub-channel switching. Minimum delay also supported without sub-channel switching. table with possible connections minimum delays will provided. broadcast connection programmed same normal connection. output time-slots released with disconnect part broadcast command. last connection must released with normal disconnect command. Sub-Channel Broadcast possible program input time-slot broadcast sub-channel connections. That means bits from input time-slot used several broadcast connections related more output time-slots. output time-slots must released with disconnect part broadcast command. last sub-channel connection must released with normal disconnect command. (Please refer Chapter 6.10.4 example)
3.3.1.5
Bidirectional Switching
Bidirectional switching allows install very easily symmetrical bidirectional connection (Figure 5).The input output mechanism same normal constant delay minimum delay connection. time program bidirectional connection twice time program normal connection since internal state machine calculate belonging connection. There special command program bidirectional connection. bidirectional connection only programmed available time-slot input/output line.
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PRELIMINARY Architectural Description
Port Local
inim delay
Port
Port Local
Port
Issued
Internal ITSA
Port
Figure
Bidirectional Mode
3.3.2
Parallel Mode Local (PCM)
parallel mode with 'set parallel mode' command configuration command register. This command first input lines first output lines local parallel bus. parallel mode enabled included lines will 2.048 Mbit/s automatically. parallel mode disabled lines will keep data rate 2.048 Mbit/s until data rate will programmed selected line. internal S/P-converter bypassed. data stream time-slot distributed data lines, every line. least significant assigned line most significant assigned line program connection line must used this special parallel data port. shift value must only programmed port this value will assigned other ports automatically. initialize sequence described Chapter
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PRELIMINARY Architectural Description
switching data handling same data handling constant delay minimum delay mode. timing diagram provided timing diagram chapter (See "PCM Parallel Mode Timing" page 96.).
3.3.3
Switching Block Error Handling
normal procedure establish connection explained Chapter program connection specific time-slot data line release connection program connection. SWITI switching concept provides internal error handling detect errors switching chain caused programming error. programming error occur because noises data lines, software errors, etc. programming error defined follows: existing connection (minimum, constant delay, message) will released. existing minimum delay connection will established. programming error connection memory overflow detected interrupt IESTA2 register will set. this case last connection which been tried establish release valid. operation switching device affected will continued with restrictions. debug purposes SWITI capability write content complete connection memory data memory microprocessor interface. This procedure described Chapter 3.3.4. recommended track established connections with specific customer application software. debug purpose useful compare contents switching memory with virtual connections application software.
3.3.4
Analyze Connection Data Memory
With special command "memory dump enable" connection command register (CCMD) possible read complete memory defined sequence from register with 8-bit access. This feature used only analyze purposes. command disables complete switching function data lines high impedance. command after specific recovery time (200 connection chain data memory read sequentially access register. internal controller writes next 8-bit memory data register read access finished. That means there specific recovery time next read access. internal memory dump controller reads present memory contents input chain memory, data memory output chain memory. During memory dump internal state machine will loose synchronization with external frame structure. Therefore software reset must issued device must programmed again, except clock configuration.
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PRELIMINARY Architectural Description
Infineon Technologies provides software driver recalculate chain recover current connections.
3.4.1
Clock Generator General Overview
following figure gives overview about clock generator with integrated PLL.
MTSI
ECLKI ECLKO
Reset
8.192MHz 2.048MHz 4.096MHz 16.384M
Master/Slave
2,4,8,16
Reset norm. Operation 49.152 APLL Bypass 16.384/32.768 DPLL APLL phase alignm Main
Bypass 2.048MHz
Program mable PCLK[7:0] 16.384M from int. Frequency Input APLL
Ref. clock
FRAM
GPCLK[7:0]
058.em
Figure
SWITI Clock Generator
SWITI clock generator provides necessary clock signals MTSI local (PCM) interface. Since device clock master capable device there digital which locked different network reference signals 2.048 MHz). digital synchronizes external crystal oscillator selected reference clock. digital (DPLL) will bypassed selected reference signal 2.048 MHz. input signal analog (APLL) 2.048 normal operation mode. APLL used multiplying 2.048 clock into 49.152 clock generate clock signals PCM, general purpose clock signals.
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PRELIMINARY Architectural Description
SWITI on-chip oscillator which allows user connect external 16.384 32.768 crystal. Instead using crystal possible assign 16.384 MHz, 32.768 oscillator ECLKI pin. After power-on hardware reset APLL bypassed. APLL will synchronized (after approximately external crystal external oscillator command 'set external frequency' set. This command must used otherwise internal working frequency equal external input frequency SWITI will work properly. APLL locked status 'APLL' ISTA1 register will set. Note: After reset necessary program correct crystal oscillator value first programming step. Otherwise operation frequency SWITI correct.
3.4.2
Features
Analog (APLL)
cycle-to-cycle jitter Natural frequency Damping factor Input Frequency 2.048 case Output Frequency 49.152 MHz, duty-cycle Rule behavior change output frequency range ±10% response changes input frequency phase slope output frequency equal phase slope input frequency Note: necessary provide "noise free" analog power (VDDA/VSSA) reduce internal jitter APLL. These pins must decoupled from digital power (VDD/VSS).
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3.4.2.1
Functional Description
iref fref
frequency detector
up/down
UP/DOWN Counter
igrob
current reference
ibias ibias
fref
phase/ frequency detector
incr decr
Charge pump
VTOI
iint
fosc
iprop
n-divider
locked
Timer
Figure
Block Diagram APLL
value output frequency depends programming n-divider. chosen output frequency SWITI 49.152 input frequency 2.048 MHz. macro consists digital analog which working together. During start-up only digital enabled makes coarse adjustment, that technology dependency circuit compensated. Afterwards digital disabled again analog switched normal operation. digital first order consists frequency detector (FD), up/down counter, digital-to-analog converter (DAC) current controlled oscillator (CCO). detects frequency difference between reference clock (fref: input clock 2.048 MHz) divided oscillator clock. output signal controls counter. reference frequency higher than divided oscillator frequency counter increased. counter output drives current steering which controls input current internal oscillator. current rises output frequency increases until both frequencies equal.
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PRELIMINARY Architectural Description
digital enabled after reset power disabled after (lock time PLL). counter keeps value output current irough constant until digital reseted. second order analog consists phase/frequency detector (PFD), charge pump (CP), loop filter CCO. which sensitive rising edge detects phase frequency difference between input clock (fref) divided output clock (feedback) generates control signal proportional phase difference. output signals down cause charge pump modulate amount charge pass filter (VTOI) integral part (iint) feed current into proportional part (iprop). With these currents output irough controlled. feedback leading fref, oscillator fast. down signal activated subtracts some current iprop. When fref phase with feedback will hold control current that level phase lock will achieved. Thus through this negative feedback arrangement, causes feedback fref signals equal with minimum phase offset. analog becomes unstable, signal pllko generated which resets digital PLL.
3.4.2.2
Jittertransferfunction
Jitter transfers jitter attenuation refers magnitude jitter output device given amount jitter input device. Input jitter applied various amplitudes frequencies, output jitter measured with various filters depending applicable standards. Figure shows jitter transfer function SWITI device. cutoff frequency integrated pass filter kHz.
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PRELIMINARY Architectural Description
20lg |H(f)|
f/fg
Figure
APLL Jitter Transfer Function
3.4.3
Phase Alignment
phase alignment function enabled output signal main divider edge synchronized with clock input. selected reference signal less than 2.048 edge synchronization resolution depends selected external crystal/oscillator frequency. phase alignment function disabled output frequency (49.152 MHz) edge synchronized with input frequency main divider output frequencies edge synchronized with output frequency. Note: phase alignment should disabled reference frequencies 2.048 MHz.
3.4.4
Synchronization
reference source selected from primary reference master source (PFS, PDC, NTWK_1/_2). selected reference signal less than 2.048 main digital used synchronize analog PLL. digital sourced from
Preliminary Data Sheet
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PRELIMINARY Architectural Description
external oscillator, crystal. this case analog output frequency tolerance equal external oscillator/crystal frequency tolerance. Furthermore analog sourced directly from external oscillator, crystal, from input. generated output frequencies will have same tolerance selected input frequency.
Loops
loop command configuration command register CMD2 provides support automatic PCM-PCM loops. input lines connected with corresponding output line. After loop disable command lines will high-impedance after approximately frames.
Read SWITI Configuration with Indirect Register Addressing
Since SWITI configuration programmed with defined instructions CMD1 CMD2 registers possible read current configuration through indirect access registers. indirect addressing started writing five read configuration commands CMD2 register. five commands separated groups, internal configuration external line configuration. internal configuration, e.g. clock generator, IREQ read with command "Read Configuration". internal settings decoded with instruction bits I3.0. data rate interface read with "Read Local (PCM) Line Configuration" command. "Read GPCLK Configuration" "Read Bit/Clock Shift Configuration" must issued GPCLK line configuration shift value. registers contain required information after internal read process complete. recovery time read correct configuration data from register allowed command "Read Time Slot Value" before register been read.
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3.7.1
Power-On Reset Behavior Hardware Reset
There independent active reset pins: RESET TRST. RESET activated, immediately sets outputs ports into tri-state, except ECLKO pin. After reset process correct external frequency must with command 'Set external frequency' accordingly. This command starts configuration process APLL. APLL locked after During this period APLL bypassed internal frequency 2.048 MHz. APLL locked internal frequency will 49.152 MHz. Individual output sections must enabled setting command configuration command register CMD1, CMD2. Internally state machines, counters registers cleared their defined reset value. RESET doesn't control boundary scan register TAP-controller. TRST asserted TAP-controller will into Test-Logic-Reset state outputs pins will tri-stated, except ECLKO pin.
3.7.2
Software Reset
software reset accomplished setting 'Set Software Reset' command CMD2 register. software reset clears complete device except clocking unit temporary microprocessor registers (e.g. CMD1). software reset deactivated with 'Set Software Reset' command. During software reset microprocessor interface doesn't accept other commands.
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Description Interfaces
Local Interface (PCM)
local interface consisting input output data lines (IN, OUT), data clock frame synchronization signal PFS.
Clock Slave
switi_037.emf
Clock Master
Figure
Interface Configurations
Frame Sync signal delimiting frame. This input signal used SWITI determine start frame. frame divided into 8-bit wide time slots. amount time slots within frame depends selected data rate which 2.048 Mbit/s, 4.096 Mbit/s, 8.192 Mbit/s, 16.384 Mbit/s. input Schmitt-Trigger characteristic. Data Clock input supplies SWITI with data clock. operated with 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 data rate clock depending selected highest data mode. clock signal must equal higher highest data rate. input Schmitt-Trigger characteristic. clock slave must receive whereas clock master drives these signals. enable disable signals clock master command 'PCM Clock Input/ Output Selection' must issued. time slots transmitted received input output lines (IN[15:0], OUT[15:0]). input lines have Schmitt-Trigger characteristic. output lines have tristate outputs with push-pull characteristic. every time slot participating connection output high impedance. With special command "Local (PCM) Standby" CMD2 register possible lines high impedance state during normal operation mode. lines high impedance state after reset process must enabled with "Local (PCM) Standby" command. lines which participating switching operation high impedance state time-slot information input lines discarded automatically.
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PRELIMINARY Description Interfaces
Data Rate Selected Line Input ffset Input ffset
utputs ffset
iti_039.em
Figure
Shifting
each input line offset time-slot zero adjusted range from half clock resolution before after rising edge. output lines offset time-slot zero adjusted range from half clock resolution after rising edge. resolution depends selected data rate that means resolution doesn't depend signal. After reset process shift disabled lines. That means time-slot starts with rising edge PFS. input data will sampled with falling edge selected data rate output data valid with rising edge selected data rate.
Data Rate
MTSI provides programming different data rates data lines. local lines operate with 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz.
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Microprocessor Interface
standard 8-bit multiplexed non-multiplexed interface provided. compatible Intel/Siemens (e.g. 80386EX, C166) Motorola (e.g. 68040, 68340, 68360, 801) systems. GPIO port needed used provide 16-bit interface. 16-bit mode determined according MODE16 input pin. MODE16 8-bit interface MODE16 16-bit interface This chapter describes configure interface each mode.
4.3.1
Intel/Siemens Motorola Mode
Intel/Siemens Motorola mode interface configured during hardware reset process conjunction with pin. permanently driven 'low' Motorola mode permanently driven 'high' Intel/Siemens mode Edge Intel/Siemens multiplexed mode falling rising edge during normal operation selects multiplexed mode immediately. With hardware reset tied possible return Motorola Intel/Siemens mode.
4.3.2
De-multiplexed Multiplexed Mode
both modes, A-bus D-bus used parallel. A-bus should connected LSBs AD-bus, coming from also multiplexed mode. next figure describes connection address data buses different modes. Note: Motorola mode used only with de-multiplexed bus. Intel/Siemens mode used with both, multiplexed de-multiplexed bus.
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Multiplexed Mode
8/16
SWITI
LATCH
De-multiplexed Mode
8/16
SWITI
LATCH
Figure
Multiplexed De-multiplexed Mode
Note: both modes only LSBs A-bus AD/bus connected Address inputs.
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PRELIMINARY Description Interfaces
General Purpose Port (GPIO)
This port consists lines each configurable input output. change input line cause interrupt masked). user access port configuration information appropriate registers interface. Figure shows example.
Signal GPIO
1->0
GPIO Direction Register
Line outputs Line inputs Changes line line cause interrupts Drive 1010 lines [7:4] Contains current value input lines Change input line detected
switi_055.emf
GPIO Mask Register
GPIO Output Register
GPIO Input Register
GPIO Interrupt Register
don't care
Figure
GPIO Port Configuration Example
General Purpose Clocks
SWITI provides general purpose clock lines. With independent commands CMD2 register lines configured frame group signals individual clock signals. last written command line valid controls multiplexer.
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4.5.1
Frame Group Outputs
output lines possible provide different framing signals which used synchronization purpose. signals have period Their offset programmed individually within determined frame resolution 16.384 MHz). default start point offset beginning frame (rising edge clock signal). start point offset shifted half clock cycle, that means second start point determined with rising edge next falling edge clock signal shown Figure 13). high time signal also programmed steps frame signals controlled high active.
125µs
16.384 Mbit/s
125µs
Frame Signal
switi_038.emf
Figure
Frame Signal Example
Figure shows example frame signal beginning with rising edge 64th clock cycle with length clock cycles. Further programming examples found Chapter 6.8.1.
4.5.2
GPCLK Clock Outputs
GPCLK lines configured individual clock outputs with kHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 test purposes with internal frequency input frequency analog (APLL). clock signals generated from analog output frequency which internal frequency. quality output frequency signals depends quality selected input frequency.
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PRELIMINARY Description Interfaces
JTAG (Boundary Scan)
SWITI provides fully IEEE 1149.1 compatible boundary scan support consisting complete boundary scan chain Test Access Port controller (TAP controller) five dedicated pins: TCK, TMS, TDI, TRST asynchronously reset controller 32-bit IDCODE register
4.6.1
Boundary Scan
pins except power supply crystal included boundary scan. Depending functionality (input), (output, enable) three (input, output, enable) boundary scan cells provided. maximum clock rate MHz.
4.6.2
Test-Access-Port (TAP)
following signal pins allow boundary scan test logic accessed: Test Clock input which central test clock applied. This test clock independent system clock. Clock phases derived from this clock test sequence control. Test Mode Select control input which desired status changes controller applying certain level (0/1) caused rising edge TCK. Test Data Input whose data inserted into test logic with rising edge TCK. Test Data Output with tristate capability which only active during SHIFT-IR SHIFT-DR controller state, whose data driven with falling edge TCK.
4.6.3
Controller
Test Access Port (TAP) controller implements state machine defined JTAG standard IEEE 1149.1.
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Transitions cause controller perform state change. possible instructions listed following table. Table Code 0000 0110 0101 0001 0111 0100 1111 Controller Instructions Instruction EXTEST INTEST IDCODE CLAMP HIGHZ BYPASS Function External testing Internal testing Reading code Reading outputs High impedance state boundary scan outputs Bypass operation
SAMPLE/PRELOAD Snap-shot testing
instruction length four bit. EXTEST used verify board interconnections. When controller state "update DR", output pins updated with falling edge TCK. When entered state "capture levels input pins latched with rising edge TCK. in/out shifting scan vectors typically done using instruction SAMPLE/PRELOAD. INTEST supports internal chip testing. When controller state "update DR", inputs updated internally with falling edge TCK. When entered state "capture levels outputs latched with rising edge TCK. in/out shifting scan vectors typically done using instruction SAMPLE/PRELOAD. SAMPLE/PRELOAD SAMPLE/PRELOAD instruction enables signal pins (inputs outputs) sampled during operation (SAMPLE) result shifted through shift register. function internal logic influenced this instruction. While shifting out, cells serially loaded same time with defined values through (PRELOAD). SAMPLE/PRELOAD instruction selects boundary scan register normal mode. state CAPTURE-DR data loaded into boundary scan register with rising edge TCK. state UPDATE-DR contents boundary scan register written into second register stage boundary scan register. This data become effective outputs only instruction been activated that sets register test mode: e.g. EXTEST CLAMP.
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PRELIMINARY IDCODE 32-bit identification register serially read TDO. contains version number bits), device code bits) manufacturer code bits). fixed '1'. Version xxxx Device Code xxxx xxxx xxxx xxxx Manufacturer Code xxxx xxxx xxxx Output Description Interfaces
Table MTSI MTSI-L MTSI-XL CLAMP
Boundary Scan IDCODE Version 0001 0001 0001 Device Code Manufacture Code Bit0 0001 1010 0000 1000 0001 1010 0000 1000 0001 1010 0000 1000
register test mode. duration CLAMP instruction, BYPASS register selected that minimal shift path created. During SHIFT-DR data shifted through BYPASS register. contents register does change during UPDATE-DR state. HIGHZ HIGHZ instruction disables outputs switched high impedance state. outputs switched high impedance state UPDATE-IR. outputs redefined according next instruction another instruction become active with UPDATE-IR. selected test data register BYPASS register. BYPASS entering shifted after clock cycle, e.g. skip testing selected printed circuit board.
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Identification Code Read Access
SWITI offers possibilities read identification code. JTAG port described Chapter processor interface After hardware reset identification code stored General Purpose Interrupt Register (GPI) read processor interface. high nibble version number nibble equal nibble device code shown Table 8-bit interface configuration first write access General Purpose Mask Register (GPM) will reset register 00H. interface configured 16-bit interface IDCODE always read from register, that means register will reset. IDCODE read access shown Table Table IDCODE Read Access 8-Bit IDCODE (MSB.LSB) Version MTSI MTSI-L MTSI-XL 0001 0001 0001 Device Code 1001 1010 1011
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Register Description
register description gives information about registers accessible microprocessor interface according address, short name, access, reset value value range.
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PRELIMINARY Register Description
Table Name ITSA OTSA CCMD CMD1 CMD2 ISTA1
Register Overview 8-Bit Interface
Register Overview 8-Bit Interface Access 8-bit Reset Address Value RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR Comment Source Port Address Register Value range Table Input Time Slot Address Register Value range Table Destination Port Address Register Value range Table Output Time Slot Address Register Value range Table Sub-Channel Address Register Value range Table General Input Register General Input Register Connection Command Register Configuration Command Register Configuration Command Register Message Value Register Interrupt Status Register Interrupt Error Status Register Interrupt Error Status Register Interrupt Mask Register Interrupt Error Mask Register Interrupt Error Mask Register General Purpose Port Input Register General Purpose Port Output Register General Purpose Direction Register General Purpose Mask Register Time Slot Value Register Configuration Register Page
IESTA1 IESTA2 INTM1 RD/WR INTEM1 RD/WR INTEM2 RD/WR GPPI GPPO RD/WR RD/WR
IDCODE General Purpose Interrupt Register
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PRELIMINARY Table Value Range SPA/DPA Value Range Bit3.0 15.0 Register Description
Addressed Lines Local-Bus input lines
Table Data Rate 2.048 Mbit/s 4.096 Mbit/s 8.192 Mbit/s
Value Range ITSA/OTSA Range Bit7.0 31.0 63.0 127.0
16.384 Mbit/s 255.0
Table Mode
Value Range Range
1-bit switching ISCA0.2; OSCA0.2 2-bit switching ISCA0.1; OSCA0.1 4-bit switching ISCA0; OSCA0
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Detailed Register Description 8-bit Interface
RD/WR Address:
Source Port Address Register Reset value:
BIT7.4 Must PA3.0 Port Address
Input Time Slot Address Register Reset value: ITSA TSA7 TSA6 TSA5
RD/WR
Address:
TSA3
TSA2
TSA1
TSA0
TSA4
TSA7.0 Time Slot Address
Destination Port Address Register Reset value:
RD/WR
Address:
BIT7.4 Must PA3.0 Port Address
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PRELIMINARY Output Time Slot Address Register Reset value: OTSA TSA7 TSA6 TSA5 TSA4 TSA3 TSA2 TSA1 TSA0 RD/WR Register Description Address:
TSA7.0 Time Slot Address
Sub-Channel Address Register Reset value:
RD/WR
Address:
OSCA2 OSCA1 OSCA0 ISCA2 ISCA1 ISCA0
OSCA2.0 Output Sub-Channel Address ISCA2.0 Input Sub-Channel Address
General Input Register Reset value:
RD/WR
Address:
GV7.0 General Value
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PRELIMINARY Register Description
case Reference Selection Command (CMD1) content this register interpreted follows: GV2.0 Clock Frequency 1.536 1.544 2.048 4.096 8.192 16.384
case Shift Command (CMD1) content this register interpreted follows: Byte shift value (only input lines) shift applies before rising edge shift applies after rising edge GV3.1 shift value (range: Edge Control (half clock shift) data transmit with rising edge sampled with falling edge data transmit with falling edge sampled with rising edge
case GPCLK Frame Signal Command (CMD2) content this register interpreted follows: GV7.2 Offset within frame number 16.384 clock cycles (lower bits; refer upper part) Edge Control data changes with rising edge sampled with falling edge data changes with falling edge sampled with rising edge used
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PRELIMINARY Register Description
case GPCLK Clock Signal Command (CMD2) content this register interpreted follows: GV2.0 Output Frequency selected line 2.048 4.096 8.192 16.384 Input Analog (2.048 MHz) Internal Frequency (49.152 MHz)
General Input Register Reset value:
RD/WR
Address:
GV7.0 General Value
case GPCLK Frame Signal Command (CMD2) content this register interpreted follows: GV7.5 Width pulse number 16.384 clock cycles from i.e. GV7.5 clock cycle, GV7.5 clock cycles GV4.0 Offset within frame number 16.384 clock cycles (upper bits; refer lower part)
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PRELIMINARY Connection Command Register Reset value: CCMD RD/WR Register Description Address:
CC3.0 Command Code 0000 operation 0001 Constant Delay Connection Command (incl. Broadcast Connection) (SPA, ITSA, DPA, OTSA, considered) I1.0 Sub-Channel Mode 8-bit wide time slots 4-bit wide time slots 2-bit wide time slots 1-bit wide time slots
0010 Minimum Delay Connection Command (incl. Broadcast Connection) (SPA, ITSA, DPA, OTSA considered) 0011 Send Message Command (always Constant Delay) (DPA, OTSA, considered) 0100 Stop Message Command (DPA, OTSA considered) 0101 Disconnect Command (SPA, ITSA, DPA, OTSA, considered) I1.0 I1.0 Constant Delay Connection Command (incl. Broadcast Connection)
0110 Disconnect Part Broadcast Command (SPA, ITSA, DPA, OTSA, considered) I1.0 I1.0 Constant Delay Connection Command (incl. Broadcast Connection)
0111 Multipoint Connect Command (SPA, ITSA, DPA, OTSA considered) Multipoint MODE logical connection logical connection
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PRELIMINARY 1000 Disconnect Command 1001 Bidirectional Connect Command (SPA, ITSA, DPA, OTSA considered) Delay MODE Minimum Delay Constant Delay Register Description
1010 Memory Dump (Connection Data Memory) Memory Dump disable enable
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PRELIMINARY Configuration Command Register Reset value: CMD1 RD/WR Register Description Address:
CC3.0 Command Code 0000 operation 0001 used 0010 Reference Selection Command (GI1 considered frequency) I3.0 Synchronization Information 0000 synchronization internal oscillator (default) 0001 synchronizes 0010 synchronizes 0011 used 0100 used 0101 synchronizes NTWK_1 0110 synchronizes NTWK_2 0011 used 0100 used 0101 used 0110 Clock Input/Output Selection Command (Default: inactive) I2.0 Frequency Information
Preliminary Data Sheet
used enable 2.048 enable 4.096 enable 8.192 enable 16.384 Input Output
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Direction Information
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PRELIMINARY 0111 used 1000 used 1001 used 1010 Phase Alignment I2.0 used Phase Alignment Note: phase alignment must disabled reference frequencies 2.048 disable (default after reset) enable Register Description
1011 Rate Command Local (PCM) (Default lines 2.048 Mbit/s) I1.0 Base Rate Information 1100 used 1101 Read Time Slot Command Destination Information 1110 used 1111 Shift Command (GI1 considered shift value) (Default: Shift inactive) I1.0 Direction Control
Preliminary Data Sheet
2.048 Mbit/s 4.096 Mbit/s 8.192 Mbit/s 16.384 Mbit/s effect rate input lines (SPA considered) effect rate output lines (DPA considered)
Destination Information
Destination Information
read input time slots (SPA, ITSA considered) read output time slots (DPA, OTSA considered)
shift value input line (SPA considered)
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PRELIMINARY shift value input lines shift value output lines shift value lines (input output) Register Description
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PRELIMINARY Configuration Command Register Reset value: CMD2 RD/WR Register Description Address:
CC3.0 Command Code 0000 operation 0001 External Frequency (Must programmed first) External Frequency 32.768 16.384
0010 Parallel Mode first local input lines parallel input lines first local output lines parallel output lines. Parallel Mode I1.0 disable enable
0011 IREQ Command IREQ (Default: IREQ inactive) IREQ active IREQ active high IREQ open-drain
Interrupt Time-Out Counter inactive time between consecutive interrupts disable enable
0100 Standby Command Local (PCM) High Impedance outputs tristated (default) outputs enabled
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PRELIMINARY used must used must Internal Clock Synchronization 0101 Loop Command PCM-PCM Loop disable (default) enable Must clock master mode Must clock slave mode Register Description
0110 GPCLK Frame Signal Command (GI1, considered) (Default: GPCLK's tristated) I2.0 GPCLK Line (7.0) Invert Mode frame signal high active frame signal active
0111 GPCLK Clock Signal Command (GI1 considered frequency) (Default: GPCLK's tristated) I2.0 GPCLK Line (7.0) 1000 Range Data Rate Command avoid loss data this command should issued only once after reset. range data rate changed later loss data must expected four frames. I3.0 Range Select specify range codes have logical combined. 0001 2.048 Mbit/s (default) 0010 4.096 Mbit/s 0100 8.192 Mbit/s 1000 16.384 Mbit/s 1001 Read Configuration I3.0 Select Configuration Command 0000 used 0001 Source
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PRELIMINARY 0010 used 0011 used 0100 0101 Local (PCM) Clock Output Selection 0110 used 0111 used 1000 used 1001 Phase Alignment 1010 External Input Frequency 1011 Parallel Mode 1100 IREQ 1101 Local Standby 1110 Loop 1111 Range Data Rate 1010 Read GPCLK Configuration I2.0 GPCLK Line Destination Information 1100 used 1101 Read Shift Configuration Destination Information 1110 used 1111 Software Reset Software Reset Deactivate Software Reset (default) Activate Software Reset Shift Value Input Line (SPA considered) Shift Value Output Lines Read Data Rate Input Line (SPA considered) Read Data Rate Output Line (DPA considered) 1011 Read Local (PCM) Line Configuration Register Description
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PRELIMINARY Message Value Register Reset value: RD/WR Register Description Address:
MV7.0 Message Value
Interrupt Status Register Reset value: ISTA1 APLL
Address:
GPIO
APLL APLL lock indication locked bypassed locked Error2 Interrupt Change Indication (not active 16-bit mode) change according error2 interrupt status register detected change according error2 interrupt status register detected Error1 Interrupt Change Indication change according error1 interrupt status register detected change according error1 interrupt status register detected GPIO General Purpose Change Indication change according port inputs detected least change according port inputs detected Time Slot Arrived Indication there time slot value register there time slot value register Further Connections Indication establishing connections possible
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PRELIMINARY maximum amount connections reached Ready Indication CCMD ready written CCMD ready written Register Description
Interrupt Error Status Register Reset value: IESTA1
Address:
NTWK_2 Failure Indication NTWK_1 Failure Indication failure detected failure detected
Interrupt Error Status Register Reset value: IESTA2
Address:
Connection Memory Error/Overflow Indication Source Failure Indication failure detected failure detected
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PRELIMINARY Interrupt Mask Register Reset value: INTM1 GPIO RD/WR Register Description Address:
Error2 Interrupt Change Indication Mask (not active 16-bit mode) mask Change Indication Mask Change Indication
Error1 Interrupt Change Indication Mask mask Change Indication Mask Change Indication
GPIO General Purpose Change Indication Mask mask Change Indication Mask Change Indication Time Slot Arrived Indication Mask mask Time Slot Arrived Indication Mask Time Slot Arrived Indication Ready Indication Mask mask Ready Indication Mask Ready Indication Mask Disable interrupt
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PRELIMINARY Interrupt Error Mask Register Reset value: INTEM1 RD/WR Register Description Address:
NTWK_2 Failure Indication Mask NTWK_1 Failure Indication Mask mask this interrupt Mask this interrupt Mask Disable interrupt Interrupt Error Mask Register Reset value: INTEM2 RD/WR Address:
Connection Memory Overflow Indication Mask Source Failure Indication Mask mask this interrupt Mask this interrupt Mask Disable interrupt
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PRELIMINARY General Purpose Port Input Register Reset value: GPPI GPB7 GPB6 GPB5 GPB4 GPB3 GPB2 GPB1 GPB0 Register Description Address:
GPB7.0 General Purpose Bits
General Purpose Port Output Register Reset value: GPPO GPB7 GPB6 GPB5 GPB4 GPB3 GPB2 GPB1
Address:
GPB0
GPB7.0 General Purpose Bits
General Purpose Direction Register Reset value:
RD/WR
Address:
DC7.0 Direction Control line input line output
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PRELIMINARY General Purpose Mask Register Reset value: RD/WR Register Description Address:
IM7.0 GPIO Interrupt Mask (bit line line enable change detection disable change detection
General Purpose Interrupt Register
Address:
Reset value: IDCODE (hardware reset) (software reset) IND7 IND6 IND5 IND4 IND3 IND2 IND1 IND0
IND7.0 GPIO Interrupt Indication (bit line line change detected least change detected this line
Time Slot Value Register Reset value: TSV7 TSV6 TSV5
Address:
TSV3
TSV2
TSV1
TSV0
TSV4
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PRELIMINARY Register Description
Read Time-Slot Value Command content register interpreted TSV7.0 Time-Slot Value
Read Configuration Command content register interpreted Reference Configuration TSV3.0 I3.0 from Reference Selection Command (page TSV6.4 1.536 1.544 2.048 4.096 8.192 16.384
Clock Output Selection TSV3.0 I3.0 from Clock Output Selection Command (page Phase Alignment TSV3 TSV0 TSV0 IREQ TSV2.0 I1.0 from IREQ Command (page Local (PCM) Standby TSV1.0 from Local (PCM) Standby Command (page
Preliminary Data Sheet 2001-01-01
2.048
Phase Alignment Command (page from External Frequency Command (page from Parallel Mode Command (page
External Frequency Parallel Mode
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PRELIMINARY Loop TSV1.0 I1.0 from Loop Command (page Range Data Rate TSV3.0 I3.0 from Range Data Rate Command (page Register Description
Read GPCLK Configuration Command content register interpreted TSV0 TSV3.1 TSV1 GPCLK Line Clock Signal GPCLK Line Frame Signal 2.048 4.096 8.192 16.384 Input Analog Internal Frequency Rising Edge Falling Edge
GPCLK Line Clock Signal
GPCLK Line Frame Signal
TSV7.2 Offset within frame number 16.384 clock cycles (lower bits; refer upper part)
Read Local (PCM) Line Configuration Command content register interpreted TSV1.0 2.048 MBit/s 4.096 MBit/s 8.192 MBit/s 16.384 MBit/s
Preliminary Data Sheet
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PRELIMINARY Register Description
case Read Shift Configuration Command content register interpreted TSV0 Edge Control TSV4 Rising Edge Falling Edge
TSV3.1 Shift Value (Range: Byte Shift Value (only input lines) shift applies byte before rising edge shift applies byte before falling edge
Configuration Register Reset value: CON7 CON6 CON5
Address:
CON3
CON2
CON1
CON0
CON4
Memory Dump Command (CCMD) content register CON7.0 Connection Data Memory
Read GPCLK Configuration Command content register CON7.5 Width pulse number 16.384 clock cycles from i.e. CON7.5 clock cycle, CON7.5 clock cycles CON4.0 Offset within frame number 16.384 clock cycles (upper bits; refer lower part)
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PRELIMINARY Register Description
Table
Register Overview 16-Bit Interface
Register Overview 16-Bit Interface Comment Source Address Register Destination Address Register General Input Register Connection Command Register 16-bit Configuration Command Register This 8-bit register Configuration Command Register This 8-bit register Message Value Register This 8-bit register Interrupt Status Register This 8-bit register Interrupt Error Status Register Interrupt Mask Register This 8-bit register Interrupt Error Mask Register Page
Access Address Reset Name Value CC16 RD/WR RD/WR RD/WR RD/WR 0000H 0000H 0000H 0000H 0000H FF3FH
CMD1 RD/WR CMD2 RD/WR ISTA1 IESTA RD/WR
INTM1 RD/WR INTEM RD/WR TSVC
IDCODE IDCODE Register This 8-bit register XXXXH Time Slot Value Configuration Register
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PRELIMINARY Register Description
Detailed Register Description 16-Bit Interface
RD/WR Address:
Source Address Register Reset value: 0000H TSA7 TSA6 TSA5
TSA4
TSA3
TSA2
TSA1
TSA0
High
Input Time Slot Address Register page Source Port Address Register page
Destination Address Register Reset value: 0000H TSA7 TSA6 TSA5
RD/WR
Address:
TSA4
TSA3
TSA2
TSA1
TSA0
High
Output Time Slot Address Register page Destination Port Address Register page
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PRELIMINARY General Input Register Reset value: 0000H GV15 GV14 GV13 GV12 GV11 GV10 RD/WR Register Description Address:
GV15.0 General Value GV15.8 General Input Register page GV7.0 General Input Register page
Connection Command Register 16-bit RD/WRAddress: Reset value: 0000H CC16 OSCA2 ISCA2
ISCA1
ISCA0
OSCA1 OSCA0
High
Sub-Channel Address Register page Connection Command Register page
Preliminary Data Sheet
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PRELIMINARY Interrupt Error Status Register Reset value: 0000H IESTA Register Description Address:
High Interrupt Error Status Register page Interrupt Error Status Register page
Interrupt Error Mask Register Reset value: FF3FH INTEM
RD/WR
Address:
High Interrupt Error Mask Register page Interrupt Error Mask Register page
Preliminary Data Sheet
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PRELIMINARY IDCODE Register Reset value: IDCODE IDC7 IDC6 IDC5 IDC4 IDC3 IDC2 IDC1 IDC0 Register Description Address:
IDC7.0 IDCODE refer Table "IDCODE Read Access" Page Time Slot Value Configuration RegisterRD Reset value: XXXXH
TSVC15
Address:
TSVC14
TSVC13
TSVC12
TSVC11
TSVC10
TSVC9
TSVC8
TSVC
TSVC7
TSVC6
TSVC5
TSVC4
TSVC3
TSVC2
TSVC1
TSVC0
TSVC15.8 Configuration Connection Data Memory (refer page TSVC7.0 Time Slot Value (refer page
Preliminary Data Sheet
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PRELIMINARY Programming Device
Programming Device
register consists parameter registers (SPA, ITSA, SCA, DPA, OTSA, GI1.), command registers (CCMD, Table Table CMD1, CMD2) status registers (ISTA1, IESTA1, IESTA2). Before issuing command parameter registers have written accordingly. connection command only issued connection command register ready written (see Figure 14). connection command register status shown with ISTA1 register. detailed description read write access command registers found Chapter 6.1.
command register ready?
command register ready?
write parameter registers write command register
write parameter registers write command register
passive waiting with interrupt
active waiting (polling) without interrupt
switi_032.emf
Figure
Order Register Access
Preliminary Data Sheet
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PRELIMINARY Programming Device
Read Write Access
read write access necessary distinguish between connection configuration command. connection command register used establish connection (described Chapter 6.10) configuration registers used configure device, e.g. clock frequency. ISTA1:RDY connection command register ready receive data from interface. parameter register connection command register written will reset from internal controller. connection established internal controller will connection command register ready next write read access. ISTA1:RDY enabled generate interrupt indicate that device ready receive data, otherwise must poll ISTA1:RDY bit. configuration command register works independent from bit. Note: There must recovery time period after every configuration command write access next write access (command parameter register).
Interrupt Handling
SWITI interrupt concept consists four interrupt status register with their corresponding mask register. five interrupt status register divided main register, group including error interrupt register, general purpose interrupt register time slot value register. Every register main register indicate interrupt assigned error general purpose register indicate value time slot value register. interrupt status register read microprocessor interface. will reset from internal controller. GPIO, TSA, ER2, set, assigned secondary interrupt status register time slot value register must read first. After secondary status register read access, error status register corresponding bits main interrupt status register will reset.
APLL
Status Register Value Register
Interrupt Error tatus Register
Interrupt Error tatus Register
eneral Purpose Interrupt Status Register
iti_063.em
Figure
8-bit Access Interrupt Structure
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Preliminary Data Sheet
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PRELIMINARY Programming Device
IREQ output level active. stays active until interrupt sources have been serviced. status while interrupt being serviced read access), IREQ stays active. duration write access INTM1 register IREQ line deactivated. When using edge-triggered interrupt controller, recommended rewrite INTM1 register interrupt service routine. APLL, Bits internal controller does first time masked interrupt will generated. reads ISTA1 register interrupt will deactivated. still active reset from internal controller. doesn't generate interrupt masked. from internal controller connection memory filled. APLL doesn't generate interrupt masked. from internal analog controller locked. Masking Interrupts interrupt masked (enabled) IREQ will active status bits interrupt status register set. mask prevents that IREQ will active status set. mask bits error status registers general purpose interrupt register disable interrupt indication interrupt status register. Only interrupt status register IREQ masked. Interrupt Structure 16-bit Microprocessor Access
APLL
iste
gister
iste
iti_
Figure
16-bit Access Interrupt Structure
opposite 8-bit access there only (ER1) indicate change 16-bit Interrupt Error Status Register
Preliminary Data Sheet
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PRELIMINARY Programming Device
Command Register Overview
following table (Table shows which parameter registers considered issuing appropriate connection command. Table Command Connect/Disconnect (without subchannels) Connect (with subchannels) Disconnect (with subchannels) Send Message Stop Message Disconnect Part Broadcast (without subchannels) Disconnect Part Broadcast (with subchannels) Multipoint Connect/ Disconnect Bidirectional Connection Disconnect Memory Dump (Connection Data Memory) Affected Registers Connection Commands Registers ITSA OTSA
Preliminary Data Sheet
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following table (Table shows which parameter registers considered issuing appropriate configuration command. Table Command Reference Clock Output Phase Alignment Rate Local Read Time Slot Clock Shift External Input Frequency Parallel Mode IREQ Standby Local Loop Frame Signal GPCLK Clock Range Data Rate Read Configuration Read GPCLK Configuration Read Local Configuration Read Shift Configuration Software Reset Affected Registers Configuration Commands Registers CMD1 CMD2 ITSA OTSA
Preliminary Data Sheet
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PRELIMINARY command registers have following structure: Programming Device
CC3.0 command code I3.0 parameter code. following tables (Table Table show valid values command parameter codes related function. Table Command1) Connection Command Parameter Codes Command Parameter Code Code (low nibble) (high nibble) minimum delay constant delay disable enable address 8-bit connections address 4-bit connections address 2-bit connections address 1-bit connections connection time slots connection time slots Note
Constant Delay Connect Disconnect
address 8-bit connections address 4-bit connections address 2-bit connections address 1-bit connections
Minimum Delay Connect Send Message Stop Message Disconnect Part Broadcast
Multipoint Connect Disconnect Bidirectional Connect Memory Dump
input port determined Bit3.0 output port Bit3.0. input time slot determined ITSA output time slot OTSA.
Preliminary Data Sheet
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PRELIMINARY Table Command Programming Device
Configuration Command Parameter Codes Command Parameter Code Code (low nibble) (high nibble) 0-3H 4-7H 8-BH C-FH Note
Rate Local Bus1)
effect rate local input port (2/4/8/ Mbit/s) rate local output port (2/4/8/16 Mbit/s) both input output (2/4/8/16 Mbit/s) read time slot input port read time slot output port shift input line shift input lines shift output lines shift input output lines
Read Time Slot2) Shift3)
input output port determined SPA, time slot determined ITSA OTSA input line determined SPA, shift information
Table
Command
Configuration Command Parameter Code
Command Code (low nibble) Parameter Note Code (high nibble)
External Frequency Parallel Mode
frequency 32.768 frequency 16.384 disable enable first local input lines parallel first local output lines parallel IREQ active low, timer IREQ active high, timer IREQ open-drain, timer IREQ active low, timer IREQ active high, timer IREQ open-drain, timer
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IREQ
Preliminary Data Sheet
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PRELIMINARY Table
Command
Programming Device
Configuration Command Parameter Code (cont'd)
Command Code (low nibble) Parameter Note Code (high nibble)
Standby Local Loop Frame Signal1)
0XXXb 1XXXb 0H-7H 0H-6H 8H-AH 0H-7H
disable Local (PCM) enable Local (PCM) loop enable Local Loop signal high active signal active line address parameter code line address logical connection from min. max. codes Master/Slave configuration Reference Clock Output Selection Phase Alignment External Input Frequency Parallel Mode IREQ Standby Local Loop Range Data Rate parameter code line address Data Rate Input Line6) Data Rate Output Line7) Shift Value Input Line9) Shift Value Output Lines
GPCLK Clock2) Range Data Rate Read Configuration3)
Read GPCLK Configuration4) Read Local Line Configuration5) Read Shift Configuration8)
offset width determined frequency determined result read from register result read from register result read from register must used line number must used line number result read from register
Preliminary Data Sheet
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PRELIMINARY Programming Device
Indirect Configuration Register Access
possible read current SWITI configuration with indirect register access analyze test purpose. There five commands CMD2 register which used read configuration. clock generator output signal external configuration SWITI read with 'Read Configuration Command'. four instruction bits select possible configuration command. current configuration determined command written register. configuration information every command found page line configuration read with command 'Read Local Line configuration'. Before command will issued register must written with port number. configuration selected line written register internal controller. interrupt handling described Chapter 6.2. shift configuration read with command 'Read Shift Configuration' dataflow same described above. With command 'Read GPCLK Configuration' possible read configuration every GPCLK line. this command written configuration read from register. register interrupt controlled will keep last data after microprocessor read access. read correct configuration data from register allowed command "Read Time Slot Value" before register read.
Preliminary Data Sheet
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PRELIMINARY Programming Device
Initialization Procedure
After reset process PLL, local (PCM) interface, some other signals need initialized. Since SWITI offers possibility different external crystal/oscillator frequencies command 'Set external frequency' must used first correct frequency correct value input frequency APLL. After approximately 750µs APLL locked APLL status next commands written.
Reset (Hardware) Internal Frequency ext. Frequency
Write CMD2 ext. Freq. 32.768 MHz) Write CMD2 ext. Freq. 16.384 MHz) WAIT ~750µs
Read Interrupt Status Register ISTA1:APLL APLL locked Int. Frequency 49.152
iti_073.em
Figure
Initialization Procedure after Reset
After this initialization procedure different functional blocks SWITI programmed. Local (PCM) Interface Interrupt's IREQ GPCLK's Frame Signals General Purpose Interface
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PRELIMINARY Programming Device
Clocking Unit
clock signals line interface will provided from external devices SWITI used clock slave will provided from internal SWITI used clock master. This clock configuration programmed with special command 'PCM Input/Output Selection' Figure CMD1 register. synchronization please refer Chapter 3.4.4 page Example: SWITI clock master, reference NTWK_1 with driven with 8.192 driven. Write Write CMD1 Write CMD1 Example SWITI clock slave, reference with 4.096 MHz. Write Write CMD1 Write CMD1 (PDC 4.096 input)
Preliminary Data Sheet
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PRELIMINARY Programming Device
6.7.1
Local (PCM) Line Interface Standby Command
data lines high impedance state after reset process. they configured (data rate, shift) they enabled with standby command. During normal operation lines enabled disabled with standby command. lines disabled device works internally like active device. Example: output lines high impedance. Write CMD1
6.7.2
Determining Clock Rates
data rate range command necessary optimize minimum delay feature. After reset process device assumes rate 2.048 Mbit/s lines. command must issued other data rates used. Example (8-bit interface): Specify that only 2.048 Mbit/s 4.096 Mbit/s used following Rate Command. Write CMD2 rate 4.096 Mbit/s Local-Bus input line Local-Bus output line Write Write Write CMD1 Example (16-bit interface): Write CMD2 Write 0008H Write 0001H Write CMD1
Preliminary Data Sheet
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PRELIMINARY Programming Device
6.7.3 6.7.3.1
Performing Shifting Input Shifting
Data Rate Selected Line
Local-Bus Input Line
switi_040.em
Figure
Example: Input Shifting
Example (8-bit interface): Begin time slot local input line with rising edge relative byte before rising edge. bits internally sampled with falling edge. Write Write Write CMD1 Example (16-bit interface): Write 0008H Write 0008H Write CMD1
6.7.3.2
Output Shifting
Data Line
Local-Bus utput Lines
switi_041.em
Figure
Example: Output Shifting
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Preliminary Data Sheet
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PRELIMINARY Example (8-bit interface): Output time slot output lines begins with first falling edge relative first byte after rising edge. bits internally sampled with rising edge. Write Write CMD1 Example (16-bit interface): Write 0011H Write CMD1 Programming Device
Preliminary Data Sheet
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PRELIMINARY Programming Device
6.8.1
Global Clock Signals Framing Groups
125µs
16.384 Mbit/s
244ns 125µs
GPCLK_1
125µs 427ns
GPCLK_2
switi_077.emf
Figure
Example Framing Groups
Example (8-bit interface): Frame signal GPCLK_1 starts with rising edge 64th clock cycle length ns). Write Write Write CMD2 Frame signal GPCLK_2 starts with falling edge clock cycle length ns). Write Write Write CMD2 Example (16-bit interface): Write 6100H Write 0016H CMD2 Write C012H Write 0026H CMD2
Preliminary Data Sheet
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PRELIMINARY Programming Device
Read Time Slot Value
issuing this command time slot value appears register after arriving interrupt will caused read time-slot value will accepted. command issued every read request. current data will overwritten read time slot command issued. Example (8-bit interface): Read time slot local-bus input line Write Write ITSA Write CMD1 Example (16-bit interface): Write 0A03H Write CMD1 Wrong Time-Slot Time-Out some case could happen that tries read wrong time-slot. wrong timeslot defined invalid time-slot number selected data rate, e.g. data rate MBit/s selected time-slot tries read wrong time-slot interrupt would generated controller doesn't accept further commands. SWITI integrated time-out counter allow read time-slot command after maximum three frames.
Preliminary Data Sheet
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PRELIMINARY Programming Device
6.10
Establish Connections
following chapter describes programming several kinds connections. programming interface allows program re-program connection during normal switching mode. Before connection specific output time-slot line will programmed specific connection released.
6.10.1
Establish 8-bit Connections
Fram Signal Local-Bus Input Line
constant delay
Local-Bus utput Line
switi_027.em
Figure
Example: 8-bit Connection
Example (8-bit interface): Connect time slot Local-Bus input line with output time-slot Local-Bus output line constant delay connection Write ITSA Write Write OTSA Write Write CCMD
Example (16-bit interface): Write 0A03H Write 1E0DH Write 0001H CC16
Preliminary Data Sheet
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PRELIMINARY Programming Device
6.10.2
Sub-Channel Switching
With sub-channel address register (SCA) constant delay command possible program 1,2, connections. following figure explains relation between sub-channel address corresponding bits time-slot.
ISCA from Register OSCA from Register
switi_070.emf
Figure
Sub-channel Address Time-Slot
6.10.2.1 Establish 4-bit Connections
Fram Signal Local-Bus Input Line
constant delay
Local-Bus utput Line
switi_028.em
Figure
Example: 4-bit Connection
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Preliminary Data Sheet
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PRELIMINARY Example (8-bit interface): Connect nibble time slot Local-Bus input line with high nibble output time-slot Local-Bus output line constant delay connection Write Write ITSA Write Write OTSA Write Write CCMD Programming Device
Example (16-bit interface): Write 0A03H Write 1E0DH Write 0811H CC16
6.10.2.2 Establish 2-bit Connections
Fram Signal Local-Bus Input Line
constant delay
Local-Bus utput Line
switi_042.em
Figure
Example: 2-bit Connection
Example (8-bit interface): Connect 2-bit sub-channel time slot Local-Bus input line with 2-bit subchannel output time-slot Local-Bus output line constant delay connection Write Write ITSA Write Write OTSA Write Write CCMD
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Preliminary Data Sheet
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PRELIMINARY Example (16-bit interface): Write 0A03H Write 1E0DH Write 1921H CC16 Programming Device
6.10.2.3 Establish 1-bit Connections
Fram Signal
Local-B Input Line
constant delay
Loca-Bus utput Line
switi_043.em
Figure
Example: 1-bit Connection
Example (8-bit interface): Connect 1-bit sub-channel time slot Local-Bus input line with 1-bit subchannel output time-slot Local-Bus output line constant delay connection Write Write ITSA Write Write OTSA Write Write CCMD
Example (16-bit interface): Write 0A03H Write 1E0DH Write 2A31H CC16
Preliminary Data Sheet
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PRELIMINARY Programming Device
6.10.3
Fram Signal
Establish Broadcast Connections
Local-Bus Input Line
constant delay
Local-Bus utput Line Local-Bus utput Line
switi_031.em
Figure
Example: Broadcast Connection
Example (8-bit interface): Connect time slot Local-Bus line with output time-slot Local-Bus output line output time slot Local-bus output line constant delay mode. connections established consecutively necessary rewrite source determining registers ITSA because they keep their values. Write ITSA Write Write OTSA Write Write CCMD Write OTSA Write Write CCMD
Example (16-bit interface): Write 0A03H Write 1E0DH Write 0001H CC16 Write 620FH Write 0001H CC16
Preliminary Data Sheet
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PRELIMINARY Programming Device
6.10.4
Establish Sub-Channel Broadcast Connection
ignal
Local-B Input Line
constant delay
Local-B utput Line
iti_081.em
Figure
Example: Sub-Channel Broadcast Connection
First Connection Write Write ITSA Write Write OTSA Write Write CCMD Second Connection Write Write ITSA Write Write OTSA Write Write CCMD Third Connection Write Write ITSA Write Write OTSA Write Write CCMD Fourth Connection Write Write ITSA Write Write OTSA
Preliminary Data Sheet 2001-01-01
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PRELIMINARY Write Write CCMD Fifth Connection Write Write ITSA Write Write OTSA Write Write CCMD Programming Device
6.10.5
Fram Signal
Establish Multipoint Connection
Local-Bus Input Line Local-Bus Input Line
constant delay
switi_03 4.em
Local-Bus utput Line
Figure
Example: Multipoint Connection
Example (8-bit interface): Connect time slot Local-Bus line time slot Local-Bus line logical with output time slot Local-Bus output line constant delay mode. connections established consecutively necessary rewrite destination determining registers OTSA because they keep their values. Write ITSA Write Write OTSA Write Write CCMD Write ITSA Write Write CCMD
Preliminary Data Sheet
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PRELIMINARY Example (16-bit interface): Write 0A03H Write 1E0DH Write 0007H CC16 Write 1408H Write 0007H CC16 Programming Device
6.11
Send Messages
Sending messages means transmit constant value time slot sub-channel after message programmed within three frames. message sent continuously until sending stopped stop message command.
Frame Signal Local-Bus Output Line
switi_029.emf
Figure
Example: Send Message
Example (8-bit interface): Send constant value time slot Local-Bus line Write Write OTSA Write Write CCMD
Example (16-bit interface): Write Write 0A03H Write 0003H CC16
Preliminary Data Sheet
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PRELIMINARY Programming Device
6.12 6.12.1
Release Connections Release 8-bit Connections
Example (8-bit interface): Release connection established Figure Write ITSA Write Write OTSA Write Write CCMD
Example (16-bit interface): Write 0A03H Write 1E0DH Write 0005H CC16
6.12.2
Release 4-bit Connections
Example (8-bit interface): Release connection established Figure Write Write ITSA Write Write OTSA Write Write CCMD
Example (16-bit interface): Write 0A03H Write 1E0DH Write 0815H CC16
6.12.3
Release 2-bit Connections
Example (8-bit interface): Release connection established Figure Write Write ITSA Write
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PRELIMINARY Write OTSA Write Write CCMD Example (16-bit interface): Write 0A03H Write 1E0DH Write 1925H CC16 Programming Device
6.12.4
Release 1-bit Connections
Example (8-bit interface): Release connection established Figure Write Write ITSA Write Write OTSA Write Write CCMD
Example (16-bit interface): Write 0A03H Write 1E0DH Write 2A35H CC16
Preliminary Data Sheet
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6.12.5
Release Broadcast Connection
Example (8-bit interface): Release connection established Figure last connection participating broadcast connection have released Disconnect Part Broadcast Command. last connection released Constant Delay Connect Disconnect Command. Write ITSA Write Write OTSA Write Write CCMD Write ITSA Write Write OTSA Write Write CCMD
Example (16-bit interface): Write 0A03H Write 620FH Write 0006H CC16 Write 0A03H Write 1E0DH Write 0005H CC16
6.12.6
Release Sub-Channel Broadcast Connection
order different establish order. last release must normal release command. First Connection Write Write ITSA Write Write OTSA Write Write CCMD Second Connection Write Write ITSA Write Write OTSA
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PRELIMINARY Write Write CCMD Third Connection Write Write ITSA Write Write OTSA Write Write CCMD Fourth Connection Write Write ITSA Write Write OTSA Write Write CCMD Fifth Connection Write Write ITSA Write Write OTSA Write Write CCMD Programming Device
6.12.7
Release Multipoint Connection
This type connections released with normal disconnect commands. (See "Release 8-bit Connections" page 90.)
6.13
Stop Sending Messages
Example (8-bit interface): Stop sending message invoked Figure Write OTSA Write Write CCMD Example (16-bit interface): Write 0A03H Write 0004H CC16
Preliminary Data Sheet
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PRELIMINARY Timing Diagrams
Timing Diagrams
Interface Timing
following tables figures give timing with capacitive load configured inputs. timing also valid configured outputs.
tPFS
CLK_H
CLK_L
thIN
tdOUT
TS63 bit/s
iti_057.em
Figure Table Parameter Period high time
Timing Timing Symbol tPFS tsFS thFS Limit Values min. max. 4.096 Unit Test Condition
time clock hold time from clock
Preliminary Data Sheet
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PRELIMINARY Table Parameter high time time clock hold time from clock high time time clock hold time from clock clock period clock period clock period high clock period clock period clock period high clock period clock period clock period high rise time fall time Serial data input time Serial data input time Serial data input time Serial data output delay Serial data output delay Serial data output delay Timing Symbol tsFS thFS tsFS thFS tCLK tCLK_L tCLK_H tCLK tCLK_L tCLK_H tCLK tCLK_L tCLK_H tsIN Limit Values min. max. 4.096 8.192 16.384 4.096 8.192 16.384 tdOUT tdOUT tdOUT tsIN tsIN 16.384 8.192 4.096 16.384 8.192 Unit Test Condition Timing Diagrams
Serial data input hold time thIN
Serial data input hold time thIN
Serial data input hold time thIN
Preliminary Data Sheet
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PRELIMINARY Timing Diagrams
Parallel Mode Timing
TIME SLOT
TCLK_L
TCLK_H TCLK
VALID DATA
VALID DATA
iti_071.em
Figure Table Parameter
Parallel Mode Timing Parallel Mode Timing Symbol TCLK TCLK_H TCLK_L Limit Values min. max. 2.048 Unit Test Condition
Frame setup time clock Frame hold time clock Input data setup time Input data hold time Output data delay clock period clock period high clock period
Preliminary Data Sheet
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PRELIMINARY Timing Diagrams
Microprocessor Interface Timing
Microprocessor accesses SWITI performed activation address driving MODE16 'low' user selects 8-bit microprocessor interface, driving 'high' 16-bit microprocessor interface. driving 'high' user selects Intel/Infineon mode, driving 'low' Motorola mode. sampled during hardware reset process. Intel/Infineon mode, distinction needed between working multiplexed address/data mode de-multiplexed address data mode. Motorola mode, only de-multiplexed busses used. driving 'high' during normal operation user selects de-multiplexed mode, falling rising edge during normal operation selects multiplexed mode.
7.3.1
Infineon/Intel Timing De-Multiplexed Mode
this mode driving 'low' causes read access, driving 'low' causes write access. de-multiplexed configuration, must driven `high'. Table Parameter Infineon/Intel Timing De-Multiplexed Mode Symbol Limit Values (CLOAD= 50pF) Address setup time pulse width recovery time Data output delay from active Data float delay from inactive pulse width recovery time Data setup time Data hold time from
Preliminary Data Sheet
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PRELIMINARY Timing Diagrams
A0-A4 Address RDxCS D0-D7 Data
Figure
Infineon/Intel Read Cycle De-Multiplexed Mode
A0-A4 Address WRxCS D0-D7 Data
Figure
Infineon/Intel Write Cycle De-Multiplexed Mode
Addresses will latched with falling edge during write cycle internally.
7.3.2
Infineon/Intel Timing Multiplexed Mode
this mode used lock address send multiplexed bus.
Preliminary Data Sheet
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PRELIMINARY Table Parameter Infineon/Intel Timing Multiplexed Mode Symbol Limit Values (CLOAD= 50pF) pulse width Address setup time falling edge Address hold time from falling edge Address latch setup time pulse width recovery time Data output delay from active Data float delay from inactive pulse width recovery time Data setup time Data hold time from tALS Timing Diagrams
tALS
RDxCS Address Data
AD0-AD7
Address
Figure
Infineon/Intel Read Cycle Multiplexed Mode
Preliminary Data Sheet
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PRELIMINARY Timing Diagrams
tALS
WRxCS Address Data
AD0-AD7
Address
Figure
Infineon/Intel Write Cycle Multiplexed Mode
7.3.3
Motorola Microprocessor Timing
this mode distinguishes between Read Write interactions, used timing. active (low) when both, active (low). must driven 'low'. Table Parameter Motorola Timing Symbol Limit Values (CLOAD= 50pF) Address setup time setup hold from CSxDS inactive pulse width recovery time Data output delay from Data float delay from pulse width recovery time Data setup time Data hold time from tDSD tRWD
Note: active (low) when, both, active (low)
Preliminary Data Sheet
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PRELIMINARY Timing Diagrams
A0-A4 Address tDSD CSxDS D0-D7 Data tRWD
Figure
Motorola Read Cycle
A0-A4 Address tDSD CSxDS D0-D7 Data tRWD
Figure
Motorola Write Cycle
Preliminary Data Sheet
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PRELIMINARY Timing Diagrams
Table Parameter
JTAG Interface Timing
JTAG Interface Timing Symbol tTCJ tCJL tCJH tSUJ tHJR Limit Values min. typ. max. Update-DR Controller State Unit Notes
Test Clock (TCK) Period Test Clock (TCK) Period Test Clock (TCK) Period High Set-up time before Rising Edge Hold time after Rising Edge
Set-up time before tDSE Rising Edge Hold time after Rising Edge Delay after Falling Edge output Delay after Falling Edge tDHE tODF tOPD
Preliminary Data Sheet
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PRELIMINARY Timing Diagrams
tTCJ tCJH tCJL
tSUJ tHJR
tDSE tDHE
tODF
tIPJ tIAJ
tOPD
Figure
Boundary Scan Timing
Preliminary Data Sheet
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PRELIMINARY Electrical Characteristics
Table Parameter
Electrical Characteristics
Absolute Maximum Ratings
Absolute Maximum Ratings Symbol Limit Values Unit
Ambient temperature under bias Storage temperature Supply voltage Voltage input output (referenced ground) robustness1) (HBM:
Tstg
VESD,HBM 1500
According MIL-Std 883D, method 3015.7 Ass. Standard EOS/ESD-5.1-1993.
Note: Stresses above those listed here cause permanent damage device. Exposure absolute maximum rating conditions extended periods affect device reliability. Maximum ratings absolute ratings; exceeding only these values cause irreversible damage integrated circuit.
Table Parameter
Operating Range Operating Range
Symbol Limit Values min. max. 3.47 3.13 Unit
Operating temperature Supply voltage Ground Voltage applied input pins
Voltage applied output pins outputs enabled VOUT outputs high-Z VOUT
Note: operating range, functions given circuit description fulfilled.
Preliminary Data Sheet
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PRELIMINARY Electrical Characteristics
Crystal Oscillator
SWITI requires 16.384 32.768 clock source. supply this 16.384 32.768 crystal connected between ECLKI ECLKO pins. Figure shows crystal with external capacitors resistors.
ECLKI 16.384 32.768 ECLKO
switi_061.em
Figure
External Crystal
crystal used, 16.384 32.768 signal must provided ECLKI ECLKO should left unconnected. Table Parameter Clock external input capacitance External Capacitances Crystal (Recommendation) Symbol Rec. Values Unit Notes
CECLKI Clock external output capacitance CECLKO
Preliminary Data Sheet
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PRELIMINARY Electrical Characteristics
Table Parameter
Characteristics Characteristics
Symbol Limit Values min. max. Unit Notes
Input voltage Input high voltage Output voltage Output high voltage Typical power supply current Input leakage current
16.384
other pins floating; VOUT
Output leakage current
Note: listed characteristics ensured over operating range integrated circuit. Typical characteristics specify mean values expected over production spread. otherwise specified, typical characteristics apply given supply voltage.
Table Parameter
Capacitances Input/Output Capacitances
Symbol Limit Values Unit Typ. Notes
ECLKI input capacitance ECLKO output capacitance Input capacitance Output capacitance
CECLKI CECLKO COUT
pins, which under test, connected
Preliminary Data Sheet
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PRELIMINARY Electrical Characteristics
Characteristics
Ambient temperature under bias range, Inputs driven logical logical '0'. Timing measurements other signals made logical logical '0'. AC-testing input/output wave forms shown below.
Test Points
Device Under Test
Figure
Wave Form AC-Test
Preliminary Data Sheet
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PRELIMINARY Package Outlines
Package Outlines
P-MQFP-100-2 (Plastic Metric Quad Flat Package)
gpr05365.eps
Figure
Outlines P-MQFP-100-2
Sorts Packing Package outlines tubes, trays etc. contained Data Book "Package Information". Surface Mounted Device Preliminary Data Sheet
Dimensions 2001-01-01
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PRELIMINARY
Analyze Memory
Bidirectional Switching Boundary Scan Broadcast Broadcast Switching
Clock Shift Constant Delay
Data Rate Adaption
Flexible Data Rates Frame Group Framing Group
General Purpose Clocks GPIO Port
Initialization Procedure Input/Output Tolerance Interrupt Handling Interrupts Masking
Local Interface
Message Mode Microprocessor Interface Minimum Delay Multipoint Multipoint Switching
Preliminary Data Sheet
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PRELIMINARY
Parallel Mode
Read Access Register Configuration Command Register Configuration Command Register Configuration Register Connection Command Register Destination Address Register Destination Port Address Register General Input Register General Input Register General Input Register General Purpose Direction Register General Purpose Interrupt Register General Purpose Mask Register General Purpose Port Input Register General Purpose Port Output Register IDCODE Register Input Time Slot Address Register Interrupt Error Mask Register Interrupt Error Mask Register Interrupt Error Status Register Interrupt Error Status Register Interrupt Error Status Register Interrupt Mask Register Interrupt Status Register Message Value Register Output Time Slot Address Register Source Address Register Source Port Address Register Sub-Channel Address Register Time Slot Value Configuration Register Time Slot Value Register
Sub-Channel Switching
Write Access
Preliminary Data Sheet
2001-01-01
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