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SWITI Switching 20451 20471 24471 Version HTSI HTSI-L HTSI-XL
Wired Communications
Edition 2001-01-01 Published Infineon Technologies St.-Martin-Strasse D-81541 Germany
Infineon Technologies 2001.
Rights Reserved. Attention please! information herein given describe certain components shall considered warranted characteristics. Terms delivery rights technical change reserved. hereby disclaim warranties, including limited warranties non-infringement, regarding circuits, descriptions charts stated herein. Infineon Technologies approved CECC manufacturer. Information further information technology, delivery terms conditions prices please contact your nearest Infineon Technologies Office Germany Infineon Technologies Representatives worldwide (see address list). Warnings technical requirements components contain dangerous substances. information types question please contact your nearest Infineon Technologies Office. Infineon Technologies Components only used life-support devices systems with express written approval Infineon Technologies, failure such components reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain and/or protect human life. they fail, reasonable assume that health user other persons endangered.
SWITI Switching 20451 20471 24471 Version HTSI
Wired Communications
HTSI-L
HTSI-XL
20451 20471 24471 PRELIMINARY Revision History: 2001-01-01 Previous Version: Page 03.00 Subjects (major changes since last revision) note unused pins Description H-Mode H.110 Mode chapter sub-channel broadcast
Change memory dump: software reset must issued instead memory dump disable. chapter 4.5.2: Analog explanation clock fallback secondary master explanation clock fallback slave Disconnect Part Broadcast Command: ITSA register. Source Selection Command. Slave Path (only H-mode): remove sync. internal oscillator. Update Timing Electrical Characteristics
questions technology, delivery prices please contact Infineon Technologies Offices Germany Infineon Technologies Companies Representatives worldwide: webpage http://www.infineon.com
20451 20471 24471
Table Contents 1.4.1 1.4.2 1.4.3 1.4.4 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 3.3.1 3.3.1.1 3.3.1.2 3.3.1.3 3.3.1.4 3.3.1.5 3.3.1.6 3.3.2 3.3.3 3.3.4 3.4.1 3.4.2 3.4.2.1 3.4.2.2 3.4.3 3.4.4 3.4.5 3.4.5.1
Page
Overview Overview Features Features Detail Logic Symbol Typical Applications Standard Application Computer Telephony Application Router Remote Access Application Voice over Application Description Diagram Definitions Functions H-Bus Interface Local Interface (PCM) General Purpose Port Clock Signals JTAG Interface Microprocessor Interface Power Supply Architectural Description Functional Block Diagram Overview Functional Blocks Switching Factory Switching Modes Minimum Constant Delay Sub-Channel Switching Multipoint Switching Broadcast Switching Bidirectional Switching Stream-to-Stream Switching Parallel Mode Local Switching Block Error Handling Analyze Connection Data Memory Clock Generator General Overview Analog (APLL) Functional Description Jittertransferfunction Master-Slave Selection Phase Alignment Synchronization Synchronization H-Mode
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Table Contents 3.4.5.2 3.4.6 3.4.7 3.4.7.1 3.4.7.2 3.7.1 3.7.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.4.1 4.4.2 4.6.1 4.6.2 4.7.1 4.7.2 4.7.3
Page
Synchronization M-Mode Error Handling Clock Fallback Clock Signal Monitoring Clock Fallback Mechanism Loops Read SWITI Configuration with Indirect Register Addressing Power-On Reset Behavior Hardware Reset Software Reset Description Interfaces Local Interface (PCM) H-Bus Interface CT_C8(A/B) /CT_FRAME(A/B) Dataports /CT_EN /CT_RESET H-MVIP /C16 Signals Data Rate Microprocessor Interface Intel/Siemens Motorola Mode De-multiplexed Multiplexed Mode General Purpose Port (GPIO) General Purpose Clocks Frame Group Outputs GPCLK Clock Outputs JTAG (Boundary Scan) Boundary Scan Test-Access-Port (TAP) Controller Identification Code Read Access Register Description Register Overview 8-Bit Interface Detailed Register Description 8-bit Interface Register Overview 16-Bit Interface Detailed Register Description 16-Bit Interface
Programming Device Read Write Access Interrupt Handling Command Register Overview Indirect Configuration Register Access
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Preliminary Data Sheet
20451 20471 24471
Table Contents 6.8.1 6.8.2 6.8.3 6.8.3.1 6.8.3.2 6.9.1 6.10 6.11 6.11.1 6.11.2 6.11.2.1 6.11.2.2 6.11.2.3 6.11.3 6.11.4 6.11.5 6.12 6.13 6.13.1 6.13.2 6.13.3 6.13.4 6.13.5 6.13.6 6.13.7 6.14 7.6.1 7.6.2 7.6.3
Page
Initialization Procedure H.1x0 Clocking Unit Clocking Unit H.1x0/PCM Line Interface Standby Command Determining Clock Rates Performing Shifting Input Shifting Output Shifting Global Clock Signals Framing Groups Read Time Slot Value Establish Connections Establish 8-bit Connections Sub-Channel Switching Establish 4-bit Connections Establish 2-bit Connections Establish 1-bit Connections Establish Broadcast Connections Establish Sub-Channel Broadcast Connection Establish Multipoint Connection Send Messages Release Connections Release 8-bit Connections Release 4-bit Connections Release 2-bit Connections Release 1-bit Connections Release Broadcast Connection Release Sub-Channel Broadcast Connection Release Multipoint Connection Stop Sending Messages Timing Diagrams Interface Timing Parallel Mode Timing H-Bus (Local Bus) Frame Structure H-Bus Timing Clock Interoperability Microprocessor Interface Timing Infineon/Intel Timing De-Multiplexed Mode Infineon/Intel Timing Multiplexed Mode Motorola Microprocessor Timing JTAG Interface Timing
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Table Contents
Page
Electrical Characteristics Absolute Maximum Ratings Operating Range Crystal Oscillator Characteristics Capacitances Characteristics
Package Outlines
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List Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Page
Logic Symbol: HTSI H-Mode Logic Symbol: HTSI M-Mode Standard Application Application Router Remote Access Applications Voice over Application Configuration Block Diagram Bidirectional Mode Example Stream-to-Stream Switching SWITI Clock Generator Block Diagram APLL APLL Jitter Transfer Function Clock Fallback Primary Master Clock Fallback Secondary Master Clock Fallback Slave Interface Configurations Shifting H-Bus Interface H.100 Mode H-Bus Interface H.110 Mode Multiplexed De-multiplexed Mode GPIO Port Configuration Example Frame Signal Example. Order Register Access 8-bit Access Interrupt Structure 16-bit Access Interrupt Structure Initialization Procedure after Reset H.100 Master Slave Configuration Process Example: Input Shifting Example: Output Shifting Example Framing Groups Example: 8-bit Connection Sub-channel Address Time-Slot Example: 4-bit Connection Example: 2-bit Connection Example: 1-bit Connection Example: Broadcast Connection Example: Sub-Channel Broadcast Connection Example: Multipoint Connection Example: Send Message Timing Parallel Mode Timing H-Bus (Local Bus) Clock Alignment
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List Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Page
H-Bus Frame Structure H.1x0 Detailed Functional Timing H.1x0 Functional Timing MBit/s Data Streams Detailed Data Timing Clock Skew Timing SCLK-D Timing SCbus Operating 8.192 Mbit/s Infineon/Intel Read Cycle De-Multiplexed Mode Infineon/Intel Write Cycle De-Multiplexed Mode Infineon/Intel Read Cycle Multiplexed Mode Infineon/Intel Write Cycle Multiplexed Mode Motorola Read Cycle Motorola Write Cycle Boundary Scan Timing. External Crystal Wave Form AC-Test Outlines P-BGA-217-1
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List Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
Page should read what? SWITI Family Tree H.100/H.110 Interface (H-mode only). Local Interface GPIO Clock Pins JTAG Interface. Microprocessor Interface Power Supply Pins. Stream-to-Stream Connection Mapping Data Rates Local H-Bus Controller Instructions Boundary Scan IDCODE IDCODE Read Access Register Overview 8-Bit Interface Value Range SPA/DPA Value Range ITSA/OTSA Value Range SCA. Register Overview 16-Bit Interface Affected Registers Connection Commands Affected Registers Configuration Commands. Connection Command Parameter Codes Configuration Command Parameter Codes. Configuration Command Parameter Code. Timing Parallel Mode Timing Component Timing Specification Clock Skew Timing SCLK-D Timing 8.192 Mbit/s Infineon/Intel Timing De-Multiplexed Mode Infineon/Intel Timing Multiplexed Mode Motorola Timing JTAG Interface Timing Absolute Maximum Ratings Operating Range External Capacitances Crystal (Recommendation) Characteristics Input/Output Capacitances
Preliminary Data Sheet
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PRELIMINARY
Preface
Switching (SWITI) family switching devices wide area telecommunication data communication applications. This document provides complete reference information according chip interfaces, programming, internal architecture applications. Organization this Document This Preliminary Data Sheet divided into chapters. organized follows: Chapter Overview Gives general description product family, lists features, presents some typical applications. Chapter Description Lists locations with associated signals, categorizes signals according function, describes signals. Chapter Architectural Description Rough overview internal architecture clock fallback feature. Chapter Description Interfaces Short introduction used interfaces. Chapter Register Description Gives information about registers accessible microprocessor interface according address, short name, access, reset value value range. Chapter Programming Device Gives variety examples programm device, lists available command parameter values. Chapter Timing Diagrams Contains timing diagrams. Chapter Electrical Characteristics Specification electrical parameters. Chapter Package Outlines Outlines available packages (P-BGA-217-1).
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PRELIMINARY Table Programmer Board Designer Related Documentation H.100 Hardware Compatibility Specification: Bus, revision H.110 Hardware Compatibility Specification: Bus, revision Specification, revision 2.1, special interest group Compact Specification PICMG 2.0, revision Compact Swap Specification PICMG 2.1, revision H-MVIP Standard, Release 1.1a, GO-MVIP Inc., January 1997 MVIP-90 Standard, Release 1.1, GO-MVIP Inc., October 1994 SC-Bus Specification, ANSI/VITA 6-1994 should read what? Relevant Chapters
Addressed Person
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PRELIMINARY Overview
Overview
switching family, called SWITI, provides complete cost-effective solution switching systems. family divided sub-families, MTSI family HTSI family. Preliminary Data Sheet describes functionality characteristic HTSI devices. devices used today's switching applications, e.g. conventional PBXs central offices (CO's), well H.100/H.110 applications (only HTSI family), which high performing CTI- Voice-over-IP-applications, most important future technologies telecommunications. main requirements today's switching applications following features: Constant delay e.g. support wide band data switching, channel bundling switching/subchannel switching support applications such mobile base stations, DECT, computer telephony addition, SWITI family provides features ensure broad range configurations make possible adapt device switching applications: compliant H.100/H.110 interface (HTSI) 8-channel stream-to-stream switching capability (HTSI) Message mode, which allows assign preset value output time-slot GPIO (General Purpose I/O) port, which controlled from external
SWITI family. SWITI family consists with different switching capacities. possible configurations shown Table HTSI versions provide additional H.100 H.110 interface, while MTSIs standard switching devices. devices programmed easily, thus helping designer/programmer integrate device into application comfortably. Table Name HTSI-XL (H-Mode) HTSI-XL (M-Mode) HTSI-L (H-Mode) HTSI-L (M-Mode) P-BGA-217-1 SWITI Family Tree Package P-BGA-217-1 Ordering Number 24471 HTSI-XL 24471 HTSI-XL 20471 HTSI-L 20471 HTSI-L 1024 Connec- Local-Bus tions IN/OUT 2048 16/16 32/32 16/16 32/32 H-Bus
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PRELIMINARY Table Name HTSI (H-Mode) HTSI (M-Mode) MTSI-XL MTSI-L MTSI SWITI Family Tree (cont'd) Package P-BGA-217-1 Ordering Number 20451 HTSI 20451 HTSI P-MQFP-100-2 24470 MTSI-XL P-MQFP-100-2 20470 MTSI-L P-MQFP-100-2 20450 MTSI 2048 1024 Connec- Local-Bus tions IN/OUT 16/16 32/32 16/16 16/16 16/16 H-Bus Overview
HTSI devices. HTSI devices operated different modes, H-Mode M-Mode. H-Mode device offers local I/Os additionally compliant H.100/H.110 interface bidirectional I/Os). complete number available connections assigned H-bus H-bus, local local connection, mixed. M-Mode lines configured local I/Os, that total local I/Os provided. Thus e.g. HTSI-XL device used non-blocking switch operating 4Mbit/s.
Preliminary Data Sheet
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PRELIMINARY
Switching SWITI
20451 20471 24471
Version
CMOS
General
Overview Features
Switching capacity 512, 1024, 2048 connections different types between different buses Programmable data rates 2.048 Mbit/s, 4.096 Mbit/s, 8.192 Mbit/s, 16.384 Mbit/s P-BGA-217-1 stream basis Constant delay minimum delay programmable connection basis Sub-channel switching ability 1-bit, 2-bit, 4-bit wide time-slots Programmable clock shift local 8-channel stream-to-stream switching H.100/H.110 interoperability Automatic data rate adaption Optional 8-bit parallel input and/or 8-bit parallel output first lines local Broadcast capabilities Multipoint switching ability Read write access time-slots Message mode (time-slot write access) Programmable framing group GPIO port 8-bit µP-interface supports both Intel Motorola mode Optional 16-bit interface mode (instead GPIO port) chip H.100/H.110, SCbus, MVIP, MVIP-H clock operation (master/slave) local clock operation (master/slave) JTAG interface Boundary scan according IEEE 1149.1 power supply tolerant inputs/outputs
Type 20451 20471 24471
Preliminary Data Sheet
Package P-BGA-217-1
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PRELIMINARY HTSI H-Mode H.100/H.110 compliant interface with mandatory signals Local ports In/16 Out) swapping HTSI M-Mode Local ports In/32 Out). Overview
Features Detail
Flexible Data Rates Each input each output line local programmable operate different data rates. possible data rates 2.048 Mbit/s, 4.096 Mbit/s, 8.192 Mbit/s, 16.384 Mbit/s. Even HTSI M-Mode input lines output lines configureable, except rate 16.384 Mbit/s. case 16.384 Mbit/s only lines used. possible data rate data lines H-Bus 2.048 Mbit/s, 4.096 Mbit/s 8.192 Mbit/s. Constant Minimum Delay Each connection independent addressed buses determined constant delay minimum delay connection. Constant delay means that input timeslot sub-channel available programmed output after frames. Minimum delay means that time-slot sub-channel appears output soon possible. minimum delay depends chosen connections possible range between frames. Sub-Channel Switching Each connection 1-bit, 2-bit, 4-bit, 8-bit connection. Sub-Channel switching applicable both local H-Bus constant delay frames. Programmable Clock Shift position time-slot each local input line programmed within time-slot before after rising edge half clock steps. Also position time-slot local output lines programmed within first time-slot after rising edge.
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PRELIMINARY 8-Channel Stream-to-Stream Switching This feature offers possibility efficiently switch data stream another same different data rates without occupying switching memory capacity. mainly supports interoperability between CT-bus (Computer Telephony) devices such SCbus MVIP-90 running different data rates. possible lines from H.1x0 data lines establish connections. Input output frequency configured differently. Automatic Data Rate Adaption Connections also possible between lines operating different data rates. programmer just specifies input output line, time-slot, necessary, subchannel. Parallel Mode first local input output lines configured parallel input output port respectively. serial mode time-slot determined consecutive data clock cycles according each line. parallel mode time-slot determined data clock cycle according first lines. Broadcast With this feature possible distribute incoming time-slot different output timeslots. Multipoint Multipoint connections seen opposite broadcast connections. Here possible generate output time-slot consisting several input time-slots. specified input time-slots logically connected (selectable) have constant delay frames. Read Access programmer access input time-slot. After issuing appropriate command arrival time-slot will reported interrupt. value read from dedicated register. every read request command issued again. Message Mode (Write Access) This feature allows constant value sent given output time-slot. Overview
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PRELIMINARY Framing Group possible specify different framing signals kHz. position rising edge pulse width programmed each signal. reference frame determined signal. pulse parameters programmed half step resolution according 16.384 clock. General Purpose Clocks GPCLK lines configured individual clock outputs with kHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 test purposes with internal frequency input frequency analog (APLL). GPIO Port Each line general purpose input/output port configured either input output. According input edge causes interrupt. outputs influenced write access microprocessor interface. Thus user possibility observe influence additional signals application. Microprocessor Interface devices provide standard 8-bit microprocessor interface operating either Intel Motorola mode. Optionally possible configure GPIO port additional data lines provide 16-bit microprocessor interface. 16-bit interface reduces number write cycles required configure connection from case 8-bit interface) write cycles. Input/Output Tolerance HTSI used environment with additional (VDD) power supply pins. Inputs outputs tolerant. outputs have level driving capability. H-Bus lines HTSI used 3.3V signaling environment. Overview
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PRELIMINARY Overview
Logic Symbol
HTSI dedicated perform time-slot switching between local HBus offer solution applications with high number local I/Os. HTSI operates modes. H-Mode (Figure works with H-Bus M-Mode (Figure operates without H-Bus. HTSI H-Mode provides input lines output lines complete H-Bus with bidirectional H.100/H.110 data lines.
IN[15:0] OUT[15:0]
CT_D[31:0] /CT_FRAME_A CT_C8_A /CT_FRAME_B CT_C8_B
General Purpose Clocks
CT_NETREF(_1) CT_NETREF_2
GPIO
HTSI 20451/20471/24471
/CT_EN /CT_RESET /FR_COMP SCLK
Misc.
TRST
SCLKx2* SCLK-D /C16+ /C16-
D[7:0]
A[4:0]
IREQ IREQ
RESET
MODE16
switi_002.emf
Figure
Logic Symbol: HTSI H-Mode
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PRELIMINARY Overview
H-Bus needed possible configure HTSI M-Mode. this mode, HTSI provides input lines output lines.
IN[31:0]
OUT[31:0]
TRST
HTSI 20451/20471/24471
General Purpose Clocks
GPIO
Misc.
D[7:0]
A[4:0]
IREQ RESET IREQ
MODE16
switi_003.emf
Figure
Logic Symbol: HTSI M-Mode
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PRELIMINARY Overview
Typical Applications
Typical applications SWITI family are: switch, concentrator multiplexer PBXs, mobile base stations H.100/H.110 interface Computer telephony systems Internet telephony systems LAN/WAN access devices Enhanced service platforms following sections give general overview system integration SWITI family.
1.4.1
Standard Application
MTSI HTSI M-Mode used, just MTSC MTSL, standard private branch exchange central office applications (Figure e.g. switching network.
Line Unit EPIC/ DELIC Switching Network MTSI/ HTSI
SLMD Subscriber Line Modul Digital EPIC/ DELIC MTSI/ HTSI HDLC
Coordination Processor
switi_014.emf
Figure
Standard Application
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PRELIMINARY Overview
1.4.2
Computer Telephony Application
Computer Telephony Integration (CTI) applications, resources such analog telephone line cards, ISDN ports, switching controllers, firmware, voice processing modules form plug-in cards that slots Resource sharing established connecting plug-in cards with cables. This Time Division Multiplex (TDM) evolved from original H-MVIP, MVIP-90, Dialogic's SC-Bus, into latest H.100/H.110 H-Bus developed Enterprise Computer Telephony Forum (ECTF). connecting H.100/H.110 interface devices, system modules send receive data from 4096 time-slots H-Bus. H-Bus also offers ideal solution routers provide bridge between data communication telecommunication system modules. Computer Telephony (CT) environment, resource sharing accomplished passing data back forth through H.100/H.110 bus. Figure shows example.
H.100/H.110
HTSI
HTSI
HTSI
HTSI
Base Transceiver Station (BTS)
Line Cards
Voice Recognition
switi_010.emf
Figure
Application
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PRELIMINARY Overview
1.4.3
Router Remote Access Application
HTSI (H-Mode) also MTSI H-Bus interface used system) used multivoice applications bridge connecting data communication modules telecommunication modules router/remote access design. Figure shows example.
H.100/H.110 PCM/IOM-2 FALC54 (Framer)
HTSI
CODEC Server HTSI HTSI MUNICH32 (HDLC)
Modem Pool
HTSI
switi_009.emf
Figure
Router Remote Access Applications
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PRELIMINARY Overview
1.4.4
Voice over Application
voice over application (Figure HTSI H-Mode) used connect conventional H-Bus. Vocoder card, also connected H-Bus, performs speech compression decompression whereas Ethernet card transmits receives compressed data over network.
H.100/ H.110 HTSI HTSI Vocoder PCI/cPCI
Processor
Ethernet
E1/T1
LAN/WAN
switi_004.emf
Figure
Voice over Application
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PRELIMINARY Description
Description
description gives overview numbers, names, direction, position function ordered different interfaces. Note: unused input pins should connected avoid leakage current.
Diagram
P-BGA-217-1
GPCLK_2
CT_D_0 /IN_16
CT_D_2/ IN_18 IN_1
IN_3 VDD5 IN_2 IN_0
IN_5
CT_D_8/ IN_24 VDD5
IN_9 CT_D_9 /IN_25
/FR_ COMP GPIO_0
/C16+ /C16VSS
CT_D_6/ CT_D_7/ IN_22 IN_23 IN_7 IN_8
IN_11
CT_D_12 CT_D_14/ IN_30 /IN_28 IN_14
CT_D_3/ CT_D_5/ IN_19 IN_21 IN_6 IN_4
CT_D_11 IN_12 /IN_27
CT_D_10 /IN_26 IN_10 IN_13
CT_D_13 CT_D_15/ /IN_29 IN_31 IN_15 RD/DS SCLK GPIO_3 GPIO_6
/CT_ FRAME_A GPCLK_0 GPCLK_3 GPCLK_1
CT_D_1/ CT_D_4/ IN_17 IN_20
GPCLK_5
GPCLK_7 GPCLK_6 CT_C8_A GPCLK_4 VSSA VDDA /CT_ FRAME_B CT_C8_B
P-BGA- 217-1
ECLKO ECLKI H110MODE
M-MODE NETREF2 RESERV. RESERV. /CT_ RESET NTWK_2 RESET OUT_0 IREQ NETREF1 OUT_1 CT_D_17/ CT_D20/ OUT_17 OUT20 VDD5 OUT_4 OUT_5
GPIO_1
MODE16 TRST
Bottom View
OUT_10 CT_D_26 /OUT_26 OUT_9 OUT_13 OUT_11 CT_D22/ OUT22 CT_D_23 CT_D_24 /OUT_23 /OUT_24 OUT_7 OUT_8
GPIO_5 CT_D_30/ OUT_30 CT_D_28/ OUT_28 OUT_15
SCLKx2* SCLK-D GPIO_2 GPIO_7 GPIO_4
/CT_EN switi_076.em
CT_D_16/ CT_D_18/ OUT_16 OUT_18 OUT_3 OUT_2
CT_D_29/ CT_D_31 OUT_29 /OUT_31
CT_D_19/ CT_D_21 OUT_19 /OUT_21 OUT_6
VDD5
CT_D_25/ CT_D_27/ OUT_25 OUT_27 OUT_12 OUT_14
Figure
Configuration
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PRELIMINARY Description
2.2.1
Definitions Functions H-Bus Interface
following table (Figure only applicable H-mode except CT_D (IN/ OUT) lines. Table
H.100/H.110 Interface (H-mode only)
Symbol /CT_FRAME_A Function H.1x0 only Frame Sync driven clock master. This negative true pulse, nominally wide that straddles beginning first first time slot. period H.1x0 only Clock driven clock master. clock frequency 8.192 MHz. duty cycle this signal nominally 50%. H.1x0 only Redundant Frame Sync driven clock master. This negative true pulse, nominally wide that straddles beginning first first time slot. period H.1x0 only Redundant Clock driven clock master. clock frequency 8.192 MHz. duty cycle this signal nominally 50%. H-Mode Serial Data lines that driven board system. However, only board drive given time slot each stream. Each signal contains time slots frame clock frequency 8.192 MHz. These signals collectively referred CT_D bus. devices connect subsets CT_D bus. Reset Behavior High
CT_C8_A
High
/CT_FRAME_B
High
CT_C8_B
High
U11, P11, U12, T13, P12, T14, A10, B11, D11, B12, A14, D12,
CT_D[31:0]1)
High
CT_D[15:0] IN[31:16] CT_D[31:16] OUT[31:16]
M-mode Receive Data Port (PCM mode only)
Transmit Data Port (PCM mode only)
High
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PRELIMINARY Table
Description
H.100/H.110 Interface (H-mode only) (cont'd)
Symbol CT_NETREF_1 Function H.1x0 Additional Network Timing Reference driven (single) digital trunk interface provide network synchronization Bus. This signal have duty cycle long period kHz), (1.544 MHz), (2.048 MHz) network synchronized. There specified phase relation CT_NETREF_2 other clocks. minimum high minimum time H.1x0 Additional Network Timing Reference driven (single) digital trunk interface provide network synchronization Bus. This signal have duty cycle long period kHz), (1.544 MHz), (2.048 MHz) network synchronized. There specified phase relation CT_NETREF_1 other clocks. minimum high time minimum time H.110 only Logic signal indicate that card fully seated. H.110 only Logic signal used reset cards that have access RST# reset from J1/P1. H.1x0 Compatibility frame pulse driven current clock master. This negative true pulse, nominally wide, that straddles beginning first first time slot. period This signal serves frame synchronization signal SCbus (Fsync*) MVIP (/F0). H.1x0 SCbus System clock driven current clock master. clock selectable. either 2.048 MHz, 4.096 MHz, 8.192 MHz. used identify data positions SCbus. positive going edge indicates beginning bit. H.100 SCbus System (SCLK) clock times driven current clock master. clock frequency exactly twice that SCLK. Transitions SCLK occur falling edge SCLKx2* SCbus operating 2.048 MHz, 4.096 MHz, 8.192 MHz. H.110 Inter-operability clock driven current clock master. clock frequency 8.192 Mhz. used identify data positions ANSI VITA SCbus. positive going edge indicates sample point bit. High Reset Behavior High
CT_NETREF_2
High
/CT_EN
/CT_RESET
/FR_COMP
SCLK
High
SCLKx2*
High
SCLK-D
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PRELIMINARY Table
Description
H.100/H.110 Interface (H-mode only) (cont'd)
Symbol Function H.1x0 MVIP-90 clock driven current clock master. clock frequency 2.048 MHz, nominally symmetrical. positive going edge indicates beginning bit. H.1x0 MVIP-90 clock times driven current clock master. clock frequency exactly twice transitions synchronous with falling edge /C4. H.1x0 H-MVIP 16.384 Positive active Clock. High transition frame boundary H.1x0 H-MVIP 16.384 Negative active Clock. high transition frame boundary Mode Selection H-Mode M-Mode low=H-Bus normal H.100/H.110 mode (H-Mode) high=H-Bus interface additional interface (port 31), (M-mode) Mode Selection H.100/H.110 H-Bus operates H.100 mode high H-Bus operates H.110 mode Note: must connected MMODE Reset Behavior High
High
/C16+
High
/C16-
High
M-MODE2)
H110-MODE3)
CT_D31, CT_D30, CT_D29. connected required. information sampled during reset. connected required information sampled during reset. must connected M-MODE.
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PRELIMINARY Description
2.2.2
Table
B10, A12, C11, A13, C13, B14, U10, T11, R11, T12, U14, R13,
Local Interface (PCM)
Local Interface
Symbol IN[15:0]1) Function Frame Synchronization Clock Data Clock 2.048 Mbit/s, 4.096 Mbit/s, 8.192 Mbit/s, 16.384 Mbit/s Receive Data Port Reset Behavior High High
OUT[15:0]2)
Transmit Data Port
High
IN15, IN14, IN13. OUT15, OUT14, OUT13.
2.2.3
Table
General Purpose Port
GPIO
Symbol GPIO[7:0]1) Function Reset Behavior
General Purpose port (only 8-bit interface used) Input
D[15:8]
Upper 16-bit interface
GPIO7, GPIO6, GPIO5.
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PRELIMINARY Description
2.2.4
Table
Clock Signals
Clock Pins
Symbol ECLKI ECLKO
Function External Crystal Input 16.384 MHz, 32.768 External Oscillator Input 16.384 MHz, 32.768 External Crystal Output 16.384 MHz, 32.768 General Purpose Clock Output (Framing Signals)
Reset Behavior
Output Output
F17, F16, GPCLK[7:0] E17, F14, E15, C17, E14, NTWK_1
Primary Network Timing Reference Input Optionally synchronized this input which kHz, kHz, 1.536 MHz, 1.544 MHz, 2.048 Secondary Network Timing Reference Input Optionally synchronized this input which kHz, kHz, 1.536 MHz, 1.544 MHz, 2.048
NTWK_2
GPCLK7, GPCLK6, GPCLK5.
2.2.5
Table
JTAG Interface
JTAG Interface
Symbol Function Test Clock Single rate test data clock. Test Mode Select transition this required step through controller state machine. Test Reset Resets controller state machine (asynchronous reset). Test Data appropriate controller state test data instruction shifted this line. Test Data Input appropriate controller state test data instruction shifted this line. High Reset Behavior
TRST
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2.2.6
Table
Microprocessor Interface
Microprocessor Interface
Symbol Function Chip Select Active low. "low" this line selects registers read/ write operations. Read (Intel/Infineon Mode) Indicates read access. Data Strobe (Motorola Mode) During read cycle, indicates that device should place valid data bus. During write access, indicates that valid data bus. Write (Intel/Infineon Mode) Indicates write access. Read/Write (Motorola Mode) Indicates direction data transfer bus. Address Latch Enable Controls on-chip address latch multiplexed mode. While 'high', latch transparent. falling edge latches current address. also evaluated determine mode (ALE 'low' Motorola, 'high' Intel/Infineon) Microprocessor 8/16-Bit Interface Selection ('low' bit, 'high' bit) Interrupt Request This programmable push/pull (active high low) open-drain. This signal activated when SWITI requests interrupt. When operated open drain mode, multiple interrupt sources connected. Address When operated address/data multiplex mode, address pins externally connected bus. Data Input High Reset Behavior
MODE16 IREQ/ IREQ
A[4:0]1)
D[7:0]2)
RESET
System Reset SWITI forced into reset state.
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2.2.7
Table
Power Supply
Power Supply Pins
Symbol Function Power Supply
R10, R14, M15, D17, B15, C10, D10, H14, P10, K14, B13, R12,
VDD5
Reference Voltage tolerant I/Os. Pins must connected signal environment Digital Ground
R8,T10, U13, P13, N16, M17, E16, C14, C12, A11, B16, C15, D14, H10, J10, J14, K10, P14, R15, U2,T15, T17, C16, A16, U16, U17, B17, A17,
VDDA VSSA
Power Supply Analog Logic Used Analog Ground Reserved. Must connected Reserved. Must connected Connected
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Architectural Description
following sections give short overview functionality SWITI.
Functional Block Diagram
Programming
GPIOs
JTAG
µP-Interface
Clocks
Switching Factory
Constant Delay Channel
Line,
Line,
Control
Input Handler
Input Data Memory
Control
Output Handler
Control
Output Data Memory
Minimum Delay
Local
Block Automatic Data Rate Adaption
H.1x0
iti_078.em
Local I/Os
H.1x0 I/Os
Figure
Block Diagram
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Overview Functional Blocks
Switching Factory switching factory responsible transferring handling incoming data streams assigned output channels time-slots. block includes 512, 1024, 2048 byte input output data memory input output connection memory. Local-Bus H-Bus Block block designed handle conversion data provided switching block external H.1x0 interface. performs H.1x0 timing, data rate selection tristate control. Microprocessor Interface Block standard 8-bit multiplexed de-multiplexed interface provided, compatible Intel/Infineon Tech. (e.g. 80386EX, C166) Motorola (e.g. 68040, 68340, 68360, 801) systems. GPIO port needed used provide 16-bit interface. GPIO Block This block supports external port lines each configurable input output. change input line cause interrupt masked). user access port configuration information appropriate registers interface. Clock Block generates frequencies supporting H.1x0, SCbus, MVIP, H-MVIP busses. internal phase-locked loop (PLL) generates frequencies synchronized selected reference signal. output frequency tolerance equal input frequency tolerance. operates from 16.384 MHz, 32.768 external crystal, oscillator. According H.1x0 specification input frequency tolerance must less.
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Switching Factory
shown Figure switching factory comprises input/output data memory input/output data handler with programmed connections. controller handles lines operating same different data rate. establish connection user must only program source line with time-slot destination line with time-slot. internal controller (data handler) writes connection connection descriptor list stores this list connection data handler. programming procedure described Chapter incoming time-slot will stored input data memory controlled input handler. output handler controls constant, minimum delay sub-channel switching.
3.3.1
Switching Modes
SWITI family supports various number switching modes. modes described following chapters.
3.3.1.1
Minimum Constant Delay
Each connection independent addressed buses determined constant delay minimum delay connection. Constant delay means that input timeslot sub-channel available programmed output after frames. Minimum delay means that time-slot sub-channel appears output soon possible. minimum delay depends chosen connections possible range between frames. application note which describes possible connection minimum delays available.
3.3.1.2
Sub-Channel Switching
Sub-Channel switching applicable both local H-Bus constant delay frames. Every connection 1-bit, 2-bit, 4-bit, normal 8-bit connection. possible combine every kind sub-channel connection, e.g. 1bit time-slots with 4-bit time-slot output time-slot. Please refer Chapter 6.11.2 detailed description about programming.
3.3.1.3
Multipoint Switching
described overview multipoint-switching allows switch several input timeslots output time-slot. input data logical connected. This mode selectable with multipoint connection command. setup (logical last connection determines other previous programmed multipoint connections. Multipoint switching always constant delay. Subchannel switching supported.
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3.3.1.4
Broadcast Switching
Broadcast switching allows distribute incoming time-slot different output timeslots. input output mechanism same normal constant delay connection mode with sub-channel switching. Minimum delay also supported without sub-channel switching. table with possible connections minimum delays will provided. broadcast connection programmed same normal connection. output time-slots released with disconnect part broadcast command. last connection must released with normal disconnect command. Sub-Channel Broadcast possible program input time-slot broadcast sub-channel connections. That means bits from input time-slot used several broadcast connections related more output time-slots. output time-slots must released with disconnect part broadcast command. last sub-channel connection must released with normal disconnect command. (Please refer Chapter 6.11.4 example)
3.3.1.5
Bidirectional Switching
input output mechanism same normal constant delay minimum delay connection. exception internal data handling explained following figure. Since internal state machine calculate belonging connection time program bidirectional connection twice time program normal connection. There special command program bidirectional connection. bidirectional connection only programmed available time-slot input/ output line.
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Port Local
minimum delay
Port
Port Local
Port
Issued Command ITSA OTSA Swap Swap ITSA OTSA
Internal ITSA OTSA
Port
Port
switi_067.emf
Figure
Bidirectional Mode
3.3.1.6
Stream-to-Stream Switching
stream-to-stream switching connection supports interoperability H.1x0 with MVIP SCbus, doesn't support local lines. Every dataline selected operation. maximum number switching channels eight. following example page 3-29 using switching channels. stream-to-stream connection established parallel normal connections. output stream-to-stream switch multiplexed with output switching factory, with stream-to-stream having priority. Every stream-to-stream connection must programmed with special command CMD1 register. establish connection must release connection must stream-to-stream connections will released. ISTA1 register indicates that
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more stream-to-stream connections (see also Chapter 6.2). internal control logic avoids wrong selection possible stream-to-stream connections thus prevents collisions. main application stream switch provide inter-rate exchange highway allowing legacy devices exchange data even though they operate different rates with minimum delay zero frames. stream-to-stream connections starts with first frame switching possibilities determined highest rate seen repetition same time-slot (TS) connections from data line another data line. first switching sequence finished starts with same sequence from next available time slots. Figure shows possible time-slot connections. Table Input Data Stream Rate 2.048 Mbit/s Stream-to-Stream Connection Mapping Output Data Steam Rate 2.048 Mbit/s 4.096 Mbit/s 8.192 Mbit/s Mode Time-Slot Connection Partition 4.096 Mbit/s 2.048 Mbit/s 4.096 Mbit/s 8.192 Mbit/s 8.192 Mbit/s 2.048 Mbit/s 4.096 Mbit/s 8.192 Mbit/s
Preliminary Data Sheet
4,., 8,., 9,., 16,., 17,., 18,., 19,., 4,., 4,., 4,., 8,., 9,., 4,., 4,., 4,., 4,., 4,., 4,., 4,.,
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PRELIMINARY Example: input stream with 2.048 Mbit/s, output stream with 8.192 Mbit/s, mode input stream with 8.192 Mbit/s, output stream with 4.092 Mbit/s, mode Architectural Description
Frame Boundary D3@8.192 Mbit/s D1@4.096 Mbit/s D0@2.048 Mbit/s
switi_059.emf
Figure
Example Stream-to-Stream Switching
3.3.2
Parallel Mode Local
parallel mode with 'set parallel mode' command configuration command register. This command first input lines first output lines local parallel bus. data rate lines must 2.048 Mbit/s. parallel mode enabled included lines will 2.048 Mbit/s automatically. parallel mode disabled lines will keep data rate 2.048 Mbit/s until data rate will programmed selected line. internal S/P-converter bypassed. data stream time-slot distributed data lines, every line. least significant assigned line most significant assigned line program connection line must used this special parallel data port. shift value must only programmed port this value will assigned other ports automatically. initialize sequence described Chapter switching data handling same data handling constant delay minimum delay mode. timing diagram provided timing diagram chapter (see "PCM Parallel Mode Timing" page 129).
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3.3.3
Switching Block Error Handling
normal procedure establish connection explained Chapter program connection specific time-slot data line release connection program connection. SWITI switching concept provides internal error handling detect errors switching chain caused programming error. programming error occur because noises data lines, software errors, etc. programming error defined follows: existing connection (minimum, constant delay, message) will released. existing minimum delay connection will established. programming error connection memory overflow detected interrupt IESTA2 register will set. this case last connection which tried establish release valid. switching mechanism affected will continue with switching process. debug purposes SWITI capability write content complete connection memory data memory microprocessor interface. This procedure described Chapter 3.3.4. recommended track established connections with specific customer application software. debug purpose useful compare contents switching memory with virtual connections application software.
3.3.4
Analyze Connection Data Memory
With special command "memory dump enable" connection command register (CCMD) possible read complete memory defined sequence from register with 8-bit access. This feature used only analyze purposes. command disables complete switching function data lines (PCM/ H.1x0) high impedance. command after specific recovery time (200 connection chain data memory read sequentially access register. internal controller writes next 8-bit memory data register read access finished. That means there specific recovery time next read access. internal memory dump controller reads present memory contents input chain memory, data memory output chain memory. During memory dump internal state machine will loose synchronization with external frame structure. Therefore software reset must issued device must programmed again, except clock configuration.
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Infineon Technologies provides software driver recalculate chain recover current connections. detailed explanation internal structure software driver please refer application note "Connection Memory Dump".
3.4.1
Clock Generator General Overview
following figure gives overview about clock generator with integrated PLL.
CT_FRAM CT_FRAME_A /FR_COMP
2,/C 8_A/B EF_1 EF_2
eset
HTSI
T_FR T_FR
8.192M eset ntr. Logic norm Operation 49.152 APLL Bypass 16.384/32.768 2.048M 4.096M 16.384M
2,/C 4,/C VIP-90 2,/C
APLL
phase alignm
fram alignm
Bypass 2.048M clock Slave path
Program able
.1x0 autom atic LKx2 Fsync 8.192M 2.048M 4.096M 16.384M
T_FR T_FR LKx2 2,/C 8_A/B
aster/Slave
2,4,8,16
16.384M from LK[7:0] int. Frequency Input APLL
CT_NETREF_1
CT_NETREF_2
2048
LK[7:0]
used M-Mode
EF_1
EF_2
switi_058.em
Figure
SWITI Clock Generator
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SWITI clock generator provides necessary clock signals SWITI (local bus) H.1x0 interfaces. Since device H.1x0 master capable device there digital PLLs which locked different network reference signals. digital synchronizes external crystal oscillator selected reference clock. digital (DPLL) will bypassed selected reference signal 2.048 MHz. input signal analog (APLL) 2.048 normal operation mode. APLL used multiplying 2.048 clock into 49.152 clock generate clock signals H.1x0, general purpose clock signals. SWITI on-chip oscillator which allows user connect external 16.384 32.768 crystal. Instead using crystal possible assign 16.384 MHz, 32.768 oscillator ECLKI pin. After power-on hardware reset APLL bypassed. APLL will synchronized (after approximately external crystal external oscillator command 'set external frequency' set. This command must used otherwise internal working frequency equal external input frequency SWITI will work properly. APLL locked status 'APLL' ISTA1 register will set. Note: After reset necessary program correct crystal oscillator value first programming step. Otherwise operation frequency SWITI correct.
3.4.2
Features
Analog (APLL)
cycle-to-cycle jitter Natural frequency Damping factor Input Frequency 2.048 case Output Frequency 49.152 MHz, duty-cycle Rule behavior change output frequency range ±10% response changes input frequency phase slope output frequency equal phase slope input frequency Note: necessary provide "noise free" analog power (VDDA/VSSA) reduce internal jitter APLL. These pins must decoupled from digital power (VDD/VSS).
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3.4.2.1
Functional Description
iref fref
frequency detector
up/down
UP/DOWN Counter
igrob
current reference
ibias ibias
fref
phase/ frequency detector
incr decr
Charge pump
VTOI
iint
fosc
iprop
n-divider
locked
Timer
Figure
Block Diagram APLL
value output frequency depends programming n-divider. chosen output frequency SWITI 49.152 input frequency 2.048 MHz. macro consists digital analog which working together. During start-up only digital enabled makes coarse adjustment, that technology dependency circuit compensated. Afterwards digital disabled again analog switched normal operation. digital first order consists frequency detector (FD), up/down counter, digital-to-analog converter (DAC) current controlled oscillator (CCO). detects frequency difference between reference clock (fref: input clock 2.048 MHz) divided oscillator clock. output signal controls counter. reference frequency higher than divided oscillator frequency counter increased. counter output drives current steering which controls input current internal oscillator. current rises output frequency increases until both frequencies equal. digital enabled after reset power disabled after (lock time PLL). counter keeps value output current irough constant until digital reseted.
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second order analog consists phase/frequency detector (PFD), charge pump (CP), loop filter CCO. which sensitive rising edge detects phase frequency difference between input clock (fref) divided output clock (feedback) generates control signal proportional phase difference. output signals down cause charge pump modulate amount charge pass filter (VTOI) integral part (iint) feed current into proportional part (iprop). With these currents output irough controlled. feedback leading fref, oscillator fast. down signal activated subtracts some current iprop. When fref phase with feedback will hold control current that level phase lock will achieved. Thus through this negative feedback arrangement, causes feedback fref signals equal with minimum phase offset. analog becomes unstable, signal pllko generated which resets digital PLL.
3.4.2.2
Jittertransferfunction
Jitter transfers jitter attenuation refers magnitude jitter output device given amount jitter input device. Input jitter applied various amplitudes frequencies, output jitter measured with various filters depending applicable standards. Figure shows jitter transfer function SWITI device. cutoff frequency integrated pass filter kHz.
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20lg |H(f)|
f/fg
Figure
APLL Jitter Transfer Function
3.4.3
Master-Slave Selection
proper working clock fallback mechanism necessary select part master slave with "select master/slave" command CMD1 register. M-Mode used allowed special master command. described Chapter 3.4.6 this command must used finish clock generator configuration and/or finish H.1x0 fallback configuration. reference source selected with "PLL Primary Reference Master Selection" command, with "PLL Source Selection" command.
3.4.4
Phase Alignment
phase alignment function enabled output signal main divider edge synchronized with clock input. selected reference signal less than 2.048 edge synchronization resolution depends selected external crystal/oscillator frequency. phase alignment function disabled output frequency (49.152 MHz) edge synchronized with input frequency main divider output frequencies edge synchronized with output frequency. Note: phase alignment should disabled reference frequencies 2.048 MHz.
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3.4.5
Synchronization
shown Figure there several possibilities synchronize PLLs. synchronization necessary distinguish between different operational modes (H.1x0 with PCM, only PCM). needs approximately lock selected reference frequency. frame synchronization clocking unit needs additionally frames synchronize incoming frame with generated frame. This frame synchronization will enabled device configured H.1x0 slave, H.1x0 secondary master, compatibility slave.
3.4.5.1
Synchronization H-Mode
following operational modes apply HTSI H-Mode. H.1x0 Master Master this mode reference frequency must selected software according H.1x0 specification. H.1x0 clock synchronization guaranteed fact, that synchronized 2.048 clock, generated from digital PLLs, used input clock analog PLL, used generation necessary clocks. reference frequency equal higher than 2.048 digital bypassed reference signal connected with analog PLL. beginning frame equal with beginning H.1x0 frame. H.1x0 Slave Master H.1x0 Slave mode both digital PLLs bypassed input signal analog comes from selected slave path clock sources. clock signals synchronized H.1x0 selected input reference clock signal there isn't phase difference between signals. beginning frame equal with beginning H.1x0 frame. This guaranteed fact, that related frame signal selected clock signal used frame synchronization. H.1x0 Master Slave This mode allowed, since frame start synchronized with H.1x0 frame start. H.1x0 Slave Slave signals must equal highest selected datarate must sourced. incoming clock/frame signals must derived from same clocking source H.1x0 clocks from master with same reference clock H.1x0 master. Since there isn't elasticity switching buffer SWITI incoming clock must synchronized, must have same phase H.1x0 frame start must equal frame start.
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3.4.5.2
Synchronization M-Mode
reference source selected from primary reference master source (PFS, PDC, NTWK_1/_2). selected reference signal less than 2.048 main digital used synchronize analog PLL. digital sourced from external oscillator, crystal. this case analog output frequency tolerance equal external oscillator/crystal frequency tolerance. Furthermore analog sourced directly from external oscillator, crystal, from input. generated output frequencies will have same tolerance selected input frequency.
3.4.6
Error Handling
SWITI H-mode integrated control logic detect possible configuration errors. errors (see below) occurred clock fallback mechanism functionality guaranteed. control mechanism starts with command 'Set H.1x0 Master/Slave (HTSI H-Mode)' CMD1 register. That means that mentioned command finished clock generator configuration. shown Figure there cntr. logic APLL multiplexer implemented. first multiplexer used select reference source master mode second multiplexer used decide between slave master path. main task this control logic make sure that input signal APLL derives from internal oscillator (external oscillator) after reset. second task control input signal APLL during normal operation decide whether programmed combination correct. following combinations occur, control logic selects internal oscillator, resets complete clock generator configuration interrupt will generated wrong source programming). Configuration errors which will detected: HTSI H-Mode Master configuration PLL2 source selected (slave path) HTSI H-Mode Slave configuration main secondary master reference selected Furthermore fallback state machine controls logic multiplex necessary signal fallback mechanism. Since there redundant paths reference clock also slave clocks clock fallback time depends only multiplexer delay time.
3.4.7
Clock Fallback
This chapter must read SWITI used H.1x0 device (H-mode).
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3.4.7.1
Clock Signal Monitoring
support clock fallback mechanism SWITI capability monitor CT_CA (CT_C8_A/CT_FRAME_A), CT_CB (CT_C8_B/CT_FRAME_B) clocks additional with selected primary reference, monitor interoperability clock signals. SWITI reports every clock failure host with interrupt masked. interrupt masked status clock errors read from IESTA1 IESTA2 registers (polling). H.1x0 clock signal monitoring will start immediately after programming reference clock. process finished with command 'master slave' from CMD1 register. following monitoring requirements H.1x0 must meet: received rising edge CT_C8_A/B (both signals must controlled independently) doesn't arrive within 35ns expected edge. There exactly 1024 clock periods frame. these requirements meet interrupt will generated masked) inform system software that clock circuits failed. following monitoring requirements interoperability clock signals must meet. /FR_COMP monitored conjunction with selected primary reference (master) signal with selected source (slave). MVIP received rising edge doesn't arrive within expected edge. There exactly 256, 512, 1024, 2048 clock periods frame SCbus received rising edge SCLK doesn't arrive within expected edge. There exactly (SCLK=2 MHz), 512, 1024 clock periods frame. NTWK Signals received rising edge NTWK signal doesn't arrive within expected edge.
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3.4.7.2
Clock Fallback Mechanism
clock fallback mechanism switched with special command "H.1x0 Fallback Mechanism Clock Monitoring" related instruction bits. described H.1x0 specification there different fallback path's fallback state machine. instruction "fallback from main secondary reference (primary master)" conjunction with command "automatic switch back main ref." covers "primary NTWK link fails" path. correct reference (main secondary) described H.1x0 specification must programmed, e.g. NTWK CT_NETREF. instruction "fallback from main secondary reference (secondary master)" "from clock clock (Slave)" covers "primary master clock circuit fails" path fallback state machine.
CT_C8_A; /CT_FRAME_A CT_C8_B; /CT_FRAME_B CT_NETREF_1 CT_NETREF_2
NTWK_1 fails Primary Master NTWK_1 returns Primary Master
NTWK_1
NTWK_2
NTWK_1
NTWK_2
means clock driving synchronized this reference clock
switi_024.wmf
Figure
Clock Fallback Primary Master
primary master synchronized reference clock (NTWK CT_NETREF) drives CT_C8_A /CT_FRAME_A clocks. Figure shows configuration example. primary network reference clock (NTWK_1) fails device automatically synchronizes secondary network reference clock (NTWK_2). primary reference clock returns device synchronize again automatically software command (depends configuration). masked failure reported interrupt.
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CT_C8_A; /CT_FRAME_A CT_C8_B; /CT_FRAME_B CT_NETREF_1 CT_NETREF_2
Architectural Description
CT_C8_A fails Secondary Master Secondary Master
NTWK_1
NTWK_2
NTWK_1
NTWK_2
means clock driving synchronized this reference clock
switi_025.wmf
Figure
Clock Fallback Secondary Master
secondary master synchronized CT_C8_A, CT_FRAME_A drives CT_C8_B CT_FRAME_B. CT_A clocks fail device synchronize automatically software command (depends configuration) another reference clock (NTWK CT_NETREF). Figure shows configuration example. masked failure reported interrupt. reference fallback must programmed again automatic fallback reference performed. fallback re-programming will performed without data loss device.
Preliminary Data Sheet
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PRELIMINARY
CT_C8_A; /CT_FRAME_A CT_C8_B; /CT_FRAME_B CT_NETREF_1 CT_NETREF_2
Architectural Description
CT_C8_A fails Slave Slave
NTWK_1
NTWK_2
NTWK_1
NTWK_2
means internal clock synchronized this reference clock square means Netref providing synchronized this reference clock
switi_026.wmf
Figure
Clock Fallback Slave
slave synchronized CT_C8_A CT_FRAME_B. clock fails slave synchronizes automatically software command CT_C8_B CT_FRAME_B. masked failure reported interrupt. case automatic fallback CT_CB CT_CA clocks reference must programmed. fallback re-programming source will done without data loss regarding Stratum specification. Additionally fallback must issued again needed.
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Loops
loop command configuration command register CMD2 provides support automatic PCM-PCM H.1x0-H.1x0 loops. PCM-PCM loop input lines connected with corresponding output line. H.1x0-H.1x0 loop first H-bus lines connected with corresponding upper H-bus lines. e.g. H16; H17; After loop disable command lines will high-impedance after approximately frames.
Read SWITI Configuration with Indirect Register Addressing
Since SWITI configuration programmed with defined instructions CMD1 CMD2 registers possible read current configuration through indirect access registers. indirect addressing started writing five read configuration commands CMD2 register. five commands separated groups, internal configuration external line configuration. internal configuration, e.g. clock generator, IREQ read with command "Read Configuration". internal settings decoded with instruction bits I3.0. data rate H.1x0 interface read with "Read H.1x0 Line Configuration" commands GPCLK line configuration shift value "Read GPCLK Configuration" "Read Bit/Clock Shift Configuration" must issued. registers contain required information after internal read process complete. recovery time read correct configuration data from register allowed command "Read Time Slot Value" before register been read.
Preliminary Data Sheet
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3.7.1
Power-On Reset Behavior Hardware Reset
There three independent active reset pins: RESET, /CT_RESET TRST. RESET /CT_RESET conjunction with mode pins M-Mode H.110 Mode) activated, immediately places outputs ports into tri-state, except ECLKO pin. After reset process correct external frequency must with command 'Set external frequency' accordingly. This command starts configuration process APLL. APLL locked after During this period APLL bypassed internal frequency 2.048 MHz. APLL locked internal frequency will 49.152 MHz. Individual output sections must enabled setting command configuration command register CMD1, CMD2. Internally state machines, counters registers cleared their defined reset value. H.110 controller reset state H.110 pins tri-stated long /CT_RESET asserted. (see CT_RESET" page RESET /CT_RESET pins don't control boundary scan register TAPcontroller. TRST asserted TAP-controller will into Test-Logic-Reset state outputs pins will tri-stated, except ECLKO pin.
3.7.2
Software Reset
software reset accomplished setting 'Set Software Reset' command CMD2 register. software reset clears complete device except clocking unit temporary microprocessor registers (e.g. CMD1). software reset deactivated with 'Set Software Reset' command. During software reset microprocessor interface doesn't accept other commands.
Preliminary Data Sheet
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PRELIMINARY Description Interfaces
Description Interfaces
Local Interface (PCM)
local interface consisting input output data lines (IN, OUT), data clock frame synchronization signal PFS.
lock lave
iti_0
lock aster
Figure
Interface Configurations
Frame Sync signal delimiting frame. This input signal used SWITI determine start frame. frame divided into 8-bit wide time slots. amount time slots within frame depends selected data rate which 2.048 Mbit/s, 4.096 Mbit/s, 8.192 Mbit/s, 16.384 Mbit/s. input Schmitt-Trigger characteristic. Data Clock input supply SWITI with data clock. operated with 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 data rate clock depending selected highest data mode. clock signal must equal higher highest data rate. input Schmitt-Trigger characteristic. clock slave must receive whereas clock master drives these signals. enable disable signals clock master command 'PCM Clock Input/ Output Selection' must issued. time slots transmitted received input output lines (IN[15:0], OUT[15:0]). input lines have Schmitt-Trigger characteristic. output lines have tristate outputs with push-pull characteristic. every time slot participating connection output high impedance. With special command "Local (PCM) Standby" CMD2 register possible lines high impedance state during normal operation mode. lines high impedance state after reset process must enabled with "Local (PCM) Standby" command. lines which participating switching operation high impedance state time-slot information input lines discarded automatically.
Preliminary Data Sheet
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Description Interfaces
Data Rate Selected Line Input ffset Input ffset
utputs ffset
iti_039.em
Figure
Shifting
each input line offset time-slot zero adjusted range from half clock resolution before after rising edge. output lines offset time-slot zero adjusted range from half clock resolution after rising edge. resolution depends selected data rate that means resolution doesn't depend signal. After reset process shift disabled lines. That means time-slot starts with rising edge PFS. input data will sampled with falling edge selected data rate output data valid with rising edge selected data rate.
Preliminary Data Sheet
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PRELIMINARY Description Interfaces
H-Bus Interface
T_FR driven aster 8.192 driven aster duty cycle T_FR redundant; driven aster ignals 8.192 redundant; driven aster duty cycle [31:0]: 4096 1.544 2.048 duty cycle sync*); 2.048, 4.096, 8.192 x2*: double frequency 2.048 4.096 16-:
iti_
aster ignals patibility bus, -90,
Figure
H-Bus Interface H.100 Mode
Preliminary Data Sheet
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PRELIMINARY Description Interfaces
driven aster 8.192 driven aster duty cycle redundant; driven aster 8.192 redundant; driven aster duty cycle ignals [31:0]: 4096 F_1: 1.544 2.048 duty cycle F_2: 1.544 2.048 duty cycle indication that fully seated (Fsync*) Inter-operability 8.192 8.192
iti_
Figure
H-Bus Interface H.110 Mode
Note: frequency SCLK H.110 mode 8.192 only.
4.2.1
CT_C8(A/B) /CT_FRAME(A/B)
functional timing relationship clocks /CT_FRAME found chapter "H-Bus (Local Bus) Frame Structure" Page 130. /CT_FRAME signal delimiting frame. negative pulse, nominally wide marks beginning first first time-slot. CT_C8 8.192 clock. duty cycle this signal nominally 50%. H.1x0 slave must receive CT_C8 /CT_FRAME whereas clock master drives these signals.
4.2.2
Dataports
There bidirectional pins available accessing H-bus. frame structure shown Chapter 7.3. every there tri-state controller. /CT_EN signal enables tri-state controller H.110 data lines. With special command "PCM H.1x0 Standby" CMD2 register possible H.1x0 lines high impedance state during normal operation mode. H.1x0 lines high
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PRELIMINARY Description Interfaces
impedance state after reset process must enabled with "PCM H.1x0 Standby" command. lines which participating switching operation high impedance state. default data rate 8.192 Mbit/s accordance H.100/H.110 specification. With configuration command register possible select individual data rate from 2.048 Mbit/s, 4.096 Mbit/s, 8.192 Mbit/s accordance support interoperabilitiy busses.
4.2.3
/CT_EN
/CT_EN signal must implemented identical manner implementation BD_SEL# signal specified PICMG CompactPCI Swap specification connecting /CT_EN logic high (de-asserted) through 1.2K resistor current source equivalent. /CT_EN signal indicates that board fully seated. H.110 interface logic enabled /CT_EN signal active (logic level enables H.110 ports, ports, clock signals).
4.2.4
/CT_RESET
/CT_RESET must functionality electrically equivalent CompactPCI signal RST#. device must respond /CT_RESET signal when asserted. H.110 outputs I/Os high impedance until /CT_RESET released well related outputs I/Os. clocking signal influence internal logic during reset state. internal state machines counters defined reset state after /CT_RESET signal released connection memory reset state. After /CT_RESET signal released device configured with configuration command register (CMD1, CMD2). RESET /CT_RESET conjunction with mode pins M-Mode H.110 Mode) signals logical connected.
4.2.5
H-MVIP /C16 Signals
differential signal driven clock master used read write bits serial data lines. Time-slot boundaries align with falling edge /C16+. /C16 signal differential. SWITI doesn't have integrated differential receiver/ transceiver with required thresholds standard RS-485. Nevertheless differential /C16+, /C16- input signals logical decoded internal /C16 signal SWITI configured clock slave. /C16- inverted /C16+ signal SWITI shall generate /C16+, /C16- signals.
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Data Rate
SWITI provides programming different data rates data lines including H.100/H.110 bus. support H.100/H.110 interoperability systems H.100/H.110 data lines operate with 2.048 MHz, 4.096 MHz, 8.192 independently. local lines operate with 2.048 MHz, 4.096 MHz, 8.192 independently local lines HTSI M-mode local lines HTSI H-mode operate with 16.384 MHz, too. maximum data rate selected lines (local bus) Mbit/s HTSI. That means summary selected data rate lines must equal less Mbit/s. PCM0.7 lines data rate Mbit/s corresponding (PCM0.7 line will deactivated (tri-state). input output lines independent each other. following table shows possible data rates different lines. Table
HTSI-M HTSI-H
Data Rates Local H-Bus
PCM0.7 (IN/OUT) 2/4/8/16 Mbit/s 2/4/8/16 Mbit/s PCM8 (IN/OUT) 2/4/8 Mbit/s 2/4/8 Mbit/s PCM16.31 (IN/OUT) 2/4/8/16 Mbit/s H0.31 2/4/8 Mbit/s
Microprocessor Interface
standard 8-bit multiplexed non-multiplexed interface provided, compatible Intel/Siemens (e.g. 80386EX, C166) Motorola (e.g. 68040, 68340, 68360, 801) systems. GPIO port needed used provide 16-bit interface. 16-bit mode determined according MODE16 input pin. MODE16 8-bit interface MODE16 16-bit interface This chapter describes configure interface each mode.
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4.4.1
Intel/Siemens Motorola Mode
Intel/Siemens Motorola mode interface configured during hardware reset process conjunction with pin. permanently driven 'low' Motorola mode permanently driven 'high' Intel/Siemens mode Edge Intel/Siemens multiplexed mode falling rising edge during normal operation selects multiplexed mode immediately. With hardware reset tied possible return Motorola Intel/Siemens mode.
4.4.2
De-multiplexed Multiplexed Mode
both modes, A-bus D-bus used parallel. A-bus should connected LSBs AD-bus, coming from also multiplexed mode. next figure describes connection address data buses different modes. Note: Motorola mode used only with de-multiplexed bus. Intel/Siemens mode used with both, multiplexed de-multiplexed bus.
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Multiplexed Mode
8/16
SWITI
LATCH
De-multiplexed Mode
8/16
SWITI
LATCH
Figure
Multiplexed De-multiplexed Mode
Note: both modes only LSBs A-bus AD/bus connected Address inputs.
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General Purpose Port (GPIO)
This port consists lines each configurable input output. change input line cause interrupt masked). user access port configuration information appropriate registers interface. Figure shows example.
1->0
Signal GPIO
GPIO Direction Register
Line outputs Line inputs Changes line line cause interrupts Drive 1010 lines [7:4] Contains current value input lines Change input line detected
switi_055.emf
GPIO Mask Register
GPIO Output Register
GPIO Input Register
GPIO Interrupt Register
don't care
Figure
GPIO Port Configuration Example
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General Purpose Clocks
SWITI provides general purpose clock lines. With independent commands CMD2 register lines configured frame group signals individual clock signals. last written command line valid controls multiplexer.
4.6.1
Frame Group Outputs
output lines possible provide different framing signals which used synchronization purpose. signals have period Their offset programmed individually within determined frame resolution 16.384 MHz). default start point offset beginning frame (rising edge clock signal). start point offset shifted half clock cycle, that means second start point determined with rising edge next falling edge clock signal shown Figure 23). high time signal also programmed steps frame signals controlled high active.
125µs
16.384 Mbit/s
125µs
Frame Signal
switi_038.emf
Figure
Frame Signal Example
Figure shows example frame signal beginning with rising edge 64th clock cycle with length clock cycles. Further programming examples found
4.6.2
GPCLK Clock Outputs
GPCLK lines configured individual clock outputs with kHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 test purposes with internal frequency input frequency analog (APLL). clock signals generated from analog output frequency which internal frequency. quality output frequency signals depends quality selected input frequency.
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JTAG (Boundary Scan)
SWITI provides fully IEEE 1149.1 compatible boundary scan support consisting complete boundary scan chain Test Access Port controller (TAP controller) five dedicated pins: TCK, TMS, TDI, TRST asynchronously reset controller 32-bit IDCODE register
4.7.1
Boundary Scan
pins except power supply crystal included boundary scan. Depending functionality (input), (output, enable) three (input, output, enable) boundary scan cells provided. maximum clock rate MHz.
4.7.2
Test-Access-Port (TAP)
following signal pins allow boundary scan test logic accessed: Test Clock input which central test clock applied. This test clock independent system clock. Clock phases derived from this clock test sequence control. Test Mode Select control input which desired status changes controller applying certain level (0/1) caused rising edge TCK. Test Data Input whose data inserted into test logic with rising edge TCK. Test Data Output with tristate capability which only active during SHIFT-IR SHIFT-DR controller state, whose data driven with falling edge TCK.
4.7.3
Controller
Test Access Port (TAP) controller implements state machine defined JTAG standard IEEE 1149.1.
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Transitions cause controller perform state change. possible instructions listed following table. Table Code 0000 0110 0101 0001 0111 0100 1111 Controller Instructions Instruction EXTEST INTEST IDCODE CLAMP HIGHZ BYPASS Function External testing Internal testing Reading code Reading outputs High impedance state boundary scan outputs Bypass operation
SAMPLE/PRELOAD Snap-shot testing
instruction length four bit. EXTEST used verify board interconnections. When controller state "update DR", output pins updated with falling edge TCK. When entered state "capture levels input pins latched with rising edge TCK. in/out shifting scan vectors typically done using instruction SAMPLE/PRELOAD. INTEST supports internal chip testing. When controller state "update DR", inputs updated internally with falling edge TCK. When entered state "capture levels outputs latched with rising edge TCK. in/out shifting scan vectors typically done using instruction SAMPLE/PRELOAD. SAMPLE/PRELOAD SAMPLE/PRELOAD instruction enables signal pins (inputs outputs) sampled during operation (SAMPLE) result shifted through shift register. function internal logic influenced this instruction. While shifting out, cells serially loaded same time with defined values through (PRELOAD). SAMPLE/PRELOAD instruction selects boundary scan register normal mode. state CAPTURE-DR data loaded into boundary scan register with rising edge TCK. state UPDATE-DR contents boundary scan register written into second register stage boundary scan register. This data becomes effective outputs only instruction been activated that sets register test mode: e.g. EXTEST CLAMP.
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PRELIMINARY IDCODE 32-bit identification register serially read TDO. contains version number bits), device code bits) manufacturer code bits). fixed '1'. Version xxxx Device Code xxxx xxxx xxxx xxxx Manufacturer Code xxxx xxxx xxxx Output Description Interfaces
Table HTSI HTSI-L HTSI-XL
Boundary Scan IDCODE Version 0001 0001 0001 Device Code Manufacture Code Bit0 0001 1011 0000 1000 0001 1011 0000 1000 0001 1011 0000 1000
CLAMP register test mode. duration CLAMP instruction, BYPASS register selected that minimal shift path created. During SHIFT-DR data shifted through BYPASS register. contents register does change during UPDATE-DR state.
HIGHZ HIGHZ instruction disables outputs switched high impedance state. outputs switched high impedance state UPDATE-IR. outputs redefined according next instruction another instruction become active with UPDATE-IR. selected test data register BYPASS register. BYPASS, entering shifted after clock cycle, e.g. skip testing selected printed circuit board.
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Identification Code Read Access
SWITI offers possibilities read identification code. JTAG port described Chapter processor interface After hardware reset identification code stored General Purpose Interrupt Register (GPI) read processor interface. high nibble version number nibble equal nibble device code shown Table 8-bit interface configuration first write access General Purpose Mask Register (GPM) will reset register 00H. interface configured 16-bit interface IDCODE always read from register, that means register will reset. IDCODE read access shown Table Table IDCODE Read Access 8-Bit IDCODE (MSB.LSB) Version HTSI HTSI-L HTSI-XL 0001 0001 0001 Device Code 1101 1110 1111
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PRELIMINARY Register Description
Register Description
register description gives information about registers accessible microprocessor interface according address, short name, access, reset value value range.
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PRELIMINARY Register Description
Table Name ITSA OTSA CCMD CMD1 CMD2 ISTA1
Register Overview 8-Bit Interface
Register Overview 8-Bit Interface Access 8-bit Reset Address Value RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR RD/WR Comment Source Port Address Register Value range Table Input Time Slot Address Register Value range Table Destination Port Address Register Value range Table Output Time Slot Address Register Value range Table Sub-Channel Address Register Value range Table General Input Register General Input Register Connection Command Register Configuration Command Register Configuration Command Register Message Value Register Interrupt Status Register Interrupt Error Status Register Interrupt Error Status Register Interrupt Mask Register Interrupt Error Mask Register Interrupt Error Mask Register General Purpose Port Input Register General Purpose Port Output Register General Purpose Direction Register General Purpose Mask Register Time Slot Value Register Configuration Register Page
IESTA1 IESTA2 INTM1 RD/WR INTEM1 RD/WR INTEM2 RD/WR GPPI GPPO RD/WR RD/WR
IDCODE General Purpose Interrupt Register
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PRELIMINARY Table Value Range SPA/DPA Value Range Bit4.0 15.0 31.0 31.0 Register Description
Addressed Lines Local-Bus input lines (H-Mode) Local-Bus input lines (M-Mode) H-Bus lines (H-Mode)
Table Data Rate 2.048 Mbit/s 4.096 Mbit/s 8.192 Mbit/s
Value Range ITSA/OTSA Range Bit7.0 31.0 63.0 127.0
16.384 Mbit/s 255.0
Table Mode
Value Range Range
1-bit switching ISCA0.2; OSCA0.2 2-bit switching ISCA0.1; OSCA0.1 4-bit switching ISCA0; OSCA0
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PRELIMINARY Register Description
Detailed Register Description 8-bit Interface
RD/WR Address:
Source Port Address Register Reset value:
Type (must logical M-mode) Local H-bus
PA4.0 Port Address
Input Time Slot Address Register Reset value: ITSA TSA7 TSA6 TSA5
RD/WR
Address:
TSA3
TSA2
TSA1
TSA0
TSA4
TSA7.0 Time Slot Address
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PRELIMINARY Destination Port Address Register Reset value: RD/WR Register Description Address:
Type (must logical M-mode) Local H-bus
PA4.0 Port Address
Output Time Slot Address Register Reset value: OTSA TSA7 TSA6 TSA5
RD/WR
Address:
TSA3
TSA2
TSA1
TSA0
TSA4
TSA7.0 Time Slot Address
Sub-Channel Address Register Reset value:
RD/WR
Address:
OSCA2 OSCA1 OSCA0 ISCA2 ISCA1 ISCA0
OSCA2.0 Output Sub-Channel Address ISCA2.0 Input Sub-Channel Address
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PRELIMINARY General Input Register Reset value: RD/WR Register Description Address:
GV7.0 General Value case Reference (main secondary) Selection Command (CMD1) content this register interpreted follows: GV2.0 Clock Frequency 1.536 1.544 2.048 4.096 8.192 16.384
case CT_NETREF_1/2 Output Selection Command (CMD1) content this register interpreted follows: GV1.0 Output CT_NETREF_1/2 Clock Frequency 2.048
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PRELIMINARY Register Description
case Shift Command (CMD1) content this register interpreted follows: Byte shift value (only input lines) shift applies before rising edge shift applies after rising edge GV3.1 shift value (range: Edge Control (half clock shift) data transmit with rising edge sampled with falling edge data transmit with falling edge sampled with rising edge
case GPCLK Frame Signal Command (CMD2) content this register interpreted follows: GV7.2 Offset within frame number 16.384 clock cycles (lower bits; refer upper part) Edge Control data changes with rising edge sampled with falling edge data changes with falling edge sampled with rising edge Reserved
case GPCLK Clock Signal Command (CMD2) content this register interpreted follows: GV2.0 Output Frequency selected line 2.048 4.096 8.192 16.384 Input Analog (2.048 MHz) Internal Frequency (49.152 MHz)
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PRELIMINARY General Input Register Reset value: RD/WR Register Description Address:
GV7.0 General Value
case GPCLK Frame Signal Command (CMD2) content this register interpreted follows: GV7.5 Width pulse number 16.384 clock cycles from i.e. GV7.5 clock cycle, GV7.5 clock cycles GV4.0 Offset within frame number 16.384 clock cycles (upper bits; refer lower part)
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PRELIMINARY Connection Command Register Reset value: CCMD RD/WR Register Description Address:
CC3.0 Command Code 0000 operation 0001 Constant Delay Connection Command (incl. Broadcast Connection) (SPA, ITSA, DPA, OTSA, considered) I1.0 Sub-Channel Mode 8-bit wide time slots 4-bit wide time slots 2-bit wide time slots 1-bit wide time slots
0010 Minimum Delay Connection Command (incl. Broadcast Connection) (SPA, ITSA, DPA, OTSA considered) 0011 Send Message Command (always Constant Delay) (DPA, OTSA, considered) 0100 Stop Message Command (DPA, OTSA considered) 0101 Disconnect Command (SPA, ITSA, DPA, OTSA, considered) I1.0 I1.0 Constant Delay Connection Command (incl. Broadcast Connection)
0110 Disconnect Part Broadcast Command (SPA, ITSA, DPA, OTSA, considered) I1.0 I1.0 Constant Delay Connection Command (incl. Broadcast Connection)
0111 Multipoint Connect Command (SPA, ITSA, DPA, OTSA considered) Multipoint MODE logical connection logical connection
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PRELIMINARY 1000 Disconnect Command 1001 Bidirectional Connect Command (SPA, ITSA, DPA, OTSA considered) Delay MODE Minimum Delay Constant Delay Register Description
1010 Memory Dump (Connection Data Memory) Memory Dump disable enable
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PRELIMINARY Configuration Command Register Reset value: CMD1 RD/WR Register Description Address:
CC3.0 Command Code 0000 operation 0001 H.100/H.110 Master/Slave (HTSI H-Mode) Must programmed only after input initialization and/or H.1x0 fallback command Mode Information Slave mode Master mode
0010 Primary Reference Selection Command Master (GI1 considered frequency) I3.0 Synchronization Information 0000 synchronization internal oscillator (default) 0001 synchronizes (only M-Mode) 0010 synchronizes (only M-Mode) 0011 synchronizes CT_NETREF_1 (only Hmode) 0100 synchronizes CT_NETREF_2 (only Hmode) 0101 synchronizes NTWK_1 0110 synchronizes NTWK_2 0111 synchronizes CT_A (CT_C8_A CT_FRAME_A) (only H-mode, isn't considered) 1000 synchronizes CT_B (CT_C8_B CT_FRAME_B) (only H-mode, isn't considered) 1001 used 1010 used 1011 synchronizes /FR_COMP (only H-mode) 1100 synchronizes SCLK (only H-mode)
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PRELIMINARY Register Description 1101 synchronizes (only H-mode) 1110 synchronizes (only H-mode) 1111 synchronizes /C16 (only H-mode) 0011 Secondary Reference Selection Command Master (only Hmode) (GI1 considered frequency) I3.0 Synchronization Information 0000 synchronization internal oscillator (default) 0001 synchronizes CT_NETREF_1 0010 synchronizes CT_NETREF_2 0011 synchronizes NTWK_1 0100 synchronizes NTWK_2 0101 synchronizes CT_C8_A 0110 synchronizes CT_C8_B 0111 synchronizes /CT_FRAME_A 1000 synchronizes /CT_FRAME_B 1001 synchronizes /FR_COMP 1010 synchronizes SCLK 1011 synchronizes SCLKx2 1100 synchronizes 1101 synchronizes 1110 synchronizes /C16 0100 Source Selection Command. Slave Path (only H-mode) I3.0 Source/Frequency Information 0000 used 0001 0010 0011 0100 0101 0110 0111 1000
Preliminary Data Sheet
used used used used CT_A (CT_C8_A CT_FRAME_A) CT_B (CT_C8_B CT_FRAME_B) SCLK 2.048 /FR_COMP SCLK 4.096 /FR_COMP
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PRELIMINARY 1001 1010 1011 1100 Register Description SCLK 8.192 /FR_COMP 2.048 /FR_COMP 4.096 /FR_COMP /C16 16.384 /FR_COMP
0101 H.100/H.110 Clock Output Selection Command (only H-mode) M-mode must issued. I1.0 Activation Information I3.2 disable /CT_FRAME CT_C8 (default) enable /CT_FRAME_A CT_C8_A enable /CT_FRAME_B CT_C8_B
used must
0110 Clock Input/Output Selection Command (Default: inactive) I2.0 Frequency Information reserved enable 2.048 enable 4.096 enable 8.192 enable 16.384 Input Output
Direction Information
0111 Compatibility Clock Output Selection Command (only H-mode) MVIP-90 Activation Information I3.2
Preliminary Data Sheet
disable MVIP-90 /C4, /FR_COMP (default) enable MVIP-90 /C4, /FR_COMP disable H-MVIP /C4, /C16, /FR_COMP (default) enable H-MVIP /C4, /C16, /FR_COMP disable SCbus SCLK, SCLKx2, Fsync* (default) enable SCbus 2.048 enable SCbus 4.096
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H-MVIP Activation Information
SCbus Activation/Frequency Information
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PRELIMINARY enable SCbus 8.192 Register Description
1000 CT_NETREF_1 Output Selection Command (only H-mode) Inversion Information I3.1 normal CT_NETREF_1 output invert CT_NETREF_1 output disable CT_NETREF_1 (default) enable CT_NETREF_1 source NTWK_1 enable CT_NETREF_1 source NTWK_2 enable CT_NETREF_1 source NETREF_2 enable CT_NETREF_1 source internal oscillator (GI1 considered output frequency)
Activation Information
1001 CT_NETREF_2 Output Selection Command (only H-mode) Inversion Information I3.1 normal CT_NETREF_2 output invert CT_NETREF_2 output disable CT_NETREF_2 (default) enable CT_NETREF_2 source NTWK_1 enable CT_NETREF_2 source NTWK_2 enable CT_NETREF_2 source NETREF_1 enable CT_NETREF_2 source internal oscillator (GI1 considered output frequency)
Activation Information
1010 H.100/H.110 Fallback Mechanism I1.0 Source (only H-mode) disable (default) from Main Ref. Secondary Ref. SWITI Primary Master system) from Main Ref. Secondary Ref. SWITI Secondary Master system) from clock clock (Slave)
Re-Fallback Activation Information Primary Master (only H-mode)
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PRELIMINARY Register Description disable automatic switch back main ref. (default) enable automatic switch back main ref.
Phase Alignment Note: phase alignment must disabled reference frequencies 2.048 disable (default after reset) enable Must H.1x0 slave
1011 Rate Command Local (Default lines 2.048 Mbit/s) I1.0 Base Rate Information 2.048 Mbit/s 4.096 Mbit/s 8.192 Mbit/s 16.384 Mbit/s effect rate local input lines (SPA considered) effect rate local output lines (DPA considered)
Destination Information
Destination Information
1100 Rate Command H.100/H.110 Interoperability Bussystems (Default lines 2.048 Mbit/s) I1.0 Base Rate Information 2.048 Mbit/s (SPA considered) 4.096 Mbit/s (SPA considered) 8.192 Mbit/s (SPA considered) lines 8.192 Mbit/s
1101 Read Time Slot Command Destination Information read input time slots(SPA, ITSA considered) read output time slots(DPA, OTSA considered)
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PRELIMINARY Register Description
1110 Stream Stream Switch Command (SPA, considered) (The value equal) command affects H-Bus only depends selected rate I1.0 Connection (see Figure page depends selected every line Mode Mode Mode Mode release current stream stream connection establish current stream stream connection reserved release programmed stream stream connections
Connection Information
Destination Information
1111 Shift Command (GI1 considered shift value) (Default: Shift inactive) I1.0 Direction Control shift value input line (SPA considered) shift value input lines shift value output lines shift value lines (input output)
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PRELIMINARY Configuration Command Register Reset value: CMD2 RD/WR Register Description Address:
CC3.0 Command Code 0000 operation 0001 External Frequency (Must programmed first) External Frequency 32.768 16.384
0010 Parallel Mode (Local only) first local input lines parallel input lines first local output lines parallel output lines. Parallel Mode I1.0 disable enable
0011 IREQ Command IREQ (Default: IREQ inactive) IREQ active IREQ active high IREQ open-drain
Interrupt Time-Out Counter inactive time between consecutive interrupts disable enable
0100 H.1x0 Standby Command High Impedance outputs tristated (default) outputs enabled
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PRELIMINARY Register Description H.1x0 High Impedance (only H-mode) I/O's tristated (default) I/Os enabled
used must Internal Clock Synchronization Must clock master mode Must clock slave mode
0101 Loop Command PCM-PCM Loop disable (default) enable disable (default) enable
H.100/H.110 Loop (only H-mode)
0110 GPCLK Frame Signal Command (GI1, considered) (Default: GPCLK's tristated) I2.0 GPCLK Line (7.0) Invert Mode frame signal high active frame signal active
0111 GPCLK Clock Signal Command (GI1 considered frequency) (Default: GPCLK's tristated) I2.0 GPCLK Line (7.0) 1000 Range Data Rate Command avoid loss data this command should issued only once after reset. range data rate changed later loss data must expected four frames. (Additionally H-mode 8.192 Mbit/s must set.) I3.0 Range Select specify range codes have logical combined. 0001 2.048 Mbit/s (default) 0010 4.096 Mbit/s
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PRELIMINARY 0100 8.192 Mbit/s 1000 16.384 Mbit/s 1001 Read Configuration I3.0 Select Configuration Command 0000 Master/Slave Configuration (only H-mode) 0001 Primary Master Source 0010 Secondary Master Source (only H-mode) 0011 Source (Slave Path) (only H-mode) 0100 Clock Output Selection H.1x0 (only H-mode) 0101 Clock Output Selection 0110 Clock Output Selection Interoperability Signals (only H-mode) 0111 Output Selection CT_NETREF_1 (only H-mode) 1000 Output Selection CT_NETREF_2 (only H-mode) 1001 Fallback Mechanism Phase Alignment 1010 External Input Frequency 1011 Parallel Mode 1100 IREQ 1101 H.1x0/PCM Standby 1110 Loop 1111 Range Data Rate 1010 Read GPCLK Configuration I2.0 GPCLK Line Destination Information Read Data Rate Input Line (SPA considered) Read Data Rate Output Line (DPA considered) 1011 Read Line Configuration Register Description
1100 Read H.1x0 Line Configuration (SPA considered) (only H-mode) 1101 Read Shift Configuration Destination Information Shift Value Input Line (SPA considered) Shift Value Output Lines
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PRELIMINARY 1110 Reserved 1111 Software Reset Software Reset Deactivate Software Reset (default) Activate Software Reset Register Description
Preliminary Data Sheet
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PRELIMINARY Message Value Register Reset value: RD/WR Register Description Address:
MV7.0 Message Value
Interrupt Status Register Reset value: ISTA1 APLL
Address:
GPIO
APLL APLL lock indication locked bypassed locked Stream Stream Indication stream stream connection stream stream connections Error2 Interrupt Change Indication (not active 16-bit mode) change according error2 interrupt status register detected change according error2 interrupt status register detected Error1 Interrupt Change Indication change according error1 interrupt status register detected change according error1 interrupt status register detected GPIO General Purpose Change Indication change according port inputs detected least change according port inputs detected Time Slot Arrived Indication there time slot value register
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PRELIMINARY there time slot value register Further Connections Indication establishing connections possible maximum amount connections reached Ready Indication CCMD ready written CCMD ready written Register Description
Interrupt Error Status Register Reset value: IESTA1
Address:
CT_NETREF_2 Failure Indication CT_NETREF_1 Failure Indication CT_C8_B CT_FRAME_B Failure Indication CT_C8_A CT_FRAME_A Failure Indication NTWK_2 Failure Indication NTWK_1 Failure Indication failure detected failure detected
Interrupt Error Status Register Reset value: IESTA2
Address:
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PRELIMINARY Connection Memory Error/Overflow Indication Source Failure Indication FR_COMP Failure Indication SCLK2 Failure Indication SCLK Failure Indication Failure Indication Failure Indication /C16 Failure Indication failure detected failure detected Register Description
Preliminary Data Sheet
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PRELIMINARY Interrupt Mask Register Reset value: INTM1 GPIO RD/WR Register Description Address:
Error2 Interrupt Change Indication Mask (not active 16-bit mode) mask Change Indication Mask Change Indication
Error1 Interrupt Change Indication Mask mask Change Indication Mask Change Indication
GPIO General Purpose Change Indication Mask mask Change Indication Mask Change Indication Time Slot Arrived Indication Mask mask Time Slot Arrived Indication Mask Time Slot Arrived Indication Ready Indication Mask mask Ready Indication Mask Ready Indication Mask Disable interrupt
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PRELIMINARY Interrupt Error Mask Register Reset value: INTEM1 RD/WR Register Description Address:
CT_NETREF_2 Failure Indication Mask CT_NETREF_1 Failure Indication Mask CT_C8_B CT_FRAME_B Failure Indication Mask CT_C8_A CT_FRAME_A Failure Indication Mask NTWK_2 Failure Indication Mask NTWK_1 Failure Indication Mask mask this interrupt Mask this interrupt Mask Disable interrupt
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PRELIMINARY Interrupt Error Mask Register Reset value: INTEM2 RD/WR Register Description Address:
Connection Memory Overflow Indication Mask Source Failure Indication Mask FR_COMP Failure Indication Mask SCLK2 Failure Indication Mask SCLK Failure Indication Mask Failure Indication Mask Failure Indication Mask /C16 Failure Indication Mask mask this interrupt Mask this interrupt Mask Disable interrupt General Purpose Port Input Register Reset value: GPPI GPB7 GPB6 GPB5 GPB4 GPB3 GPB2 GPB1 GPB0 Address:
GPB7.0 General Purpose Bits
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PRELIMINARY General Purpose Port Output RegisterWR Reset value: GPPO GPB7 GPB6 GPB5 GPB4 GPB3 GPB2 GPB1 GPB0 Register Description Address:
GPB7.0 General Purpose Bits
General Purpose Direction Register Reset value:
RD/WR
Address:
DC7.0 Direction Control line input line output
General Purpose Mask Register Reset value:
RD/WR
Address:
IM7.0 GPIO Interrupt Mask (bit line line enable change detection disable change detection
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PRELIMINARY General Purpose Interrupt Register Reset value: IDCODE IND7 IND6 IND5 IND4 IND3 IND2 IND1 IND0 Register Description Address:
IND7.0 GPIO Interrupt Indication (bit line line change detected least change detected this line
Time Slot Value Register Reset value: TSV7 TSV6 TSV5
Address:
TSV3
TSV2
TSV1
TSV0
TSV4
Read Time-Slot Value Command content register interpreted TSV7.0 Time-Slot Value
Read Configuration Command content register interpreted Master/Slave Configuration only H-mode (page TSV0 Slave Master
Primary Master Configuration TSV3.0 I3.0 from Primary Master Reference Selection Command (page TSV6.4 1.536
Preliminary Data Sheet
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PRELIMINARY 1.544 2.048 4.096 8.192 16.384 Register Description
Secondary Master Configuration TSV3.0 I3.0 from Secondary Master Reference Selection Command (page TSV6.4 1.536 1.544 2.048 4.096 8.192 16.384
Source Selection TSV3.0 I3.0 from Source Selection Command (page H.1x0 Clock Output Selection only H-mode TSV1.0 I1.0 from H.1x0 Clock Output Selection Command (page Clock Output Selection TSV3.0 I3.0 from Clock Output Selection Command (page Compatibility Clock Output Selection only H-mode TSV3.0 I3.0 from Compatibility Clock Output Selection Command (page CT_NETREF_1 Output Selection only H-mode TSV3.0 I3.0 from CT_NETREF_1 Output Selection Command (page TSV5.4 TSV5.4, TSV3.0 100x
Preliminary Data Sheet
2001-01-01
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PRELIMINARY 2.048 Register Description
CT_NETREF_2 Output Selection only H-mode TSV3.0 I3.0 from CT_NETREF_2 Output Selection Command (page TSV5.4 TSV5.4, TSV3.0 100x 2.048
H.1x0 Fallback Mechanism Phase Alignment TSV3.0 I3.0 from H.1x0 Fallback Mechanism Phase Alignment Command (page External Frequency TSV0 TSV0 IREQ TSV2.0 I1.0 from IREQ Command (page H.1x0/PCM Standby TSV1.0 from H.1x0/PCM Standby Command (page Loop TSV1.0 I1.0 from Loop Command (page Range Data Rate TSV3.0 I3.0 from Range Data Rate Command (page from External Frequency Command (page from Parallel Mode Command (page Parallel Mode
Preliminary Data Sheet
2001-01-01
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PRELIMINARY Register Description
Read GPCLK Configuration Command content register interpreted TSV0 TSV3.1 TSV1 GPCLK Line Clock Signal GPCLK Line Frame Signal 2.048 4.096 8.192 16.384 Input Analog Internal Frequency Rising Edge Falling Edge
GPCLK Line Clock Signal
GPCLK Line Frame Signal
TSV7.2 Offset within frame number 16.384 clock cycles (lower bits; refer upper part)
Read H.1x0 Line Configuration Command content register interpreted TSV1.0 2.048 MBit/s 4.096 MBit/s 8.192 MBit/s 16.384 MBit/s (only PCM)
Preliminary Data Sheet
2001-01-01
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PRELIMINARY Register Description
case Read Shift Configuration Command content register interpreted TSV0 Edge Control TSV4 Rising Edge Falling Edge
TSV3.1 Shift Value (Range: Byte Shift Value (only input lines) shift applies byte before rising edge shift applies byte before falling edge
Configuration Register Reset value: CON7 CON6 CON5
Address:
CON3
CON2
CON1
CON0
CON4
Memory Dump Command (CCMD) content register CON7.0 Connection Data Memory
Read GPCLK Configuration Command content register CON7.5 Width pulse number 16.384 clock cycles from i.e. CON7.5 clock cycle, CON7.5 clock cycles CON4.0 Offset within frame number 16.384 clock cycles (upper bits; refer lower part)
Preliminary Data Sheet
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PRELIMINARY Register Description
Table
Register Overview 16-Bit Interface
Register Overview 16-Bit Interface Comment Source Address Register Destination Address Register General Input Register Connection Command Register 16-bit Configuration Command Register This 8-bit register Configuration Command Register This 8-bit register Message Value Register This 8-bit register Interrupt Status Register This 8-bit register Interrupt Error Status Register Interrupt Mask Register This 8-bit register Interrupt Error Mask Register Page
Access Address Reset Name Value CC16 RD/WR RD/WR RD/WR RD/WR 0000H 0000H 0000H 0000H 0000H FF3FH
CMD1 RD/WR CMD2 RD/WR ISTA1 IESTA RD/WR
INTM1 RD/WR INTEM RD/WR TSVC
IDCODE IDCODE Register This 8-bit register XXXXH Time Slot Value Configuration Register
Preliminary Data Sheet
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PRELIMINARY Register Description
Detailed Register Description 16-Bit Interface
RD/WR Address:
Source Address Register Reset value: 0000H TSA7 TSA6 TSA5
TSA4
TSA3
TSA2
TSA1
TSA0
High
Input Time Slot Address Register page Source Port Address Register page
Destination Address Register Reset value: 0000H TSA7 TSA6 TSA5
RD/WR
Address:
TSA4
TSA3
TSA2
TSA1
TSA0
High
Output Time Slot Address Register page Destination Port Address Register page
Preliminary Data Sheet
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PRELIMINARY General Input Register Reset value: 0000H GV15 GV14 GV13 GV12 GV11 GV10 RD/WR Register Description Address:
GV15.0 General Value GV15.8 General Input Register page GV7.0 General Input Register page
Connection Command Register 16-bit Reset value: 0000H CC16 OSCA2
RD/WR
Address:
ISCA2
ISCA1
ISCA0
OSCA1 OSCA0
High
Sub-Channel Address Register page Connection Command Register page
Preliminary Data Sheet
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PRELIMINARY Interrupt Error Status Register Reset value: 0000H IESTA Register Description Address:
High Interrupt Error Status Register page Interrupt Error Status Register page
Interrupt Error Mask Register Reset value: FF3FH INTEM
RD/WR
Address:
High Interrupt Error Mask Register page Interrupt Error Mask Register page
Preliminary Data Sheet
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PRELIMINARY IDCODE Register Reset value: IDCODE IDC7 IDC6 IDC5 IDC4 IDC3 IDC2 IDC1 IDC0 Register Description Address:
IDC7.0 IDCODE refer Table Time Slot Value Configuration RegisterRD Reset value: XXXXH
TSVC15
Address:
TSVC14
TSVC13
TSVC12
TSVC11
TSVC10
TSVC9
TSVC8
TSVC
TSVC7
TSVC6
TSVC5
TSVC4
TSVC3
TSVC2
TSVC1
TSVC0
TSVC15.8 Configuration Connection Data Memory (refer page TSVC7.0 Time Slot Value (refer page
Preliminary Data Sheet
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PRELIMINARY Programming Device
Programming Device
register consists parameter registers (SPA, ITSA, SCA, DPA, OTSA, GI1.), command registers (CCMD, CMD1, CMD2) status registers (ISTA1, IESTA1, IESTA2). Before issuing command parameter registers have written accordingly. connection command only issued connection command register ready written (see Figure 24). connection command register status shown with ISTA1 register. detailed description read write access command registers found Chapter 6.1.
command register ready?
command register ready?
write parameter registers write command register
write parameter registers write command register
passive waiting with interrupt
active waiting (polling) without interrupt
switi_032.emf
Figure
Order Register Access
Preliminary Data Sheet
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PRELIMINARY Programming Device
Read Write Access
read write access necessary distinguish between connection configuration command. connection command register used establish connection (described Chapter 6.11) configuration registers used configure device, i.e. clock frequency. ISTA1:RDY connection command register ready receive data from interface. parameter register connection command register written will reset from internal controller. connection established internal controller will connection command register ready next write read access. ISTA1:RDY enabled generate interrupt indicate that device ready receive data, otherwise must poll ISTA1:RDY bit. configuration command register works independent from bit. Note: There must recovery time period after every configuration command write access next write access (command parameter register).
Preliminary Data Sheet
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PRELIMINARY Programming Device
Interrupt Handling
SWITI interrupt concept consists four interrupt status register with their corresponding mask register. five interrupt status register divided main register, error interrupt register, general purpose interrupt register time slot value register. Every secondary status register time slot value register main register indicate interrupt assigned error general purpose register indicate value time slot value register. interrupt status register read microprocessor interface. will reset from internal controller. GPIO, TSA, ER2, set, assigned secondary interrupt status register time slot value register must read first. After secondary status register read access, error status register corresponding bits main interrupt status register will reset.
APLL
Status Register Value Register
Interrupt Error tatus Register
Interrupt Error tatus Register
eneral Purpose Interrupt Status Register
iti_063.em
Figure
8-bit Access Interrupt Structure
IREQ output level active. stays active until interrupt sources have been serviced. status while interrupt being serviced read access), IREQ stays active. duration write access INTM1 register IREQ line deactivated. When using edge-triggered interrupt controller, thus recommended rewrite INTM1 register interrupt service routine. APLL, STR, Bits internal controller does first time masked interrupt will generated. reads ISTA1 register interrupt will deactivated. still active reset from internal controller. doesn't generate interrupt masked. from internal controller connection memory filled. doesn't generate interrupt masked. from internal stream stream controller stream stream connection set. APLL doesn't generate interrupt masked. from internal analog controller locked. Masking Interrupts interrupt masked (enabled) IREQ will active status bits interrupt status register set. mask prevents that IREQ will
Preliminary Data Sheet 2001-01-01
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PRELIMINARY Programming Device
active status set. mask bits error status registers general purpose interrupt register disables interrupt indication interrupt status register. Only interrupt status register IREQ masked. Interrupt Structure 16-bit Microprocessor Access
APLL GPIO
Time Slot Value Register
General Purpose Interrupt Status Register
Interrupt Error Status Register
switi_068.emf
Figure
16-bit Access Interrupt Structure
opposite 8-bit access there only (ER1) indicate change 16-bit Interrupt Error Status Register
Preliminary Data Sheet
2001-01-01
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PRELIMINARY Programming Device
Command Register Overview
following table (Table shows which parameter registers considered issuing appropriate connection command. Table Command Connect/Disconnect (witho
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