FEATURES 6-Phase Vertical Transfer Clock Support Correlated Double Sam
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12-Bit Signal Processor with Precision Timing Generator AD9995
FEATURES 6-Phase Vertical Transfer Clock Support Correlated Double Sampler (CDS) 10-Bit Variable Gain Amplifier (VGA) 12-Bit Converter Black Level Clamp with Variable Level Control Complete On-Chip Timing Generator Precision Timing Core with <600 Resolution On-Chip Horizontal Drivers 2-Phase 4-Phase H-Clock Modes Electronic Mechanical Shutter Modes On-Chip Driver External Crystal On-Chip Sync Generator with External Sync Input 56-Lead LFCSP Package APPLICATIONS Digital Still Cameras Digital Video Camcorders Industrial Imaging GENERAL DESCRIPTION
AD9995 highly integrated signal processor digital still camera camcorder applications. includes complete analog front with conversion, combined with full-function programmable timing generator. timing generator capable supporting both 6-phase vertical clocking. Precision Timing core allows adjustment high speed clocks with less than resolution operation. AD9995 specified pixel rates MHz. analog front includes black level clamping, CDS, VGA, 12-bit converter. timing generator provides necessary clocks: H-clocks, V-clocks, sensor gate pulses, substrate clock, substrate bias control. Operation programmed using 3-wire serial interface. Packaged space-saving 56-lead LFCSP, AD9995 specified over operating temperature range -20°C +85°C.
AD9995
42dB CCDIN VREF 12-BIT DOUT
CLAMP INTERNAL CLOCKS DCLK
HORIZONTAL DRIVERS
H1-H4
PRECISION TIMING GENERATOR
MSHUT STROBE
V1-V6
CONTROL SYNC GENERATOR INTERNAL REGISTERS
VSG1-VSG5
VSUB SUBCK
SYNC
DATA
REV.
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AD9995
TABLE CONTENTS SPECIFICATIONS Digital Specifications AD9995 Analog Specifications Timing Specifications ABSOLUTE MAXIMUM RATINGS PACKAGE THERMAL CHARACTERISTICS. ORDERING GUIDE. CONFIGURATION FUNCTION DESCRIPTIONS TERMINOLOGY EQUIVALENT CIRCUITS. TYPICAL PERFORMANCE CHARACTERISTICS SYSTEM OVERVIEW. PRECISION TIMING HIGH SPEED TIMING GENERATION Timing Resolution. High Speed Clock Programmability H-Driver Outputs Digital Data Outputs HORIZONTAL CLAMPING BLANKING Individual CLPOB PBLK Patterns. Individual HBLK Patterns Generating Special HBLK Patterns. Generating HBLK Line Alternation HORIZONTAL TIMING SEQUENCE EXAMPLE VERTICAL TIMING GENERATION Vertical Pattern Groups (VPAT) Vertical Sequences (VSEQ) Complete Field: Combining V-Sequences Generating Line Alternation V-Sequence HBLK Second V-Pattern Group during Active Line Sweep Mode Operation. Multiplier Mode Vertical Sensor Gate (Shift Gate) Patterns MODE Register VERTICAL TIMING EXAMPLE Important Note about Signal Polarities SHUTTER TIMING CONTROL Normal Shutter Operation High Precision Shutter Operation Speed Shutter Operation SUBCK Suppression Readout after Exposure. Using TRIGGER Register VSUB Control MSHUT STROBE Control TRIGGER Register Limitations EXPOSURE READOUT EXAMPLE DESCRIPTION OPERATION Restore Correlated Double Sampler Variable Gain Amplifier Converter Optical Black Clamp Digital Data Outputs POWER-UP SYNCHRONIZATION Recommended Power-Up Sequence Master Mode. Generating Software SYNC without External SYNC Signal SYNC during Master Mode Operation Power-Up Synchronization Slave Mode STANDBY MODE OPERATION CIRCUIT LAYOUT INFORMATION SERIAL INTERFACE TIMING Register Address Banks Updating Register Values. COMPLETE LISTING REGISTER BANK COMPLETE LISTING REGISTER BANK OUTLINE DIMENSIONS
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AD9995-SPECIFICATIONS
Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE AVDD (AFE Analog Supply) TCVDD (Timing Core Analog Supply) RGVDD Driver) HVDD (H1-H4 Drivers) DRVDD (Data Output Drivers) DVDD (Digital) POWER DISSIPATION (See Power Curves) MHz, Supply Levels, H1-H4 Loading Power from HVDD Only* Standby Mode Standby Mode Standby Mode MAXIMUM CLOCK RATE (CLI)
*The total power dissipated HVDD supply approximated using equation Total HVDD Power LOAD HVDD Pixel Frequency HVDD Number outputs used Reducing H-loading, using only outputs, and/or using lower HVDD supply will reduce power dissipation. Specifications subject change without notice.
+150
Unit
DIGITAL SPECIFICATIONS
Parameter LOGIC INPUTS High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current Input Capacitance LOGIC OUTPUTS (Except High Level Output Voltage Level Output Voltage H-DRIVER OUTPUTS (H1-H4) High Level Output Voltage Current Level Output Voltage Current Maximum Output Current (Programmable) Maximum Load Capacitance (For Each Output)
Specifications subject change without notice.
Symbol
Unit
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AD9995 ANALOG SPECIFICATIONS (AVDD
Parameter
CDS* Allowable Reset Transient Input Range before Saturation Black Pixel Amplitude VARIABLE GAIN AMPLIFIER (VGA) Gain Control Resolution Gain Monotonicity Gain Range Gain (VGA Code Gain (VGA Code 1023) BLACK LEVEL CLAMP Clamp Level Resolution Clamp Level Clamp Level (Code Clamp Level (Code 255) CONVERTER Resolution Differential Nonlinearity (DNL) Missing Codes Full-Scale Input Voltage VOLTAGE REFERENCE Reference Voltage (REFT) Reference Bottom Voltage (REFB) SYSTEM PERFORMANCE Gain Accuracy Gain (VGA Code Gain (VGA Code 1023) Peak Nonlinearity, Input Signal Total Output Noise Power Supply Rejection (PSR)
*Input signal characteristics defined follows:
MHz, Typical Timing Specifications, TMIN TMAX, unless otherwise noted.)
Unit
Steps
Notes
1024 Guaranteed -1.0
Steps Measured output. Bits Includes entire signal chain.
±0.5 Guaranteed
+1.0
40.5
41.5
42.5
Gain (0.0351 Code) gain applied. grounded input, gain applied. Measured with step change supply.
500mV RESET TRANSIENT 50mV OPTICAL BLACK PIXEL INPUT SIGNAL RANGE
Specifications subject change without notice.
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AD9995 TIMING SPECIFICATIONS AVDD DVDD DRVDD
MHz, unless otherwise noted.)
27.8 11.2 Unit Pixels Cycles
Parameter MASTER CLOCK, (Figure Clock Period High/Low Pulsewidth Delay from Rising Edge Internal Pixel Position CLPOB Pulsewidth
Symbol tCONV tCLIDLY
13.9 13.9
16.6
(Figures
SAMPLE LOCATION (Figure Sample Edge Sample Edge DATA OUTPUTS (Figures Output Delay from DCLK Rising Edge1 Pipeline Delay from SHP/SHD Sampling DOUT SERIAL INTERFACE (Figures 40b) Maximum Frequency Setup Time Hold Time SDATA Valid Rising Edge Setup Falling Edge SDATA Valid Hold Falling Edge SDATA Valid Read
12.5
fSCLK
NOTES 1Parameter programmable. 2Minimum CLPOB pulsewidth functional operation only. Wider typical pulses recommended achieve good clamp performance. Specifications subject change without notice.
ABSOLUTE MAXIMUM RATINGS*
Parameter AVDD TCVDD HVDD RGVDD DVDD DRVDD Output
With Respect AVSS TCVSS HVSS RGVSS DVSS DRVSS RGVSS
HVSS DVSS DVSS DVSS AVSS
PACKAGE THERMAL CHARACTERISTICS Thermal Resistance
25°C/W* -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3
-0.3 -0.3 -0.3 -0.3 -0.3
+3.9 +3.9 +3.9 +3.9 +3.9 +3.9 RGVDD
HVDD DVDD DVDD DVDD AVDD
Unit
measured using 4-layer with exposed paddle soldered board.
ORDERING GUIDE
Model AD9995KCP AD9995KCPRL
Temperature Range -20°C +85°C -20°C +85°C
Package Description LFCSP LFCSP
Package Option CP-56 CP-56
H1-H4 Output Digital Outputs Digital Inputs SCK, SDATA REFT, REFB, CCDIN Junction Temperature Lead Temperature,
*Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only. Functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Absolute maximum ratings apply individually only, combination. Unless otherwise specified, other voltages referenced GND.
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000V readily accumulate human body test equipment discharge without detection. Although AD9995 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
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AD9995
CONFIGURATION
(LSB) SYNC_CLP STROBE MSHUT DCLK DVDD DVSS
(MSB) DRVDD DRVSS
IDENTIFIER
REFB REFT AVSS CCDIN AVDD TCVDD TCVSS RGVDD RGVSS
AD9995
VIEW
VSUB SUBCK
VSG3
VSG1 VSG2
VSG4
HVSS
VSG5
HVDD
FUNCTION DESCRIPTIONS1
Mnemonic DRVDD DRVSS VSUB SUBCK VSG1 VSG2 VSG3 VSG4 VSG5 HVSS HVDD RGVSS RGVDD TCVSS TCVDD
Type2
Description Data Output Data Output Data Output Data Output Data Output Data Output Data Output (MSB) Data Output Driver Supply Data Output Driver Ground Substrate Bias Substrate Clock (E-Shutter) Vertical Transfer Clock Vertical Transfer Clock Vertical Transfer Clock Vertical Transfer Clock Vertical Transfer Clock Vertical Transfer Clock Sensor Gate Pulse Sensor Gate Pulse Sensor Gate Pulse Sensor Gate Pulse Sensor Gate Pulse Horizontal Clock Horizontal Clock H1-H4 Driver Ground H1-H4 Driver Supply Horizontal Clock Horizontal Clock Driver Ground Reset Gate Clock Driver Supply Analog Ground Timing Core Analog Supply Timing Core Clock Output Crystal Reference Clock Input
Mnemonic AVDD CCDIN AVSS REFT REFB MSHUT STROBE SYNC DVSS DVDD DCLK
Type2
Description Analog Supply Signal Input Analog Ground Voltage Reference Bypass Voltage Reference Bottom Bypass 3-Wire Serial Load Pulse 3-Wire Serial Data Input 3-Wire Serial Clock Mechanical Shutter Pulse Strobe Pulse External System Sync Input Vertical Sync Pulse (Input Slave Mode, Output Master Mode) Digital Ground Power Supply VSG, V1-V6, HD/VD, MSHUT, STROBE, SYNC, Serial Interface Horizontal Sync Pulse (Input Slave Mode, Output Master Mode) Data Clock Output Data Output (LSB) Data Output Data Output Data Output Data Output
NOTES 1See Figure circuit configuration. Analog Input, Analog Output, Digital Input, Digital Output, Digital Input/Output, Power.
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AD9995
TERMINOLOGY Differential Nonlinearity (DNL)
ideal exhibits code transitions that exactly apart. deviation from this ideal value. Therefore, every code must have finite width. missing codes guaranteed 12-bit resolution indicates that 4096 codes must present over operating conditions.
Peak Nonlinearity
full-scale signal. input signal always appropriately gained fill ADC's full-scale range.
Total Output Noise
Peak nonlinearity, full signal chain specification, refers peak deviation output AD9995 from true straight line. point used zero scale occurs before first code transition. Positive full scale defined level beyond last code transition. deviation measured from middle each particular output code true straight line. error then expressed percentEQUIVALENT CIRCUITS
output noise measured using histogram techniques. standard deviation output codes calculated represents noise level total signal chain specified gain setting. output noise converted equivalent voltage using relationship (ADC Full Scale/2n codes), where resolution ADC. AD9995, 0.488
Power Supply Rejection (PSR)
measured with step change applied supply pins. specification calculated from change data outputs given step change supply voltage.
DVDD
AVDD
AVSS
AVSS
DVSS
Circuit CCDIN
Circuit Digital Inputs
HVDD RGVDD
DVDD
DRVDD H1-H4
DATA
THREESTATE
DOUT
ENABLE
OUTPUT
DVSS
DRVSS
HVSS RGVSS
Circuit Digital Data Outputs
Circuit H1-H4, Drivers
REV.
AD9995-Typical Performance Characteristics
POWER DISSIPATION (mW) 3.3V OUTPUT NOISE (LSB) 3.0V
2.7V
1000
SAMPLE RATE (MHz)
GAIN CODE (LSB)
Power Dissipation Sample Rate
Output Noise Gain
(LSB)
-0.5
-1.0
1000
1500
2000 CODES
2500
3000
3500
4000
Typical Performance
REV.
AD9995
SYSTEM OVERVIEW
Figure shows typical system block diagram AD9995 used Master mode. output processed AD9995's circuitry, which consists CDS, VGA, black level clamp, converter. digitized pixel information sent digital image processor chip, which performs postprocessing compression. operate CCD, timing parameters programmed into AD9995 from system microprocessor through 3-wire serial interface. From system master clock, CLI, provided image processor external crystal, AD9995 generates CCD's horizontal vertical clocks internal clocks. External synchronization provided SYNC pulse from microprocessor, which will reset internal counters resync outputs. Alternatively, AD9995 operated Slave mode, which provided externally from image processor. this mode, AD9995 timing will synchronized with
V-DRIVER V1-V6, VSG1-VSG5, SUBCK
H-drivers H1-H4 included AD9995, allowing these clocks directly connected CCD. H-drive voltage supported. external V-driver required vertical transfer clocks, sensor gate pulses, substrate clock. AD9995 also includes programmable MSHUT STROBE outputs, which used trigger mechanical shutter strobe (flash) circuitry. Figures show maximum horizontal vertical counter dimensions AD9995. internal horizontal vertical clocking controlled these counters specify line pixel locations. Maximum length 4095 pixels line, maximum length 4095 lines field.
MAXIMUM FIELD DIMENSIONS
12-BIT HORIZONTAL 4096 PIXELS H1-H4, VSUB DOUT CCDIN MSHUT STROBE SYNC
AD9995 AFETG
DCLK
DIGITAL IMAGE PROCESSING ASIC 12-BIT VERTICAL 4096 LINES
SERIAL INTERFACE
Figure Vertical Horizontal Counters Figure Typical System Block Diagram, Master Mode
LENGTH 4095 LINES
LENGTH 4095 PIXELS
Figure Maximum VD/HD Dimensions
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AD9995
PRECISION TIMING HIGH SPEED TIMING GENERATION
AD9995 generates high speed timing signals using flexible Precision Timing core. This core foundation generating timing used both AFE: reset gate horizontal drivers H1-H4, SHP/SHD sample clocks. unique architecture makes routine system designer optimize image quality providing precise control over horizontal readout correlated double sampling. high speed timing AD9995 operates same either Master Slave mode configuration. more information synchronization pipeline delays, Power-Up Synchronization section.
Timing Resolution
CLIDIVIDE register (Addr. 0x30). AD9995 will then internally divide frequency AD9995 also includes master clock output, CLO, which inverse CLI. This output intended used crystal driver. crystal placed between pins generate master clock AD9995. more information using crystal, Figure
High Speed Clock Programmability
Precision Timing core uses master clock input (CLI) reference. This clock should same pixel clock frequency. Figure illustrates internal timing core divides master clock period into steps edge positions. Using frequency, edge resolution Precision Timing core system clock available, also possible reference clock programming
POSITION P[0] P[12]
Figure shows high speed clocks H1-H4, SHP, generated. pulse programmable rising falling edges, inverted using polarity control. horizontal clocks have programmable rising falling edges polarity control. clocks always inverses respectively. Table summarizes high speed timing registers their parameters. Figure shows typical 2-phase H-clock arrangement which programmed same edge location edge location registers bits wide, there only valid edge locations available. Therefore, register values
P[24]
P[36]
P[48] P[0]
tCLIDLY
PIXEL PERIOD
NOTES PIXEL CLOCK PERIOD DIVIDED INTO POSITIONS, PROVIDING FINE EDGE RESOLUTION HIGH SPEED CLOCKS. THERE FIXED DELAY FROM INPUT INTERNAL PIXEL PERIOD POSITIONS (tCLIDLY TYP).
Figure High Speed Clock Resolution from Master Clock Input
SIGNAL
PROGRAMMABLE CLOCK POSITIONS: RISING EDGE FALLING EDGE SAMPLE LOCATION SAMPLE LOCATION
RISING EDGE POSITION FALLING EDGE POSITION INVERSE RISING EDGE POSITION FALLING EDGE POSITION INVERSE
Figure High Speed Clock Programmable Locations
-10-
REV.
AD9995
mapped into four quadrants, with each quadrant containing edge locations. Table shows correct register values corresponding edge locations. Figure shows default timing locations high speed clock signals.
H-Driver Outputs Digital Data Outputs
addition programmable timing positions, AD9995 features on-chip output drivers H1-H4 outputs. These drivers powerful enough directly drive inputs. H-driver current adjusted optimum rise/fall time into particular load using DRVCONTROL register (Addr. 0x35). 3-bit drive setting each output adjustable increments, with minimum setting equal three-state, maximum setting equal 30.1 shown Figures outputs inverses respectively. H1/H2 crossover voltage approximately output swing. crossover voltage programmable.
AD9995 data output DCLK phases programmable using DOUTPHASE register (Addr. 0x37, Bits [5:0]). edge from programmed, shown Figure Normally, DOUT DCLK signals will track phase based DOUTPHASE register contents. DCLK output phase also held fixed with respect data outputs changing DCLKMODE register high (Addr. 0x37, this mode, DCLK output will remain fixed phase equal (the inverse CLI) while data output phase still programmable. There fixed output delay from DCLK rising edge DOUT transition, called tOD. This delay programmed four values between using DOUTDELAY register (Addr. 0x037, Bits [8:7]). default value pipeline delay through AD9995 shown Figure After input sampled SHD, there 11-cycle delay until data available.
Table Timing Core Register Parameters SHP/SHD
Parameter Polarity Positive Edge Negative Edge Sampling Location Drive Strength
Length
Range High/Low 0-47 Edge Location 0-47 Edge Location 0-47 Edge Location 0-47 Current Steps
Description Polarity Control Inversion, Inversion) Positive Edge Location Negative Edge Location Sampling Location Internal Signals Drive Current H1-H4 Outputs (4.1 Step)
SIGNAL
H1/H3
H2/H4
USING SAME TOGGLE POSITIONS GENERATES STANDARD 2-PHASE H-CLOCKING.
Figure 2-Phase H-Clock Operation
Table Precision Timing Edge Locations
Quadrant
Edge Location (Dec)
Register Value (Dec)
Register Value (Bin) 000000 001011 010000 011011 100000 101011 110000 111011
REV.
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AD9995
POSITION P[0] P[12] P[24] P[36] P[48] P[0] PIXEL PERIOD RGr[0] Hr[0] H1/H3 Hf[24] RGf[12]
H2/H4
SHP[24] SIGNAL
SHD[0]
NOTES SIGNAL EDGES FULLY PROGRAMMABLE POSITIONS WITHIN PIXEL PERIOD. DEFAULT POSITIONS EACH SIGNAL SHOWN.
Figure High Speed Timing Default Locations
P[0]
P[12]
P[24]
P[36]
P[48] P[0]
PIXEL PERIOD
DCLK
DOUT
NOTES DATA OUTPUT (DOUT) DCLK PHASE ADJUSTABLE WITH RESPECT PIXEL PERIOD. WITHIN CLOCK PERIOD, DATA TRANSITION PROGRAMMED DIFFERENT LOCATIONS. OUTPUT DELAY (tOD) FROM DCLK RISING EDGE DOUT RISING EDGE PROGRAMMABLE.
Figure Digital Output Phase Adjustment
tCLIDLY
CCDIN SAMPLE PIXEL (INTERNAL) N+10 N+11 N+12 N+13
DCLK PIPELINE LATENCY=11 CYCLES DOUT N-13 N-12 N-11 N-10
NOTES DEFAULT TIMING VALUES SHOWN: SHDLOC DOUT PHASE DCLKMODE HIGHER VALUES AND/OR DOUTPHASE WILL SHIFT DOUT TRANSITION RIGHT, WITH RESPECT LOCATION.
Figure Pipeline Delay
-12-
REV.
AD9995
HORIZONTAL CLAMPING BLANKING
AD9995's horizontal clamping blanking pulses fully programmable suit variety applications. Individual control provided CLPOB, PBLK, HBLK during different regions each field. This allows dark pixel clamping blanking patterns changed each stage readout order accommodate different image transfer timing high speed line shifts.
Individual CLPOB PBLK Patterns
each containing unique pulse pattern CLPOB PBLK. Figure shows sequence change positions divide readout field into different regions. different V-sequence assigned each region, allowing CLPOB PBLK signals changed accordingly with each change vertical timing.
Individual HBLK Patterns
horizontal timing consists CLPOB PBLK, shown Figure These signals independently programmed using registers Table III. SPOL start polarity signal, TOG1 TOG2 first second toggle positions pulse. Both signals active should programmed accordingly. separate pattern CLPOB PBLK programmed every V-sequences. described Vertical Timing Generation section, separate V-sequences created,
HBLK programmable timing shown Figure similar CLPOB PBLK. However, there start polarity control. Only toggle positions used designate start stop positions blanking period. Additionally, there polarity control HBLKMASK that designates polarity horizontal clock signals H1-H4 during blanking period. Setting HBLKMASK high will high during blanking, shown Figure with CLPOB PBLK signals, HBLK registers available each V-sequence, allowing different blanking signals used with different vertical timing sequences.
CLPOB PBLK
ACTIVE
ACTIVE
NOTES PROGRAMMABLE SETTINGS: START POLARITY (CLAMP BLANK REGION ACTIVE LOW) FIRST TOGGLE POSITION SECOND TOGGLE POSITION
Figure Clamp Pre-Blank Pulse Placement
Table III. CLPOB PBLK Pattern Registers
Register SPOL TOG1 TOG2
Length
Range High/Low 0-4095 Pixel Location 0-4095 Pixel Location
Description Starting Polarity CLPOB/PBLK V-Sequence First Toggle Position within Line V-Sequence Second Toggle Position within Line V-Sequence
Table HBLK Pattern Registers
Register HBLKMASK HBLKALT HBLKTOG1 HBLKTOG2 HBLKTOG3 HBLKTOG4 HBLKTOG5 HBLKTOG6
Length
Range High/Low Alternation Mode 0-4095 Pixel Location 0-4095 Pixel Location 0-4095 Pixel Location 0-4095 Pixel Location 0-4095 Pixel Location 0-4095 Pixel Location
Description Masking Polarity H1/H3 H1/H3 Low, H1/H3 High) Enables Odd/Even Alternation HBLK Toggle Positions Disable Alternation. TOG1-TOG2 Odd, TOG3-TOG6 Even. TOG1-TOG2 Even, TOG3-TOG6 First Toggle Position within Line Each V-Sequence Second Toggle Position within Line Each V-Sequence Third Toggle Position within Line Each V-Sequence Fourth Toggle Position within Line Each V-Sequence Fifth Toggle Position within Line Each V-Sequence Sixth Toggle Position within Line Each V-Sequence
REV.
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AD9995
Generating Special HBLK Patterns Generating HBLK Line Alternation
There toggle positions available HBLK. Normally, only toggle positions used generate standard HBLK interval. However, additional toggle positions used generate special HBLK patterns, shown Figure pattern this example uses toggle positions generate extra groups pulses during HBLK interval. changing toggle positions, different patterns created.
further feature AD9995 ability alternate different HBLK toggle positions even lines. This used conjunction with V-pattern odd/even alternation own. When written HBLKALT register, TOG1 TOG2 used lines only, while TOG3-TOG6 used even lines. Writing HBLKALT register gives opposite result: TOG1 TOG2 used even lines, while TOG3-TOG6 used lines. Vertical Timing Generation, Line Alternation section more information.
HBLK BLANK
BLANK
PROGRAMMABLE SETTINGS: FIRST TOGGLE POSITION START BLANKING SECOND TOGGLE POSITION BLANKING
Figure Horizontal Blanking (HBLK) Pulse Placement
HBLK
H1/H3
H1/H3
H2/H4
POLARITY DURING BLANKING PROGRAMMABLE OPPOSITE POLARITY H1).
Figure HBLK Masking Control
TOG1 TOG2 TOG3 TOG4 TOG5 TOG6
HBLK
H1/H3
H2/H4
SPECIAL H-BLANK PATTERN CREATED USING MULTIPLE HBLK TOGGLE POSITIONS.
Figure Generating Special HBLK Patterns
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AD9995
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure shows example layout. horizontal register contains dummy pixels, which will occur each line clocked from CCD. vertical direction, there optical black (OB) lines front readout back readout. horizontal direction four pixels front back. Figure shows basic sequence layout used during effective pixel readout. pixels each line used CLPOB signals. PBLK optional often used blank digital outputs during noneffective pixels. HBLK used during vertical shift interval.
HBLK, CLPOB, PBLK parameters programmed V-sequence registers. More elaborate clamping schemes used, such adding separate sequence clamp during entire shield lines. This requires configuring separate V-sequence reading lines.
VERTICAL LINES
EFFECTIVE IMAGE AREA
VERTICAL LINES
PIXELS HORIZONTAL REGISTER PIXELS
DUMMY PIXELS
Figure Example Configuration
CCDIN OPTICAL BLACK VERTICAL SHIFT DUMMY EFFECTIVE PIXELS OPTICAL BLACK VERT SHIFT
H1/H3 H2/H
HBLK
PBLK
CLPOB
Figure Horizontal Sequence Example
REV.
-15-
AD9995
VERTICAL TIMING GENERATION
AD9995 provides very flexible solution generating vertical timing, support multiple CCDs different system architectures. 6-phase vertical transfer clocks V1-V6 used shift each line pixels into horizontal output register CCD. AD9995 allows these outputs individually programmed into various readout configurations using 4-step process. Figure shows overview vertical timing generated four steps. First, individual pulse patterns V1-V6
CREATE VERTICAL PATTERN GROUPS (MAXIMUM GROUPS). VPAT
created using vertical pattern group registers. Second, V-pattern groups used build sequences, where additional information added. Third, readout entire field constructed dividing field into different regions then assigning sequence each region. Each field contain seven different regions accommodate different steps readout such high speed line shifts unique vertical line transfers. different fields created. Finally, Mode register allows different fields combined into order various readout configurations.
BUILD V-SEQUENCES ADDING LINE START POSITION, REPEATS, HBLK/CLPOB PULSES (MAXIMUM V-SEQUENCES). V-SEQUENCE (VPAT0, REP)
VPAT V-SEQUENCE (VPAT9, REP)
V-SEQUENCE (VPAT9, REP)
MODE REGISTER CONTROL WHICH FIELDS USED, WHAT ORDER (MAXIMUM FIELDS COMBINED ORDER).
BUILD EACH FIELD DIVIDING INTO DIFFERENT REGIONS, ASSIGNING DIFFERENT V-SEQUENCE EACH (MAXIMUM REGIONS EACH FIELD) (MAXIMUM FIELDS). FIELD REGION V-SEQUENCE REGION V-SEQUENCE REGION V-SEQUENCE REGION V-SEQUENCE REGION V-SEQUENCE REGION V-SEQUENCE REGION V-SEQUENCE
FIELD
FIELD
FIELD
FIELD
FIELD
REGION V-SEQUENCE REGION V-SEQUENCE FIELD FIELD FIELD FIELD REGION V-SEQUENCE REGION V-SEQUENCE FIELD FIELD
Figure Summary Vertical Timing Generation
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AD9995
Vertical Pattern Groups (VPAT)
vertical pattern groups define individual pulse patterns each V1-V6 output signal. Table summarizes registers available generating each V-pattern groups. start polarity (VPOL) determines starting polarity vertical sequence, programmed high each V1-V6 output. first, second, third toggle position (VTOG1, VTOG2, VTOG3) pixel locations within line where pulse transitions. fourth toggle position (VTOG4) also available V-Pattern Groups toggle positions 12-bit values, allowing their placement anywhere horizontal line. separate register, VPATSTART, specifies start position V-pattern group within line (see Vertical Sequences section). VPATLEN register designates total
length V-pattern group, which will determine number pixels between each pattern repetitions, when repetitions used (see Vertical Sequences section). FREEZE RESUME registers used temporarily stop operation V1-V6 outputs. pixel location specified FREEZE register, V1-V6 outputs will held static their current state, high low. V1-V6 outputs held until pixel location specified RESUME register. sets FREEZE/RESUME registers provided, allowing vertical outputs interrupted twice same line. FREEZE RESUME positions programmed V-pattern group registers, separately enabled using VMASK registers, which described Vertical Sequence section.
Table Vertical Pattern Group Registers
Register VPOL VTOG1 VTOG2 VTOG3 VTOG4 VPATLEN FREEZE1 RESUME1 FREEZE2 RESUME2
Length
Range High/Low 0-4096 Pixel Location 0-4096 Pixel Location 0-4096 Pixel Location 0-4096 Pixel Location 0-4096 Pixels 0-4096 Pixel Location 0-4096 Pixel Location 0-4096 Pixel Location 0-4096 Pixel Location
Description Starting Polarity Each V1-V6 Output First Toggle Position within Line Each V1-V6 Output Second Toggle Position within Line Each V1-V6 Output Third Toggle Position within Line Each V1-V6 Output Fourth Toggle Position, only Available V-Pattern Groups Total Length Each V-Pattern Group Holds V1-V6 Outputs Their Current Levels (Static Resumes Operation V1-V6 Outputs Finish Their Pattern Holds V1-V6 Outputs Their Current Levels (Static Resumes Operation V1-V6 Outputs Finish Their Pattern
START POSITION V-PATTERN GROUP PROGRAMMABLE V-SEQUENCE REGISTERS
PROGRAMMABLE SETTINGS EACH V-PATTERN: START POLARITY FIRST TOGGLE POSITION SECOND TOGGLE POSITION (3RD TOGGLE POSITION ALSO AVAILABLE, TOGGLE POSITION AVAILABLE V-PATTERN GROUPS TOTAL PATTERN LENGTH V1-V6 OUTPUTS
Figure Vertical Pattern Group Programmability
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AD9995
Vertical Sequences (VSEQ)
vertical sequences created selecting V-pattern groups adding repeats, start position, horizontal clamping blanking information. V-sequences programmed, each using registers shown Table Figure shows different registers used generate each V-sequence. VPATSEL register selects which V-pattern group will used given V-sequence. basic V-pattern group have repetitions added, high speed line shifts line binning, using VPATREPO VPATREPE registers. Generally, same number repetitions programmed into both registers, different number repetitions required
even lines, separate values used each register (see V-Sequence Line Alternation section). VPATSTART register specifies where line V-pattern group will start. VMASK register used conjunction with FREEZE/ RESUME registers enable optional masking V-outputs. Either both FREEZE1/RESUME1 FREEZE2/ RESUME2 registers enabled. line length pixels) programmable using HDLEN registers. Each V-sequence have different line length accommodate various image readout techniques. maximum number pixels line 4096. Note that last line field separately programmable using HDLAST register located Field register section.
Table V-Sequence Registers (see Tables HBLK, CLPOB, PBLK Registers)
Register VPATSEL VMASK
Length
Range V-Pattern Group Mask Mode
Description Selected V-Pattern Group Each V-Sequence. Enables Masking V1-V6 Outputs Locations Specified FREEZE/RESUME Registers. Mask, Enable FREEZE1/RESUME1, Enable FREEZE2/RESUME2, Enable both Number Repetitions V-Pattern Group Lines. odd/even alternation required, VPATREPE. Number Repetitions V-Pattern Group Even Lines. odd/even alternation required, VPATREPO. Start Position Selected V-Pattern Group. Line Length Lines Each V-Sequence.
VPATREPO VPATREPE VPATSTART HDLEN
0-4095 Repeats 0-4095 Repeats 0-4095 Pixel Location 0-4095 Pixels
V1-V6 V-PATTERN GROUP VPAT VPAT
CLPOB PBLK
HBLK
PROGRAMMABLE SETTINGS EACH V-SEQUENCE: START POSITION LINE SELECTED V-PATTERN GROUP LINE LENGTH V-PATTERN SELECT (VPATSEL) SELECT V-PATTERN GROUP NUMBER REPETITIONS V-PATTERN GROUP NEEDED) START POLARITY TOGGLE POSITIONS CLPOB PBLK SIGNALS MASKING POLARITY TOGGLE POSITIONS HBLK SIGNAL
Figure V-Sequence Programmability
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REV.
AD9995
Complete Field: Combining V-Sequences
After V-sequences have been created, they combined create different readout fields. field consists seven different regions, within each region different V-sequence selected. Figure shows sequence change positions (SCP) designate line boundary each region, VSEQSEL registers then select which V-sequence used during each region. Registers control outputs also included Field registers. Table summarizes registers used create different fields. different fields preprogrammed using Field registers. VEQSEL registers, each region, select which V-sequences will active during each region. SWEEP registers used enable SWEEP mode during region. MULTI registers used enable Multiplier mode dur-
region. registers create line boundaries each region. VDLEN register specifies total number lines field. total number pixels line (HDLEN) specified V-sequence registers, HDLAST register specifies number pixels last line field. VPATSECOND register used second V-pattern group V1-6 outputs during sensor gate (VSG) line. SGMASK register used enable disable each individual output. There single each output; setting high will mask output, setting will enable output. SGPAT register assigns four different patterns each output. individual patterns created separately using pattern registers. SGLINE1 register specifies which line field will contain outputs. optional SGLINE2 register allows same pulses repeated different line.
Table VII. Field Registers
Register VSEQSEL SWEEP MULTI VDLEN HDLAST VPATSECOND SGMASK SGPATSEL SGLINE1 SGLINE2
Length
Range V-Sequence High/Low High/Low 0-4095 Line 0-4095 Lines 0-4095 Pixels V-Pattern Group High/Low, Each Pattern Each 0-4095 Line 0-4095 Line
Description Selected V-Sequence Each Region Field. Enables Sweep Mode Each Region, When High. Enables Multiplier Mode Each Region, When High. Sequence Change Position Each Region. Total Number Lines Each Field. Length Pixels Last Line Each Field. Selected V-Pattern Group Second Pattern Applied During Line. High Mask Each Individual Output. VSG1 [0], VSG2 [1], VSG3 [2], VSG4 [3], VSG5 [4]. Selects Pattern Number Each Output. VSG1 [1:0], VSG2 [3:2], VSG3 [5:4], VSG4 [7:6], VSG5 [9:8]. Selects Line Field where Active. Selects Second Line Field Repeat Signals.
REGION REGION REGION REGION REGION REGION REGION
V1-V6
VSEQSEL0
VSEQSEL1 SGLINE1 SGLINE
VSEQSEL2
VSEQSEL3
VSEQSEL4
VSEQSEL5
VSEQSEL6
FIELD SETTINGS: SEQUENCE CHANGE POSITIONS (SCP1-6) DEFINE EACH REGIONS FIELD. VSEQSEL0-6 SELECTS DESIRED V-SEQUENCE (0-9) EACH REGION. SGLINE1 REGISTER SELECTS WHICH LINE FIELD WILL CONTAIN SENSOR GATE PULSE(S).
Figure Complete Field Divided into Regions
REV.
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AD9995
Generating Line Alternation V-Sequence HBLK Second V-Pattern Group during Active Line
During resolution readout, some CCDs require different number vertical clocks alternate lines. AD9995 support this using VPATREPO VPATREPE registers. This allows different number VPAT repetitions programmed even lines. Note that only number repeats different even lines, VPAT group remains same. Additionally, HBLK signal also alternated even lines. When HBLKALT register high, HBLK TOG1 TOG2 positions will used lines TOG3-TOG6 positions will used even lines. This allows HBLK interval adjusted even lines needed. Figure shows example VPAT repetition alternation HBLK alternation used together. also possible VPAT HBLK alternation separately.
Most CCDs require additional vertical timing during sensor gate line. AD9995 supports option output second V-pattern group V1-V6 during line when sensor gates VSG1-VSG5 active. Figure shows typical line, which includes separate sets V-pattern groups V1-V6. V-pattern group start line selected same manner other regions, using appropriate VSEQSEL register. second V-pattern group, unique line, selected using VPATSECOND register, located with Field registers. start position second VPAT group uses VPATLEN register from selected VPAT registers. Because VPATLEN register used start position VPAT length, possible program multiple repetitions second VPAT group.
VPATREPO VPATREPE VPATREPO
TOG1 HBLK
TOG2
TOG3
TOG4
TOG1
TOG2
NOTES NUMBER REPEATS V-PATTERN GROUP ALTERNATED EVEN LINES. HBLK TOGGLE POSITIONS ALTERNATED BETWEEN EVEN LINES ORDER GENERATE DIFFERENT HBLK PATTERNS ODD/EVEN LINES.
Figure Odd/Even Line Alternation VPAT Repetitions HBLK Toggle Positions
START POSITION VPAT GROUP USES VPATLEN REGISTER
VPAT GROUP
Figure Example Second VPAT Group during Sensor Gate Line
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AD9995
Sweep Mode Operation
AD9995 contains additional mode vertical timing operation called Sweep mode. This mode used generate large number repetitive pulses that span multiple lines. example where this mode needed start readout operation. image exposure before image transferred sensor gate pulses, vertical interline registers should free charge. This accomplished quickly shifting charge using long series pulses from V1-V6 outputs. Depending vertical resolution CCD, 2,000 3,000 clock cycles will needed shift charge each vertical line. This operation will span across multiple line lengths. Normally, AD9995's vertical timing must contained within line length, when Sweep mode enabled, boundaries will ignored until region finished. enable Sweep mode within region, program appropriate SWEEP register high. Figure shows example Sweep mode operation. number vertical pulses needed will depend vertical resolution CCD. V1-V6 output signals generated using V-pattern registers (shown Table VII). single pulse created using polarity toggle position registers. number repetitions then programmed match number vertical shifts required CCD. Repetitions programmed V-sequence registers using VPATREP registers. This produces pulse train appropriate length. Normally, pulse train would truncated line length, with Sweep mode enabled this region, boundaries will ignored. Figure Sweep
region occupies lines. After Sweep mode region completed, next region, normal sequence operation will resume. When using Sweep mode, sure region boundaries (using sequence change positions) appropriate lines prevent Sweep operation from overlapping next V-sequence.
Multiplier Mode
generate very wide vertical timing pulses, vertical region configured into multiplier region. This mode uses V-pattern registers slightly different manner. Multiplier mode used support unusual timing requirements, such vertical pulses that wider than single line length. start polarity toggle positions still used same manner standard VPAT group programming, VPATLEN used differently. Instead using pixel counter counter) specify toggle position locations (VTOG1, VPAT group, VPATLEN multiplied with VTOG position allow very long pulses generated. calculate exact toggle position, counted pixels after start position, equation Multiplier ModeTogglePosition VTOG VPATLEN Because VTOG register multiplied VPATLEN, resolution toggle position placement reduced. VPATLEN toggle position accuracy reduced 4-pixel steps instead single pixel steps. Table VIII summarizes VPAT group registers used Multiplier mode operation. Multiplier mode, VPATREPO VPATREPE registers should always programmed same value highest toggle position.
LINE
LINE
LINE
LINE
LINE
V1-V6 REGION REGION SWEEP REGION REGION
Figure Example Sweep Region High Speed Vertical Shift
Table VIII. Multiplier Mode Register Parameters
Register MULTI VPOL VTOG1 VTOG2 VTOG3 VPATLEN VPATREP
Length
Range High/Low High/Low 0-4095 Pixel Location 0-4095 Pixel Location 0-4095 Pixel Location 0-1023 Pixels 0-4096
Description High enables Multiplier mode. Starting Polarity V1-V6 Signal Each VPAT Group. First Toggle Position V1-V6 Signal Each VPAT Group. Second Toggle Position V1-V6 Signal Each VPAT Group. Third Toggle Position V1-V6 Signal Each VPAT Group. Used Multiplier Factor Toggle Position Counter. VPATREPE/VPATREPO should same value TOG2
REV.
-21-
AD9995
example shown Figure illustrates this operation. first toggle position second toggle position non-Multiplier mode, this causes V-sequence toggle pixel then pixel within single line. However, toggle positions multiplied VTPLEN first toggle occurs pixel count second toggle occurs pixel count Sweep mode also been enabled allow toggle positions cross line boundaries.
Vertical Sensor Gate (Shift Gate) Patterns
interline CCD, vertical sensor gates (VSG) used transfer pixel charges from light-sensitive image area into light-shielded vertical registers. From light-shield vertical registers, image then read line-by-line using vertical transfer pulses V1-V6 conjunction with high speed horizontal clocks.
Table contains summary pattern registers. AD9995 five outputs, VSG1-VSG5. Each outputs assigned four programmed patterns using SGPATSEL registers. Each pattern generated similar manner V-pattern groups, with programmable start polarity (SGPOL), first toggle position (SGTOG1), second toggle position (SGTOG2). active line where VSG1-VSG5 pulses occur programmable using SGLINE1 SGLINE2 registers. Additionally, VSG1-VSG5 pulses individually disabled using SGMASK register. individual masking allows patterns preprogrammed, appropriate pulses different fields separately enabled. maximum flexibility, SGPATSEL, SGMASK, SGLINE registers separately programmable each field. More detail given Complete Field section.
START POSITION VPAT GROUP STILL PROGRAMMED V-SEQUENCE REGISTERS
VPATLEN
PIXEL NUMBER
V1-V6
MULTIPLIER MODE V-PATTERN GROUP PROPERTIES: START POLARITY (ABOVE: STARTPOL FIRST, SECOND, THIRD TOGGLE POSITIONS (ABOVE: VTOG1 VTOG2 LENGTH VPAT COUNTER (ABOVE: VPATLEN THIS MINIMUM RESOLUTION TOGGLE POSITION CHANGES. TOGGLE POSITIONS OCCUR LOCATION EQUAL (VTOG VPATLEN) SWEEP REGION ENABLED, V-PULSES ALSO CROSS BOUNDRIES, SHOWN ABOVE
Figure Example Multiplier Region Wide Vertical Pulse Timing
Table Pattern Registers (also Field Registers Table VII)
Register SGPOL SGTOG1 SGTOG2
Length
Range High/Low 0-4095 Pixel Location 0-4095 Pixel Location
Description Sensor Gate Starting Polarity Pattern First Toggle Position Pattern Second Toggle Position Pattern
PATTERNS
PROGRAMMABLE SETTINGS EACH PATTERN: START POLARITY PULSE FIRST TOGGLE POSITION SECOND TOGGLE POSITION ACTIVE LINE PULSES WITHIN FIELD (PROGRAMMABLE FIELD REGISTER, EACH PATTERN)
Figure Vertical Sensor Gate Pulse Placement
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AD9995
MODE Register
MODE register single register that selects field timing AD9995. Typically, field, V-sequence, V-pattern group information programmed into AD9995 startup. During operation, MODE register allows user select combination field timing meet current requirements system. advantage using MODE register conjunction with preprogrammed timing that greatly reduces system programming requirements during camera operation. Only register writes required when camera operating mode changed, rather than having write vertical timing information with each camera mode change. basic still camera application might require five different fields vertical timing: draft mode operation, autofocusing, three still image readout. register timing information five fields would loaded
startup. Then, during camera operation, MODE register would select which field timing would active, depending camera being used. Table shows MODE register bits used. three MSBs, D23-D21, used specify many total fields will used. value from selected using these three bits. remaining register bits divided into 3-bit sections select which fields used which order. seven fields used single MODE write. AD9995 will start with Field timing specified first Field bits, next will switch timing specified second Field bits, After completing total number fields specified Bits D21, AD9995 will repeat starting first Field again. This will continue until write MODE register occurs. Figure shows example MODE register settings different field configurations.
Table MODE Register Data Breakdown (D23 MSB)
Total Number Fields Use. Field Only Fields Invalid
Field Field Field Invalid
Field Field Field Invalid
Field Field Field Invalid
Field Field Field Invalid
Field Field Field Invalid
Field Field Field Invalid
Field Field Field Invalid
EXAMPLE TOTAL FIELDS FIELD FIELD FIELD FIELD FIELD FIELD MODE REGISTER CONTENTS 0x600088 FIELD FIELD FIELD
EXAMPLE TOTAL FIELDS FIELD FIELD FIELD FIELD MODE REGISTER CONTENTS 0x400023 FIELD FIELD
EXAMPLE TOTAL FIELDS FIELD FIELD FIELD FIELD FIELD FIELD FIELD FIELD MODE REGISTER CONTENTS 0x80050D FIELD FIELD FIELD FIELD
Figure Using MODE Register Select Field Timing
REV.
-23-
AD9995
VERTICAL TIMING EXAMPLE
better understand AD9995's vertical timing generation used, consider example timing chart Figure This particular example illustrates using general 3-field readout technique. described Field section, each readout field should divided into separate regions perform each step readout. sequence change positions (SCP) determine line boundaries each region, VSEQSEL registers will then assign particular V-sequence each region. V-sequences will contain specific timing information required each region: V1-V6 pulses (using VPAT groups), HBLK/CLPOB timing, patterns active lines. This particular timing example requires four regions each three fields, labeled Region Region Region Region Because AD9995 allows individual fields programmed, Field Field Field registers used meet requirements this timing example. four regions each field very similar this example, individual registers each field allow flexibility accommodate other timing charts. Region high speed vertical shift region. Sweep mode used generate this timing operation, with desired number high speed vertical pulses needed clear charge from CCD's vertical registers.
Region consists only lines, uses standard single line vertical shift timing. timing this region area will same timing Region Region sensor gate line, where pulses transfer image into vertical registers. This region require second V-pattern group active line. Region also uses standard single line vertical shift timing, same timing Region summary, four regions required each three fields. timing Regions essentially same, reducing complexity register programming. Other registers will need used during actual readout operation, such MODE register, shutter control registers (TRIGGER, SUBCK, VSUB, MSHUT, STROBE), gain register. These registers will explained other examples.
Important Note about Signal Polarities
When programming AD9995 generate V1-V6, VSG1-VSG5, SUBCK signals, important note that V-driver circuit usually inverts these signals. Carefully check required timing signals needed input output V-driver circuit being used adjust polarities AD9995's outputs accordingly.
-24-
REV.
Figure Timing Example: Dividing Each Field into Regions
REGION REGION FIELD REGION
REGION
REGION REGION
REGION REGION FIELD
REGION REGION
REGION REGION FIELD
REV.
SECOND FIELD READOUT THIRD FIELD READOUT CLOSED OPEN
EXPOSURE (tEXP) FIRST FIELD READOUT
-25-
SUBCK
MSHUT
OPEN
VSUB
AD9995
AD9995
SHUTTER TIMING CONTROL High Precision Shutter Operation
image exposure time controlled substrate clock signal (SUBCK), which pulses substrate clear accumulated charge. AD9995 supports three types electronic shuttering: normal shutter, high precision shutter, speed shutter. Along with SUBCK pulse placement, AD9995 accommodate different readout configurations further suppress SUBCK pulses during multiple field readouts. AD9995 also provides programmable outputs control external mechanical shutter (MSHUT), strobe/flash (STROBE), bias select signal (VSUB).
Normal Shutter Operation
High precision shuttering used same manner normal shuttering, uses additional register control very last SUBCK pulse. this mode, SUBCK still pulses once line, last SUBCK field will have additional SUBCK pulse whose location determined SUBCK2TOG register, shown Figure Finer resolution exposure time possible using this mode. Leaving SUBCK2TOG register value (0xFFFFFF) will disable last SUBCK pulse (default setting).
Speed Shutter Operation
default, AD9995 always operating normal shutter configuration which SUBCK signal pulsing every field (see Figure 26). SUBCK pulse occurs once line, total number repetitions within field will determine length exposure time. SUBCK pulse polarity toggle positions within line programmable using SUBCKPOL SUBCK1TOG registers (see Table XI). number SUBCK pulses field programmed SUBCKNUM register (Addr. 0x63). shown Figure SUBCK pulses will always begin line following active line, which specified SGACTLINE registers each field. SUBCKPOL, SUBCK1TOG, SUBCK2TOG, SUBCKNUM, SUBCKSUPPRESS registers updated start line after sensor gate line, described Updating Register Values section.
Normal high precision shutter operations used when exposure time less than field long. long exposure times greater than field interval, speed shutter operation used. AD9995 uses separate exposure counter achieve long exposure times. number fields speed shutter operation specified EXPOSURE register (Addr. 0x62). shown Figure this shutter mode will suppress SUBCK outputs 4095 fields periods). outputs suppressed during exposure period programming VDHDOFF register generate speed shutter operation, necessary trigger start long exposure writing TRIGGER register When this high, AD9995 will begin exposure operation next edge. value greater than zero specified EXPOSURE register, AD9995 will suppress SUBCK output subsequent fields.
tEXP
tEXP
SUBCK SUBCK PROGRAMMABLE SETTINGS: PULSE POLARITY USING SUBCKPOL REGISTER. NUMBER PULSES WITHIN FIELD USING SUBCKNUM REGISTER (SUBCKNUM ABOVE FIGURE). PIXEL LOCATION PULSE WITHIN LINE PULSEWIDTH PROGRAMMED USING SUBCK1 TOGGLE POSITION REGISTER.
Figure Normal Shutter Mode
tEXP
tEXP
SUBCK NOTES SECOND SUBCK PULSE ADDED LAST SUBCK LINE. LOCATION PULSE FULLY PROGRAMMABLE USING SUBCK2 TOGGLE POSITION REGISTER.
Figure High Precision Shutter Mode
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REV.
AD9995
exposure generated using TRIGGER register EXPOSURE register zero, behavior SUBCK will different than normal shutter high precision shutter operations, which TRIGGER register used.
SUBCK Suppression
frame readout mode will generally require additional fields SUBCK suppression (READOUT 3-field, 6-phase will require three additional fields SUBCK suppression after readout begins (READOUT SUBCK output required start back during last field readout, simply program READOUT register less than total number readout fields. Like exposure operation, readout operation must triggered using TRIGGER register.
Using TRIGGER Register
Normally, SUBCKs will begin pulse line following sensor gate line (VSG). With some CCDs, SUBCK pulse needs suppressed more lines following line. SUBCKSUPPRESS register allows suppression SUBCK pulses additional lines following line.
Readout after Exposure
After exposure, readout data occurs, beginning with sensor gate (VSG) operation. default, AD9995 generating pulses every field. case where only single exposure single readout frame needed, such CCD's preview mode, SUBCK pulses operating every field. However many cases, during readout SUBCK output needs further suppressed until readout completed. READOUT register specifies number additional fields after exposure continue suppression SUBCK. READOUT programmed zero seven additional fields, should preprogrammed startup, same time exposure write. typical interlaced
TRIGGER EXPOSURE
described previously, default AD9995 will output SUBCK signals every field. This works well continuous single field exposure readout operations, such CCD's live preview mode. However, requires longer exposure time, multiple readout fields needed, TRIGGER register needed initiate specific exposure readout sequences. Typically, exposure readout bits TRIGGER register used together. This will initiate complete exposureplus-readout operation. Once exposure been completed, readout will automatically occur. values EXPOSURE READOUT registers will determine length each operation.
tEXP
SUBCK
NOTES SUBCK SUPPRESSED MULTIPLE FIELDS PROGRAMMING EXPOSURE REGISTER GREATER THAN ZERO. ABOVE EXAMPLE USES EXPOSURE TRIGGER REGISTER MUST ALSO USED START SPEED EXPOSURE. VD/HD OUTPUTS ALSO SUPPRESSED USING VDHDOFF REGISTER
Figure Speed Shutter Mode Using EXPOSURE Register
Table Shutter Mode Register Parameters
Register TRIGGER READOUT EXPOSURE VDHDOFF SUBCKPOL* SUBCK1TOG* SUBCK2TOG* SUBCKNUM* SUBCKSUPPRESS*
Length
Range On/Off Five Signals Fields 0-4095 Fields On/Off High/Low 0-4095 Pixel Locations 0-4095 Pixel Locations 1-4095 Pulses 0-4095 Pulses
Description Trigger VSUB [0], MSHUT [1], STROBE [2], Exposure [3], Readout Start Number Fields Suppress SUBCK after Exposure Number Fields Suppress SUBCK during Exposure Time (Low Speed Shutter) Disable VD/HD Output during Exposure Off) SUBCK Start Polarity SUBCK1 SUBCK2 Toggle Positions First SUBCK Pulse (Normal Shutter) Toggle Positions Second SUBCK Pulse Last Line (High Precision) Total Number SUBCKs Field Pulse Line Number Lines Further Suppress SUBCK after Line
*Register updated, updated start line after sensor gate line.
REV.
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AD9995
possible independently trigger readout operation without triggering exposure operation. This will cause readout occur next SUBCK output will suppressed according value READOUT register. TRIGGER register also used control STROBE, MSHUT, VSUB signal transitions. Each these signals individually controlled, although they will dependent triggering exposure readout operation. Figure complete example triggering exposure readout operations.
VSUB Control
field. VSUB will remain active until image readout. Mode VSUB activated until start readout. additional function called VSUB KEEP-ON also available. When this high, VSUB output will remain (active) even after readout finished. disable VSUB later time, this back low.
MSHUT STROBE Control
readout bias (VSUB) programmed accommodate different CCDs. Figure shows different modes that available. Mode VSUB goes active during field last SUBCK when exposure begins. position (rising edge Figure programmable line within
TRIGGER VSUB
MSHUT STROBE operation shown Figures Table shows register parameters controlling MSHUT STROBE outputs. MSHUT output switched with MSHUTON registers, will remain until location specified MSHUTOFF registers. location MSHUTOFF fully programmable anywhere within exposure period, using (field), (line), (pixel) registers. STROBE pulse defined
VSG1
tEXP
SUBCK VSUB MODE MODE
READOUT
VSUB OPERATION: ACTIVE POLARITY POLARITY (ABOVE EXAMPLE VSUB ACTIVE HIGH). POSITION PROGRAMMABLE. MODE TURNS START EXPOSURE, MODE TURNS START READOUT. POSITION OCCURS READOUT. OPTIONAL VSUB KEEP-ON MODE WILL LEAVE VSUB ACTIVE READOUT.
Figure VSUB Programmability
TRIGGER EXPOSURE MSHUT
tEXP
SUBCK
MSHUT
MSHUT PROGRAMMABLE SETTINGS: ACTIVE POLARITY. POSITION UPDATED SWITCHED TIME. POSITION PROGRAMMED ANYWHERE FROM FIELD LAST SUBCK UNTIL FIELD BEFORE READOUT.
Figure MSHUT Output Programmability
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REV.
AD9995
positions. STROBON_FD field which STROBE turned measured from field containing last SUBCK before exposure begins. STROBON_ register gives line pixel positions with respect STROBON_FD. STROBE position programmable field, line, pixel location with respect field last SUBCK.
TRIGGER Register Limitations
same limitation applies triggering MSHUT signal. There must least idle field after completion MSHUT operation before another MSHUT operation programmed. VSUB trigger requires idle fields between exposure/ readout operations order ensure proper VSUB on/off triggering. VSUB signal required turned between each successive exposure/readout operation, this limitation ignored. VSUB Keep-On mode useful when successive exposure/readout operations required.
While TRIGGER register used perform complete exposure readout operation, there limitations use. Once exposure-plus-readout operation been triggered, another exposure/readout operation cannot triggered right away. There must least idle field intervals) before next exposure/readout triggered.
TRIGGER EXPOSURE STROBE
tEXP
SUBCK
STROBE
STROBE PROGRAMMABLE SETTINGS: ACTIVE POLARITY. POSITION PROGRAMMABLE FIELD DURING EXPOSURE TIME (WITH RESPECT FIELD CONTAINING LAST SUBCK). POSITION PROGRAMMABLE FIELD DURING EXPOSURE TIME.
Figure STROBE Output Programmability
Table XII. VSUB, MSHUT, STROBE Register Parameters
Register VSUBMODE[0] VSUBMODE[1] VSUBON[11:0] VSUBON[12] MSHUTPOL[0] MSHUTPOL[1] MSHUTON MSHUTOFF_FD MSHUTOFF_LNPX STROBPOL STROBON_FD STROBON_LNPX STROBOFF_FD STROBOFF_LNPX
Length
Range High/Low High/Low 0-4095 Line Location High/Low High/Low On/Off 0-4095 Line/Pix Location 0-4095 Field Location 0-4095 Line/Pix Location High/Low 0-4095 Field Location 0-4095 Line/Pix Location 0-4095 Field Location 0-4095 Line/Pix Location
Description VSUB Mode Mode Mode (See Figure 29). VSUB Keep-On Mode. VSUB will stay active after readout when high. VSUB Position. Active starting line field. VSUB Active Polarity. MSHUT Active Polarity. MSHUT Manual Enable Active Open). MSHUT Position Line [11:0] Pixel [23:12] Location. Field Location Switch MSHUT (Inactive Closed). Line/Pixel Position Switch MSHUT (Inactive Closed). STROBE Active Polarity. STROBE Field Location, with Respect Last SUBCK Field. STROBE Line/Pixel Position. STROBE Field Location, with Respect Last SUBCK Field. STROBE Line/Pixel Position.
REV.
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AD9995
EXPOSURE READOUT EXAMPLE
SERIAL WRITES
STILL IMAGE READOUT
SUBCK
STROBE
tEXP
MSHUT
MECHANICAL SHUTTER
OPEN
CLOSED
OPEN
VSUB MODE MODE
DRAFT IMAGE
DRAFT IMAGE
STILL IMAGE FIELD
STILL IMAGE FIELD
STILL IMAGE FIELD
DRAFT IMAGE
Figure Example Exposure Still Image Readout Using Shutter Signals Mode Register
Write READOUT register (Addr. 0x61) specify number fields further suppress SUBCK while data read out. this example, READOUT Write EXPOSURE register (Addr. 0x62) specify number fields suppress SUBCK outputs during exposure. this example, EXPOSURE Write TRIGGER register (Addr. 0x60) enable STROBE, MSHUT, VSUB signals, start exposure/readout operation. trigger these events Figure 32), register TRIGGER Readout will automatically occur after exposure period finished. Write MODE register (Addr. 0x1B) configure next five fields. first fields during exposure same current draft mode fields, following three fields still frame readout fields. registers Draft mode field three readout fields have already been programmed. VD/HD falling edge will update serial writes from VSUB mode (Addr. 0x67), VSUB output turns line specified VSUBON register (Addr. 0x68). STROBE output turns location specified STROBEON registers (Addr. 0x6E Addr. 0x71).
MSHUT output turns location specified MSHUTOFF registers (Addr. 0x6B 0x6C). next falling edge will automatically start first readout field. next falling edge will automatically start second readout field. next falling edge will automatically start third readout field. Write MODE register reconfigure single Draft mode field timing. Write MSHUTON register (Addr. 0x6A) open mechanical shutter. VD/HD falling edge will update serial write from outputs return Draft mode timing. SUBCK output resumes operation. MSHUT output returns position (active open). VSUB output returns position (inactive).
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AD9995
1.0F 1.0F REFB RESTORE 1.5V 0.1F 1.0V REFT 2.0V
AD9995
INTERNAL VREF FULL SCALE 12-BIT OUTPUT DATA LATCH DOUT PHASE
6dB-42dB
CCDIN
DOUT
GAIN REGISTER
OPTICAL BLACK CLAMP CLPOB PBLK DIGITAL FILTER
DOUT PHASE
CLPOB
PBLK
CLAMP LEVEL REGISTER
PRECISION TIMING GENERATION
TIMING GENERATION
Figure Analog Front Functional Block Diagram
ANALOG FRONT DESCRIPTION OPERATION
AD9995 signal processing chain shown Figure Each processing step essential achieving high quality image from pixel data.
Restore
with full-scale range When compared full-scale systems, equivalent gain range gain curve follows linear-in-dB characteristic. exact gain calculated gain register value using equation Gain (dB) (0.0351 Code) where code range 1023.
reduce large offset output signal, restore circuit used with external series coupling capacitor. This restores level signal approximately compatible with supply voltage AD9995.
Correlated Double Sampler
circuit samples each pixel twice extract video information reject frequency noise. timing shown Figure illustrates internally generated clocks, SHD, used sample reference level level signal, respectively. placement sampling edges determined setting SAMPCONTROL register located Addr. 0x63. Placement these clock signals critical achieving best performance from CCD.
Variable Gain Amplifier
GAIN (dB)
stage provides gain range programmable with 10-bit resolution through serial digital interface. minimum gain needed match input signal
GAIN REGISTER CODE
1023
Figure Gain Curve
REV.
-31-
AD9995
Converter
AD9995 uses high performance architecture optimized high speed power. Differential nonlinearity (DNL) performance typically better than LSB. uses input range. typical linearity noise performance plots AD9995.
Optical Black Clamp
optical black clamp loop used remove residual offsets signal chain track frequency variations CCD's black level. During optical black (shielded) pixel interval each line, output compared with fixed black level reference, selected user Clamp Level register. value programmed between steps. resulting error signal filtered reduce noise, correction value applied input through converter. Normally, optical black clamp loop turned once horizontal line, this loop updated more slowly suit particular application. external digital clamping used during postprocessing, AD9995 optical black clamping disabled using OPRMODE register. When loop disabled, Clamp Level register still used provide programmable offset adjustment.
CLPOB pulse should placed during CCD's optical black pixels. recommended that CLPOB pulse duration least pixels wide minimize clamp noise. Shorter pulsewidths used, clamp noise increase, ability track frequency variations black level will reduced. Horizontal Clamping Blanking section Horizontal Timing Sequence Example section timing examples.
Digital Data Outputs
AD9995 digital output data latched using DOUT PHASE register value, shown Figure Output data timing shown Figure also possible leave output latches transparent that data outputs valid immediately from converter. Programming CONTROL register will output latches transparent. data outputs also disabled (three-stated) setting CONTROL register data output coding normally straight binary, coding changed gray coding setting CONTROL register
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AD9995
POWER-UP SYNCHRONIZATION Recommended Power-Up Sequence Master Mode
When AD9995 powered following sequence recommended (refer Figure each step). Note that SYNC signal required Master mode operation. external SYNC pulse available, also possible generate internal SYNC pulse writing SYNCPOL register, described next section. Turn power supplies AD9995. Apply master clock input CLI. Reset internal AD9995 registers writing SW_RESET register (Addr. 0x10 Bank default, AD9995 Standby3 mode. place part into normal power operation, write 0x004 OPRMODE register (Addr. 0x00 Bank Write BANKSELECT register (Addr. 0x7F). This will select Register Bank Load Bank registers with required VPAT group, V-sequence, field timing information. Write BANKSELECT register select Bank default, internal timing core held reset state with TGCORE_RSTB register Write TGCORE_RSTB register (Addr. 0x15 Bank start internal timing core operation. Load required registers configure high speed timing, horizontal timing, shutter timing information. Configure AD9995 Master mode timing writing MASTER register (Addr. 0x20 Bank
Write OUT_CONTROL register (Addr. 0x11 Bank This will allow outputs become active after next SYNC rising edge. Generate SYNC event: SYNC high power-up, bring SYNC input minimum Then bring SYNC back high. This will cause internal counters reset will start VD/HD operation. first VD/HD edge allows most Bank register updates occur, including OUT_CONTROL enable outputs.
Table XIII. Power-Up Register Write Sequence
Address 0x10 0x00 0x7F 0x00-0xFF 0x7F 0x15 0x30-71 0x20 0x11 0x13
Data 0x01 0x04 0x01 0x00 0x01 0x01 0x01 0x01
Description Reset Registers Default Values Power Oscillator Select Register Bank VPAT, V-Sequence, Field Timing Select Register Bank Reset Internal Timing Core Horizontal Shutter Timing Configure Master Mode Enable Outputs after SYNC SYNCPOL (for Software SYNC Only)
Generating Software SYNC without External SYNC Signal
external SYNC pulse available, possible generate internal SYNC AD9995 writing SYNCPOL register (Addr. 0x13). software SYNC option used, SYNC input (Pin should tied ground (VSS). After power-up, follow same procedure before Steps Then, Step instead using external SYNC pulse, write SYNCPOL register. This will generate SYNC internally, timing operation will begin.
(INPUT)
(INPUT)
tPWR
SERIAL WRITES SYNC (INPUT)
tSYNC
(OUTPUT)
FIELD
(OUTPUT)
H2/H4 DIGITAL OUTPUTS H1/H3, DCLK CLOCKS ACTIVE WHEN CONTROL REGISTER UPDATED VD/HD EDGE
Figure Recommended Power-Up Sequence Synchronization, Master Mode
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AD9995
SYNC during Master Mode Operation STANDBY MODE OPERATION
SYNC input used time during operation resync AD9995 counters with external timing, shown Figure operation digital outputs suspended during SYNC operation setting SYNCSUSPEND register (Addr. 0x14)
Power-Up Synchronization Slave Mode
AD9995 contains three different standby modes optimize overall power dissipation particular application. Bits [1:0] OPRMODE register control power-down state device: OPRMODE [1:0] Normal Operation (Full Power) OPRMODE[1:0] Standby Mode OPRMODE[1:0] Standby Mode OPRMODE[1:0] Standby Mode (Lowest Overall Power) Table summarizes operation each power-down mode. Note that OUT_CONTROL register takes priority over Standby Standby modes determining digital output states, Standby mode takes priority over OUT_CONTROL. Standby lowest power consumption, even shuts down crystal oscillator circuit between CLO. Therefore, being used with crystal generate master clock, this circuit will powered down there will clock signal. When returning from Standby mode normal operation, timing core must reset least after OPRMODE register written This will allow sufficient time crystal circuit settle.
power-up procedure Slave mode operation same procedure described Master mode operation, with exceptions: Eliminate Step write part into Master mode. SYNC pulse required Slave mode. Substitute Step with starting external signals. This will synchronize part, allow Bank register updates, start timing operation. When AD9995 used Slave mode, inputs used synchronize internal counters. Following falling edge there will latency master clock cycles (CLI) after falling edge until internal H-counter will reset. reset operation shown Figure
SYNC
SUSPEND
H124, V1-V4, VSG, SUBCK NOTES SYNC RISING EDGE RESETS VD/HD COUNTERS ZERO. SYNC POLARITY PROGRAMMABLE USING SYNCPOL REGISTER (ADDR 0x13). DURING SYNC LOW, INTERNAL COUNTERS RESET VD/HD SUSPENDED USING SYNCSUSPEND REGISTER (ADDR 0x14). SYNCSUSPEND VERTICAL CLOCKS, H1-H2, HELD THEIR DEFAULT POLARITIES. SYNCSUSPEND CLOCK OUTPUTS CONTINUE OPERATE NORMALLY UNTIL SYNC RESET EDGE.
Figure SYNC Timing Synchronize AD9995 with External Timing
H-COUNTER RESET
H-COUNTER (PIXEL COUNTER)
NOTES INTERNAL H-COUNTER RESET CYCLES AFTER FALLING EDGE (WHEN USING VDHDPOL TYPICAL TIMING RELATIONSHIP: RISING EDGE COINCIDENT WITH FALLING EDGE.
Figure External VD/HD Internal H-Counter Synchronization, Slave Mode
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AD9995
Table XIV. Standby Mode Operation
Block Timing Core Oscillator VSG1 VSG2 VSG3 VSG4 VSG5 SUBCK VSUB MSHUT STROBE DCLK DOUT
Standby (Default) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
OUT_CONT LO2, Change Change Change Running VDHDPOL Value VDHDPOL Value
Standby Running (4.3 (4.3 (4.3 (4.3 (4.3 VDHDPOL Value VDHDPOL Value
Standby Only REFT, REFB Running (4.3 (4.3 (4.3 (4.3 (4.3 Running Running Running
NOTES exit Standby first write OPRMODE[1:0], then reset Timing Core after ~500 guarantee proper settling oscillator. Standby mode takes priority over OUT_CONTROL determining output polarities. These polarities assume OUT_CONT because OUT_CONTROL takes priority over Standby Standby will drive strength minimum value (4.3 mA).
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AD9995
ANALOG SUPPLY 0.1F STROBE CIRCUIT MECHANICAL SHUTTER CIRCUIT SERIAL INTERFACE ASIC
EXTERNAL SYNC FROM ASIC/DSP LINE/FIELD/DCLK ASIC/DSP
DCLK
STROBE MSHUT
DVDD DVSS
SYNC
DRVDD DRVSS 0.1F
IDENTIFIER
REFB REFT AVSS CCDIN AVDD TCVDD TCVSS RGVDD RGVSS 0.1F 0.1F 0.1F OUTPUT FROM MASTER CLOCK INPUT ANALOG SUPPLY 4.7F SUPPLY
AD9995
VIEW
DATA OUTPUTS
DRIVER SUPPLY 4.7F
VSUB SUBCK
0.1F
VSUB
4.7F
VSG3
VSG1 VSG2
VSG4
HVSS
VSG5
HVDD
H1-H4
V1-V4, VSG1-VSG4, SUBCK V-DRIVER 0.1F
4.7F
H1-H4 SUPPLY
Figure Typical Circuit Configuration CIRCUIT LAYOUT INFORMATION
AD9995 typical circuit connection shown Figure layout critical achieving good image quality from AD999x products. supply pins, particularly AVDD1, TCVDD, RGVDD, HVDD supplies, must decoupled ground with good quality, high frequency chip capacitors. decoupling capacitors should located close possible supply pins should have very impedance path continuous ground plane. There should also larger value bypass capacitor each main supply-AVDD, RGVDD, HVDD, DRVDD-although this necessary each individual pin. most applications, easier share supply RGVDD HVDD, which done long individual supply pins separately bypassed. separate supply also used DRVDD, this supply should still decoupled same ground plane rest chip. separate ground DRVSS recommended. recommended that exposed paddle bottom package soldered large pad, with multiple vias connecting ground plane. analog bypass pins (REFT, REFB) should also carefully decoupled ground close possible their respective pins. analog input (CCDIN) capacitor should also located close pin.
H1-H4 traces should designed have inductance avoid excessive distortion signals. Heavier traces recommended because large transient current demand H1-H4 CCD. possible, locating AD9995 physically closer will reduce inductance these lines. always, routing path should direct possible from AD9995 CCD. AD9995 also contains on-chip oscillator driving external crystal. Figure shows example application using typical crystal. exact values external resistors capacitors, best consult with crystal manufacturer's data sheet.
AD9995
500M 20pF
20pF
24MHz XTAL
Figure Crystal Driver Application
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AD9995
SERIAL INTERFACE TIMING
internal registers AD9995 accessed through 3-wire serial interface. Each register consists 8-bit address 24-bit data-word. Both 8-bit address 24-bit dataword written starting with LSB. write each register, 32-bit operation required, shown Figure 40a. Although many registers fewer than bits wide, bits must written each register. example, register only bits wide, upper bits don't cares filled with during serial write operation. fewer than bits written, register will updated with data.
8-BIT ADDRESS SDATA
Figure shows more efficient write registers, using AD9995's address auto-increment capability. Using this method, lowest desired address written first, followed multiple 24-bit data-words. Each 24-bit data-word will automatically written next highest register address. eliminating need write each 8-bit address, faster register loading achieved. Continuous write operations used starting with register location, used write registers, many entire register space.
24-BIT DATA
NOTES SDATA BITS LATCHED RISING EDGES. IDLE HIGH BETWEEN WRITE OPERATIONS. BITS MUST WRITTEN: BITS ADDRESS BITS DATA. REGISTER LENGTH BITS, "DON'T CARE" BITS MUST USED COMPLETE 24-BIT DATA LENGTH. DATA VALUES UPDATED SPECIFIED REGISTER LOCATION DIFFERENT TIMES, DEPENDING PARTICULAR REGISTER WRITTEN REGISTER UPDATES SECTION MORE INFORMATION.
Figure 40a. Serial Write Operation
DATA STARTING REGISTER ADDRESS SDATA
DATA NEXT REGISTER ADDRESS
NOTES MULTIPLE SEQUENTIAL REGISTERS LOADED CONTINUOUSLY. FIRST (LOWEST ADDRESS) REGISTER ADDRESS WRITTEN, FOLLOWED MULTIPLE 24-BIT DATA-WORDS. ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 24-BIT DATA-WORD (ALL BITS MUST WRITTEN). HELD UNTIL LAST DESIRED REGISTER BEEN LOADED.
Figure 40b. Continuous Serial Write Operation
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AD9995
Register Address Banks
AD9995 address space divided into different register banks, referred Register Bank Register Bank Figure illustrates banks divided. Register Bank contains registers AFE, miscellaneous functions, VD/HD parameters, timing core, CLPOB masking, patterns, shutter functions. Register Bank contains information V-pattern groups, V-sequences, field information.
When writing AD9995, Address 0x7F used specify which address bank being written write Bank Address 0x7F should write Bank Address 0x7F should Note that Register Bank contains many unused addresses. undefined addresses between 0x00 0x7F considered don't cares, acceptable these addresses filled with during continuous register write operation. However, undefined addresses above 0x7F must written AD9995 operate properly.
REGISTER BANK
ADDR 0x00
REGISTER BANK
ADDR 0x00 ADDR 0x10 MISCELLANEOUS REGISTERS ADDR 0x20 ADDR 0x30 ADDR 0x40 ADDR 0x50 PATTERN REGISTERS ADDR 0x60 SHUTTER REGISTERS ADDR 0xCF ADDR 0xD0 VD/HD REGISTERS TIMING CORE REGISTERS CLPOB MASK REGISTERS ADDR 0x7E ADDR 0x7F ADDR 0x80 REGISTERS
VPAT0-VPAT9 REGISTERS
SWITCH REGISTER BANK
VSEQ0-VSEQ9 REGISTERS
ADDR 0x7F ADDR 0x8F
SWITCH REGISTER BANK INVALID-DO ACCESS
FIELD 0-FIELD REGISTERS ADDR 0xFF
ADDR 0xFF
WRITE ADDRESS 0x7F SWITCH REGISTER BANKS
Figure Layout Internal Register Banks
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AD9995
Updating Register Values
AD9995's internal registers updated different times, depending particular register. Table summarizes four different types register updates: Updated: Some registers Bank updated immediately, soon 24th data (D23) written. These registers used functions that require gating with next boundary, such power-up reset functions. These registers lightly shaded gray Bank register list. Bank Select register (Addr. 0x7F Bank also updated. Updated: Most registers Bank well Field registers Bank updated next falling edge. updating these values next edge, current field will corrupted register values will applied next field. Bank register updates further delayed past falling edge using UPDATE register (Addr. 0x19). This will delay updated register updates line field. Note that Bank registers affected UPDATE register.
SG-Line Updated: registers Bank updated active line, falling edge. These registers control SUBCK signal that SUBCK output will updated until after line been completed. These registers darkly shaded gray Bank register list. Updated: Bank V-pattern group V-sequence registers (Addr. 0x00 through 0xCF, excluding 0x7F) updated next SCP, where they will used. example, Figure this field selected Region V-Sequence vertical outputs. This means that write V-Sequence registers, V-pattern group registers that referenced V-Sequence will updated SCP1. multiple writes done same register, last done before SCP1 will that updated. Likewise, register writes V-Sequence registers will updated SCP2, register writes V-Sequence registers will updated SCP3.
Table Register Update Locations
Update Type Updated Updated Line Updated Updated
Register Bank Bank Only Bank Bank Bank Only Bank Only
Description Register immediately updated when 24th data (D23) clocked Register updated falling edge. updated registers Bank delayed further using UPDATE register Address 0x19 Bank Bank updates will affected UPDATE register. Register updated falling edge SG-active line. Register updated next when register will used.
UPDATED SERIAL WRITE
UPDATED
UPDATED
UPDATED
SGLINE
V1-V6
VSEQ2 REGION
VSEQ3 REGION
VSEQ5 REGION
VSEQ8 REGION
Figure Register Update Locations (See Table Definitions)
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AD9995
COMPLETE LISTING REGISTER BANK
registers updated, except where noted: address default values hexadecimal.
Updated
SG-Line Updated
Table XVI. Register
Data Default Address Content Value Register Name [11:0] [9:0] [7:0] [11:0] OPRMODE VGAGAIN CLAMPLEVEL CTLMODE
Register Description Operation Modes (see Table XXIV detail). Gain. Optical Black Clamp Level. Control Modes (see Table detail).
Table XVII. Miscellaneous Register
Data Default Address Content Value Register Name [11:0] [23:0] [1:0] TEST UPDATE PREVENTUPDATE MODE FIELDVAL SW_RST OUTCONTROL TEST SYNCPOL SYNCSUSPEND TGCORE_RSTB OSC_PWRDOWN
Register Description Software Reset. Reset registers default, then self-clear back Output Control. Make outputs inactive. Internal Only. Must SYNC Active Polarity Active Low). Suspend Clocks during SYNC Active Suspend). Timing Core Reset Bar. Reset Core, Resume Operation. Oscillator Power-Down Oscillator powered-down). Unused. Internal Only. Must Serial Update. Line (HD) field update updated registers. Prevents Update Updated Registers. Prevent update. Mode Register. Field Value Sync. Next Field Next Field Next Field
Table XVIII. VD/HD Register
Data Default Address Content Value Register Name [17:0] MASTER VDHDPOL VDHDRISE
Register Description VD/HD Master Slave Timing Slave mode). VD/HD Active Polarity. Low, High. Rising Edge Location [17:12] [11:0].
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Table XIX. Timing Core Register
Data Default Address Content Value Register Name [12:0] [12:0] [12:0] [1:0] 01001 01001 00801 CLIDIVIDE H1CONTROL H3CONTROL RGCONTROL HBLKRETIME
Register Description Divide Input Clock Divide Signal Control: Polarity [0](0 Inversion, Inversion). Positive Edge Location [6:1]. Negative Edge Location [12:7]. Signal Control: Polarity [0](0 Inversion, Inversion). Positive Edge Location [6:1]. Negative Edge Location [12:7]. Signal Control: Polarity [0](0 Inversion, Inversion). Positive Edge Location [6:1]. Negative Edge Location [12:7]. Retime HBLK Internal H1/H3 Clocks. Retime [0]. Retime [1]. Preferred setting each bit. Setting each will cycle delay HBLK toggle positions. Drive Strength Control [2:0], [5:3], [8:6], [11:9], [14:12]. Drive Current Values: Off, 12.9 17.2 21.5 25.8 30.1 SHP/SHD Sample Control: Sampling Location [5:0]. Sampling Location [11:6]. DOUT Phase Control [5:0]. DCLK Mode [6]. DOUTDELAY [8:7].
[14:0]
1249
DRVCONTROL
[11:0] [8:0]
00024
SAMPCONTROL DOUTCONTROL
Table CLPOB Masking Register
Data Default Address Content Value Register Name [23:0] [23:0] [11:0] FFFFFF CLPMASK01 FFFFFF CLPMASK23 FFFFFF CLPMASK4
Register Description CLPOB Line Masking. Line [11:0]. Line [23:0]. CLPOB Line Masking. Line [11:0]. Line [23:0]. CLPOB Line Masking. Line [11:0].
Table XXI. Pattern Register
Data Default Address Content Value Register Name [3:0] [23:0] [23:0] [23:0] [23:0] SGPOL
Register Description Start Polarity Patterns. Pattern [0]. Pattern [1]. Pattern [2]. Pattern [3]. Pattern Toggle Position [11:0]. Toggle Position [23:12]. Pattern Toggle Position [11:0]. Toggle Position [23:12]. Pattern Toggle Position [11:0]. Toggle Position [23:12]. Pattern Toggle Position [11:0]. Toggle Position [23:12].
FFFFFF SGTOG12_0 FFFFFF SGTOG12_1 FFFFFF SGTOG12_2 FFFFFF SGTOG12_3
Table XXII. Shutter Control Register
Data Default Address Content Value Register Name [4:0] TRIGGER
Register Description Trigger VSUB [0], MSHUT [1], STROBE [2], Exposure [3], Readout [4]. Note that trigger readout automatically occur after exposure period, both exposure readout should triggered together. Number Fields Suppress SUBCK Pulses after Line. Number Fields Suppress SUBCK Pulses. disable VD/HD outputs during exposure (when field). Number SUBCK Pulses Suppress after Line. Number SUBCK Pulses Field. SUBCK Pulse Start Polarity. First SUBCK Pulse. Toggle Position [11:0]. Toggle Position [23:0]. Second SUBCK Pulse. Toggle Position [11:0]. Toggle Position [23:0]. -41-
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[2:0] [11:0] [12] [11:0] [23:12] [23:0] [23:0]
READOUT EXPOSURE VDHDOFF SUBCKSUPPRESS SUBCKNUM SUBCKPOL
FFFFFF SUBCK1TOG FFFFFF SUBCK2TOG
AD9995
Table XXII. Shutter Control Register (continued)
Data Default Address Content Value Register Name [1:0] [12:0] [1:0] [23:0] [11:0] [23:0] [11:0] [23:0] [11:0] [23:0] 1000 VSUBMODE VSUBON MSHUTPOL MSHUTON MSHUTOFF_FD MSHUTOFF_LNPX STROBPOL STROBON_FD STROBON_LNPX STROBOFF_FD STROBOFF_LNPX
Register Description VSUB Readout Mode [0]. VSUB Keep-On Mode [1]. VSUB Position [11:0]. VSUB Active Polarity [12]. MSHUT Active Polarity [0]. MSHUT Manual Enable [1]. MSHUT Position. Line [11:0]. Pixel [23:0]. MSHUT Field Position. MSHUT Position. Line [11:0]. Pixel [23:12]. STROBE Active Polarity. STROBE Field Position. STROBE Position. Line [11:0]. Pixel [23:12]. STROBE Field Position. STROBE Position. Line [11:0]. Pixel [23:12].
Table XXIII. Register Selection
Data Default Address Content Value Register Name BANKSELECT1
Register Description Register Bank Access from Bank Bank Bank Bank
Table XXIV. Operation Register Detail
Data Default Address Content Value Register Name [1:0] [7:6] PWRDOWN CLPENABLE CLPSPEED TEST PBLK_LVL TEST DCBYP TEST
Register Description Normal Operation, Standby Standby Standby Disable Clamp, Enable Clamp. Select Normal Clamp Settling, Select Fast Clamp Settling. Test Only. DOUT Value during PBLK: Blank Zero, Blank Clamp Level. Test Only. Enable Restore Circuit, Bypass Restore Circuit during PBLK. Test Only.
Table XXV. Control Register Detail
Data Default Address Content Value Register Name [1:0] TEST TEST DOUTDISABLE DOUTLATCH GRAYENCODE
Register Description Test Only. Test Only. Data Outputs Driven, Data Outputs Three-Stated. Latch Data Outputs with DOUT Phase, Output Latch Transparent. Binary Encode Data Outputs, Gray Encode Data Outputs.
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COMPLETE LISTING REGISTER BANK
V-pattern group V-sequence registers updated, Field registers updated. address default values hexadecimal.
Table XXVI. V-Pattern Group (VPAT0) Register
Data Default Address Content Value Register Name [5:0] [11:6] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] VPOL_0 UNUSED VPATLEN_0 V1TOG1_0 V1TOG2_0 V1TOG3_0 V2TOG1_0 V2TOG2_0 V2TOG3_0 V3TOG1_0 V3TOG2_0 V3TOG3_0 V4TOG1_0 V4TOG2_0 V4TOG3_0 V5TOG1_0 V5TOG2_0 V5TOG3_0 V6TOG1_0 V6TOG2_0 V6TOG3_0 FREEZE1_0 RESUME1_0 FREEZE2_0 RESUME2_0
Description VPAT0 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5]. Unused. Total Length VPAT0. Note: using VPAT0 second V-sequence active line, this value start position second V-sequence. Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position V1-V6 Freeze Position V1-V6 Resume Position V1-V6 Freeze Position V1-V6 Resume Position
Table XXVII. V-Pattern Group (VPAT1) Register
Data Default Address Content Value Register Name [5:0] [11:6] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] VPOL_1 UNUSED VPATLEN_1 V1TOG1_1 V1TOG2_1 V1TOG3_1 V2TOG1_1 V2TOG2_1 V2TOG3_1 V3TOG1_1 V3TOG2_1 V3TOG3_1 V4TOG1_1 V4TOG2_1 V4TOG3_1
Description VPAT1 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5]. Unused. Total Length VPAT1. Note: using VPAT1 second V-sequence active line, this value start position second V-sequence. Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position -43-
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AD9995
Table XXVII. V-Pattern Group (VPAT1) Register (continued)
Data Default Address Content Value Register Name [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] V5TOG1_1 V5TOG2_1 V5TOG3_1 V6TOG1_1 V6TOG2_1 V6TOG3_1 FREEZE1_1 RESUME1_1 FREEZE2_1 RESUME2_1
Description Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position V1-V6 Freeze Position V1-V6 Resume Position V1-V6 Freeze Position V1-V6 Resume Position
Table XXVIII. V-Pattern Group (VPAT2) Register
Data Default Address Content Value Register Name [5:0] [11:6] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] VPOL_2 UNUSED VPATLEN_2 V1TOG1_2 V1TOG2_2 V1TOG3_2 V2TOG1_2 V2TOG2_2 V2TOG3_2 V3TOG1_2 V3TOG2_2 V3TOG3_2 V4TOG1_2 V4TOG2_2 V4TOG3_2 V5TOG1_2 V5TOG2_2 V5TOG3_2 V6TOG1_2 V6TOG2_2 V6TOG3_2 FREEZE1_2 RESUME1_2 FREEZE2_2 RESUME2_2
Description VPAT2 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5]. Unused. Total Length VPAT2. Note: using VPAT2 second V-sequence active line, this value start position second V-sequence. Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position V1-V6 Freeze Position V1-V6 Resume Position V1-V6 Freeze Position V1-V6 Resume Position
Table XXIX. V-Pattern Group (VPAT3) Register
Data Default Address Content Value Register Name [5:0] [11:6] [23:12] [11:0] [23:12] VPOL_3 UNUSED VPATLEN_3 V1TOG1_3 V1TOG2_3
Description VPAT3 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5]. Unused. Total Length VPAT3. Note: using VPAT3 second V-sequence active line, this value start position second V-sequence. Toggle Position Toggle Position -44- REV.
AD9995
Table XXIX. V-Pattern Group (VPAT3) Register (continued)
Data Default Address Content Value Register Name [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] V1TOG3_3 V2TOG1_3 V2TOG2_3 V2TOG3_3 V3TOG1_3 V3TOG2_3 V3TOG3_3 V4TOG1_3 V4TOG2_3 V4TOG3_3 V5TOG1_3 V5TOG2_3 V5TOG3_3 V6TOG1_3 V6TOG2_3 V6TOG3_3 FREEZE1_3 RESUME1_3 FREEZE2_3 RESUME2_3
Description Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position V3Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position V1-V6 Freeze Position V1-V6 Resume Position V1-V6 Freeze Position V1-V6 Resume Position
Table XXX. V-Pattern Group (VPAT4) Register
Data Default Address Content Value Register Name [5:0] [11:6] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] VPOL_4 UNUSED VPATLEN_4 V1TOG1_4 V1TOG2_4 V1TOG3_4 V2TOG1_4 V2TOG2_4 V2TOG3_4 V3TOG1_4 V3TOG2_4 V3TOG3_4 V4TOG1_4 V4TOG2_4 V4TOG3_4 V5TOG1_4 V5TOG2_4 V5TOG3_4 V6TOG1_4 V6TOG2_4 V6TOG3_4 FREEZE1_4 RESUME1_4 FREEZE2_4 RESUME2_4
Description VPAT4 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5]. Unused. Total Length VPAT4. Note: using VPAT4 second V-sequence active line, this value start position second V-sequence. Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position V3Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position V1-V6 Freeze Position V1-V6 Resume Position V1-V6 Freeze Position V1-V6 Resume Position -45-
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AD9995
Table XXXI. V-Pattern Group (VPAT5) Register
Data Default Address Content Value Register Name [5:0] [11:6] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] VPOL_5 UNUSED VPATLEN_5 V1TOG1_5 V1TOG2_5 V1TOG3_5 V2TOG1_5 V2TOG2_5 V2TOG3_5 V3TOG1_5 V3TOG2_5 V3TOG3_5 V4TOG1_5 V4TOG2_5 V4TOG3_5 V5TOG1_5 V5TOG2_5 V5TOG3_5 V6TOG1_5 V6TOG2_5 V6TOG3_5 FREEZE1_5 RESUME1_5 FREEZE2_5 RESUME2_5
Description VPAT5 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5]. Unused. Total Length VPAT5. Note: using VPAT5 second V-sequence active line, this value start position second V-sequence. Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position V1-V6 Freeze Position V1-V6 Resume Position V1-V6 Freeze Position V1-V6 Resume Position
Table XXXII. V-Pattern Group (VPAT6) Register
Data Default Address Content Value Register Name [5:0] [11:6] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] VPOL_6 UNUSED VPATLEN_6 V1TOG1_6 V1TOG2_6 V1TOG3_6 V2TOG1_6 V2TOG2_6 V2TOG3_6 V3TOG1_6 V3TOG2_6 V3TOG3_6 V4TOG1_6 V4TOG2_6 V4TOG3_6 V5TOG1_6 V5TOG2_6
Description VPAT6 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5]. Unused. Total Length VPAT6. Note: using VPAT6 second V-sequence active line, this value start position second V-sequence. Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position
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REV.
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Table XXXII. V-Pattern Group (VPAT6) Register (continued)
Data Default Address Content Value Register Name [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] V5TOG3_6 V6TOG1_6 V6TOG2_6 V6TOG3_6 FREEZE1_6 RESUME1_6 FREEZE2_6 RESUME2_6
Description Toggle Position Toggle Position Toggle Position Toggle Position V1-V6 Freeze Position V1-V6 Resume Position V1-V6 Freeze Position V1-V6 Resume Position
Table XXXIII. V-Pattern Group (VPAT7) Register
Data Default Address Content Value Register Name [5:0] [11:6] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] VPOL_7 UNUSED VPATLEN_7 V1TOG1_7 V1TOG2_7 V1TOG3_7 V2TOG1_7 V2TOG2_7 V2TOG3_7 V3TOG1_7 V3TOG2_7 V3TOG3_7 V4TOG1_7 V4TOG2_7 V4TOG3_7 V5TOG1_7 V5TOG2_7 V5TOG3_7 V6TOG1_7 V6TOG2_7 V6TOG3_7 FREEZE1_7 RESUME1_7 FREEZE2_7 RESUME2_7
Description VPAT7 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5]. Unused. Total Length VPAT7. Note: using VPAT7 second V-sequence active line, this value start position second V-sequence. Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position V1-V6 Freeze Position V1-V6 Resume Position V1-V6 Freeze Position V1-V6 Resume Position
Table XXXIV. V-Pattern Group (VPAT8) Register
Data Default Address Content Value Register Name [5:0] [11:6] [23:12] [11:0] [23:12] [11:0] [23:12] VPOL_8 UNUSED VPATLEN_8 V1TOG1_8 V1TOG2_8 V1TOG3_8 V1TOG4_8
Description VPAT8 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5]. Unused. Total Length VPAT8. Note: using VPAT8 second V-sequence active line, this value start position second V-sequence. Toggle Position Toggle Position Toggle Position Toggle Position -47-
REV.
AD9995
Table XXXIV. V-Pattern Group (VPAT8) Register (continued)
Data Default Address Content Value Register Name [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] V2TOG1_8 V2TOG2_8 V3TOG3_8 V3TOG4_8 V3TOG1_8 V4TOG2_8 V4TOG3_8 V4TOG4_8 V5TOG1_8 V5TOG2_8 V5TOG3_8 V6TOG4_8 V6TOG1_8 V6TOG2_8 V6TOG3_8 V6TOG4_8 V6TOG1_8 V6TOG2_8 V6TOG3_8 V6TOG4_8 FREEZE1_8 RESUME1_8 FREEZE2_8 RESUME2_8 UNUSED
Description Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position V1-V6 Freeze Position V1-V6 Resume Position V1-V6 Freeze Position V1-V6 Resume Position Unused
Table XXXV. V-Pattern Group (VPAT9) Register
Data Default Address Content Value Register Name [5:0] [11:6] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] VPOL_9 UNUSED VPATLEN_9 V1TOG1_9 V1TOG2_9 V1TOG3_9 V1TOG4_9 V2TOG1_9 V2TOG2_9 V3TOG3_9 V3TOG4_9 V3TOG1_9 V4TOG2_9 V4TOG3_9 V4TOG4_9 V5TOG1_9 V5TOG2_9 V5TOG3_9 V6TOG4_9
Description VPAT9 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5]. Unused. Total Length VPAT9. Note: using VPAT9 second V-sequence active line, this value start position second V-sequence. Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position -48- REV.
AD9995
Table XXXV. V-Pattern Group (VPAT9) Register (continued)
Data Default Address Content Value Register Name [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] V6TOG1_9 V6TOG2_9 V6TOG3_9 V6TOG4_9 V6TOG1_9 V6TOG2_9 V6TOG3_9 V6TOG4_9 FREEZE1_9 RESUME1_9 FREEZE2_9 RESUME2_9
Description Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position Toggle Position V1-V6 Freeze Position V1-V6 Resume Position V1-V6 Freeze Position V1-V6 Resume Position
Table XXXVI. Register Selection (SCK Updated Register)
Data Default Address Content Value Register Name BANKSELECT2
Register Description Register Bank Access from Bank Bank Bank Bank
Table XXXVII. V-Sequence (VSEQ0) Register
Data Default Address Content Value Register Name [1:0] [7:4] [9:8] [11:10] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] HBLKMASK_0 CLPOBPOL CLPOBPOL_0 PBLKPOL PBLKPOL_0 VPATSEL VPATSEL_0 VMASK VMASK_0 HBLKALT_0 UNUSED VPATREPO_0 VPATREPE_0 VPATSTART_0 HDLEN_0 PBLKTOG1_0 PBLKTOG2_0 HBLKTOG1_0 HBLKTOG2_0 HBLKTOG3_0 HBLKTOG4_0 HBLKTOG5_0 HBLKTOG6_0 CLPOBTOG1_0 CLPOBTOG2_0
Description Masking Polarity during HBLK. [0]. [1]. CLPOB Start Polarity PBLK Start Polarity Selected V-Pattern Group V-Sequence Enable Masking V-Outputs (Specified FREEZE/RESUME Registers) Enable HBLK Alternation Unused Number Selected V-Pattern Group Repetitions Lines Number Selected V-Pattern Group Repetitions Even Lines Start Position Line Selected V-Pattern Group Line Length (Number Pixels) V-Sequence PBLK Toggle Position V-Sequence PBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence CLPOB Toggle Position V-Sequence CLPOB Toggle Position V-Sequence
REV.
-49-
AD9995
Table XXXVIII. V-Sequence (VSEQ1) Register
Data Default Address Content Value Register Name [1:0] [7:4] [9:8] [11:10] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] HBLKMASK_1 CLPOBPOL CLPOBPOL_1 PBLKPOL PBLKPOL_1 VPATSEL VPATSEL_1 VMASK VMASK_1 HBLKALT_1 UNUSED VPATREPO_1 VPATREPE_1 VPATSTART_1 HDLEN_1 PBLKTOG1_1 PBLKTOG2_1 HBLKTOG1_1 HBLKTOG2_1 HBLKTOG3_1 HBLKTOG4_1 HBLKTOG5_1 HBLKTOG6_1 CLPOBTOG1_1 CLPOBTOG2_1
Description Masking Polarity during HBLK. [0]. [1]. CLPOB Start Polarity PBLK Start Polarity Selected V-Pattern Group V-Sequence Enable Masking V-Outputs (Specified FREEZE/RESUME Registers) Enable HBLK Alternation Unused Number Selected V-Pattern Group Repetitions Lines Number Selected V-Pattern Group Repetitions Even Lines Start Position Line Selected V-Pattern Group Line Length (Number Pixels) V-Sequence PBLK Toggle Position V-Sequence PBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence CLPOB Toggle Position V-Sequence CLPOB Toggle Position V-Sequence
Table XXXIX. V-Sequence (VSEQ2) Register
Data Default Address Content Value Register Name [1:0] [7:4] [9:8] [11:10] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] HBLKMASK_2 CLPOBPOL CLPOBPOL_2 PBLKPOL PBLKPOL_2 VPATSEL VPATSEL_2 VMASK VMASK_2 HBLKALT_2 UNUSED VPATREPO_2 VPATREPE_2 VPATSTART_2 HDLEN_2 PBLKTOG1_2 PBLKTOG2_2 HBLKTOG1_2 HBLKTOG2_2 HBLKTOG3_2 HBLKTOG4_2 HBLKTOG5_2 HBLKTOG6_2 CLPOBTOG1_2 CLPOBTOG2_2
Description Masking Polarity during HBLK. [0]. [1]. CLPOB Start Polarity PBLK Start Polarity Selected V-Pattern Group V-Sequence Enable Masking V-Outputs (Specified FREEZE/RESUME Registers) Enable HBLK Alternation Unused Number Selected V-Pattern Group Repetitions Lines Number Selected V-Pattern Group Repetitions Even Lines Start Position Line Selected V-Pattern Group Line Length (Number Pixels) V-Sequence PBLK Toggle Position V-Sequence PBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence CLPOB Toggle Position V-Sequence CLPOB Toggle Position V-Sequence
-50-
REV.
AD9995
Table V-Sequence (VSEQ3) Register
Data Default Address Content Value Register Name [1:0] [7:4] [9:8] [11:10] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] HBLKMASK_3 CLPOBPOL CLPOBPOL_3 PBLKPOL PBLKPOL_3 VPATSEL VPATSEL_3 VMASK VMASK_3 HBLKALT_3 UNUSED VPATREPO_3 VPATREPE_3 VPATSTART_3 HDLEN_3 PBLKTOG1_3 PBLKTOG2_3 HBLKTOG1_3 HBLKTOG2_3 HBLKTOG3_3 HBLKTOG4_3 HBLKTOG5_3 HBLKTOG6_3 CLPOBTOG1_3 CLPOBTOG2_3
Description Masking Polarity during HBLK. [0]. [1]. CLPOB Start Polarity PBLK Start Polarity Selected V-Pattern Group V-Sequence Enable Masking V-Outputs (Specified FREEZE/RESUME Registers) Enable HBLK Alternation Unused Number Selected V-Pattern Group Repetitions Lines Number Selected V-Pattern Group Repetitions Even Lines Start Position Line Selected V-Pattern Group Line Length (Number Pixels) V-Sequence PBLK Toggle Position V-Sequence PBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence CLPOB Toggle Position V-Sequence CLPOB Toggle Position V-Sequence
Table XLI. V-Sequence (VSEQ4) Register
Data Default Address Content Value Register Name [1:0] [7:4] [9:8] [11:10] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] HBLKMASK_4 CLPOBPOL CLPOBPOL_4 PBLKPOL PBLKPOL_4 VPATSEL VPATSEL_4 VMASK VMASK_4 HBLKALT_4 UNUSED VPATREPO_4 VPATREPE_4 VPATSTART_4 HDLEN_4 PBLKTOG1_4 PBLKTOG2_4 HBLKTOG1_4 HBLKTOG2_4 HBLKTOG3_4 HBLKTOG4_4 HBLKTOG5_4 HBLKTOG6_4 CLPOBTOG1_4 CLPOBTOG2_4
Description Masking Polarity during HBLK. [0]. [1]. CLPOB Start Polarity PBLK Start Polarity Selected V-Pattern Group V-Sequence Enable Masking V-Outputs (Specified FREEZE/RESUME Registers) Enable HBLK Alternation Unused Number Selected V-Pattern Group Repetitions Lines Number Selected V-Pattern Group Repetitions Even Lines Start Position Line Selected V-Pattern Group Line Length (Number Pixels) V-Sequence PBLK Toggle Position V-Sequence PBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence CLPOB Toggle Position V-Sequence CLPOB Toggle Position V-Sequence
REV.
-51-
AD9995
Table XLII. V-Sequence (VSEQ5) Register
Data Default Address Content Value Register Name [1:0] [7:4] [9:8] [11:10] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] HBLKMASK_5 CLPOBPOL CLPOBPOL_5 PBLKPOL PBLKPOL_5 VPATSEL VPATSEL_5 VMASK VMASK_5 HBLKALT_5 UNUSED VPATREPO_5 VPATREPE_5 VPATSTART_5 HDLEN_5 PBLKTOG1_5 PBLKTOG2_5 HBLKTOG1_5 HBLKTOG2_5 HBLKTOG3_5 HBLKTOG4_5 HBLKTOG5_5 HBLKTOG6_5 CLPOBTOG1_5 CLPOBTOG2_5
Description Masking Polarity during HBLK. [0]. [1]. CLPOB Start Polarity PBLK Start Polarity Selected V-Pattern Group V-Sequence Enable Masking V-Outputs (Specified FREEZE/RESUME Registers) Enable HBLK Alternation Unused Number Selected V-Pattern Group Repetitions Lines Number Selected V-Pattern Group Repetitions Even Lines Start Position Line Selected V-Pattern Group Line Length (Number Pixels) V-Sequence PBLK Toggle Position V-Sequence PBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence CLPOB Toggle Position V-Sequence CLPOB Toggle Position V-Sequence
Table XLIII. V-Sequence (VSEQ6) Register
Data Default Address Content Value Register Name [1:0] [7:4] [9:8] [11:10] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] HBLKMASK_6 CLPOBPOL CLPOBPOL_6 PBLKPOL PBLKPOL_6 VPATSEL VPATSEL_6 VMASK VMASK_6 HBLKALT_6 UNUSED VPATREPO_6 VPATREPE_6 VPATSTART_6 HDLEN_6 PBLKTOG1_6 PBLKTOG2_6 HBLKTOG1_6 HBLKTOG2_6 HBLKTOG3_6 HBLKTOG4_6 HBLKTOG5_6 HBLKTOG6_6 CLPOBTOG1_6 CLPOBTOG2_6
Description Masking Polarity during HBLK. [0]. [1]. CLPOB StartPolarity PBLK Start Polarity Selected V-Pattern Group V-Sequence Enable Masking V-Outputs (Specified FREEZE/RESUME Registers) Enable HBLK Alternation Unused Number Selected V-Pattern Group Repetitions Lines Number Selected V-Pattern Group Repetitions Even Lines Start Position Line Selected V-Pattern Group Line Length (Number Pixels) V-Sequence PBLK Toggle Position V-Sequence PBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence CLPOB Toggle Position V-Sequence CLPOB Toggle Position V-Sequence
-52-
REV.
AD9995
Table XLIV. V-Sequence (VSEQ7) Register
Data Default Address Content Value Register Name [1:0] [7:4] [9:8] [11:10] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] HBLKMASK_7 CLPOBPOL CLPOBPOL_7 PBLKPOL PBLKPOL_7 VPATSEL VPATSEL_7 VMASK VMASK_7 HBLKALT_7 UNUSED VPATREPO_7 VPATREPE_7 VPATSTART_7 HDLEN_7 PBLKTOG1_7 PBLKTOG2_7 HBLKTOG1_7 HBLKTOG2_7 HBLKTOG3_7 HBLKTOG4_7 HBLKTOG5_7 HBLKTOG6_7 CLPOBTOG1_7 CLPOBTOG2_7
Description Masking Polarity during HBLK. [0]. [1]. CLPOB Start Polarity PBLK Start Polarity Selected V-Pattern Group V-Sequence Enable Masking V-Outputs (Specified FREEZE/RESUME Registers) Enable HBLK Alternation Unused Number Selected V-Pattern Group Repetitions Lines Number Selected V-Pattern Group Repetitions Even Lines Start Position Line Selected V-Pattern Group Line Length (Number Pixels) V-Sequence PBLK Toggle Position V-Sequence PBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence CLPOB Toggle Position V-Sequence CLPOB Toggle Position V-Sequence
Table XLV. V-Sequence (VSEQ8) Register
Data Default Address Content Value Register Name [1:0] [7:4] [9:8] [11:10] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] HBLKMASK_8 CLPOBPOL CLPOBPOL_8 PBLKPOL PBLKPOL_8 VPATSEL VPATSEL_8 VMASK VMASK_8 HBLKALT_8 UNUSED VPATREPO_8 VPATREPE_8 VPATSTART_8 HDLEN_8 PBLKTOG1_8 PBLKTOG2_8 HBLKTOG1_8 HBLKTOG2_8 HBLKTOG3_8 HBLKTOG4_8 HBLKTOG5_8 HBLKTOG6_8 CLPOBTOG1_8 CLPOBTOG2_8
Description Masking Polarity during HBLK. [0]. [1]. CLPOB Start Polarity PBLK Start Polarity Selected V-Pattern Group V-Sequence Enable Masking V-Outputs (Specified FREEZE/RESUME Registers) Enable HBLK Alternation Unused Number Selected V-Pattern Group Repetitions Lines Number Selected V-Pattern Group Repetitions Even Lines Start Position Line Selected V-Pattern Group Line Length (Number Pixels) V-Sequence PBLK Toggle Position V-Sequence PBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence CLPOB Toggle Position V-Sequence CLPOB Toggle Position V-Sequence
REV.
-53-
AD9995
Table XLVI. V-Sequence (VSEQ9) Register
Data Default Address Content Value Register Name [1:0] [7:4] [9:8] [11:10] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] HBLKMASK_9 CLPOBPOL CLPOBPOL_9 PBLKPOL PBLKPOL_9 VPATSEL VPATSEL_9 VMASK VMASK_9 HBLKALT_9 UNUSED VPATREPO_9 VPATREPE_9 VPATSTART_9 HDLEN_9 PBLKTOG1_9 PBLKTOG2_9 HBLKTOG1_9 HBLKTOG2_9 HBLKTOG3_9 HBLKTOG4_9 HBLKTOG5_9 HBLKTOG6_9 CLPOBTOG1_9 CLPOBTOG2_9
Description Masking Polarity during HBLK. [0]. [1]. CLPOB Start Polarity PBLK Start Polarity Selected V-Pattern Group V-Sequence Enable Masking V-Outputs (Specified FREEZE/RESUME Registers) Enable HBLK Alternation Unused Number Selected V-Pattern Group Repetitions Lines Number Selected V-Pattern Group Repetitions Even Lines Start Position Line Selected V-Pattern Group Line Length (Number Pixels) V-Sequence PBLK Toggle Position V-Sequence PBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence HBLK Toggle Position V-Sequence CLPOB Toggle Position V-Sequence CLPOB Toggle Position V-Sequence
Table XLVII. Field Register
Data Default Address Content Value Register Name [3:0] [9:6] [10] [11] [15:12] [16] [17] [21:18] [22] [23] [3:0] [9:6] [10] [11] [15:12] [16] [17] [23:18] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] VSEQSEL0_0 SWEEP0_0 MULTI0_0 VSEQSEL1_0 SWEEP1_0 MULTI1_0 VSEQSEL2_0 SWEEP2_0 MULTI2_0 VSEQSEL3_0 SWEEP3_0 MULTI3_0 VSEQSEL4_0 SWEEP4_0 MULTI4_0 VSEQSEL5_0 SWEEP5_0 MULTI5_0 VSEQSEL6_0 SWEEP6_0 MULTI6_0 UNUSED SCP1_0 SCP2_0 SCP3_0 SCP4_0 VDLEN_0 HDLAST_0
Description Selected V-Sequence Region Select Sweep Region Region Sweep, Sweep. Select Multiplier Region Region Multiplier, Multiplier. Selected V-Sequence Region Select Sweep Region Region Sweep, Sweep. Select Multiplier Region Region Multiplier, Multiplier. Selected V-Sequence Region Select Sweep Region Region Sweep, Sweep. Select Multiplier Region Region Multiplier, Multiplier. Selected V-Sequence Region Select Sweep Region Region Sweep, Sweep. Select Multiplier Region Region Multiplier, Multiplier. Selected V-Sequence Region Select Sweep Region Region Sweep, Sweep. Select Multiplier Region Region Multiplier, Multiplier. Selected
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