mAgic Audio, Communication Beam-forming Applications High Perform

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

mAgic Audio, Communication Beam-forming Applications High Perform

Datasheet Thumbnail

Top Searches for this datasheet

Dual Core System Integrating ARM7TDMI Thumb Processor Core
mAgic Audio, Communication Beam-forming Applications
High Performance Operating
GFLOPS Gops Arithmetic Operations Cycle Multiply, Add/subtract, Add, Subtract Floating Fixed Point) Allowing Single Cycle Butterfly Native Support Complex Arithmetic Vectorial SIMD Operations: Complex Multiply with Dual Add/sub Clock Cycle Real Multiply Add/sub Simple Scalar Operations 32-bit Integer IEEE 40-bit Extended Precision Floating Point Numeric Format Large Multi-port Data Register File: Registers Organized 4-input 4output 256-register Banks Orthogonal VLIW Architecture, Code Compression Code Size Reduction Flexible Addressing Capability: Independent Address Generation Units Operating Registers Address Register File Supporting Programmable Stride, Circular Pointers Reversal Mbits On-chip SRAM: 40-bit Data Memory Locations 128-bit Program Memory Location, Equivalent Instructions Access External Program Data Memory Main Operating Modes: System Mode Efficient Optimizing Assembler: Allows Easy Exploitation Available Hardware Resources Parallelism Utilizes ARM7TDMI Processor Core with Byte Integrated SRAM, Operating Fully-programmable External Interface (EBI) Maximum External Address Space Bytes Chip Selects Software-programmable 8/16-bit External Data 8-channel Peripheral Data Controller (PDC) 8-level Priority, Individually Maskable Vectored Interrupt Controller External, Internal Interrupt Sources, Including High-priority, Low-latency Interrupt Request Programmable Lines 8-channel 11-bit Programmable Clock Prescaler Feeding Timer, Watchdog, USARTs, SPIs 3-channel 16-bit Timer/Counter Internal Clock Sources Configurable Sources (External Source Cascaded Timer Configuration) Multi-purpose Output Pins plus Output Dedicated ADDA Interface plus Outputs Dedicated mAgic USARTs Dedicated Peripheral Data Controller (PDC) Channels USART USART Supporting Full Modem Interface Master/Slave Interfaces Dedicated Peripheral Data Controller (PDC) Channels 16-bit Programmable Data Length External Slave Chip Selects each Programmable Watchdog Timer ADDA (A/D Converters) Interface Supporting Analog Digital Digital Analog, Stereo 24-bit Converters IEEE 1149.1 JTAG Boundary Scan Active Pins Efficient Interface Based 40-bit Dual Ported Shared Memory, Memory Mapped Register Access, Interrupt Lines Core Operating Voltage, Operating Voltage On-chip Operation from Reference Clock 352-ball PBGA Package
DIOPSIS Dual Core AT572D740 Summary
7001AS-DSP-03/04
Note: This summary document. complete document available this time. more information, please contact your local Atmel sales office.
Description
DIOPSIS Dual Processor integrating mAgic ARM7TDMIRISC MCU, plus total Kbytes SRAM. system combines flexibility ARM7TDMI RISC controller with very high performance DSP. mAgic high performance VLIW delivering Giga floating-point operations second (GFLOPS) clock rate MHz. data registers, address registers, independent operating units independent address generation units. instance, activating computing units, produce complete butterfly cycle. mAgic operates 32-bit fixed-point IEEE 40-bit extended precision floating-point numeric format. also on-chip 40-bit data memory locations 128-bit program memory locations. Efficient usage internal program memory achieved through code compression mechanism. optimizing assembler frees user from burden dealing with parallelism processor resources drastically simplifies code development. ARM7TDMIembedded micro controller core member Advanced RISC Machines (ARM®) family general purpose 32-bit microprocessors, which offer high performance very power consumption. architecture based Reduced Instruction Computer (RISC) principles, instruction related decode mechanism much simpler than those micro programmed Complex Instruction Computers. This simplicity results high instruction throughput impressive real-time interrupt response. ARM7TDMIsupports 16-bit Thumb® subset most commonly used 32-bit instructions. These expanded time with degradation system performance. This gives 16-bit code density (saving memory area cost) coupled with 32-bit processor performance. rich peripheral Kbytes internal memory provide highly flexible integrated system solution.
AT572D740
7001AS-DPS-03/04
AT572D740
Configuration
Table D740 Ball Assignment (243 I/O)
Name ADDA_BRCK ADDA0_IN ADDA1_IN ADDA2_IN ADDA3_IN ADDA0_OUT ADDA1_OUT ADDA2_OUT ADDA3_OUT ADDA_TOPLL ADDA_WCK ARM_A[0] ARM_A[1] ARM_A[2] ARM_A[3] ARM_A[4] ARM_A[5] ARM_A[6] ARM_A[7] ARM_A[8] ARM_A[9] ARM_A[10] ARM_A[11] ARM_A[12] ARM_A[13] ARM_A[14] ARM_A[15] ARM_A[16] ARM_A[17] ARM_A[18] ARM_D[0] ARM_D[1] ARM_D[2] ARM_D[3] Ball Name ARM_D[6] ARM_D[7] ARM_D[8] ARM_D[9] ARM_D[10] ARM_D[11] ARM_D[12] ARM_D[13] ARM_D[14] ARM_D[15] ARM_NCS0 ARM_NCS1 ARM_NCS2 ARM_NCS3 ARM_NRD ARM_NWEB0 ARM_NWEB1 BIST_RES (dnc) BIST_RUN (dnc) FPU_EXC FPU_HALT FPU_MODE ICE_NTRST ICE_TCK ICE_TDI ICE_TDO ICE_TMS JCFG PIO[0] PIO[1] PIO[2] PIO[3] PIO[4] Notes: PIO[5] Ball AA26 AA24 AA25 AB26 AB24 AD15 AD13 AE15 AB23 AB25 AC26 AC24 AC25 AD26 Name PIO[8] PIO[9] PIO[10] PIO[11] PIO[12] PIO[13] PIO[14] PIO[15] PIO[16] PIO[17] PIO[18] PIO[19] PIO[20] PIO[21] PIO[22] PIO[23] PIO[24] PIO[25] PIO[26] PIO[27] PLL_CLKIN PLL_CLKOUT PLL_DIV (dnc) PLL_DN (dnc) PLL_EN PLL_LFT PLL_LOCK PLL_TST (dnc) PLL_UP (dnc) RESET SCAN_EN (dnc) SCAN_TEST (dnc) SINGLE SPI0_MISO Ball AD23 AE24 AD22 AC22 AE23 AD21 AF22 AE22 AD20 AF21 AC20 AE21 AD19 AF20 AC19 AE20 AD18 AE19 AF18 AD17 AD14 AE16 Name SPI0_NSS[1] SPI0_NSS[2] SPI0_NSS[3] SPI0_SCK SPI1_MISO SPI1_MOSI SPI1_NSS SPI1_NSS SPI1_NSS SPI1_NSS SPI1_SCK TEST_CLK (dnc) USART0_RXD USART0_SCK USART0_TXD USART1_CTS USART1_DCD USART1_DSR USART1_DTR USART1_RI USART1_RTS USART1_RXD USART1_SCK USART1_TXD XM_A[0] XM_A[1] XM_A[2] XM_A[3] XM_A[4] XM_A[5] XM_A[6] XM_A[7] XM_A[8] XM_A[9] Ball AE17 AF17 AE18 AD12 AE14 AC14 AF14 AF15 AF16 AC15 AD16 AC17 AC12 AE13 AD11 AD10 AE11 AC10 AE10
7001AS-DPS-03/04
Table D740 Ball Assignment (243 I/O) (Continued)
Name ARM_D[4] ARM_D[5] XM_A[12] XM_A[13] XM_A[14] XM_A[15] XM_A[16] XM_A[17] XM_A[18] XM_A[19] XM_A[20] XM_A[21] XM_A[22] XM_A[23] XM_D[1] XM_D[2] XM_D[3] XM_D[4] XM_D[5] XM_D[6] XM_D[7] XM_D[8] XM_D[9] XM_D[10] XM_D[11] XM_D[12] XM_D[13] Ball Name PIO[6] PIO[7] XM_D[14] XM_D[15] XM_D[16] XM_D[17] XM_D[18] XM_D[19] XM_D[20] XM_D[21] XM_D[22] XM_D[23] XM_D[24] XM_D[25] XM_D[26] XM_D[27] XM_D[28] XM_D[29] XM_D[30] XM_D[31] XM_D[32] XM_D[33] XM_D[34] XM_D[35] XM_D[36] XM_D[37] XM_D[38] Note: Ball AD25 AE26 Name SPI0_MOSI SPI0_NSS XM_D[39] XM_D[40] XM_D[41] XM_D[42] XM_D[43] XM_D[44] XM_D[45] XM_D[46] XM_D[47] XM_D[48] XM_D[49] XM_D[50] XM_D[51] XM_D[52] XM_D[53] XM_D[54] XM_D[55] XM_D[56] XM_D[57] XM_D[58] XM_D[59] XM_D[60] XM_D[61] XM_D[62] XM_D[63] Ball Name XM_A[10] XM_A[11] XM_CLKOUT[0] XM_CLKOUT[1] XM_CLKOUT[2] XM_D[0] XM_D[64] XM_D[65] XM_D[66] XM_D[67] XM_D[68] XM_D[69] XM_D[70] XM_D[71] XM_D[72] XM_D[73] XM_D[74] XM_D[75] XM_D[76] XM_D[77] XM_D[78] XM_D[79] XM_GNT XM_NCS XM_NWE XM_REQ Ball
connect pins. These pins reserved test only described Table
Table D740 Ball Assignment (VDD 3.3V)
AC16 AA23 AC21 AC11
AT572D740
7001AS-DPS-03/04
AT572D740
Table D740 Ball Assignment (VDDI 1.8V)
AF11 AF19 AF23
Table D740 Ball Assignment (VDDPLL 1.8V)
Table D740 Ball Assignment (GND)
AC13 AF26 AE25 AC18 AF25 AD24 AC23
balls comprised Tables "not connected".
name conventions
names built using following structure: (functional block name) (activity level) (line name) (bus index) where: functional block name name functional block which belongs activity level active lines; blank high active lines line name name function line index number corresponding index when line element
7001AS-DPS-03/04
Description
Table D740 Description
Module ADDA ADDA ADDA ADDA ADDA ADDA ADDA ADDA ADDA ADDA ADDA mAgic Name ADDA_BRCK ADDA0_IN ADDA1_IN ADDA2_IN ADDA3_IN ADDA0_OUT ADDA1_OUT ADDA2_ ADDA3_ ADDA_TOPLL ADDA_WCK ARM_A[18:0] ARM_D[15:0] ARM_NCS0 ARM_NCS1 ARM_NCS2 ARM_NCS3 ARM_NRD ARM_NWEB0 ARM_NWEB1 FPU_HALT Function ADDA rate clock ADDA input channel ADDA input channel ADDA input channel ADDA input channel ADDA output channel ADDA output channel ADDA output channel ADDA output channel ADDA clock generator Strobe ADDA Word clock external memory address external memory data external memory Chip select command external memory Chip select command external memory Chip select command external memory Chip select command external Memory Read enable external memory Byte Write enable external memory High Byte Write enable Fast from mAgic "halt" Type out-02 out-02 out-03 out-02 bi-02 out-02 out-02 out-02 out-02 bi-02 bi-03 bi-03 out-02 high data byte d[7:0] data byte d[15:8] used monitoring (internal Pull-Down) Active Level Notes digital serial audio stream rate clock sampling) Left right digital serial stereo audio stream Left right digital serial audio stream Left right digital serial audio stream Left right digital serial audio stream Left right digital serial stereo audio stream Left right digital serial audio stream Left right digital serial audio stream Left right digital serial audio stream Sampling toward external ADCs/DACs synchronism generation Sampling clock toward ADCs/DACs
AT572D740
7001AS-DPS-03/04
AT572D740
Table D740 Description (Continued)
Module mAgic mAgic Name FPU_EXC FPU_MODE Function IRQ15 from mAgic "exception" IRQ25 from mAgic "mode" Type out-02 out-02 Active Level high Notes used monitoring used monitoring mAgic system mode mAgic mode (internal Pull-Up)
JTAG JTAG JTAG JTAG JTAG D740 D740 mAgic
ICE_NTRST ICE_TCK ICE_TDI ICE_TDO ICE_TMS JCFG PIO[27:0] PLL_CLKIN PLL_CLKOUT PLL_EN PLL_LFT PLL_LOCK RESET SINGLE
JTAG Test reset JTAG Test clock JTAG Test data input JTAG Test data output JTAG Test mode JTAG D740 Boundary Scan selection Parallel Input/Output Reference clock Clock output enable (PLL_CLKIN multiply) lowpass filter input lock condition System reset Single user mAgic external memory
out-02 bi-02 out-02 out-02
(internal Pull-Up)
(internal Pull-Up) D740 Boundary Scan JTAG general purpose programmable I/Os peripheral I/Os 25MHz (max) PLL_EN 100MHz (max) PLL_EN 100MHz (max) PLL_EN fixed PLL_EN
high
system clock PLL_CLKIN system clock PLL_CLKIN
high high
used monitoring asynchronous (internal Pull-Up) default user shared Single user shared default user shared data input data output data output data input Input Output n.a. Outputs clock input clock output data input data output
SPI0_MOSI SPI0_MISO SPI0_NSS SPI0_NSS[3:1] SPI0_SCK SPI1_MOSI
Master Out/Slave data Master In/Slave data Input/Output Chip select Output Chip Selects Serial clock Master Out/Slave data
bi-02 bi-02 bi-02 out-02 bi-03 bi-02
7001AS-DPS-03/04
Table D740 Description (Continued)
Module USART USART USART USART USART USART USART USART USART USART USART USART mAgic mAgic mAgic mAgic mAgic mAgic mAgic Power Power Power Ground Name SPI1_MISO SPI1_NSS SPI1_NSS[3:1] SPI1_SCK USART0_RXD USART0_SCK USART0_TXD USART1_CTS USART1_DCD USART1_DSR USART1_DTR USART1_RI USART1_RTS USART1_RXD USART1_SCK USART1_TXD XM_A[23:0] XM_CLKOUT[ 2:0] XM_D[39:0] XM_D[79:40] XM_GNT XM_NCS XM_NWE VDDI VDDPLL Function Master In/Slave data Input/Output Chip select Output Chip Selects Serial clock USART Data USART Serial clock USART Data USART Clear send USART Data carriage detect USART Data ready USART Data terminal ready USART Ring indicator USART Request send USART Data USART Serial clock USART Data mAgic external Memory address mAgic external Memory clocks mAgic external Memory data mAgic external Memory data mAgic shared external memory grant mAgic external Memory Chip select mAgic external Memory Write enable power supply Core power supply power supply D740 ground reference Type bi-02 bi-02 out-02 bi-03 bi-03 bi-02 out-02 out-02 bi-03 bi-02 out-03 out-03 bi-03 bi-03 out-02 out-03 out-03 Power Power Power Ground high nominal Supply nominal Supply nominal Supply common Supplies 100MHz (max) line three mAgic chip. Right bank (internal Pull-Down) Left bank (internal Pull-Down) (internal Pull-Down) synchronous mode only used output Active Level Notes data output data input Input Output n.a. Outputs clock input clock output (internal Pull-Down) synchronous mode only used output
AT572D740
7001AS-DPS-03/04
AT572D740
Block Diagram
Figure D740 Architecture
Memory
Arm7TDMI
Bridge
SPI0
Amba MAAR Shared Memory Data Demux
SPI1 USART0 USART1
Program Demux
TIMER Watchdog
8Kx128 Program Memory
mAgic core
Data Memory (6k+6k) Double Bank Double Port
ADDA
Data Buffer word Double Bank Double Port Data Program
Clock Ctrl
Mode data paths System Mode data paths exclusive data paths
7001AS-DPS-03/04
Architectural Overview
DIOPSIS (also named D740) high performance dual-core processing platform audio, communication beam-forming applications, integrating floating-point (mAgic DSP) ARM7TDMIReduced Instruction Computer (RISC). D740 optimally suited floating point applications with significant need complex domain computations like frequency domain phase-shift algorithms, requiring high dynamic range maximum numerical precision. D740 combines flexibility ARM7 RISC controller with very high performance oriented VLIW architecture mAgic.
System management
availability standard RISC on-chip lowers software development effort critical control segments application. ARM7TDMI supports usage light RTOS efficient interrupt management, leaving mAgic fully available numerically intensive part application. synchronization between processors either based software polling semaphores interrupts. D740 master processor. bootstrap sequence D740 starts from bootstrap from external non-volatile memory. then boots mAgic from non-volatile memory. After bootstrap D740 start normal operations. side many applications implemented D740 using only internal memory. fact program memory size 128-bit coupled with availability code compression, gives equivalent on-chip program memory size about instructions (typical). standard In-Circuit Emulation debug interface supported port.
mAgic Processor
mAgic VLIW numeric processor D740. operates IEEE 40-bit extended precision floating-point 32-bit integer numeric format. main components subsystem core processor, on-chip memories interfaces from subsystem. operators block, register file, address generation unit program decoding sequencing unit compose core processor. short description each block given following paragraphs. mAgic VLIW engine, from user point view, works like RISC machine implementing triadic computing operations data coming from register file, data move operations between local memories register file. operators pipelined maximum performance. pipeline depth depends operator used. operations scheduling parallelism automatically defined managed compile time assembler-optimizer, allowing efficient code execution. order give best support RISC-like programming model, mAgic equipped with complex 256-entry register file. used complex register file (real imaginary part), dual register file vectorial operations. When performing single instructions register file used ordinary register file. Both left right side register file 8-ported, making total port available data move from operator block memory. total data bandwidth between register file operator block bytes clock cycle, avoiding bottlenecks data flow between units.
Core processor
AT572D740
7001AS-DPS-03/04
AT572D740
Figure mAgic Block Diagram
mAgic VLIW Program Memory Local Controller VLIW Decoder
Instruction Decoder Condition Generation Status Register Program Counter
PARM Memory Left 512x40
PARM Memory Right 512x40
Data Register File
Multiple Address Generation Unit Address Register File
Data Memory Left 6Kx40
Data Memory Right 6Kx40
Operator Block Controller Buffer Data Memory Left 2Kx40 Buffer Data Memory Right 2Kx40
External Memory
operators block, register file, address generation unit programsequencing unit compose core processor. Operators Block contains hardware that performs arithmetical operations. works 32-bit integers IEEE extended precision 40-bit floating-point data. Operators Block composed four integer/floating point multipliers, adder, subtractor add-subtract integer/floating point units; moreover, shift/logic units, Min/Max operator seed generators efficient division inverse square root computation. operators block arranged order natively support complex arithmetic (single cycle complex multiply multiply add), fast (single cycle butterfly computation) vectorial computations. peak performance mAgic achieved during single cycle butterfly execution, when mAgic delivers floating-point operations clock cycle. mAgic equipped with independent address generation units. able generate pairs addresses, access left right memory reading access left right memory writing. also used loop control test loop reached. Multiple Address Generation Unit (MAGU) supports linear addressing with stride, circular addressing reversed addressing. address generation unit registers. Program Address Generation Unit devoted control correct Program Counter generation according program flow. generates addresses linear code execution well non-sequential program flow. Condition Generation Unit combines flags generated operators produce complex conditions flags used control program execution. Predicated instruction execution supported different groups instructions: arithmetical instructions, memory write, immediate load, them. Program Address Generation Unit also allows perform conditioned unconditioned branch instructions, loops, call subroutines return from subroutines.
7001AS-DPS-03/04
Internal memories, External memories
mAgic four on-chip memory blocks: Program Memory, Data Memory, Data Buffer, dual ported memory shared with processor. External Memory Interface multiplexes Data accesses Program accesses from External Memory. Program Memory stores VLIW program executed mAgic. words 128-bit single port memory. When mAgic System Mode modify content mAgic Program Memory different ways. directly write Program Memory location accessing memory address space assigned mAgic Program Memory memory map. this access mode writes four 32-bit words four consecutive addresses correct address boundaries, order properly complete single VLIW word write cycle. also modify content mAgic Program Memory initiating transfer from External Memory mAgic Program Memory. this access mode single VLIW word transferred from mAgic External Memory mAgic Program Memory 64bit cycle, that complete word every clock cycles. program compression scheme used, which allows average program compression between code accessing capability mAgic from External Memory greater than instruction clock cycle. When mAgic Mode, cannot access mAgic Program Memory. When Mode mAgic initiate transfer from External Memory mAgic Program Memory load code segment. mAgic internal Data Memory made three memory pages, words 40-bit left data memory words 40-bit right data memory, giving total words left right memory banks total words Each Data Memory bank dual port memory that allows four simultaneous accesses, read write. core access vectorial single data stored Data Memory. Accessing complex data equivalent accessing vectorial data. During simultaneous read write memory accesses, MAGU generates independent read write addresses common both left right memory banks. total available bandwidth between Register File Data Memory bytes clock cycle, allowing full speed implementation numerically intensive algorithms (e.g. complex FIR). Buffer Memory words 40-bit both left right memory. Buffer Memory dual port memory. port connected core processor. MAGU generates Buffer Memory addresses transferring data from core. second port Buffer Memory connected External Memory Interface. Buffer Memory does support dual read write accesses neither from core from External Memory Interface. available bandwidth between core processor Buffer Memory equal available bandwidth between External Memory Interface Buffer Memory: bytes clock cycle. maximum External Memory size mAgic Mword Left Right (equivalent Mword Mbytes; 24-bit address bus). controller manages data transfer between External Memory Buffer Memory. controller generate accesses with stride External Memory. transfers from Buffer Memory executed parallel with full speed core instructions execution with zero-overhead without intervention core processor, except initiating last memory block address space mAgic memory shared (PARM) between mAgic processor. dual port memory words both left right bank (total 40-bit). This memory used efficiently transfer data between processors. available bandwidth between core processor shared memory bytes clock cycle.
AT572D740
7001AS-DPS-03/04
AT572D740
side available bandwidth limited size processor bits) giving bandwidth bytes clock cycle. interface (mAAr) D740 master ARM7 RISC processor. mAgic behaves standard AMBA slave device, allowing access different resources depending operating mode (Run System). System Mode, mAgic halts execution takes control When mAgic System mode access many mAgic internal devices. ability access internal mAgic resources System Mode used initialization debugging purposes. accessing Command Register, change operating status (Run/System Mode), initiate transactions, force single multiple step execution, simply read operating status. Mode, mAgic works under direct control VLIW program access only 40-bit dual ported shared memory (PARM) mAgic Command Register. order allow tight coupling between operations mAgic time, they exchange synchronization signals, based interrupts.
System: ARM7TDMI ARM7TDMI 32-bit RISC microprocessor; member Advanced RISC Machines (ARM) family general-purpose 32-bit microprocessors, offering high perforProcessor mance very power consumption. Peripherals
architecture based Reduced Instruction Computer (RISC) principles, instruction related decode mechanism much simpler than those microprogrammed Complex Instruction Computers. This simplicity results high instruction throughput real-time interrupt response. Pipelining employed that parts processing memory systems operate continuously. typical operating scheme ARM7TDMI sequence fetch-decode-execute. ARM7TDMI processor employs architectural strategy known THUMB. THUMB instructions operate with standard register configuration, allowing excellent interoperability between THUMB states. Each 16-bit THUMB instruction corresponding 32-bit instruction with same effect processor model. 16-bit instructions expanded time with degradation system performance. This provides better performance than 16-bit architecture, with better code density than 32-bit architecture. ARM7TDMI processor built around bank 32-bit registers status registers. ARM7TDMI supports seven operation modes: User (usr): normal program execution state (fiq): Fast Interrupt reQuest; connected mAgic Halt signal (irq): Used general-purpose interrupt handling Supervisor (svc): Protected mode operating system Abort mode (abt): Entered after data instruction prefetch abort System (sys): privileged user mode operating system Undefined (und):Entered when undefined instruction executed Mode changes made under software control brought about external interrupts exception processing. Most application programs execute User mode. non-user modes known privileged modes entered order service interrupts exceptions, access protected resources. Each operating mode dedicated banked registers fast exception handling. mode five addi-
7001AS-DPS-03/04
tional banked working registers, r8_fiq r12_fiq, enhance interrupt processing speed. ARM7TDMI processor operates little-endian mode. speed-up critical routine execution critical data segment access, ARM7 equipped with Kbyte zero wait states on-chip memory. system buses. main (ARM System Bus). (ARM Peripheral Bus) designed accesses on-chip peripherals. AMBA Bridge provides interface between APB. D740 equipped with peripherals controlled ARM. on-chip Peripheral Data Controller (PDC) transfers data between on-chip USARTs/SPI off-chip memories without intervention processor. Most importantly, removes processor interrupt handling overhead significantly reduces number clock cycles required data transfer. Each peripheral 16K-byte address space allocated upper bytes 4Gbyte address space. peripheral register composed control, mode, data, status, interrupt registers. maximize efficiency manipulation, frequently written registers mapped into three memory locations. short description available peripherals given following. (External Interface): generates signals that control access External Memory peripheral devices. ADDA (Analog Digital Digital Analog interface): ADDA provides channel serial interface toward stereo audio 24-bit DAC. (Peripheral Data Controller): provides communication channels dedicated USARTs SPIs. channel connected receiving channel transmitting channel each peripheral. USART (Universal Synchronous Asynchronous Receiver Transmitter): two, fullduplex, universal synchronous/asynchronous receiver/transmitters provide simple standard communication managed Peripheral Data Controller. (Serial Peripheral Interface): four-wire serial interfaces provide simple industry-standard communication managed Peripheral Data Controller. (Advanced Interrupt Controller): 8-level priority, individuallymaskable, vectored interrupt controller. interrupt controller connected NFIQ (fast interrupt request) NIRQ (standard interrupt request) inputs ARM7TDMI processor. (Parallel Controller): features programmable lines, lines available D740 pads, while remaining only internal. (Timer Counter): contains three identical 16-bit timer/counter channels. (Watchdog Timer): used guard against system lock-up software becomes trapped deadlock. overflow occurs, watchdog timer generates processor interrupts Advanced Interrupt Controller (AIC) external pulse through PIO. CLKGEN (Clock Generator): clock generator provides divided clocks several peripherals: Timer Counter, Watchdog, USARTs SPIs.
AT572D740
7001AS-DPS-03/04
AT572D740
Figure Armsystem Architecture
7001AS-DPS-03/04
Development Tools
D740 supported with complete software hardware development tools. MADE D740 supported development tools integrated into visual development environment called MADE (Multicore Application Development Environment). MADE provides user with integrated environment producing applications both D740 cores, ARM7TDMI mAgic DSP, means common project management support MARMOS Minimal Bios. Code generation tools include Code Development Chain ARM7 (C-C++ compiler, assembler, linker utilities) Code Development Chain (C-C++ compiler, assembler, linker utilities). Code generation tools mAgic include compiler (GNU based, ANSI compliant), VLIW assembler-optimizer, code compressor, linker utilities. MADE supports MARMOS Minimal Bios, helper functions ARMmAgic intercommunication D740 peripherals management. MARMOS gives user basic APIs building integrated ARM-mAgic application. MADE provides user with simulation engine emulation kernel: CycleAccurate simulator D740 emulator board support. JTAG-ICE Standard In-Circuit-Emulation debug interface supported JTAG-ICE port D740. When configuration selected, usual debug capabilities System supported, while support mAgic core limited memory status registers inspection. jtag pins shared between ARM7TDMI functionality DIOPSIS chip Boundary Scan Logic. "JCFG" acts jtag D740 selector. When "JCFG" high selected, while DIOPSIS selected when "JCFG" low. JTST
JTST cost general-purpose module that provides appropriate resources order test DIOPSIS 740. JTST provides following resources DIOPSIS 740:
mAgic SSRAM, FLASH SRAM Stereo Audio CODECs Full Mbps) RS232/LVTTL a/synchronous serial lines serial lines Reset Logic (Power Push Button, WDG) connectors (USART, SPI, USB, PIO, AUDIO) PLL-Clock Logic oscillator connector) SWITCH Status 7-segment Display Voltage Regulators 5V/3.3V 5V/1.8V M-ICE JTAG
AT572D740
7001AS-DPS-03/04
AT572D740
Mechanical Drawing
7001AS-DPS-03/04
Table D740 Dimensions (mm)
Symbol D1/E1 34.8 2.12 0.44 0.50 0.60 0.60 0.75 0.30 0.25 0.35 0.30 0.15 2.33 0.52 1.27 35.0 30.0 11.0 1.62 35.2 30.7 2.56 0.60 0.70 0.90
AT572D740
7001AS-DPS-03/04
AT572D740
Power Dissipation
D740 three kinds power supply pins: VDDCORE pins, which power chip core (1.8V) VDDIO pins, which power lines (3.3V) VDDPLL pins, which power oscillator cells (1.8V)
total power dissipation basic contributions: PCORE represents contribute pads current output load current. PCORE represents contribute internal activity current. following table defines current consumption different conditions: Table Power Dissipation
Parameters typical conditions (3.3V) peak high mode CORE (1.8V) worst conditions (3.3V) CORE (1.8V)
peak mAgic FFT; both mAgic written 100% with continuous toggling data high mAgic FFT; both mAgic read written alternatively 100% with toggling data mAgic FFT; FLASH access 100%; mAgic access mode mAgic system mode; FLASH accesses 100%; D740 under reset typical condition typical process; 25°; worst condition worst process; 100°;
estimate power consumption specific application following equation where amount time your program spends that state each "Idd" contribute corresponds "IO" "CORE" columns: PCORE ((%peak peak) (%high high) (%no ext) (%sys mode mode) (%rst rst)) ((%peak peak) (%high mode) (%rst rst))
Note:
high)
(%no ext) (%sys mode
peak represents worst-case processor operation (for particularly) considerable also hard applications where data bits toggle every cycle.
7001AS-DPS-03/04
Reliability Data
following table summarizes some basic data that used reliability calculations. Table Silicon Block Size
Parameters Logic Gates Memories Register File total Device Size (pad excluded) Data Unit Kgates transistors transistors Data 10.5 Unit
AT572D740
7001AS-DPS-03/04
AT572D740
Ordering Guide
Table Ordering Information
Part Number AT572D740 Temperature Range 70°C Working Frequency Operating Supplies 3.3V (I/O) 1.8V (core) Package 352PBGA
7001AS-DPS-03/04
Atmel Corporation
2325 Orchard Parkway Jose, 95131, Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway Jose, 95131, Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
RF/Automotive
Theresienstrasse Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, 80906, Tel: 1(719) 576-3300 Fax: 1(719) 540-1759
Regional Headquarters
Europe
Atmel Sarl Route Arsenaux Case Postale CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500
Microcontrollers
2325 Orchard Parkway Jose, 95131, Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 Chantrerie 70602 44306 Nantes Cedex France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60
Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
Avenue Rochepleine 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80
Asia
Room 1219 Chinachem Golden Plaza Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, 80906, Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743
Japan
Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Literature Requests
www.atmel.com/literature
Disclaimer: Atmel Corporation makes warranty products, other than those expressly contained Company's standard warranty which detailed Atmel's Terms Conditions located Company's site. Company assumes responsibility errors which appear this document, reserves right change devices specifications detailed herein time without notice, does make commitment update information contained herein. licenses patents other intellectual property Atmel granted Company connection with sale Atmel products, expressly implication. Atmel's products authorized critical components life support devices systems.
Atmel Corporation 2003. rights reserved. Atmel combinations thereof, ccc® registered trademarks, trademarks Atmel Corporation subsidiaries. registered trademarks, trademarks xxxx Company. Other terms product names trademarks others.
Printed recycled paper.
7001AS-DPS-03/04

mAgic Audio, Communication Beam-forming Applications High Perform

Top Searches for this datasheet

Other recent searches