EDAC Parity Generator Checker Memory Interface Chip Select Generator W

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EDAC Parity Generator Checker Memory Interface Chip Select Generator W

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Integer Unit Based SPARC High-performance RISC Architecture Optimized Integrated 32/64-bit Floating-point Unit On-chip Peripherals
EDAC Parity Generator Checker Memory Interface Chip Select Generator Waitstate Generation Memory Protection Arbiter Timers General Purpose Timer (GPT) Real-time Clock Timer (RTCT) Watchdog Timer (WDT) Interrupt Controller with External Inputs General Purpose Interface (GPI) Dual UART Speed Optimized Code Interface 40-bit boot-PROM (Flash) Interface IEEE 1149.1 Test Access Port (TAP) Debugging Test Purposes Fully Static Design Performance: MIPs/5 MFlops (Double Precision) SYSCLK Core Consumption: 1.0W Typ. MIPs/0.7W typ. MIPs Operating Range: 4.5V 5.5V(1) -55°C +125°C Tested Total Dose KRADs (Si) according Method 1019 Event Rate Better than Error/Component/Day (Worst Case) Single Event Latch-up below Threshold MeV/mg/cm Quality Grades: ESCC with 9512/003 QML-Q with 5962-00540 Package: MQFPF; Bare 3.3V capability TSC695FL datasheet Atmel site.
Rad-Hard 32-bit SPARC Embedded Processor TSC695F
Note:
Description
TSC695F (ERC32 Single-Chip) highly integrated, high-performance 32-bit RISC embedded processor implementing SPARC architecture specification. been developed with support (European Space Agency), offers full development environment embedded space applications. processor manufactured using Atmel radiation tolerant KRADs (Si)) CMOS enhanced process (RTP). been specially designed space, on-chip concurrent transient permanent error detection. TSC695F includes on-chip Integer Unit (IU), Floating Point Unit (FPU), Memory Controller arbiter. real-time applications, TSC695F offers high security watchdog, timers, interrupt controller, parallel serial interfaces. Fault tolerance supported using parity internal/external buses EDAC external data bus. design highly testable with support On-Chip Debugger (OCD), boundary scan through JTAG interface.
Rev. 4118J-AERO-08/04
Block Diagram
Figure TSC695F Block Diagram
32-bit Integer Unit Arbiter Access Controller Wait State Controller Address Interface EDAC General Purpose Interface UART UART Interrupt Controller Parity Gen./Check. Ctrl
Clock Parity Reset Managt Gen./Chk.
32/64-bit Floating-Point Unit Parity Gen./Chk.
Ctrl Ready/Busy Add.+Size+ASI
Error Managt
General Purpose Timer
Real Time Clock Timer
Watch
Data+Check bits Parities
bits
RxD,
Interrupts
Descriptions
Table Descriptions
Signal RA[31:0] RAPAR RASI[3:0] RSIZE[1:0] RASPAR CPAR D[31:0] CB[6:0] DPAR RLDSTO DXFER LOCK MHOLD MEXC PROM8 BA[1:0] ROMCS ROMWRT MEMCS[9:0] MEMWR Type I/O,
assignment, refer package section.
Active
Description 32-bit registered address Output buffer: MHOLD+FHOLD +BHOLD+FCCV Output buffer: Output buffer:
High
Registered address parity 4-bit registered address space identifier 2-bit registered transaction size
High High
Registered SIZE parity Control parity 32-bit data 7-bit check-bit
High High High High High High
Data parity Registered atomic load-store Address latch enable Data transfer lock Read access Write enable Advanced write Memory hold Memory data strobe Memory exception Select 8-bit wide PROM Latched address used 8-bit wide boot PROM PROM chip select write enable Memory chip select Memory write strobe
TSC695F
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TSC695F
Table Descriptions (Continued)
Signal BUFFEN DDIR DDIR IOSEL[3:0] IOWR EXMCS BUSRDY BUSERR DMAREQ DMAGNT DMAAS DRDY IUERR CPUHALT SYSERR SYSHALT SYSAV NOPAR INULL INST FLUSH RxA/RxB TxA/TxB GPI[7:0] GPIINT EXTINT[4:0] EXTINTACK IWDE EWDINT WDCLK CLK2 SYSCLK RESET SYSRESET TMODE[1:0] DEBUG TRST VCCI/VSSI VCCO/VSSO Type High High High High High Active High High High High High High High High Description Memory output enable Data buffer enable Data buffer direction Data buffer direction chip select exchange memory write strobe Exchange memory chip select ready error request grant address strobe Data ready during access error Processor FPU) halt freeze System error System halt System availability parity Integer unit nullify cycle Instruction fetch instruction flush Delay instruction annulled Real Time Clock Counter output Receive data UART Transmit data UART input/output interrupt External interrupt External interrupt acknowledge Internal watch enable External watch input interrupt Watch clock Double frequency clock System clock Output reset System input reset Factory test mode Software debug mode Test (JTAG) clock Test (JTAG) reset Test (JTAG) mode select Test (JTAG) data input Test (JTAG) data output Main internal power Output driver power Output buffer: Used check execute stage instruction pipeline Input trigger Input trigger Input trigger Input trigger Input trigger Functional mode=00 pull-up pull-up pull-up
Note:
specified, output buffer type input buffer type TTL.
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System Architecture
TSC695F used embedded processor requiring only memory application specific peripherals added form complete on-board computer. other system support functions provided core.
Figure System Architecture Based TSC695F Unit Ax[31:0]
PROM Xchg
Boot PROM
Master
Local Memory
Glue Logic
DPAR
DMAGNT DMAREQ DMAAS
(BUFFEN, DDIR)
general
MEMCtrl
Memory Interface
RA[31:0]
CB[6:0]
(ROMCS, EXMCS, IOSEL[3:0], MEMWR, IOWR, BUSRDY,.)
RAMCtrl
(MEMCS[9:0], MEMWR, SYSCLK
Memory
A[31:0]
D[31:0]
Peripherals
User Application
TSC695F
TSC695F
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TSC695F
Product Description
Integer Unit
Integer Unit (IU) designed highly dependable space military applications, includes support error detection. RISC architecture makes creation processor that execute instructions rate approaching instruction processor clock possible. achieve that rate execution, employs four-stage instruction pipeline that permits parallel execution multiple instructions. Fetch processor outputs instruction address fetch instruction. Decode instruction placed instruction register decoded. processor reads operands from register file computes next instruction address. Execute processor executes instruction saves results temporary registers. Pending traps prioritized internal traps taken during this stage. Write trap taken, processor writes result destination register.
four stages operate parallel, working four different instructions time. basic `single-cycle' instruction enters pipeline completes infour cycles. time reaches write stage, three more instructions have entered moving through pipeline behind after first four cycles, single-cycle instruction exits pipeline single-cycle instruction enters pipeline every cycle. course, 'single-cycle' instruction actually takes four cycles complete, they called single cycle because with this type instruction processor complete instruction cycle after initial four-cycle delay.
Floating-point Unit
FLoating Point Unit (FPU) designed provide execution single doubleprecision floating-point instructions concurrently with execution integer instructions compliant ANSI/IEEE-754 (1985) floating-point standard. designed highly dependable space military applications, includes support concurrent error detection testability. uses four stage instruction pipeline consisting fetch, decode, execute write stages fetch unit captures instructions their addresses from data address buses. decode unit contains logic decode floatingpoint instruction opcodes. execution unit handles instruction execution. execution unit includes floating-point queue queue), which contains stored floatingpoint operate (FPop) instructions under execution their addresses. execution unit controls load unit, store unit, datapath unit. depends upon access addresses control signals memory access. Floating-point loads stores executed conjunction with which provides addresses control signals while supplies stores data. Instruction fetch integer floating-point instructions provided provides three types registers: registers, FSR, queue. 32-bit status control register. keeps track rounding modes, floating-point trap types, queue status, condition codes, various IEEE exception information. floating-point queue contains floating-point instruction currently under execution, along with corresponding address.
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Instruction
TSC695F instructions fall into functional categories: load/store, arithmetic/logical/shift, control transfer, read/write control register, floating-point, miscellaneous. Please refer SPARC Instruction-set Manual.
Note: execution IFLUSH will cause illegal instruction trap.
On-chip Peripherals
Memory Interface Table Memory Mapping
Memory Contents Boot PROM Start Address 0000 0000 Size (bytes) 128K Data Size Parity Options 8-bit mode 40-bit mode Extended PROM 0100 0000 Max: 8-bit mode 40-bit mode Exchange Memory System Registers blocks) Extended Area Area Area Area Extended Area Extended General 01F0 0000 01F8 0000 0200 0000 0400 0000 1000 0000 1100 0000 1200 0000 1300 0000 1400 0000 8000 0000 512k 512K (124 used) 8*32K 8*4M Max: 192M Max: 1728M Max: parity/-All data sizes allowed Parity option/-All data sizes allowed parity/-No EDAC/-Only byte write Parity EDAC mandatory/-Only word write parity/-No EDAC/-Only byte write Parity EDAC mandatory/-Only word write
TSC695F designed allow easy interfacing internal/external memory resources.
Parity EDAC option/-Only word write Parity/-Only word read/write access Parity EDAC option/-All data sizes allowed
System Registers
system registers only writable supervisor mode during halt mode. Table System Registers Address
System Register Name System Control Register Software Reset Power Down System Fault Status Register Failing Address Register Error Reset Status Register Test Control Register SYSCTR SWRST PDOWN SYSFSR FAILAR ERRRSR TESCTR Address 01F8 0000 01F8 0004 01F8 0008 01F8 00A0 01F8 00A4 01F8 00B0 01F8 00D0
TSC695F
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TSC695F
Table System Registers Address (Continued)
System Register Name Memory Configuration Register Configuration Register Waitstate Configuration Register Access Protection Segment Base Register Access Protection Segment Register Access Protection Segment Base Register Access Protection Segment Register Interrupt Shape Register Interrupt Pending Register Interrupt Mask Register Interrupt Clear Register Interrupt Force Register Watchdog Timer Register Watchdog Timer Trap Door Real Time Clock Timer <Counter> Register Real Time Clock Timer <Scaler> Register General Purpose Timer <Counter> Register General Purpose Timer <Scaler> Register Timers Control Register General Purpose Interface Configuration Register General Purpose Interface Data Register UART Register UART Register UART Status Register MCNFR IOCNFR WSCNFR APS1BR APS1ER APS2BR APS2ER INTSHR INTPDR INTMKR INTCLR INTFCR WDOGTR WDOGST RTCCR RTCSR GPTCR GPTSR TIMCTR GPICNFR GPIDATR UARTAR UARTBR UARTSR Address 01F8 0010 01F8 0014 01F8 0018 01F8 0020 01F8 0024 01F8 0028 01F8 002C 01F8 0044 01F8 0048 01F8 004C 01F8 0050 01F8 0054 01F8 0060 01F8 0064 01F8 0080 01F8 0084 01F8 0088 01F8 008C 01F8 0098 01F8 00A8 01F8 00AC 01F8 00E0 01F8 00E4 01F8 00E8
Wait-state Time-out Generator
possible control wait-state generation programming Wait-state Configuration Register. maximum programmable number wait-states applied default reset. possible program number wait-states following combinations: read write PROM read write (i.e. EEPROM Flash write) Exchange Memory read/write Four individual peripherals read/write
time-out function system clock cycles provided ready controlled memory areas, i.e., Extended PROM, Exchange Memory, Extended RAM,
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Extended Extended General areas. EDAC TSC695F includes 32-bit EDAC (Error Detection Correction). Seven bits (CB[6:0]) used check bits over data bus. Data Parity signal (DPAR) used check generate parity over 32-bit data bus. This means that altogether bits used when EDAC enabled. TSC695F EDAC uses 7-bit Hamming code which detects double error 40-bit non-correctable error. addition, EDAC detects bits stuck-atone stuck-at-zero failure nibble data word non-correctable error. Stuck-at-one stuck-at-zero bits data word also detected noncorrectable error. Memory Parity TSC695F handles parity towards memory special way. processor programmed parity, only parity parity EDAC protection towards memory parity towards I/O. signal used parity DPAR. Programming Memory Configuration Register, TSC695F provides chip selects redundant memory banks replacement faulty banks. Unimplemented Areas Access unimplemented memory areas handled TSC695F detected illegal. Write Access Protection TSC695F programmed detect mask write accesses part RAM. protection scheme enabled only data area, instruction area. programmable write access protection based segments. Boot PROM Write Protection TSC695F supports qualified PROM write 8-bit wide PROM and/or 40-bit wide PROM.
Memory Redundancy
Memory Access Protection
Interface TSC695F supports Direct Memory Access (DMA). unit requests access processor asserting request signal (DMAREQ). When unit receives DMAGNT signal response, processor granted. case processor power-down mode processor permanent tri-stated, DMAREQ will directly give DMAGNT. TSC695F includes session time-out function. TSC695F always lowest priority system bus. trap vectored transfer control supervisor through special trap table that contains first four instructions each trap handler. base address table established supervisor displacement, within table, determined trap type. categories traps appear.
Arbiter
Traps
TSC695F
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TSC695F
Synchronous Traps Table Synchronous Traps
Trap Priority Trap Type (tt) Comments Sources: SYSRESET* software reset watchdog reset System error reset Severe error requiring re-boot TSC695F enters masked) halt reset mode Error removable, TSC695F enters masked) halt reset mode Special case non-restartable, precise error. TSC695F enters masked) halt reset mode Retrying instruction have re-adjusted TSC695F enters masked) halt reset mode Retrying instruction TSC695F enters masked) halt reset mode Parity error control Parity error data Parity error address Access protected unimplemented area Uncorrectable error memory time error
Reset Non-restartable, imprecise error Non-restartable, precise error Register file error Hardware Error Restartable, late error Restartable, precise error
Instruction access (Error instruction fetch) Illegal Instruction Privileged instruction disabled Overflow Window Underflow
During SAVE instruction trap taken During RESTORE instruction RETT instruction
Non-restartable error Data error Restartable error Sequence error Unimplemented FPop exception
Parity error data removed restarting instruction
IEEE exceptions:
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Memory address aligned
Severe error, cannot restart instruction
Invalid operation Division zero Overflow Underflow Inexact
Table Synchronous Traps (Continued)
Trap Data access exception (Error data load) overflow Trap instructions Priority Trap Type (tt) Comments Idem "instruction access" System register access violation TADDccTV TSUBccTV instructions Trap integer condition codes (Ticc)
Table Interrupts Asynchronous Traps
Trap Watchdog time-out External Real time clock timer General purpose timer External External time-out access error UART Error Correctable error memory UART UART Data ready Transmitter ready Data ready Transmitter ready Priority
Trap Type (tt) Comments
Internal external (EWDINT pin) EXTINTAK only EXTINT[4:0]
External External
EXTINTAK only EXTINT[4:0] EXTINTAK only EXTINT[4:0] Logical hardware error masked error mode masked System hardware error masked
Masked hardware errors
possible mask each individual interrupt (except Watchdog time-out). interrupts Interrupt Pending Register cleared automatically when interrupt acknowledged. programming Interrupt Shape Register, possible define external interrupts either active active high define external interrupts either edge level sensitive.
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EXTINTAK only EXTINT[4:0] EXTINTAK only EXTINT[4:0]
Data read source updated
TSC695F
Timers
General Purpose Timer software debug mode timers controlled system register external DEBUG. General Purpose Timer (GPT) provides, addition generalized counter function, mechanism setting step size which actual time counts performed. clocked internal system clock. They possible program either single-shot type periodical type both cases generate interrupt when delay time elapsed. current value scaler counter read. Real Time Clock Timer only functional differences between timers that Real Time Clock Timer (RTCT) 8-bit scaler (16-bit scaler GPT) that RTCT interrupt higher priority than interrupt. RTCT information available output pin. Watchdog Timer Setting external IWDE enables internal watchdog timer. Otherwise watchdog function must externally provided. watchdog supplied from separate external input (WDCLK). After reset, timer enabled starts running with maximum range. timer refreshed (reprogrammed) before counter reaches zero value, interrupt sent. Simultaneo usly, timer starts counting reset time -out period. timer acknowledged before reset time-out period elapses, reset applied TSC695F.
UARTs
full duplex asynchronous receiver transmitters (UART) included. software debug mode UART's controlled system register bits. data format UART's eight bits. possible choose between even parity, parity, between stop bits. UART's provide double buffering, i.e. each UART consists transmitter holding register, receiver holding register, transmitter shift register, receiver shift register. Each these registers 8-bit wide. each UART Register provided. UART's generate interrupt each time byte been received byte been sent. There another interrupt indicate errors. baud rate both UART's programmable. clock derived either from system clock watchdog clock.
General Purpose Interface
General Purpose Interface (GPI) 8-bit parallel port. Each configured input output. falling rising edge detection made each selected inputs. Every input transition generates external positive pulse GPIINT SYSCLK width.
Execution Modes
Reset Mode Reset mode entered when: SYSRES input asserted Software reset which caused software writing Software Reset Register Watchdog reset which caused Watchdog counter time-out Error reset which caused hardware parity error
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This RESET output minimum 1024 SYSCLK width allow usage Flash memories. error Reset Status Register contain source last processor reset. Mode this mode IU/FPU executing, while peripherals running software enabled). System Halt mode entered when SYSHALT input asserted. this mode, frozen, while timers (includeing internal watchdog timer) UART's stopped. This mode entered writing Power-down Register. this mode, frozen. TSC695F leaves power-down mode external interrupt asserted. Error Halt mode entered under following circumstances: internal hardware parity error. enters error mode.
System Halt Mode
Power Down Mode
Error Halt Mode
only exit Error Halt Mode through Cold Reset asserting SYSRESET.
Error Handler
TSC695F error output signal (SYSERR) which indicates that unmasked error occurred. error signalled error inputs from latched reflected Error Reset Status Register. default, error leads processor halt. TSC695F includes: Parity checking generation required) external data Parity checking external address Parity checking SIZE Parity checking generation system registers Parity generation checking internal control
Parity Checking
external parity checking disabled using NOPAR signal.
System Clock
TSC695F uses CLK2 clock input directly creates system clock signal dividing CLK2 two. drives SYSCLK with nominal duty cycle application. highly recommended that only SYSCLK rising edge used reference possible. SYSAV Error Reset Status Register used software indicate system availability. TSC695F includes number software test facilities such EDAC test, Parity test, Interrupt test, Error test simple Test Access Port. These test functions controlled using Test Control Register.
System Availability Test Mode
TSC695F
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TSC695F
Test Diagnostic Hardware Functions
Test Access Port
variety TSC695F test diagnostic hardware functions, including boundary scan, internal scan, clock control On-chip Debugger, controlled through IEEE 1149.1 (JTAG) standard Test Access Port (TAP). interfaces JTAG dedicated pins TSC695F chip. These pins are: (input): Test Clock (input): Test Mode Select (input): Test Data Input (output): Test Data Output TRST (input): Test Reset
Instruction Register
Five standard instructions supported TSC695F TAP.
Binary Value 0000 0001 0011 1111 0000 Name Instruction EXTEST SAMPLE/PRELOAD INTEST BYPASS IDCODE Data Register Boundary Scan Register Boundary Scan Register Boundary Scan Register Bypass Register Device Register Scan Chain Accessed Boundary scan chain Boundary scan chain Boundary scan chain Bypass register register scan chain
Debugging
design highly testable with support On-Chip Debugger (OCD), internal boundary scan through JTAG interface.
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Electrical Characteristics
Absolute Maximum Ratings
Military Range. -55°C +125°C Storage Temperature -65°C +150°C Supply Voltage. -0.5V +7.0V Input Voltage.-0.5V +7.0V Note: Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions affect device reliability.
Characteristics
Table Characteristics
Symbol
trigger
Parameter Input Voltage trigger input Input High Voltage trigger input Input Hysteresis trigger input Input Voltage input Input High Voltage input Output Voltage buffer Output High Voltage buffer Output Voltage buffer Output High Voltage buffer
Unit
Test Conditions 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V 5.5V,
trigger
VOL400 VOL150
Operating Supply Current core processor
5.5V, 5.5V, 5.5V, 25MHz
IccPD
Power Down Supply Current core processor
5.5V, 5.5V,
TSC695F
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TSC695F
Capacitance Ratings
Parameter COUT Description Input Capacitance Output Capacitance Input/Output Capacitance
Characteristics
Table Characteristics (SYSCLK Freq. ±10%) Cload Vref 2.5V
Parameter (ns) 9.75 (ns) 12.5 23.5 Comment CLK2 period SYSCLK period CLK2 high pulse width RA(31:0) RAPAR RSIZE RLDSTO output delay MEMCS*(9:0) ROMCS* EXMCS* output delay DDIR DDIR* output delay MEMWR* IOWR*output delay formula: 13.5 output delay formula: 10.5 Data setup time during load Data setup time during load NOPAR either Data hold time during load Data output delay Data output valid guaranteed design output delay ALE* output delay BUFFEN* output delay formula: MHOLD* output delay guaranteed design MDS* DRDY* output delay MEXC* output delay RASI(3:0) RSIZE(1:0) RASPAR setup time RASI(3:0) RSIZE(1:0) RASPAR hold time BOOT PROM address output delay Reference Edge SYSCLK+ SYSCLK+ SYSCLK+
SYSCLK- SYSCLK+
t9_1 t9_2
11.5
20.5
SYSCLK+ SYSCLK+ SYSCLK+ SYSCLK+ SYSCLKSYSCLK+ SYSCLK+ SYSCLK-
SYSCLK+ SYSCLK+ SYSCLK+ SYSCLKSYSCLK+ SYSCLK+ SYSCLK+
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Table Characteristics (SYSCLK Freq. ±10%) Cload Vref 2.5V (Continued)
Parameter (ns) (ns) Comment BUSRDY* setup time BUSRDY* hold time IOSEL output delay DMAAS setup time formula max: DMAAS hold time formula max: DMAREQ* setup time DMAGNT* output delay RA(31:0) RAPAR CPAR setup time RA(31:0) RAPAR CPAR hold time period setup time hold time setup time hold time output delay INULL output delay RESET* CPUHALT* output delay SYSERR* SYSAV output delay IUERR* output delay EXTINT(4:0) setup time EXTINT(4:0) hold time EXTINTACK output delay output delay mode) BUFFEN* output delay INST output delay Reference Edge SYSCLK+ SYSCLK+ SYSCLK+ SYSCLK-
SYSCLK+
SYSCLKSYSCLK+ SYSCLK+ SYSCLK+ SYSCLK+ TCK+ TCK+ TCK+ TCK+ TCKSYSCLK+ SYSCLK+ SYSCLK+ SYSCLK+ SYSCLKSYSCLK+ SYSCLK+ SYSCLK+ SYSCLK+ SYSCLK+
Data output delay low-Z guaranteed design formula: SYSCLK+ BUSERR* setup time SYSCLK+
BUSERR* hold time formula:
SYSCLK+
TSC695F
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Figure Buffer Response (Data from simulation)
TSC695F
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Figure Buffer Response (Data from simulation)
TSC695F
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TSC695F
Figure OE*/400 Buffer Response (Data from simulation)
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Timing Diagrams
Figure Fetch, Load Store Sequence Waitstates Read, Waitstates Write
(RAM load) (RAM fetch) (RAM store) (RAM fetch) t4_1
(RAM fetch)
CLK2
SYSCLK t4_1 t4_1 t4_1
TSC695F
previous stored data
[31:0]
MEMCS*
MEMCS*
ROMCS*
DDIR
MEMWR*
BUFFEN*
[31:0]
previous stored parity
DPAR
previous stored checkbyte
[6:0]
INST
MHOLD*
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MDS*
(RAM fetch)
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(RAM atomic load store) (RAM fetch)
SYSCLK
t4_1
ALSA
t4_1
[31:0]
ALE*
MEMCS*
MEMCS*
DDIR
MEMWR*
BUFFEN*
byte from word from word
Figure "Atomic-load-store" byte Sequence Waitstate
[31:0]
parity checkbyte from checkbyte
DPAR
parity from
parity from
[6:0] checkbyte from
INST
held update full word
MHOLD*
MDS*
INULL
t4_1 t4_2
t4_1
RLDSTO
t4_2
TSC695F
LOCK
Figure Load-double Store-double Sequence Waitstate
(RAM double load) (RAM fetch) (RAM double store) (RAM fetch)
t4_1
(RAM fetch)
SYSCLK
t4_1 t4_1 t4_1 t4_1 t4_1
[31:0]
TSC695F
ALE*
MEMCS*
MEMCS*
DDIR
MEMWR*
BUFFEN*
[31:0]
DPAR
[6:0]
INST
MHOLD*
MDS*
INULL
t4_2 t4_2
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LOCK
(RAM fetch) load internal error correction
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(RAM load correctable data)
(RAM fetch)
(RAM fetch)
SYSCLK
ALE*
t4_1 t4_1 t4_1
RA[31-0]
MEMCS*[0]
MEMCS*[1]
DDIR
MEMWR*
IOWR*
Figure Load with Correctable Error Waitstate
BUFFEN* 1-bit error 40-bit data
D[31-0]
data correction made inside
CB[6-0]
DPAR
MHOLD*
MEXC*
MDS*
INST
TSC695F
INULL
Figure Load with Uncorrectable Error Waitstate
(RAM load) load internal error detection exception trap (RAM fetch) (null cycle) (RAM fetch) (RAM fetch)
t4_1 t4_1 t4_1 t4_1
(RAM fetch)
SYSCLK
TSC695F
2-bit error 40-bit data
ALE*
RA[31-0]
MEMCS*[0]
MEMCS*[1]
DDIR
MEMWR*
IOWR*
BUFFEN*
D[31-0]
CB[6-0]
DPAR
MHOLD*
MEXC*
MDS*
INST
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INULL
(RAM fetch) internal error fetch trap
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(RAM load)
(RAM fetch)
(null cycle)
(RAM fetch)
(RAM fetch)
SYSCLK
ALE*
t4_1 t4_1
RA[31-0]
unimplemented address
MEMCS*[0]
MEMCS*[1]
DDIR
MEMWR*
IOWR*
BUFFEN*
Figure Load with Unimplemented Area Access Waitstate
data
D[31-0]
MHOLD*
MEXC*
MDS*
INST
TSC695F
INULL
Figure Store Sequence with BUSRDY* Waitstates (Timing Waitstate Timing Waitstates)
start cycle (n-1) waiting cycle (i/o store) (RAM fetch)
t4_1 t4_1
(RAM fetch)
SYSCLK
TSC695F
previous stored data
ALE*
t4_1
RA[31-0]
MEMCS*[0]
IOSEL*[0]
BUSRDY*
DDIR
MEMWR*
IOWR*
BUFFEN*
D[31-0]
INST
MHOLD*
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MDS*
(RAM fetch) start cycle (n-1) waiting cycle
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(i/o load)
(RAM fetch)
SYSCLK
ALE* t4_1
t4_1
RA[31-0]
MEMCS*[0]
IOSEL*[0]
BUSRDY*
DDIR
MEMWR*
IOWR*
BUFFEN*
data driven external buffers (c.f BUFFEN*)
D[31-0]
Figure Load Sequence with BUSRDY* Waitstates (Timing Timing
INST
MHOLD*
TSC695F
MDS*
Figure EXCHANGE Store with BUSDRY* Waitstates
(xchgRAM store) start cycle waiting between cycle (RAM fetch) t4_1 t4_1 previous stored data
(RAM fetch)
SYSCLK
TSC695F
ALE*
RA[31-0]
MEMCS*[0]
EXMCS*
DDIR
MEMWR*
IOWR*
BUFFEN*
BUSRDY*
D[31-0]
INST
MHOLD*
MDS*
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(RAM fetch) start cycle waiting cycle
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(xchgRAM load)
(RAM fetch)
SYSCLK
ALE*
t4_1 t4_1
RA[31-0]
MEMCS*[0]
EXMCS*
DDIR
MEMWR*
IOWR*
Figure EXCHANGE Load with BUSDRY* Waitstates
BUFFEN*
BUSRDY* data driven external buffers (c.f BUFFEN*)
D[31-0]
INST
MHOLD*
TSC695F
MDS*
Figure 8-bit BOOT PROM Fetch Load Word) Waitstates
(8-bit fetch load word) start cycle cycle byte (n-1) byte (n-1) byte (n-1) byte (n-1) (ROM fetch)
(ROM fetch)
TSC695F
t4_1
SYSCLK
ALE*
t4_1 t4_1
(address mod.
RSIZE[0,1]
t4_1
RA[31-0]
BA[0,1]
ROMCS*
MEMCS*[0]
DDIR
MEMWR*
BUFFEN* data driven external buffers (c.f BUFFEN*) FD2-0 fetch, load word) FD2-1 FD2-2
D[31-8]
D[7-0]
FD2-3
INST
MHOLD*
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MDS*
(RAM fetch) start cycle (n-1) (n-1) start cycle
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(8-bit write)
(RAM fetch)
(8-bit write)
(RAM fetch)
SYSCLK
ALE*
t4_1
addr.=mod. addr.=mod.
t4_1
t4_1
RA[31-0]
t4_1
BA[0,1]
t4_1
t4_1
t4_1
t4_1
RSIZE[0,1]
MEMCS*[0]
Figure 8-bit BOOT PROM Store byte Waitstate
ROMCS*
DDIR
MEMWR*
IOWR*
BUFFEN*
byte D[7:0] byte D[7:0]
D[31-0]
INST
MHOLD*
TSC695F
MDS*
Figure load with without Correctable Error Store Waitstates
(DMA session) cycle min) load cycle min) store lead-out (held access) (RAM fetch) (RAM fetch) cont'
(RAM fetch) (RAM fetch) (null cycle)lead-in
SYSCLK
ALE*
TSC695F
t4_1 t4_1
early time DMAREQ* desassertion corrected data needed (only word access)
RA[31-0]
t4_1 t4_1 t4_1
(only word access) (held access)
t4_1 t4_1 t4_1
RASI[3-0]
RSIZE[1-0]
t4_1
DMAREQ*
DMAGNT*
DMAAS
(pull-up WE*)
MEMCS*[9-0]
DRDY*
MEMWR*
DDIR
D[31-0]
DPAR
CB[7-0]
(from RAM) (from TSC695F) (held access) DSPn (from RAM) Parity generated TSC695F (from TSC695F) else, same timing D[31-0] corrected parity needed (from RAM)
4118J-AERO-08/04
MHOLD*
4118J-AERO-08/04
Sampled Latched Taken
Figure Edge Triggered Interrupt Timing
Prioritized
SYSCLK FA(-1) TTA0 TTA1 TSA0 TSA1 TSA2
RA[31:0]
ALE* FD(-1) TSD0 TSD1
D[31:0]
INULL
EXTINT[i]
EXTINTACK
TSC695F
Figure Halt Timing
TSC695F
FAn-1 FAn+1 FAn+1 FAn+2 FDn-1
FDn+1 FDn+2
SYSCLK
RA[31:0]
RASI[3:0]
RSIZE[1:0]
ALE*
SYSHALT*
MHOLD*
SYSAV
CPUHALT*
D[31:0]
4118J-AERO-08/04
4118J-AERO-08/04
SYSCLK FAn-1 FAn+1
RA[31:0]
RASI[3:0]
Figure External Error with Halt Timing
RSIZE[1:0]
ALE*
IUERR*
SYSERR*
MHOLD*
SYSAV
CPUHALT* FDn-1
D[31:0]
TSC695F
Figure Reset Timing
TSC695F
SYSCLK
SYSRESET*
RA[31:0]
RASI[3:0]
RSIZE[1:0]
ALE*
INULL
RESET*
4118J-AERO-08/04
TSC695F
Figure External Error signaling with BUSERR* BUSRDY*
SYSCLK BUSRDY* BUSERR* MEXC*
4118J-AERO-08/04
Package Drawings
256-lead MQFP-F Package
TSC695F
4118J-AERO-08/04
TSC695F
256-lead MQFP-F Assignments
Table Assignments
Signal GPIINT GPI[7] VCCO VSSO GPI[6] GPI[5] GPI[4] GPI[3] VCCO VSSO GPI[2] GPI[1] GPI[0] D[31] D[30] VCCO VSSO D[29] D[28] VCCI VSSI D[27] D[26] VCCO VSSO D[25] D[24] D[23] D[22] VCCO VSSO D[21] D[20] D[19] D[18] Signal D[0] RSIZE[1] RSIZE[0] RASI[3] VCCO VSSO RASI[2] RASI[1] RASI[0] RA[31] RA[30] VCCO VSSO RA[29] RA[28] RA[27] VCCO VSSO RA[26] RA[25] RA[24] VCCI VSSI VCCO VSSO RA[23] RA[22] RA[21] VCCO VSSO RA[20] RA[19] RA[18] VCCO VSSO Signal RA[0] VCCO VSSO RAPAR RASPAR DPAR VCCO VSSO SYSCLK TRST CLK2 DRDY DMAAS VCCO VSSO DMAGNT EXMCS VCCI VSSI DMAREQ BUSERR BUSRDY ROMWRT NOPAR SYSHALT CPUHALT VCCO VSSO SYSERR SYSAV EXTINT[4] Signal DXFER MEXC VCCO VSSO RESET SYSRESET BA[1] BA[0] CB[6] CB[5] VCCO VSSO CB[4] CB[3] CB[2] CB[1] VCCO VSSO CB[0] VCCI VSSI PROM8 ROMCS MEMCS[9] VCCO VSSO MEMCS[8] MEMCS[7] MEMCS[6] MEMCS[5] MEMCS[4] MEMCS[3] VCCO VSSO
4118J-AERO-08/04
Table Assignments (Continued)
Signal VCCO VSSO D[17] D[16] VCCI VSSI D[15] D[14] VCCO VSSO D[13] D[12] D[11] D[10] VCCO VSSO D[9] D[8] D[7] D[6] VCCO VSSO D[5] D[4] D[3] D[2] VCCO VSSO D[1] Signal RA[17] RA[16] RA[15] VCCO VSSO RA[14] VCCI VSSI RA[13] RA[12] VCCO VSSO RA[11] RA[10] RA[9] VCCO VSSO RA[8] RA[7] RA[6] VCCO VSSO RA[5] RA[4] RA[3] VCCO VSSO RA[2] RA[1] Signal EXTINT[3] EXTINT[2] EXTINT[1] EXTINT[0] VCCI VSSI EXTINTACK IUERR VCCO VSSO CPAR IOWR IOSEL[3] VCCO VSSO IOSEL[2] IOSEL[1] IOSEL[0] VCCO VSSO RLDSTO LOCK Signal MEMCS[2] MEMCS[1] MEMCS[0] VCCI VSSI VCCO VSSO MEMWR BUFFEN DDIR VCCO VSSO DDIR MHOLD WDCLK IWDE EWDINT TMODE[1] TMODE[0] DEBUG INULL VCCO VSSO FLUSH INST
TSC695F
4118J-AERO-08/04
TSC695F
Ordering Information
Table Possible Order Entries
Temperature Part-Number TSC695F-25MA-E TSC695F-25MA 5962-0054001QXC 5962-0054001VXC 5962R0054001VXC 951200301 TSC695F-25MB-E 5962-0054001Q9A 5962-0054001V9A Supply Voltage Range 25°C -55° +125°C -55° +125°C -55° +125°C -55° +125°C -55° +125°C 25°C -55° +125°C -55° +125°C Maximum Speed (MHz) Packaging MQFP-F256 MQFP-F256 MQFP-F256 MQFP-F256 MQFP-F256 MQFP-F256 Quality Flow Engineering Samples Standard Mil. QML-Q QML-V QMLV-RHA ESCC Engineering Samples QML-Q QML-V
4118J-AERO-08/04
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4118J-AERO-08/04

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