with Constant-Voltage Trickle Charger DS12R885 functional drop-in
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4/04
with Constant-Voltage Trickle Charger
DS12R885 functional drop-in replacement DS12885 real-time clock (RTC). device provides RTC/calendar, time-of-day alarm, three maskable interrupts with common interrupt output, programmable square wave, bytes batterybacked static RAM. date month automatically adjusted months with fewer than days, including correction leap years. also operates either 24-hour 12-hour format with AM/PM indicator. precision temperature-compensated circuit monitors status VCC. primary power failure detected, device automatically switches backup supply. VBACKUP supports rechargeable battery super includes integrated, always enabled trickle charger. DS12R885 accessed through multiplexed byte-wide interface, which supports both Intel Motorola modes. DS12CR887 DS12R887 integrate DS12R885 with crystal battery.
Features
Trickle-Charge Capability Rechargeable Battery Super Selectable Intel Motorola Timing Counts Seconds, Minutes, Hours, Day, Date, Month, Year with Leap-Year Compensation 2100 Interrupt Output with Three Independently Maskable Interrupt Flags Time-of-Day Alarm Once-per-Second Onceper-Day Periodic Rates from 122µs 500ms End-of-Clock Update Cycle Flag Bytes Clock Control Registers Bytes General-Purpose with Clear Input Programmable Square-Wave Output Automatic Power-Fail Detect Switch Circuitry +5.0V +3.3V Operation Industrial Temperature Range DS12CR887 Encapsulated (EDIP) Module with Integrated Battery Crystal DS12R887 Module Surface-Mountable Package with Integrated Crystal Rechargeable Battery
DS12R885/DS12CR887/DS12R887
Applications
Embedded Systems Utility Meters Security Systems Network Hubs, Bridges, Routers
Typical Operating Circuit
CRYSTAL
Ordering Information
PART DS12R885-5 DS12R885-33 DS12CR887-5 TEMP RANGE -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C PINPACKAGE (300 mils) (300 mils) EDIP (700 mils) EDIP (700 mils) MARK DS12R885-5 DS12R885-33 DS12CR887-5 DS12CR887-33 DS12R887-5 DS12R887-33
RESET RCLR
DS83C520
AD(0-7)
DS12R885
VBACKUP
DS12CR887-33
SUPER
DS12R887-5* DS12R887-33*
-40°C +85°C -40°C +85°C
*Future product-contact factory availability.
Configurations appear data sheet.
Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim/Dallas Direct! 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
with Constant-Voltage Trickle Charger DS12R885/DS12CR887/DS12R887
ABSOLUTE MAXIMUM RATINGS
Voltage Range Relative Ground .-0.3V +6.0V Operating Temperature Range .-40°C +85°C Storage Temperature Range .-55°C +125°C Soldering Temperature .See IPC/JEDEC J-STD-020A Specification Soldering Temperature (leads, 10s) .+260°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC VCC(MIN) VCC(MAX), -40°C +85°C, unless otherwise noted.) (Note
PARAMETER Supply Voltage (Note VBACKUP Input Voltage (DS12R885 Only) Input Logic Input Logic Power-Supply Current (Note Standby Current (Note Input Leakage Leakage Input Current Output Current 2.4V Output Current 0.4V Power-Fail Voltage (Note Trip Point Trickle-Charger Current-Limiting Resistor Trickle-Charger Output Voltage SYMBOL VBACKUP ICC1 ICCS IMOT VRTTRIP VOUT (Note (Note (Note (Note DS12R885 Only DS12R885 Only 4.05 2.88 4.33 3.05 (Note (Note (Note -1.0 -1.0 -1.0 -1.0 2.97 CONDITIONS 2.97 -0.3 0.250 0.140 3.63 VOUT +0.8 +1.0 +1.0 +500 UNITS
with Constant-Voltage Trickle Charger
ELECTRICAL CHARACTERISTICS (DS12R885 Only)
(VCC VBACKUP 3.2V, -40°C +85°C, unless otherwise noted.) (Note
PARAMETER VBACKUP Current (OSC On); +25°C, VBACKUP 3.0V VBACKUP Current (Oscillator Off) SYMBOL IBACKUP2 (Note CONDITIONS 1000 UNITS
DS12R885/DS12CR887/DS12R887
IBACKUPDR (Note
ELECTRICAL CHARACTERISTICS
(VCC 4.5V 5.5V, -40°C +85°C.) (Note
PARAMETER Cycle Time Pulse Width, High Pulse Width, High Input Rise Fall Hold Time Setup Time Before DS/E Chip-Select Setup Time Before Chip-Select Hold Time Read-Data Hold Time Write-Data Hold Time Address Valid Time Fall Address Hold Time Fall Delay Time DS/E Rise Pulse Width High Delay Time, DS/E Rise Output Data Delay Time from Data Setup Time Reset Pulse Width Release from Release from RESET SYMBOL tCYC PWEL PWEH tRWH tRWS tDHR tDHW tASL tAHL tASD PWASH tASED tDDR tDSW tRWL tIRDS tIRR (Note CONDITIONS UNITS
with Constant-Voltage Trickle Charger DS12R885/DS12CR887/DS12R887
ELECTRICAL CHARACTERISTICS
(VCC 2.97V 3.63V, -40°C +85°C.) (Note
PARAMETER Cycle Time Pulse Width, High Pulse Width, High Input Rise Fall Hold Time Setup Time Before Chip-Select Setup Time Before Chip-Select Hold Time Read-Data Hold Time Write-Data Hold Time Address Valid Time Fall Address Hold Time Fall Delay Time Rise Pulse Width High Delay Time, Rise Output Data Delay Time from Data Setup Time Reset Pulse Width Release from Release from RESET SYMBOL tCYC PWEL PWEH tRWH tRWS tDHR tDHW tASL tAHL tASD PWASH tASED tDDR tDSW tRWL tIRDS tIRR (Note CONDITIONS UNITS
with Constant-Voltage Trickle Charger DS12R885/DS12CR887/DS12R887
Motorola Read/Write Timing
PWASH tASD tCYC PWEL tRWS tDSW AD0-AD7 WRITE tASL AD0-AD7 READ tAHL tDHR tDDR tDHW PWEH tRWH tASED
Intel Write Timing
tCYC tASD tASD PWASL tASL AD0-AD7 WRITE tAHL tDSW tDHW PWEH PWASH
with Constant-Voltage Trickle Charger DS12R885/DS12CR887/DS12R887
Intel Read Timing
tCYC tASD tASD tASL AD0-AD7 tAHL tDDR tDHR PWASL PWASH tASED PWEH
Release Delay Timing
RESET tIRDS
tIRDS
tIRDS
Power-Up/Power-Down Timing
VPF(MAX)
VPF(MIN)
tRPU
INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
HIGH-Z OUTPUTS VALID VALID
with Constant-Voltage Trickle Charger
POWER-UP/POWER-DOWN CHARACTERISTICS
-40°C +85°C) (Note
PARAMETER Recovery Power-Up Fall Time; VPF(MAX) VPF(MIN) Rise Time; VPF(MIN) VPF(MAX) SYMBOL tRPU CONDITIONS UNITS
DS12R885/DS12CR887/DS12R887
CAPACITANCE
+25°C)
PARAMETER Capacitance Input Pins Except Capacitance IRQ, SQW, Pins SYMBOL (Note (Note CONDITIONS UNITS
TEST CONDITIONS
PARAMETER Input Pulse Levels (-5) Input Pulse Levels (-33) Output Load Including Scope (-5) Output Load Including Scope (-33) Input Output Timing Measurement Reference Levels Input-Pulse Rise Fall Times 3.0V 2.7V 50pF 1TTL Gate 25pF 1TTL Gate Input/Output: maximum minimum TEST CONDITIONS
WARNING: Negative undershoots below -0.3V while part battery-backed mode cause loss data.
Note Note Note Note Note Note Note Note Note Limits -40°C guaranteed design production tested. voltages referenced ground. outputs open. Specified with RESET VCC; MOT, AD0-AD7 VBACKUP open. Applies pins, pin, when each high-impedance state. internal pulldown. Measured with 32.768kHz crystal attached Measured with 50pF capacitance load. Guaranteed design. production tested.
with Constant-Voltage Trickle Charger DS12R885/DS12CR887/DS12R887
Typical Operating Characteristics
(VCC +3.3V, +25°C, unless otherwise noted.)
IBACKUP VBACKUP (DS12R885)
DS12R885 toc01
VBACKUP IBACKUP (DS12R885)
DS12R885 toc02
-15µA -30µA -45µA
SUPPLY CURRENT (nA)
VBACKUP VBACKUP
-60µA
IBACKUP TEMPERATURE (DS12R885)
SUPPLY CURRENT (nA) TEMPERATURE (°C) FREQUENCY (Hz) VBACKUP 3.0V
DS12R885 toc03
OSCILLATOR FREQUENCY SUPPLY VOLTAGE
32768.08 32768.06 32768.04 32768.02 32768.00 32767.98 32767.96 32767.94 32767.92 32767.90 SUPPLY
DS12R885 toc04
32768.10
with Constant-Voltage Trickle Charger DS12R885/DS12CR887/DS12R887
Functional Diagram
DS12R887/ DS12CR887 ONLY VBACKUP POWER CONTROL TRICKLE CHARGER DIVIDE DIVIDE DIVIDE
16:1 SQUAREWAVE GENERATOR
DS12R887/ DS12CR887 ONLY
DS12R885
RESET AD0-AD7 INTERFACE CLOCK/CALENDAR UPDATE LOGIC
GENERATOR
REGISTERS
CLOCK/CALENDAR ALARM REGISTERS BUFFERED CLOCK/ CALENDAR ALARM REGISTERS USER BYTES
RLCR
Description
EDIP NAME FUNCTION Motorola Intel Timing Selector. This selects types. When connected VCC, Motorola timing selected. When connected left disconnected, Intel timing selected. internal pulldown resistor. Connections Standard 32.768kHz Quartz Crystal. internal oscillator circuitry designed operation with crystal having 12.5pF specified load capacitance (CL). input oscillator optionally connected external 32.768kHz oscillator. output internal oscillator, floated external oscillator connected Multiplexed, Bidirectional Address/Data Bus. addresses presented during first portion cycle latched into DS12R885 falling edge Write data latched falling edge (Motorola timing) rising edge (Intel timing). read cycle, DS12R885 outputs data during latter portion high Motorola timing, high Intel timing). read cycle terminated returns high-impedance state transitions case Motorola timing transitions high case Intel timing.
4-11
4-11
AD0-
with Constant-Voltage Trickle Charger DS12R885/DS12CR887/DS12R887
Description (continued)
EDIP D5-D8, E1-E8, F5-F8 NAME FUNCTION
Ground Chip-Select Input. active-low chip-select signal must asserted cycle DS12R885 accessed. must kept active state during Motorola timing during Intel timing. cycles that take place without asserting latch addresses, access occurs. When below volts, DS12R885 inhibits access internally disabling input. This action protects data data during power outages. Address Strobe Input. positive-going address-strobe pulse serves demultiplex bus. falling edge causes address latched within DS12R885. next rising edge that occurs clears address regardless whether asserted. address strobe must immediately precede each write read access. write read performed with deasserted, another address strobe must performed prior read write access with asserted. Read/Write Input. modes operation. When connected Motorola timing, level that indicates whether current cycle read write. read cycle indicated with high level while high. write cycle indicated when during When connected Intel timing, signal active-low signal. this mode, operates similar fashion write-enable signal (WE) generic RAMs. Data latched rising edge signal. Connection. This should remain unconnected. EDIP, these pins missing design. Data Strobe Read Input. modes operation depending level pin. When connected VCC, Motorola timing selected. this mode, positive pulse during latter portion cycle called data strobe. During read cycles, signifies time that DS12R885 drive bidirectional bus. write cycles, trailing edge causes DS12R885 latch written data. When connected GND, Intel timing selected. identifies time period when DS12R885 drives with read data. this mode, operates similar fashion output-enable (OE) signal generic RAM.
20-22
N.C.
with Constant-Voltage Trickle Charger
Description (continued)
EDIP NAME FUNCTION Reset Input. RESET effect clock, calendar, RAM. power-up, RESET held time allow power supply stabilize. amount time that RESET held dependent application. However, RESET used power-up, time RESET should exceed 200ms ensure that internal timer that controls DS12R885 power-up timed out. When RESET above VPF, following occurs: Periodic interrupt-enable (PIE) cleared Alarm interrupt-enable (AIE) cleared Update-ended interrupt-enable (UIE) cleared Periodic-interrupt flag (PF) cleared Alarm-interrupt flag (AF) cleared Update-ended interrupt flag (UF) cleared Interrupt-request status flag (IRQF) cleared high-impedance state. device accessible until RESET returned high. Square-wave output-enable (SQWE) cleared typical application, RESET connected VCC. This connection allows DS12R885 power fail without affecting control registers. Interrupt Request Output. active-low output DS12R885 that used interrupt input processor. output remains long status causing interrupt present corresponding interrupt-enable set. processor program normally reads register clear pin. RESET also clears pending interrupts. When interrupt conditions present, level high-impedance state. Multiple interrupting devices connected bus, provided that they open drain. open-drain output requires external pullup resistor VCC. Connection Rechargeable Battery Super Cap. This provides trickle charging when greater than VBACKUP. Clear. active-low RCLR used clear (set logic bytes general-purpose RAM, does affect associated with RTC. clear RAM, RCLR must forced input logic during battery-backup mode when applied. RCLR function designed used through human interface (shorting ground manually switch) driven with external buffers. This internally pulled external pullup resistor this pin. Square-Wave Output. output signal from taps provided internal divider stages RTC. frequency changed programming Register shown Table signal turned using SQWE Register signal available when less than VPF. Power Primary Power Supply. When applied within normal limits, device fully accessible data written read. When below reads writes inhibited.
DS12R885/DS12CR887/DS12R887
RESET
VBACKUP
RCLR
A6-A8, B1-B8, C6-C8
with Constant-Voltage Trickle Charger DS12R885/DS12CR887/DS12R887
Detailed Description
DS12R885 drop-in replacement DS12885 RTC. device provides bytes realtime clock/calendar, alarm, control/status registers bytes nonvolatile, battery-backed static RAM. time-of-day alarm, three maskable interrupts with common interrupt output, programmable square-wave output available. DS12R885 also operates either 24-hour 12-hour format with AM/PM indicator. precision temperature-compensated circuit monitors status primary power-supply failure detected, device automatically switches backup supply. backup supply input supports either rechargeable battery super cap, includes integrated trickle charger. trickle charger always enabled. DS12R885 accessed through multiplexed address/data that supports Intel Motorola modes. DS12R887 surface-mount package using DS12R885 die, 32.768kHz crystal, rechargeable battery. device provides real-time clock/calendar, time-of-day alarm, three maskable interrupts with common interrupt output, programmable square wave, bytes nonvolatile, batterybacked static RAM. date month automatically adjusted months with fewer than days, including correction leap years. also operates either 24-hour 12-hour format with AM/PM indicator. precision temperature-compensated circuit monitors status VCC. primary power failure detected, device automatically switches backup battery included package. device accessed through multiplexed byte-wide interface, which supports both Intel Motorola modes. DS12CR887 EDIP integrates DS12R885 with crystal battery. charging circuit DS12R885 disabled. battery sufficient capacity power oscillator registers five years absence +25°C. DS12R887 includes crystal rechargeable battery. fully charged battery power oscillator registers (typical current +25°C) absence approximately days (10% capacity consumed) days (90% capacity consumed). When discharge depth capacity, battery recharged 1,000 times. discharge depth capacity, battery recharged times. Thus, life device would approximately years days 1,000 cycles) years days cycles). Charging time full capacity approximately days with applied. Please consult related application notes detailed information battery lifetime versus depth discharge, expected product lifetime based upon battery cycles.
Oscillator Circuit
DS12R885 uses external 32.768kHz crystal. oscillator circuit does require external resistors capacitors operate. Table specifies several crystal parameters external crystal. Figure shows functional schematic oscillator circuit. enable control register controls oscillator. Oscillator startup times highly dependent upon crystal characteristics, board leakage, layout. High excessive capacitive loads major contributors long startup times. circuit using crystal with recommended characteristics proper layout usually starts within second. external 32.768kHz oscillator also drive DS12R885. this configuration, connected external oscillator signal floated.
Table Crystal Specifications*
PARAMETER Nominal Frequency Series Resistance Load Capacitance SYMBOL 12.5 32.768 UNITS
*The crystal, traces, crystal input pins should isolated from generating signals. Refer Application Note Crystal Considerations Dallas Real-Time Clocks additional specifications.
COUNTDOWN CHAIN
REGISTERS
DS12R885
CRYSTAL
Figure Oscillator Circuit Showing Internal Bias Network
with Constant-Voltage Trickle Charger
Clock Accuracy
accuracy clock dependent upon accuracy crystal accuracy match between capacitive load oscillator circuit capacitive load which crystal trimmed. Additional error added crystal frequency drift caused temperature shifts. External circuit noise coupled into oscillator circuit result clock running fast. Figure shows typical board layout isolation crystal oscillator from noise. Refer Application Note Crystal Considerations with Dallas Real-Time Clocks more detailed information. DS12R887 DS12CR887 calibrated factory accuracy minute month +25°C during data-retention time period tOR.
LOCAL GROUND PLANE (LAYER CRYSTAL
DS12R885/DS12CR887/DS12R887
NOTE: AVOID ROUTING SIGNAL LINES CROSSHATCHED AREA (UPPER LEFT QUADRANT) PACKAGE UNLESS THERE GROUND PLANE BETWEEN SIGNAL LINE DEVICE PACKAGE.
Figure Layout Example
Power-Down/Power-Up Considerations
real-time clock continues operate regardless input level, alarm memory locations remain nonvolatile. VBACKUP must remain within minimum maximum limits when applied. When applied exceeds (power-fail trip point), device becomes accessible after tREC-if oscillator running oscillator countdown chain reset (Register This time allows system stablize after power applied. oscillator enabled, oscillator-enable enabled power-up, device becomes immediately accessible.
Before writing internal time, calendar, alarm registers, Register should written logic prevent updates from occurring while access being attempted. addition writing time, calendar, alarm registers selected format (binary BCD), data mode (DM) Register must appropriate logic level. time, calendar, alarm bytes must same data mode. Register should cleared after data mode been written allow update time calendar bytes. Once initialized, makes updates selected mode. data mode cannot changed without reinitializing data bytes. Tables show binary formats time, calendar, alarm locations. 24-12 cannot changed without reinitializing hour locations. When 12-hour format selected, higher-order hours byte represents when logic time, calendar, alarm bytes always accessible because they double-buffered. Once second seven bytes advanced second checked alarm condition. read time calendar data occurs during update, problem exists where seconds, minutes, hours, etc., correlate. probability reading incorrect time calendar data low. Several methods avoiding possible incorrect time calendar reads covered later this text.
Time, Calendar, Alarm Locations
time calendar information obtained reading appropriate register bytes. time, calendar, alarm initialized writing appropriate register bytes. contents time, calendar, alarm bytes either binary binary-coded decimal (BCD) format. day-of-week register increments midnight, incrementing from through day-of-week register used daylight savings function, value defined Sunday. date month automatically adjusted months with fewer than days, including correction leap years.
with Constant-Voltage Trickle Charger DS12R885/DS12CR887/DS12R887
three alarm bytes used ways. First, when alarm time written appropriate hours, minutes, seconds alarm locations, alarm interrupt initiated specified time each day, alarm-enable high. this mode, bits alarm registers corresponding time registers must always written (Table 2B). Writing bits alarm and/or time registers result undefined operation. second condition insert "don't care" state more three alarm bytes. don'tcare code hexadecimal value from most significant bits each byte don't-care condition when logic alarm generated each hour when don't-care bits hours byte. Similarly, alarm generated every minute with don't-care codes hours minute alarm bytes. don't-care codes three alarm bytes create interrupt every second. bytes directly written read, except following: Registers read-only. register read-only. seconds byte read-only.
Table Time, Calendar, Alarm Data Modes-BCD Mode
ADDRESS 0EH-7F IRQF AM/PM AM/PM Years SQWE Seconds Seconds Minutes Minutes Hours Hours Hours Hours Date Months Date Month Year 24/12 Seconds Seconds Minutes Minutes Hours Hours FUNCTION Seconds Seconds Alarm Minutes Minutes Alarm Hours Hours Alarm Date Month Year Control Control Control Control RANGE 00-59 00-59 00-59 00-59 1-12 +AM/PM 00-23 1-12 +AM/PM 00-23 01-07 01-31 01-12 00-99
Read/Write Bit. Note: Unless otherwise specified, state registers defined when power first applied. Except seconds register, bits time date registers written modified when clock updates. bits should always written except alarm mask bits.
with Constant-Voltage Trickle Charger DS12R885/DS12CR887/DS12R887
Table Time, Calendar, Alarm Data Modes-Binary Mode
ADDRESS AM/PM 0EH-7F IRQF Year SQWE Hours Date Month 24/12 Date Month Year Control Control Control Control AM/PM Hours Hours Hours Alarm Seconds Seconds Minutes Minutes Hours Hours FUNCTION Seconds Seconds Alarm Minutes Minutes Alarm RANGE 00-3B 00-3B 00-3B 00-3B 01-0C +AM/PM 00-17 01-0C +AM/PM 00-17 01-07 01-1F 01-0C 00-63
Read/Write Bit. Note: Unless otherwise specified, state registers defined when power first applied. Except seconds register, bits time date registers written modified when clock updates. bits should always written except alarm mask bits.
with Constant-Voltage Trickle Charger DS12R885/DS12CR887/DS12R887
Control Registers
DS12R885 four control registers that accessible times, even during update cycle.
Control Register
Update-In-Progress (UIP). This status flag that monitored. When update transfer occurs soon. When update transfer does occur least 244µs. time, calendar, alarm information fully available access when read-only affected RESET. Writing Register inhibits update transfer clears status bit. Bits DV2, DV1, DV0. These three bits used turn oscillator reset countdown chain. pattern only combination bits that turn oscillator allow keep time. pattern enables oscillator holds countdown chain reset. next update occurs 500ms after pattern written DV0, DV1, DV2.
Bits Rate Selector (RS3, RS2, RS1, RS0). These four rate-selection bits select taps 15-stage divider disable divider output. selected used generate output square wave (SQW pin) and/or periodic interrupt. user following: Enable interrupt with bit; Enable output with SQWE bit; Enable both same time same rate; Enable neither. Table lists periodic interrupt rates squarewave frequencies that chosen with bits. These four read/write bits affected RESET.
with Constant-Voltage Trickle Charger DS12R885/DS12CR887/DS12R887
Control Register
SQWE 24/12
SET. When update transfer functions normally advancing counts once second. When written update transfer inhibited, program initialize time calendar bytes without update occurring midst initializing. Read cycles executed similar manner. read/write affected RESET internal functions DS12R885. Periodic Interrupt Enable (PIE). read/write that allows periodic interrupt flag (PF) Register drive low. When periodic interrupts generated driving rate specified RS3-RS0 bits Register blocks output from being driven periodic interrupt, still periodic rate. modified internal DS12R885 functions, cleared RESET. Alarm Interrupt Enable (AIE). This read/write that, when permits alarm flag (AF) Register assert IRQ. alarm interrupt occurs each second that three time bytes equal three alarm bytes, including don't-care alarm code binary 11XXXXXX. does initiate signal when internal functions DS12R885 affect bit, cleared RESET. Update-Ended Interrupt Enable (UIE). This read/write that enables update-end flag (UF) Register assert IRQ. RESET going going high clears bit. modified internal DS12R885 functions, cleared RESET.
Square-Wave Enable (SQWE). When this square-wave signal frequency rate-selection bits RS3-RS0 driven pin. When SQWE held low. SQWE read/write cleared RESET. SQWE disabled, high impedance when below VPF. SQWE cleared RESET. Data Mode (DM). This indicates whether time calendar information binary format. program appropriate format read required. This modified internal functions RESET. signifies binary data, while specifies data. 24/12. 24/12 control establishes format hours byte. indicates 24-hour mode indicates 12-hour mode. This read/write affected internal functions RESET. Daylight Savings Enable (DSE). This read/write that enables daylight savings adjustments when first Sunday April, time increments from 1:59:59 3:00:00 last Sunday October when time first reaches 1:59:59 changes 1:00:00 When enabled, internal logic tests first/last Sunday condition midnight. when test occurs, daylight savings function does operate correctly. These adjustments occur when This affected internal functions RESET.
with Constant-Voltage Trickle Charger DS12R885/DS12CR887/DS12R887
Control Register
IRQF
Interrupt Request Flag (IRQF). This when following true: time IRQF driven low. This cleared reading Register with RESET. Periodic Interrupt Flag (PF). This readonly when edge detected selected divider chain. through bits establish periodic rate. independent state bit. When both signal active sets IRQF bit. This cleared reading Register with RESET.
Alarm Interrupt Flag (AF). indicates that current time matched alarm time. also goes appears IRQF bit. This cleared reading Register with RESET. Update-Ended Interrupt Flag (UF). This after each update cycle. When causes IRQF which asserts pin. This cleared reading Register with RESET. Bits Unused. These bits unused Register These bits always read cannot written.
Control Register
Valid Time (VRT). This indicates condition battery connected VBACKUP pin. This writeable should always when read. ever present, exhausted internal lithium energy source indicated both contents data data questionable. This unaffected RESET.
Bits Unused. remaining bits Register usable. They cannot written they always read
with Constant-Voltage Trickle Charger
Nonvolatile RAM)
general-purpose bytes dedicated special function within DS12R885. They used processor program battery-backed memory fully available during update cycle. second flag method used with fully enabled interrupts. When interrupt flag corresponding interrupt-enable also set, asserted low. asserted long least three interrupt sources flag enable bits set. IRQF Register whenever driven low. Determination that initiated interrupt accomplished reading Register logic (IRQF bit) indicates that more interrupts have been initiated DS12R885. reading Register clears active flag bits IRQF bit.
DS12R885/DS12CR887/DS12R887
Interrupts
DS12R885 includes three separate, fully automatic sources interrupt processor. alarm interrupt programmed occur rates from once second once day. periodic interrupt selected rates from 500ms 122µs. updateended interrupt used indicate program that update cycle complete. Each these independent interrupt conditions described greater detail other sections this text. processor program select which interrupts, any, used. Three bits Register enable interrupts. Writing logic interrupt-enable permits that interrupt initiated when event occurs. interrupt-enable prohibits from being asserted from that interrupt condition. interrupt flag already when interrupt enabled, immediately active level, although interrupt initiating event have occurred earlier. result, there cases where program should clear such earlier initiated interrupts before first enabling interrupts. When interrupt event occurs, relating flag logic Register These flag bits independent state corresponding enable Register flag used polling mode without enabling corresponding enable bits. interrupt flag status that software interrogate necessary. When flag set, indication given software that interrupt event occurred since flag last read; however, care should taken when using flag bits they cleared each time Register read. Double latching included with Register that bits that remain stable throughout read cycle. bits that (high) cleared when read, interrupts that pending during read cycle held until after cycle completed. One, two, three bits when reading Register Each used flag should examined when Register read ensure that interrupts lost.
Oscillator Control Bits
When DS12R887 DS12CR887 shipped from factory, internal oscillator turned off. This feature prevents lithium energy cell from being used until installed system. pattern bits Register turns oscillator enables countdown chain. pattern (DV2 turns oscillator holds countdown chain oscillator reset. other combinations bits keep oscillator off.
Square-Wave Output Selection
Thirteen divider taps made available 1of-16 multiplexer, shown functional diagram. square-wave periodic-interrupt generators share output multiplexer. RS0-RS3 bits Register establish output frequency multiplexer (see Table Once frequency selected, output turned under program control with square-wave enable bit, SQWE.
Periodic Interrupt Selection
periodic interrupt causes active state from once every 500ms once every 122µs. This function separate from alarm interrupt, which output from once second once day. periodic interrupt rate selected using same Register bits that select squarewave frequency (Table Changing Register bits affects square-wave frequency periodicinterrupt output. However, each function separate enable Register SQWE controls square-wave output. Similarly, Register enables periodic interrupt. periodic interrupt used with software counters measure inputs, create output intervals, await next needed software function.
with Constant-Voltage Trickle Charger
Table Periodic Interrupt Rate Square-Wave Output Frequency
SELECT BITS REGISTER PERIODIC INTERRUPT RATE None 3.90625ms 7.8125ms 122.070µs 244.141µs 488.281µs 976.5625µs 1.953125ms 3.90625ms 7.8125ms 15.625ms 31.25ms 62.5ms 125ms 250ms 500ms OUTPUT FREQUENCY None 256Hz 128Hz 8.192kHz 4.096kHz 2.048kHz 1.024kHz 512Hz 256Hz 128Hz 64Hz 32Hz 16Hz
Update Cycle
DS12R885 executes update cycle once second regardless Register When Register user copy double-buffered time, calendar, alarm bytes frozen does update time increments. However, time countdown chain continues update internal copy buffer. This feature
allows time maintain accuracy independent reading writing time, calendar, alarm buffers, also guarantees that time calendar information consistent. update cycle also compares each alarm byte with corresponding time byte issues alarm match don't-care code present three positions. There three methods that handle access that avoid possibility accessing inconsistent time calendar data. first method uses updateended interrupt. enabled, interrupt occurs after every update cycle that indicates over 999ms available read valid time date information. this interrupt used, IRQF Register should cleared before leaving interrupt routine. second method uses update-in-progress (UIP) Register determine update cycle progress. pulses once second. After goes high, update transfer occurs 244µs later. read bit, user least 244µs before time/calendar data changed. Therefore, user should avoid interrupt service routines that would cause time needed read valid time/calendar data exceed 244µs. third method uses periodic interrupt determine update cycle progress. Register high between setting Register (Figure Periodic interrupts that occur rate greater than tBUC allow valid time date information reached each occurrence periodic interrupt. reads should complete within 1(tPI/2 ensure that data read during update cycle.
DS12R885/DS12CR887/DS12R887
SECOND tBUC
tP1/2
tBUC DELAY TIME BEFORE UPDATE CYCLE 244µs
tP1/2
Figure Periodic Interrupt Timing
with Constant-Voltage Trickle Charger
Handling, Board Layout, Assembly
EDIP packages contain quartz tuningfork crystal. Pick-and-place equipment used, precautions should taken ensure that excessive shocks avoided. Ultrasonic cleaning should avoided prevent damage crystal. package reflowed long following conditions met: Preheating (below 160°C) within seconds. Maximum time above 150°C less than seconds. Maximum time above 170°C less than seconds. Maximum time above 200°C less than seconds. Maximum time above 220°C less than seconds. Peak temperature less than equal 230°C. Exposure reflow limited times maximum. Moisture-sensitive packages shipped from factory dry-packed. Handling instructions listed package label must followed prevent damage during reflow. Refer IPC/JEDEC J-STD-020B standard Moisture-Sensitive Device (MSD) classifications.
DS12R885/DS12CR887/DS12R887
Configurations
VIEW
N.C. RCLR VBACKUP N.C. N.C. N.C. N.C. N.C.
DS12R885
RESET N.C.
DS12CR887
RESET N.C.
(0.300")
EDIP (0.700")
with Constant-Voltage Trickle Charger DS12R885/DS12CR887/DS12R887
Configurations (continued)
VIEW (BUMP SIDE DOWN)
RESET N.C. RCLR
Thermal Information
PACKAGE THETA-JA (°C/W) THETA-JC (°C/W)
Chip Information
TRANSISTOR COUNT: 17,061 PROCESS: CMOS SUBSTRATE CONNECTED GROUND
DS12R887
Package Information
latest package outline information,
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2004 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.
DALLAS registered trademark Dallas Semiconductor Corporation.
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