Single +3.3V Power Supply Operation DESIGNATION DESCRIPTION 0.1µF

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Single +3.3V Power Supply Operation DESIGNATION DESCRIPTION 0.1µF

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19-2694; 07/04
Single +3.3V Power Supply Operation
DESIGNATION DESCRIPTION 0.1µF ±10% ceramic capacitors C13, C15, C16, (0402) C11, R10, R26, R27, R34, R35,
DESIGNATION DESCRIPTION 500k potentiometer JU1-JU8, JU10 J1-J7 MOSFET (SOT23)
transistors (SOT23)
0.047µF ±10% ceramic capacitor (0402) 0.01µF ±10% ceramic capacitors (0402) Open 10µF ±10% ceramic capacitor (0805) 10µF ±10% tantalum capacitor Case) VCSEL laser photodiode* LED, package inductor (1008CS) potentiometers
2-pin headers, 0.1in centers connectors, round contacts
TP1-TP11, TP20, Test points TP21 None None None MAX3740AETG (24QFN) MAX495ESA Shunts MAX3740A board MAX3740A data sheet
These components supplied populated VCSEL testing.
resistor (0402) 2.49k resistor (0402) resistors (0402) resistors (0402) resistor (0402)* 4.7k resistor (0402) 49.9 resistors (0402) Open potentiometer potentiometer
SUPPLIER Coilcraft Digi-Key
PHONE
843-444-2863 847-639-6400 218-681-6674 402-474-4800 415-964-6321
843-626-3123 847-639-1469 218-681-3380 402-474-4858 415-964-8165
Johnson Murata
Note: Please indicate that using MAX3701 when ordering from these suppliers.
_Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim/Dallas Direct! 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
PART TEMP. RANGE PACKAGE MAX3740AEVKIT -40°C +85°C
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output evaluation interfaced connector, which connected terminated oscilloscope. With slight modifications, evaluation also used evaluate MAX3740A operation with common-cathode VCSEL.
Allows Optical Electrical Evaluation
MAX3740A evaluation kit) assembled demonstration board that provides complete optical electrical evaluation MAX3740A VCSEL driver.
Fully Assembled Tested
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electrical configuration, automatic power control (APC) test circuit included emulate semiconductor laser with monitor photodiode. Monitor diode current provided transistor which controlled operational amplifier (U2). test circuit, consisting applies simulated monitor diode current MAX3740. ensure proper operation electrical configuration, evaluation board follows: Place shunts JU10 (see Adjustment Control Description section details). Remove shunts JU2. enable output connect TX_DISABLE placing shunt JU3. Note: When performing following resistance checks, autoranging DMMs forward bias onchip protection cause inaccurate measurements. avoid this, manually high range. Adjust R15, RBIASSET potentiometer, 1.7k resistance between (BIASSET) ground. Adjust RPWRSET potentiometer, resistance between (REF) (MD) JU2. Adjust R14, RPEAKSET potentiometer, resistance between TP10 (PEAKSET) ground, disable peaking. Adjust R16, potentiometer, resistance between (TC1) (TC2), disable temperature compensation. Adjust RMODSET potentiometer, resistance between (MODSET) ground. Apply differential input signal (250mVP-P 2200mVP-P) between connectors (IN+ IN-). Attach high-speed oscilloscope with input connector (OUT). Connect +3.3V supply between TP20 (VCC) TP21 (GND). Adjust power supply until voltage between TP11 ground +3.3V. Adjust (RPWRSET) until desired laser bias current achieved.
optical evaluation MAX3740A, configure evaluation follows: Place shunts JU2, JU6, JU7, JU10 (See Adjustment Control Description section details). Remove components Remove shunts from JU1, JU5. Install resistor connect anode VCSEL output. enable output connect TX_DISABLE placing shunt JU3. Connect common cathode VCSEL shown Figure Keep leads short reduce reflection. Note: When performing following resistance checks, autoranging DMMs forward bias onchip protection cause inaccurate measurements. avoid this, manually high range. Adjust R15, RBIASSET potentiometer, 1.7k resistance between (BIASSET) ground. Adjust RPWRSET potentiometer, resistance between (REF) (MD) JU2. Adjust R14, RPEAKSET potentiometer, resistance between TP10 (PEAKSET) ground, disable peaking. Adjust R16, potentiometer, resistance between (TC1) (TC2), disable temperature compensation.
BIAS
49.9
BIAS currents monitored (VPWRMON) (VBIASMON) using equations below:
PWRMON
PWRSET
BIAS
BIASMON
Note: voltage exceeds VPMTH (0.8V typ) exceeds VBMTH (0.8V typ), FAULT signal will asserted latched. Adjust until desired laser modulation current achieved.
IMOD
Adjust (RPEAKSET) until desired amount peaking achieved.
Signal Amplitude
PWRSET
COMPONENT JU10
NAME
FUNCTION
Fault Indicator COMP PHOTODIODE TX_DISABLE APCOPEN FAULT SQUELCH POWER VCCEXT RPWRSET RMODSET RPEAKSET RBIASSET
illuminated when fault condition occurred (refer Detailed Description section MAX3740 data sheet). Enables/disables circuit. Remove shunt enable circuit. Installing shunt connects photodiode VCSEL pin. Used when VCSEL installed. Enable/disable output currents. Install shunt enable output currents. Determines gain photodiode emulator. When open, gain 0.02A/A. When shunted, gain 0.12A/A. Installing shunt connects electrical output part emulation circuit. Installing shunt enables external fault-indicator circuit. Installing shunt enables squelch function. Installing shunt provides power part. Installing shunt provides power emulation fault-indicator circuits. Adjusts transmit optical power maintained loop. Adjusts laser modulation current. Adjusts peaking falling edge VCSEL. closed-loop configuration: adjusts maximum bias current available APC. open-loop configuration: adjusts bias level output. Adjusts temperature compensation modulation current.
PWRMON
Adjust (RMODSET) until desired optical amplitude achieved. Optical amplitude observed oscilloscope connected optical/electrical converter. VCSEL overshoot ringing improved appropriate selection C10, described Design Procedure section MAX3740 data sheet.
Note: voltage exceeds VPMTH (typical 0.8V) exceeds VBMTH (typical 0.8V), FAULT signal will asserted latched.
BIAS
BIASMON
Adjust RMODSET potentiometer, resistance between (MODSET) ground. Apply differential input signal (250mVP-P 2200mVP-P) between connectors (IN+ IN-). Attach VCSEL fiber connector optical/electrical converter. Connect +3.3V supply between TP20 (VCC) TP21 (GND). Adjust power supply until voltage between TP11 ground +3.3V. Adjust (RPWRSET) until desired average optical power achieved. BIAS currents monitored (VPWRMON) (VBIASMON) using equations below:
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POWER
TP11 NOISEGEN
VCC1 JU10 VCCEXT VCCEXT 0.1µF 0.01µF
BLM18HD102SN1
TP20
10µF PORTEST 0.1µF 0.1µF 10µF
TP21
OPEN
PHOTODIODE 0.01µF VCCEXT
CALIN+
0.1µF
PWRSET CALOUT+ 0.047µF
VCC1 0.01µF COMP FMMT491A
MAX495
0.1µF CALINJ4 CALOUTTP1 PWRMON
BIASMON
PWRMON
BIASMON
COMP
BLM18HD102SN1
2.49k
APCOPEN
TX_DISABLE
BIAS
BIASSET OPEN BIASSET VCC1
49.9 BLM18HD102SN1
INVCCEXT
0.1µF 0.1µF
INFAULT
MAX3740A
PEAKSET MODSET
OUT+ OUTGND
0.01µF
0.01µF 49.9 OPEN OPEN OPEN
0.1µF
VCC1 FAULT
SQUELCH
SQUELCH
FAULT FAULT
VCC1
FMMT491A
4.7k 0.01µF
VCSEL PHOTODIODE
500k
MODSET MODSET OPEN PEAKSET OPEN
TP10 PEAKSET OPEN
Figure MAX3740A Schematic Diagram
TX_DISABLE
BIASSET
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Figure MAX3740A Component Placement Guide Component Side
Figure MAX3740A Board Layout Solder Side
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Figure MAX3740A Board Layout Ground Plane
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600
2003 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.
Figure MAX3740A Board Layout Power Plane

Single +3.3V Power Supply Operation DESIGNATION DESCRIPTION 0.1µF

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