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DS26528 single-chip 8-port framer line interface unit (LIU) combinatio


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DS26528 Octal T1/E1/J1 Transceiver
DS26528 single-chip 8-port framer line interface unit (LIU) combination applications. Each port independently configurable, supporting both long-haul short-haul lines.
FEATURES
Eight Complete Long-Haul/ShortHaul Transceivers (LIU plus Framer) Independent Selections Each Transceiver Internal Software-Selectable Transmit- Receive-Side Termination 100W Twisted Pair, 110W Twisted Pair, 120W Twisted Pair, Coaxial Applications Crystal-Less Jitter Attenuators Selected Transmit Receive Path. Jitter Attenuator meets ETSI 12/13, G.736, G.742, G.823, AT&T 62411. External Master Clock Multiple 2.048MHz 1.544MHz T1/J1 operation. This Clock Internally Adapted Usage Host Mode. Receive Signal Level Indication from -2.5dB -36dB Mode -2.5dB -44dB Mode Approximate 2.5dB Increments Transmit Open Short Circuit Detection Accordance with G.775, ETSI 300233, T1.231 Transmit Synchronizer Flexible Signaling Extraction Insertion Using Either System Interface Microprocessor Port Alarm Detection Insertion Framing Formats SLC-96, Support G.704 CRC-4 Multiframe Conversion
APPLICATIONS
Routers Channel Service Units (CSUs) Data Service Units (DSUs) Muxes Switches Channel Banks T1/E1 Test Equipment
FUNCTIONAL DIAGRAM
T1/E1/J1 NETWORK
DS26528
T1/J1/E1 Transceiver
BACKPLANE
Features continued Section
ORDERING INFORMATION
PART DS26528 TEMP RANGE -40°C +85°C PIN-PACKAGE TE-CSBGA
Note: Some revisions this device incorporate deviations from published specifications known errata. Multiple revisions device simultaneously available through various sales channels. information about device errata, click here: www.maxim-ic.com/errata.
REV: 072304
DS26528 Octal T1/E1/J1 Transceiver
TABLE CONTENTS
DETAILED DESCRIPTION.8 FEATURE HIGHLIGHTS
GENERAL LINE INTERFACE CLOCK SYNTHESIZER JITTER ATTENUATOR FRAMER/FORMATTER SYSTEM INTERFACE HDLC CONTROLLERS TEST DIAGNOSTICS CONTROL PORT
APPLICATIONS SPECIFICATIONS COMPLIANCE ACRONYMS GLOSSARY MAJOR OPERATING MODES.15 BLOCK DIAGRAMS.15 DESCRIPTIONS
FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION
PROCESSOR INTERFACE CLOCK STRUCTURE RESETS POWER-DOWN MODES INITIALIZATION CONFIGURATION GLOBAL RESOURCES. PER-PORT RESOURCES DEVICE INTERRUPTS SYSTEM BACKPLANE INTERFACE
Elastic Stores Multiplexer. H.100 (CT-Bus) Compatibility Transmit Receive Channel Blocking Registers. Transmit Fractional Support (Gapped Clock Mode) Receive Fractional Support (Gapped Clock Mode) Framing Framing. Transmit Synchronizer Signaling Datalink Datalink Maintenance Alarms Automatic Alarm Generation Error Count Registers Monitoring Function. Transmit Per-Channel Idle Code Insertion. Receive Per-Channel Idle Code Insertion. Per-Channel Loopback G.706 Intermediate CRC-4 Updating Mode Only) Programmable In-Band Loop Code Generator.
9.8.1 9.8.2 9.8.3 9.8.4 9.8.5 9.8.6
FRAMERS
9.9.1 9.9.2 9.9.3 9.9.4 9.9.5 9.9.6 9.9.7 9.9.8 9.9.9 9.9.10 9.9.11 9.9.12 9.9.13 9.9.14 9.9.15
DS26528 Octal T1/E1/J1 Transceiver 9.9.16 Framer Payload Loopbacks
9.10
9.10.1 9.10.2 9.10.3 9.10.4
HDLC CONTROLLERS
Receive HDLC Controller. Transmit HDLC Controller. FIFO Information HDLC Transmit Example
9.11
9.11.1 9.11.2 9.11.3 9.11.4 9.11.5
LINE INTERFACE UNITS (LIU)
Operation. Transmitter Receiver Jitter Attenuator. Loopbacks
9.12
9.12.1 9.12.2
ERROR RATE TEST FUNCTION (BERT)
BERT Repetitive Pattern BERT Error Counter.
DEVICE REGISTERS
REGISTER LISTINGS
Global Register List. Framer Register List. BERT Register List 10.1.1 10.1.2 10.1.3
10.1
10.2
10.2.1 10.2.2 10.2.3 10.2.4
REGISTER MAPS
Global Register Framer Register Register BERT Register
10.3 10.4
10.4.1 10.4.2
GLOBAL REGISTER DEFINITIONS FRAMER REGISTER DEFINITIONS
Receive Register Definitions Transmit Register Definitions
10.5 10.6
REGISTER DEFINITIONS BERT REGISTER DEFINITIONS RECEIVER FUNCTIONAL TIMING DIAGRAMS TRANSMITTER FUNCTIONAL TIMING DIAGRAMS RECEIVER FUNCTIONAL TIMING DIAGRAMS TRANSMITTER FUNCTIONAL TIMING DIAGRAMS LINE INTERFACE CHARACTERISTICS MICROPROCESSOR CHARACTERISTICS JTAG INTERFACE TIMING SYSTEM CLOCK CHARACTERISTICS INSTRUCTION REGISTER JTAG CODES TEST REGISTERS BOUNDARY SCAN REGISTER BYPASS REGISTER IDENTIFICATION REGISTER
FUNCTIONAL TIMING .224
11.1 11.2 11.3 11.4
OPERATING PARAMETERS.239 TIMING CHARACTERISTICS .241
12.1 13.1 13.2 13.3
JTAG-BOUNDARY SCAN TEST ACCESS PORT.252
14.1 14.2 14.3 14.4 14.5 14.6
DOCUMENT REVISION HISTORY .261 PACKAGE INFORMATION.262
DS26528 Octal T1/E1/J1 Transceiver
LIST FIGURES
Figure 7-1. Block Diagram Figure 7-2. Detailed Block Diagram. Figure 8-1. Pinout. Figure 9-1. Backplane Clock Generation. Figure 9-2. Device Interrupt Information Flow Diagram. Figure 9-3. Multiplexer Equivalent Circuit-4.096MHz Figure 9-4. Multiplexer Equivalent Circuit-8.192MHz Figure 9-5. Multiplexer Equivalent Circuit-16.384MHz Figure 9-6. RSYNC Input H.100 (Ct-Bus) Mode. Figure 9-7. TSSYNCIO(Input Mode) Input H.100 (CT-Bus) Mode Figure 9-8. CRC-4 Recalculate Method. Figure 9-9. Receive HDLC Example. Figure 9-10. HDLC Message Transmit Example. Figure 9-11. Basic Balanced Network Connections Figure 9-12. Recommended Supply Decoupling. Figure 9-13. T1/J1 Transmit Pulse Templates Figure 9-14. Transmit Pulse Templates Figure 9-15. Typical Monitor Application Figure 9-16. Jitter Attenuation Figure 9-17. Analog Loopback. Figure 9-18. Local Loopback Figure 9-19. Remote Loopback Figure 9-20. Dual Loopback Figure 10-1. Register Memory DS26528. Figure 11-1. Receive Side Timing Figure 11-2. Receive Side Timing Figure 11-3. Receive Side Boundary Timing (elastic store disabled) Figure 11-4. Receive Side 1.544MHz Boundary Timing (e-store enabled). Figure 11-5. Receive Side 2.048MHz Boundary Timing (e-store enabled). Figure 11-6. Receive Side Interleave Operation, BYTE Mode Figure 11-7. Receive Side Interleave Operation, FRAME Mode Figure 11-8. Transmit Side Timing Figure 11-9. Transmit Side Timing Figure 11-10. Transmit Side Boundary Timing (e-store disabled) Figure 11-11. Transmit Side 1.544MHz Boundary Timing (e-store enabled) Figure 11-12. Transmit Side 2.048MHz Boundary Timing (e-store enabled) Figure 11-13. Transmit Side Interleave Operation, BYTE Mode Figure 11-14. Transmit Interleave Operation, FRAME Mode Figure 11-15. Receive Side Timing Figure 11-16. Receive Side Boundary Timing (elastic store disabled) Figure 11-17. Receive Side 1.544MHz Boundary Timing (e-store enabled) Figure 11-18. Receive Side 2.048MHz Boundary Timing (e-store enabled) Figure 11-19. Transmit Side Timing Figure 11-20. Transmit Side Boundary Timing (elastic store disabled) Figure 11-21. Transmit Side 1.544MHz Boundary Timing (e-store enabled) Figure 11-22. Transmit Side 2.048MHz Boundary Timing (e-store enabled) Figure 11-23. G.802 Timing Figure 13-1. Intel Read Timing (BTS Figure 13-2. Intel Write Timing (BTS Figure 13-3. Motorola Read Timing (BTS Figure 13-4. Motorola Write Timing (BTS Figure 13-5. Receive Framer Timing-Backplane Mode). Figure 13-6. Receive Side Timing, Elastic Store Enabled Mode) Figure 13-7. Receive Framer Timing-Line Side Figure 13-8. Transmit Formatter Timing-Backplane Figure 13-9. Transmit Formatter Timing, Elastic Store Enabled
DS26528 Octal T1/E1/J1 Transceiver Figure 13-10. Transmit Formatter Timing-Line Side Figure 13-11. JTAG Interface Timing Diagram. Figure 14-1. JTAG Functional Block Diagram Figure 14-2. Controller State Diagram
DS26528 Octal T1/E1/J1 Transceiver
LIST TABLES
Table 4-1. T1-Related Telecommunications Specifications Table 4-2. E1-Related Telecommunications Specifications Table 8-1. Detailed Descriptions Table 9-1. Reset Functions. Table 9-2. Registers Related Elastic Store. Table 9-3. Elastic Store Delay After Initialization. Table 9-4. Registers related Multiplexer. Table 9-5. RSER Output Definitions. Table 9-6. RSIG Output Definitions Table 9-7. TSER Input Definitions Table 9-8. TSIG Input Definitions Table 9-9. RSYNC Input Definitions Table 9-10. Framing Mode. Table 9-11. Framing Mode Table 9-12. SLC-96 Framing Table 9-13. FAS/NFAS Framing Table 9-14. Registers Related Setting Framer Table 9-15. Registers Related Transmit Synchronizer. Table 9-16. Registers Related Signaling Table 9-17. Registers Related SLC96 Table 9-18. Registers Related Transmit BOC. Table 9-19. Registers Related Receive BOC. Table 9-20. Registers Related Transmit FDL. Table 9-21. Registers Related Receive FDL. Table 9-22. Registers Related Maintenance Alarms Table 9-23. Alarm Criteria Table 9-24. Line Code Violation Counting Options Table 9-25. Line Code Violation Counting Options Table 9-26. Path Code Violation Counting Arrangements Table 9-27. Frames Sync Counting Arrangements Table 9-28. Registers Related Monitoring Table 9-29. Registers Related In-Band Loop Code Generator Table 9-30. Registers Related In-Band Loop Code Detection Table 9-31. Register Related Framer Payload Loopbacks Table 9-32. Registers Related Control DS26528 LIU. Table 9-33. Telecommunications Specification Compliance DS26528 Transmitters Table 9-34. Transformer Specifications. Table 9-35. T1.231, G.775, ETSI Loss Criteria Specifications. Table 9-36. Jitter Attenuator Standards Compliance. Table 10-1. Register Address Ranges Hex). Table 10-2. Global Register List Table 10-3. Framer Register List Table 10-4. Register List Table 10-5. BERT Register List Table 10-6. Global Register Map. Table 10-7. Framer Register Table 10-8. Register Table 10-9. BERT Register Table 10-10. Backplane Reference Clock Select Table 10-11. Master Clock Input Selection. Table 10-12. Device Codes this Product Family Table 10-13. Register Table 10-14. Transmit Load Impedance Selection. Table 10-15. Transmit Pulse Shape Selection Table 10-16. Receive Level Indication Table 10-17. Receive Impedance Selection.
DS26528 Octal T1/E1/J1 Transceiver Table 10-18. Receiver Sensitivity Selection with Monitor Mode Disabled. Table 10-19. Receiver Sensitivity Selection with Monitor Mode Enabled Table 10-20. BERT Register Table 10-21. BERT Pattern Select Table 10-22. BERT Error Insertion Rate. Table 10-23. BERT Repetitive Pattern Length Select Table 12-1. Transmitter Characteristics Table 12-2. Reciever Characteristics. Table 13-1. Characteristics -Microprocessor Timing. Table 13-2. Receiver Characteristics Table 13-3. Transmit Characteristics. Table 14-1. Instruction Codes IEEE 1149.1 Architecture. Table 14-2. Code Structure. Table 14-3. Boundary Scan Control Bits
DS26528 Octal T1/E1/J1 Transceiver
DETAILED DESCRIPTION
DS26528 8-port monolithic device featuring independent transceivers that software configured operation. Each transceiver composed line interface unit, framer, HDLC controller, elastic store, backplane interface. DS26528 controlled 8-bit parallel port. Internal impedance matching provided both transmit receive paths, reducing external component count. composed transmit interface, receive interface, jitter attenuator. transmit interface responsible generating necessary waveshapes driving network providing correct source impedance depending type media used. waveform generation includes DSX-1 line build-outs well line build-outs 0dB, -7.5dB, -15dB, -22.5dB. waveform generation includes G.703 waveshapes both coax 120W twisted cables. receive interface provides network termination recovers clock data from network. receive sensitivity adjusts automatically incoming signal level programmed -43dB -12dB applications -15dB -36dB applications. jitter attenuator removes phase jitter from transmitted received signal. crystal-less jitter attenuator requires only clock rate, multiple thereof, both applications, placed either transmit receive data paths. transmit side, clock, data, frame-sync signals provided framer backplane interface section. framer inserts appropriate synchronization framing patterns, alarm information, calculates inserts codes, provides B8ZS/HDB3 (zero code suppression) line coding. receiveside framer decodes AMI, B8ZS, HDB3 line coding, synchronizes data stream, reports alarm information, counts framing/coding/CRC errors, provides clock, data, frame-sync signals backplane interface section. Both transmit receive paths have access HDLC controller. HDLC controller transmits receives data framer block. HDLC controller assigned time slot, portion time slot (T1) bits (E1). Each controller 64-byte FIFOs, reducing amount processor overhead required manage flow data. backplane interface provides versatile method sending receiving data from host system. Elastic stores provide method interfacing asynchronous systems, converting from T1/E1 network 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz, 64kHz system backplane. elastic stores also manage slip conditions (asynchronous interface). interleave option (IBO) provided allow eight transceivers (single DS26528) share high-speed backplane. DS26528 also contains internal clock adapter useful creation synchronous, high-frequency backplane timing source. parallel port provides access configuration status DS26528's features. Diagnostic capabilities include loopbacks, PRBS pattern generation/detection, 16-bit loop-up loop-down code generation detection.
DS26528 Octal T1/E1/J1 Transceiver
FEATURE HIGHLIGHTS
General
17mm 17mm, 256-pin TE-CSBGA (1.00mm pitch) 3.3V supply with tolerant inputs outputs IEEE 1149.1 JTAG boundary scan Development support will include evaluation kit, driver source code, reference designs
Line Interface
Requires single master clock (MCLK) both operation. Master clock 1.544MHz, 2.048MHz, 3.088MHz, 4.096MHz, 6.276MHz, 8.192MHz, 12.552MHz, 16.384MHz. Fully software configurable Short- long-haul applications Ranges include -43dB, -30dB, 20dB, -12dB -36dB, 30dB, 20dB, -15dB Receiver signal level indication from -2.5dB -36dB mode -2.5dB -44dB mode 2.5dB increments Internal receive termination option 75±, 100W, 110W, 120W lines Monitor application gain settings 14dB, 20dB, 26dB, 32dB G.703 receive synchronization signal mode Flexible transmit waveform generation DSX-1 line build-outs line build-outs 0dB, -7.5dB, -15dB, -22.5dB waveforms include G.703 waveshapes both coax 120W twisted cables Analog loss signal detection generation independent loopbacks Alternating ones zeros generation Receiver power-down Transmitter power-down Transmitter short-circuit limiter with current limit exceeded indication Transmit open-circuit-detected indication
Clock Synthesizer
Output frequencies include 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz Derived from user selected recovered receive clock
Jitter Attenuator
32-bit 128-bit crystal-less jitter attenuator Requires only 1.544MHz 2.048MHz master clock multiple thereof, both operation placed either receive transmit path disabled Limit trip indication
Framer/Formatter
Fully independent transmit receive functionality Full receive transmit path transparency framing formats T1.403, expanded SLC-96 support (TR-TSY-008). framing CRC-4 multiframe G.704/G.706, G.732 multiframe Transmit side synchronizer Transmit midpath recalculate (E1) Detailed alarm status reporting with optional interrupt support
DS26528 Octal T1/E1/J1 Transceiver Large path line error counters T1:- BPV, CRC6, framing errors BPV, CRC4, E-bit, frame alignment errors Timed manual update modes Idle Code Generation per-channel basis both transmit receive paths User defined Digital Milliwatt ANSI T1.403-1999 Support G.965 V5.2 link detect Ability monitor channel both transmit receive paths In-Band Repeating Pattern Generators Detectors Three independent Generators Detectors Patterns from bits bits Length Oriented Code (BOC) support Flexible signaling support Software hardware based Interrupt generated change signaling data Optional receive signaling freeze loss frame, loss signal, frame slip Hardware pins provided indicate Loss Frame (LOF), Loss Signal (LOS), Loss Transmit Clock (LOTC), signaling freeze condition. Automatic generation specifications RAI-CI AIS-CI support Expanded access bits Option extend carrier loss criteria period Japanese support Ability calculate check CRC6 according Japanese standard Ability generate Yellow Alarm according Japanese standard conversion
System Interface
Independent two-frame receive transmit elastic stores Independent control clocking Controlled slip capability with status Minimum delay mode supported Flexible backplane supports rates from 1.544MHz 16.384MHz Supports CEPT (E1) conversion Programmable output clocks fractional applications Interleaving operation Hardware signaling capability Receive signaling reinsertion backplane multiframe sync Availability signaling separate data stream Signaling freezing Ability pass F-bit position through elastic stores 2.048MHz backplane mode User-selectable synthesized clock output
HDLC Controllers
HDLC controller engine each T1/E1 port Independent 64-byte buffers with interrupt support Access FDL, single channel Compatible with polled interrupt driven environments
DS26528 Octal T1/E1/J1 Transceiver
Test Diagnostics
IEEE 1149.1 Support Per-channel programmable on-chip error-rate testing (BERT) Pseudorandom patterns including QRSS User-defined repetitive patterns Daly pattern Error insertion single continuous Total-bit errored-bit counts Payload error insertion Error insertion payload portion frame transmit path Errors inserted over entire frame selected channels Insertion options include continuous absolute number with selectable insertion rates F-bit corruption line testing Loopbacks (remote, local, analog, per-channel loopback)
Control Port
8-bit parallel control port Intel Motorola nonmultiplexed support Flexible status registers support polled, interrupt, hybrid program environments Software reset supported Hardware reset Software access device silicon revision
APPLICATIONS
DS26528 useful applications such Routers Channel Service Units (CSUs) Data Service Units (DSUs) Muxes Switches Channel Banks T1/E1 Test Equipment
DS26528 Octal T1/E1/J1 Transceiver
SPECIFICATIONS COMPLIANCE
DS26528 meets latest relevant telecommunications specifications. Table provides specifications relevant sections that applicable DS26528.
Table 4-1. T1-Related Telecommunications Specifications
ANSI T1.102- Digital Hierarchy Electrical Interface. Coding. B8ZS Substitution Definition. Electrical Interface. Line rate 32ppm; Pulse Amplitude between peak; Power Level between 12.6 17.9dbm; pulse mask provided that comply. DSX-1 cross connects return loss greater than -26dB. DSX-1 cable restricted feet. This specification also provides cable characteristics DSX-Cross Connect cable cables 1000 feet. ANSI T1.231- Digital Hierarchy- Layer Service Performance Monitoring Error Definition; Excessive Zero Definition; description; definition. ANSI T1.403- Network Customer Installation Interface- Electrical Interface Description Measurement Characteristics-100W. Pulse shape template compliance according T1.102; Power level 12.4 19.7dbm when ones transmitted. Customer Interface (CI) specified 0dB, -7.5dB -15dB. Line rate +/-32 ppm. Pulse Amplitude 3.6V. generation unframed ones defined. total cable attenuation defined 22dB. DS26528 will function with -36dB cable loss. Note that pulse template defined T1.403 T1.102 different specifically Times .61, -.27, .77. DS26528 complaint both templates. 62411 This specification tighter jitter tolerance transfer characteristics than other specifications. jitter transfer characteristics tighter than G.736 Jitter Tolerance tighter G.823. (ANSI) "Digital Hierarchy Electrical Interfaces" (ANSI) "Digital Hierarchy Formats Specification" (ANSI) "Digital Hierarchy Layer In-Service Digital Transmission Performance Monitoring" (ANSI) "Network Customer Installation Interfaces Electrical Interface" (AT&T) "Requirements Interfacing Digital Terminal Equipment Services Employing Extended Super frame Format" (AT&T) "High Capacity Digital Service Channel Interface Specification" (TTC) "Frame Structures Primary Secondary Hierarchical Digital Interfaces" (TTC) "ISDN Primary Rate User-Network Interface Layer Specification"
DS26528 Octal T1/E1/J1 Transceiver
Table 4-2. E1-Related Telecommunications Specifications
ITUT G.703 Physical/Electrical Characteristics G.703 Hierarchical Digital Interfaces Defines 2048Kbit/s rate-2048 ±50ppm; transmission media coax 120W twisted pair; peak peak space voltage ±0.237V; Nominal pulse width Return loss 102Hz 6dB, 3072 8dB, 2048 3072 14dB Nominal peak voltage 2.37V coax twisted pair. pulse template defined G.703. ITUT G.736 Characteristics Synchronous Digital Multiplex Equipment operating 2048Kbit/s peak peak jitter 2048Kbit/s less than 0.05 100Hz. Jitter transfer between 2.048 synchronization signal 2.048 transmission signal provided. ITUT G.742 Second Order Digital Multiplex Equipment Operating 8448Kbit/s DS26528 jitter attenuator complaint with Jitter transfer curve sinusoidal jitter input. ITUT G.772 This specification provides method using receiver transceiver monitor rest transmitter/receiver combinations. ITUT G.775 detection criterion defined. ITUT G.823 control jitter wander within digital networks which based 2.048Kbit/s hierarchy G.823 provides jitter amplitude tolerance different frequencies, specifically 20Hz, 2.4kHz, 18kHz, 100kHz. ETSI This specification provides signal criteria mode 62411 This specification tighter jitter tolerance transfer characteristics than other specifications. jitter transfer characteristics tighter than G.736 Jitter Tolerance tighter then G.823. (ITU) "Synchronous Frame Structures used 1544, 6312, 2048, 8488 44736Kbit/s Hierarchical Levels" (ITU) "Frame Alignment Cyclic Redundancy Check (CRC) Procedures Relating Basic Frame Structures Defined Recommendation G.704" (ITU) "Characteristics primary Multiplex Equipment Operating 2048Kbit/s" (ITU) Characteristics synchronous digital multiplex equipment operating 2048Kbit/s" (ITU) "Loss Signal (LOS) Alarm Indication Signal (AIS) Defect Detection Clearance Criteria" (ITU) "The Control Jitter Wander Within Digital Networks Which Based 2048Kbit/s Hierarchy" (ITU) "Primary Rate User-Network Interface Layer Specification" (ITU) "Error Performance Measuring Equipment Operating Primary Rate Above" (ITU) "In-service code violation monitors digital systems" (ETSI) "Integrated Services Digital Network (ISDN); Primary rate User-Network Interface (UNI); Part Layer specification" (ETSI) "Transmission multiplexing; Physical/electrical characteristics hierarchical digital interfaces equipment using 2048Kbit/s-based plesiochronous synchronous digital hierarchies" (ETSI) "Integrated Services Digital Network (ISDN); Access digital section ISDN primary rate" (ETSI) "Integrated Services Digital Network (ISDN); Attachment requirements terminal equipment connect ISDN using ISDN primary rate access" (ETSI) "Business Telecommunications (BT); Open Network Provision (ONP) technical requirements; 2048 Kbit/s digital unstructured leased lines (D2048U) attachment requirements terminal equipment interface" (ETSI) "Business Telecommunications (BTC); 2048 Kbit/s digital structured leased lines (D2048S); Attachment requirements terminal equipment interface" (ITU) "Synchronous Frame Structures used 1544, 6312, 2048, 8488 44736Kbit/s Hierarchical Levels" (ITU) "Frame Alignment Cyclic Redundancy Check (CRC) Procedures Relating Basic Frame Structures Defined Recommendation G.704"
DS26528 Octal T1/E1/J1 Transceiver
ACRONYMS GLOSSARY
This data sheet assumes particular nomenclature operating environment. each 125ms frame, there 8-bit channels plus framing bit. assumed that framing sent first followed channel each channel made bits, which numbered MSB, transmitted first. LSB, transmitted last. Locked refers clock signals that phase- frequency-locked derived from common clock (i.e., 1.544MHz clock locked 2.048MHz clock they share same 8kHz component).
TIME SLOT NUMBERING SCHEMES
Channel Phone Channel
DS26528 Octal T1/E1/J1 Transceiver
MAJOR OPERATING MODES
DS26528 major modes operation: mode mode. mode operation each configured LTRCR register. mode operation each framer configured TMMR register. operation special case operating mode.
BLOCK DIAGRAMS
Figure 7-1. Block Diagram
DS26528
RTIP RRING TTIP TRING LINE INTERFACE UNIT FRAMER FRAMER FRAMER FRAMER FRAMER FRAMER FRAMER T1/E1 FRAMER HDLC BERT ELASTIC STORES INTERFACE INTERFACE INTERFACE INTERFACE INTERFACE INTERFACE INTERFACE BACKPLANE INTERFACE RECEIVE BACKPLANE SIGNALS TRANSMIT BACKPLANE SIGNALS HARDWARE ALARM INDICATORS MICRO PROCESSOR INTERFACE CLOCK GENERATION
JTAG PORT
CONTROLLER PORT
TEST PORT
CLOCK ADAPTER
DS26528 Octal T1/E1/J1 Transceiver
Figure 7-2. Detailed Block Diagram
TRANSCEIVER
BERT FRAMER:
HDLC
Signaling/ Channel Blocking
TTIPn ANALOG OUTPUTS TRINGn
TRANSMIT JITTER ATTENUATOR
Waveform Shaper/Line Driver
B8ZS/ HDB3 Encode
TCLKn TSERn
TRANSMIT ENABLE
System
BACKPLANE INTERFACE
Elastic Store
TSYNCn
TSYSCLK RSYSCLK
RTIPn ANALOG INPUTS RRINGn
RECEIVE
Clock/Data Recovery
FRAMER:
System B8ZS/ HDB3 Decode Elastic Store
RSYNCn RSERn RCLKn Signaling/ Channel Blocking
DS26528
BERT
HDLC
MICROPROCESSOR INTERFACE
JTAG PORT
RESET BLOCK
PRE-SCALER
MCLK
BACKPLANE CLOCK GENERATOR
TSSYNCIO BPCLK REFCLK
A[12:0] D[7:0] RDB/DSB WRB/RWB INTB
JTDO JTDI JTMS JTCLK JTRST
RESETB
DS26528 Octal T1/E1/J1 Transceiver
DESCRIPTIONS
Functional Description Table 8-1. Detailed Descriptions
NAME
ANALOG TRANSMIT
TTIP1 TTIP2 TTIP3 TTIP4 TTIP5 TTIP6 TTIP7 TTIP8 TRING1 TRING2 TRING3 TRING4 TRING5 TRING6 TRING7 TRING8 TXENABLE ANALOG RECEIVE RTIP1 RTIP2 RTIP3 RTIP4 RTIP5 RTIP6 RTIP7 RTIP8 RRING1 RRING2 RRING3 RRING4 RRING5 RRING6 RRING7 RRING8 TRANSMIT FRAMER TSER1 TSER2 TSER3 TSER4 TSER5 TSER6 TSER7 TSER8 TCLK1 TCLK2 TCLK3 TCLK4 TCLK5 TCLK6 TCLK7 TCLK8 T15, J15, H15, A15, R14,T14 J14, G14, A14, Transmit Bipolar Transceiver These pins differential line driver outputs. These pins High-Z Analog Output High-Z TXENABLE TTIP/TRING will High-Z. Note that TXENABLE low, register settings control TTIP/TRING ignored output High-Z. differential outputs TTIPn TRINGn provide internal matched impedance 120W, 100W, 110W. user option turning internal termination. Transmit Bipolar Ring Transceiver These pins differential line driver ring outputs. These pins High-Z Analog Output High-Z TXENABLE TTIP/TRING will High-Z. Note that TXENABLE low, register settings control TTIP/TRING ignored output High-Z. differential outputs TTIPn TRINGn provide internal matched impedance 75W, 120W, 100W, 110W. user option turning internal termination. Transmit Enable. this pulled low, transmitter outputs (TTIP TRING) High-Z. register settings tri-state control TTIP/TRING ignored TXEnable low. TXEnable high, particular driver tri-stated register settings.
TYPE
DESCRIPTION
Analog Input
Receive Bipolar Transceiver differential inputs RTIPn RRINGn provide internal matched impedance 75W, 120W, 100W, 110W. user option turning internal termination receive impedance sensitivity monitor Register.
Analog Input
Receive Bipolar Ring Transceiver differential inputs RTIPn RRINGn provide internal matched impedance 75W, 120W, 100W, 110W. user option turning internal termination receive impedance sensitivity monitor register.
Transmit Serial Data. Sampled falling edge TCLK when transmit side elastic store disabled. Sampled falling edge TSYSCLK when transmit side elastic store enabled. Mode, data multiple framers used High Speed Multiplexed Scheme. This described Section 9.8.2. table there presents combination framer data each streams. TSYSCLK used reference when invoked. Table 9-7.
Transmit Clock. 1.544 2.048MHz primary clock. Used clock data through transmit side transceiver. TSER data sampled falling edge TCLK. TCLK used sample TSER when elastic store enabled used.
DS26528 Octal T1/E1/J1 Transceiver
NAME TYPE DESCRIPTION
Transmit System Clock. 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz clock. Only used when transmit-side elastic store function enabled. Should tied applications that transmit side elastic store. This common clock that used transmitters. clock 4.096MHz, 8.912MHz, 16.384MHz when mode used.
TSYSCLK
TSYNC1 TSYNC2 TSYNC3 TSYNC4 TSYNC5 TSYNC6 TSYNC7 TSYNC8
Transmit Synchronization. pulse this establishes either frame multiframe boundaries transmit side. This signal also programmed output either frame multiframe pulse. this output pulses frame boundaries, also output double-wide pulses signaling frames mode. operation this signal synchronous with TCLK. Transmit System Synchronization Only used when transmit-side elastic store enabled. pulse this will establish either frame multiframe boundaries transmit side. Note that elastic store enabled, frame multiframe boundary will established transmitters. Should tied applications that transmit side elastic store. operation this signal synchronous with TSYSCLK.
TSSYNCIO
Transmit System Synchronization Out. configured output, 8kHz pulse synchronous BPCLK will generated. This pulse combination with Bpclk used Master. BPCLK sourced RSYSCLK TSYSCLK TSSYNCIO source RSYNC TSSYNCIO DS26528 RSYNC TSSYNC other Dallas Semiconductor Parts.
TSIG1 TSIG2 TSIG3 TSIG4 TSIG5 TSIG6 TSIG7 TSIG8 TCHBLK/CLK1 TCHBLK/CLK2 TCHBLK/CLK3 TCHBLK/CLK4 TCHBLK/CLK5 TCHBLK/CLK6 TCHBLK/CLK7 TCHBLK/CLK8 RECEIVE FRAMER RSER1 RSER2 RSER3 RSER4 RSER5 RSER6 RSER7 RSER8 RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7 RCLK8
Transmit Signaling. When enabled, this input samples signaling bits insertion into outgoing data stream. Sampled falling edge TCLK when transmit-side elastic store disabled. Sampled falling edge TSYSCLK when transmit-side elastic store enabled. mode, TSIG streams 16.384MHz. Table 9-8.
Transmit Channel Block Transmit Channel Block Clock. dual function pin. TCHBLK user programmable output that forced high during channels. Synchronous with TCLK when transmit side elastic store disabled. Synchronous with TSYSCLK when transmit side elastic store enabled. Useful blocking clocks serial UART LAPD controller applications where channels used such Fractional Fractional KBPS (H0), KBPS ISDN-PRI. Also useful locating individual channels drop-and-insert applications, external per-channel loopback, per-channel conditioning. TCHCLK. TCHCLK 192kHz (T1) 256kHz (E1) clock that pulses high during each channel. also programmed output gated transmit clock controlled TCHBLK. synchronous with TCLK when transmit-side elastic store disabled. synchronous with TSYSCLK when transmit-side elastic store enabled. Useful parallel-to-serial conversion channel data.
Received Serial Data. Received serial data. Updated rising edges RCLK when receive side elastic store disabled. Updated rising edges RSYSCLK when receive side elastic store enabled. When mode used, RSER pins output data multiple framers. RSER data synchronous RSYSCLK. This described Section 9.8.2 Table 9-5.
Receive Clock. 1.544MHz (T1) 2.048MHz (E1) clock that used clock data through receive-side framer. This clock recovered from signal RTIP RRING. RSER data output rising edge RCLK. RCLK used output RSER when elastic store enabled used. When elastic store enabled used RSER clocked RSYSCLK.
DS26528 Octal T1/E1/J1 Transceiver
NAME TYPE DESCRIPTION
Receive System Clock. 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz 16.384MHz receive backplane clock. Only used when receive side elastic store function enabled. Should tied applications that receive side elastic store. Multiple 2.048MHz expected when Mode used. Note that RSYSCLK used transceivers.
RSYSCLK
RSYNC1 RSYNC2 RSYNC3 RSYNC4 RSYNC5 RSYNC6 RSYNC7 RSYNC8 RM/RFSYNC1 RM/RFSYNC2 RM/RFSYNC3 RM/RFSYNC4 RM/RFSYNC5 RM/RFSYNC6 RM/RFSYNC7 RM/RFSYNC8 RSIG1 RSIG2 RSIG3 RSIG4 RSIG5 RSIG6 RSIG7 RSIG8 AL/RSIGF/ FLOS1 AL/RSIGF/ FLOS2 AL/RSIGF/ FLOS3 AL/RSIGF/ FLOS4 AL/RSIGF/ FLOS5 AL/RSIGF/ FLOS6 AL/RSIGF/ FLOS7 AL/RSIGF/ FLOS8 RLF/LTC1 RLF/LTC2 RLF/LTC3 RLF/LTC4 RLF/LTC5 RLF/LTC6 RLF/LTC7 RLF/LTC8
Receive Synchronization. receive side elastic store enabled, then this signal used input frame multiframe boundary pulse output frame boundaries then RSYNC programmed output double-wide pulses signaling frames mode. Mode RSYNC used indicate CRC4 Multiframe. DS26528 also facility accept H.100 compatible synchronization signal.
Receive Multiframe Frame Synchronization. dual function indicate Frame Multiframe Synchronization. RFSYNC extracted pulse, RCLK wide that identifies frame boundaries. RMSYNC extracted pulse, RCLK wide (elastic store disabled) RSYSCLK wide (elastic store enabled), which identifies multiframe boundaries. When receive elastic store enabled, RMSYNC signal indicates multiframe sync system (backplane) side Elastic Store. mode, will indicate either CRC4 multiframe determined RSMS2 control RIOCR.1 Register.
Receive Signaling. Outputs signaling bits format. Updated rising edges RCLK when receive side elastic store disabled. Updated rising edges RSYSCLK when receive side elastic store enabled. Table 9-6.
Analog Loss Receive Signaling Freeze Framer LOS. Analog reflects (Loss Signal) detected front Framer detection corresponding framer; same pins reflect Receive Signaling Freeze indications. This selection made settings Global Transceiver Control Register. Framer selected, this programmed toggle high when framer detects loss signal condition, when signaling data frozen either automatic manual intervention. indication used alert downstream equipment condition.
Receive Loss Frame Loss Transmit Clock. This also programmed either toggle high when synchronizer searching frame multiframe toggle high TCLK been toggled approximately three clock periods.
DS26528 Octal T1/E1/J1 Transceiver
NAME
RCHBLK/CLK1 RCHBLK/CLK2 RCHBLK/CLK3 RCHBLK/CLK4 RCHBLK/CLK5 RCHBLK/CLK6 RCHBLK/CLK7 RCHBLK/CLK8
TYPE
DESCRIPTION
Receive Channel Block Receive Channel Block Clock. configured output either RCHBLK RCHCLK. RCHBLK user-programmable output that forced high during channels. Synchronous with RCLK when receive side elastic store disabled. Synchronous with RSYSCLK when receive-side elastic store enabled. Useful blocking clocks serial UART LAPD controller applications where channels used such fractional service, 384kbps service, 768kbps, ISDN-PRI. Also useful locating individual channels drop-and-insert applications, external per-channel loopback, per-channel conditioning. RCHCLK (T1) 256kHz (E1) clock that pulses high during each channel. Synchronous with RCLK when receive-side elastic store disabled. Synchronous with RSYSCLK when receive-side elastic store enabled. Useful parallel-to-serial conversion channel data. Backplane Clock. Programmable clock output that 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz. reference this clock RCLK from LIU, 1.544MHz 2.048MHz frequency derived from MCLK external reference clock. This allows clock reference from external source T1J1E1 recovered clock MCLK oscillator.
BPCLK
MICROPROCESSOR INTERFACE
Address12 Address0. This selects specific register DS26528 during read/write access. LSB.
Data7 Data0. This 8-bit, bidirectional data used read/write access DS26528 information control registers. LSB.
Chip Select Bar. This active-low signal used qualify register read/write accesses. RDDSB signals qualified with CSB. Read Data Strobe Bar. This active-low signal along with qualifies read access DS26528 registers. DS26528 drives data with contents addressed register while both low. Write Bar/Read-Write Bar. This active-low signal along with qualifies write access DS26528 registers. Data D[7/0] written into addressed register rising edge while low. Interrupt Bar. This active-low, open-drain output asserted when unmasked interrupt event detected. INTB will deasserted when interrupts have been acknowledged serviced. Extensive Mask bits provided global level, framer, LIU, BERT level. Type Select. high select Motorola timing, select Intel timing. This controls function RDDSB, pins.
RDB/DSB
WRB/RWB
INTB SYSTEM INTERFACE
MCLK
Master Clock. This independent free-running clock whose input multiple 2.048MHz ±50ppm 1.544MHz ±50ppm. clock selection available bits MPS0 MPS1 FREQSEL. Multiple 2.048MHz internally adapted 1.544MHz. Multiple 1.544MHz adapted 2.048MHz. Note that TCLK 2.048MHz 1.544MHz T1/J1 operation. Table 10-11.
DS26528 Octal T1/E1/J1 Transceiver
NAME
RESETB
TYPE
DESCRIPTION
Reset Bar. Active-low reset. This input forces complete DS26528 reset. This includes reset registers, framers, LIUs. Reference Clock Input/Output Input: 2.048MHz 1.544MHz clock input. This clock used generate backplane clock. This allows users synchronize system backplane with reference clock. other options backplane clock reference LIU-received clocks MCLK. Output: This signal also used output 1.544MHz 2.048MHz reference clock. This allows multiple DS26528 share same reference generation backplane clock. Hence, system consisting multiple DS26528s, master others slave using same Reference Clock.
REFCLKIO
TEST DIGIOEN Pullup Digital Enable. When this JTRST pulled Digital pins placed high-impedance state. this High Digital pins operate normally. This connected normal operation. JTAG Reset. JTRST used asynchronously reset test access port controller. After power JTRST must toggled from high. This action will device into JTAG DEVICE mode. Pulling JTRST restores normal device operation. JTRST pulled HIGH internally 10kW resistor operation. boundary scan used, this should held low. JTAG Mode Select. This sampled rising edge JTCLK used place test access port into various defined IEEE 1149.1 states. This pull resistor. JTAG Clock. This signal used shift data into JTDI rising edge JTDO falling edge. JTAG Data Test instructions data clocked into this rising edge JTCLK. This 10kW pullup resistor. JTAG Data Out. Test instructions data clocked this falling edge JTCLK. used, this should left unconnected.
JTRST
Pullup
JTMS
Pullup Pullup High-Z
JTCLK JTDI JTDO POWER SUPPLIES ATVDD
ATVSS
ARVDD
ARVSS
B16, G16, K16, B15, G15, K15, D16, E16, M16, D15, E15, M15, G5-G12, H10, H12, H13, J10,
3.3V Analog Transmit Power Supply. These inputs used transmit sections DS26528.
Analog Transmit VSS. These pins used transmit analog VSS.
Analog Receive Power Supply. This inputs used Receive sections DS26528.
Analog Receive VSS. These pins used analog receivers.
ACVDD ACVSS DVDD DVDDIO DVSS DVSSIO
Analog Clock Conversion VDD. This inputs used clock conversion unit DS26528. Analog Clock VSS. This used clock converter analog VSS. 3.3V Power Supply Digital Framers 3.3V Power Supply I/Os Digital Ground Framers Digital Ground I/Os
DS26528 Octal T1/E1/J1 Transceiver
Figure 8-1. Pinout
TTIP1
TTIP1
TRING1
RSYNC1
TCHBLK1
TSIG2
REFCLKIO
TSIG7
RSIG7
TSYNC8
TRING8
TTIP8
TTIP8
ATVDD
ATVSS
TRING1
TSYNC1
RCHBLK2
RSYNC2
MCLK
TSYNC7
RSER7
TCLK8
TRING8
ATVSS
ATVDD
RTIP1
RRING1 ALRSIGF1 RMRFSYNC1
TCLK1
RMRFSYNC2 TCHBLK2
RSYNC7
RCHBLK7
TSIG8
ALRSIGF8
RRING8
RTIP8
ARVDD
ARVSS
RLFLTC1
RSIG1
TSIG1
RSER2
TCLK2
DIGIOEN
TCHBLK7
RMRFSYNC7
TSER8
RSYNC8
RLFLTC8
ARVSS
ARVDD
ARVDD
ARVSS
RLFLTC2
RCHBLK1
RSER1
RSIG2
TSER2
BPCLK
TCLK7
TCHBLK8
RMFSYC8
RCLK8
RLFLTC7
ARVSS
ARVDD
RTIP2
RRING2 ALRSIGF2
RCLK1
JTCLK
TSER1
TSYNC2
TSER7
RSER8
RSIG8
RCLK7
ALRSIGF7
RRING7
RTIP7
ATVDD
ATVSS
TRING2
RCLK2
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
RCHBLK8
TRING7
ATVSS
ATVDD
TTIP2
TTIP2
TRING2
JTDI
DVDDIO
DVDDIO
ACVDD
DVDD
DVDD
DVDDIO
DVDDIO
DVSS
DVSS
TRING7
TTIP7
TTIP7
TTIP3
TTIP3
TRING3
JTDO
DVSSIO
DVSSIO
ACVSS
DVSS
DVSS
DVSSIO
DVSSIO
RESETB
RCLK6
TRING6
TTIP6
TTIP6
ATVDD
ATVSS
TRING3
JTMS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
RCLK5
TRING6
ATVSS
ATVDD
RTIP3
RRING3 ALRSIGF3
RCLK3
JTRST
RCHBLK3
TCHBLK3
TCLK4
TCLK5
TSER6
RSYSCLK
TXENABLE
ALRSIGF6
RRING6
RTIP6
ARVDD
ARVSS
RLFLTC3
RCLK4
RSIG3
TSYNC3
TSYNC4
RDB/
TSER5
RSER5
RSER6
RLFLTC6
ARVSS
ARVDD
ARVDD
ARVSS
RLFLTC4
RSER3
RSYNC3
RSER4
TSER4
TSYNC5
TCLK6
RMRFSYNC6 TSSYNCIO
RLFLTC5
ARVSS
ARVDD
RTIP4
RRING4 ALRSIGF4 RMRFSYNC3
TCLK3
RMRFSYNC4 TCHBLK4
TCHBLK5 RMRFSYNC5
TCHBLK6
RSYNC6
TSYSCLK
ALRSIGF5
RRING5
RTIP5
ATVDD
ATVSS
TRING4
TSER3
RSIG4
TSIG4
WRB/
INTB
RSYNC5
RSIG5
TSIG6
RSIG6
TRING5
ATVSS
ATVDD
TTIP4
TTIP4
TRING4
TSIG3
RCHBLK4
RSYNC4
TSIG5
RCHBLK5
TSYNC6
RCHBLK6
TRING5
TTIP5
TTIP5
DS26528 Octal T1/E1/J1 Transceiver
FUNCTIONAL DESCRIPTION
Processor Interface
Microprocessor control DS26528 accomplished through hardware pins microprocessor port. 8-bit parallel data configured Intel Motorola modes operation with Type Select (BTS) pin. When logic timing Intel mode, shown Figure 13-1 Figure 13-2. When logic timing Motorola mode, shown Figure 13-3 Figure 13-4. address space mapped through address lines, A0-A12. Multiplexed Mode supported processor interface. Chip Select (CSB) must brought logic level gain read write access microprocessor port. With Intel timing selected, Read (RDB) Write (WRB) pins used indicate read write operations latch data data through interface. With Motorola timing selected, Read-Write (RWB) used indicate read write operations while Data Strobe (DSB) used latch data through interface. interrupt output (INTB) open-drain output that will assert logic-low level upon number software maskable interrupt conditions. This normally connected microprocessor interrupt input. device bulk write mode that allows microprocessor write eight internal transceivers with each write cycle. setting (GTCR1.2), each port write cycle will write eight framers, LIUs, BERTs same time. must cleared before normal write operation resumed. This function useful device initialization. register shown Figure 10-1.
Clock Structure
user should provide system clock MCLK input 2.048MHz, 1.544MHz, multiple frequencies. meet many specifications, MCLK source should have ±50ppm accuracy.
9.2.1.1 Backplane Clock Generation
DS26528 provides facility provision BPCLK 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz (see Figure 9-1). Global Transceiver Control Register (GTCCR used control backplane clock generation. This register also used program REFCLKIO input output. REFCLKIO output sourcing MCLKT1 MCLKE1 shown Figure 9-1. This backplane clock frame pulse (TSSYNCIO) used DS26528 other equipped devices "IBO Master." Hence DS26528 will provide Sync Pulse 4,8,16MHz clock. This used link layer devices frames connected Bus.
DS26528 Octal T1/E1/J1 Transceiver
Figure 9-1. Backplane Clock Generation
BPREFSEL3:0
BPCLK1:0 RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7 RCLK8 MCLK Scaler MCLKT1 MCLKE1 REFCLKIO BFREQSEL
Clock Multiplexor
BPCLK
TSSYNCIO REFCLKIO
reference clock Backplane Clock generator External Master Clock. pre-scaler used generate Frequency External Reference Clock REFCLKIO. This allows multiple DS26528 Backplane Clock from common reference. Internal recovered RCLKs Clock Generator used generate BPCLK 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz IBO. MCLK RCLKs used reference, REFCLKIO used provide 2.048MHz 1.544MHz clock external use.
DS26528 Octal T1/E1/J1 Transceiver
Resets Power-Down Modes
hardware reset issued forcing RESETB logic low. RESETB input resets framers, LIUs, BERTs. Note that registers cleared reset condition. register space must reinitialized appropriate values after hardware software reset occurred. This includes writing reserved locations 00h.
Table 9-1. Reset Functions
RESET FUNCTION Hardware Device Reset Hardware JTAG Reset Global Framer BERT Resets Global Resets Framer Receive Reset Framer Transmit Reset HDLC Receive Reset HDLC Transmit Reset Elastic Store Receive Reset Elastic Store Transmit Reset Oriented Code Receive Reset Loop Code Integration Reset LOCATION RESETB JTRST GFSRR.0 GLSRR.0 RMMR.1 TMMR.1 RHC.6 THC1.5 RESCR.2 TESCR.2 T1RBOCC.7 T1RDNCD1, T1RUPCD1 T1RSCD1 COMMENTS Transition logic level resets DS26528. Resets JTAG test port. Writing these bits resets associated Framer BERT (transmit receive). Writing these bits resets associated Line Interface Unit. Writing this resets Receive Framer. Writing this resets Transmit Framer. Writing this resets Receive HDLC controller. Writing this resets Transmit HDLC controller. Writing this resets Receive Elastic Store. Writing this resets Transmit Elastic Store. Writing this resets Receive controller. Writing these registers resets programmable in-band code integration period. Writing this register resets programmable in-band code integration period.
Spare Code Integration Reset
DS26528 several features included reduce power consumption. individual transmitters powered down setting TPDE maintenance control register (LMCR). Note that powering down transmit results High-Z state corresponding TTIP TRING pins, reduced operating current. RPDE LMCR register used power down receiver. (Transmit Enable) LMCR register used disable TTIP TRING outputs place them high-impedance mode, while keeping active state (powered up). This useful equipment protection switching applications.
DS26528 Octal T1/E1/J1 Transceiver
Initialization Configuration
EXAMPLE DEVICE INITIALIZATION SEQUENCE: STEP Reset device pulling RESETB low, applying power device, using software reset bits outlined Section 9.3. Clear reset bits. Allow time reset recovery. STEP Check Device register STEP Write GTCCR register correctly configure system clocks. supplying 1.544MHz MCLK follows this write with least 300ns delay order allow clock system properly adjust. STEP Write entire remainder register space each port with 00h, including reserved register locations. STEP Choose T1/J1 operation framers configuring T1/E1 TMMR RMMR registers each framer. FRM_EN TMMR RMMR registers. using Software Transmit Signaling mode, program E1TAF E1TNAF registers required. Configure framer Transmit Control Registers (TCR1 TCR4). Configure framer Receive Control Registers (RCR1 RCR3). Configure other framer features appropriate. STEP Choose T1/J1 operation LIUs configuring T1J1E1S LTRCR register. Configure Line Build each LIU. Configure other features appropriate. (Transmit Enable) turn TTIP TRING outputs. STEP Configure Elastic Stores, HDLC Controller, BERT needed. STEP INIT_DONE TMMR RMMR registers each framer.
Global Resources
eight framers share common microprocessor port. ports share common MCLK, there common software configurable BPCLK output. Global registers located 0F0h-0FFh include Global resets, global interrupt status, interrupt masking, clock configuration, Device registers. Global Register Definitions Table 10-6. common JTAG controller used ports.
Per-Port Resources
Each port associated Framer, LIU, BERT, Jitter Attenuator, Transmit/Receive HDLC controller. Each per-port functions register space.
DS26528 Octal T1/E1/J1 Transceiver
Device Interrupts
Figure diagrams flow interrupt conditions from their source status bits through multiple levels information registers mask bits interrupt pin. When interrupt occurs, host read Global Interrupt Information registers GFISR, GLISR, GBISR quickly identify which eight transceivers is(are) causing interrupt(s). host then read specific transceiver's Interrupt Information registers (TIIR, RIIR) Latched Status Registers (LLSR, BLSR) further identify source interrupt(s). TIIR RIIR source, host will then read Transmit Latched Status Receive Latched Status Registers source interrupt. Interrupt Information Register bits real-time bits that will clear once appropriate interrupt been serviced cleared, long additional, un-masked interrupt condition present associated status register. Latched Status bits must cleared host writing location interrupt condition that been serviced. Latched Status bits that have been masked Interrupt Mask registers will masked from Interrupt Information Registers. Interrupt Mask register bits prevent individual Latched Status conditions from generating interrupt, they prevent Latched Status bits from being set. Therefore, when servicing interrupts, user should Latched Status with associated Interrupt Mask order exclude bits which user wished prevent interrupt service. This architecture allows application host periodically poll latched status bits non-interrupt conditions, while using only registers.
DS26528 Octal T1/E1/J1 Transceiver
Figure 9-2. Device Interrupt Information Flow Diagram
Receive Remote Alarm Indication Clear Receive Alarm Condition Clear Receive Loss Signal Clear Receive Loss Frame Clear Receive Remote Alarm Indication Receive Alarm Condition Receive Loss Signal Receive Loss Frame Receive Signal Ones Receive Signal Zeros Receive CRC4 Multiframe Receive Align Frame Loss Receive Clear Loss Receive Clear Spare Code Detected Condition Clear Loop Down Code Clear Link Clear Loop Code Clear Receive Distant Alarm Clear Loss Receive Loss Receive Spare Code Detect Loop Down Detect Link Detect Loop Detect Receive Distant Alarm Detect Receive Elastic Store Full Receive Elastic Store Empty Receive Elastic Store Slip Receive Signaling Change State (Enable RSCSE1-4) Second Timer Timer Receive Multiframe Receive FIFO Overrun Receive HDLC Opening Byte Receive Packet Receive Packet Start Receive Packet High Watermark Receive FIFO Empty Receive RAI-CI Receive AIS-CI Receive SLC-96 Alignment Receive Register Full Receive Clear Receive Transmit Elastic Store Full Transmit Elastic Store Empty Transmit Elastic Store Slip Transmit SLC96 Multiframe Transmit Pulse Density Violation Transmit Align Frame Transmit Multiframe Loss Transmit Clock Clear Loss Transmit Clock Transmit Register Empty Transmit FIFO Underrun Transmit Message Transmit FIFO Below Watermark Transmit FIFO Full Loss Frame Loss Frame Synchronization Jitter Attenuator Limit Trip Clear Open Circuit Detect Clear Short Circuit Detect Clear Loss Signal Detect Clear Jitter Attenuator Limit Trip Open Circuit Detect Short Circuit Detect Loss Signal Detect BERT Error Detected BERT Counter Overflow BERT Error Counter Overflow BERT Receive Ones BERT Receive Zeros BERT Receive Loss Synchronization BERT Synchronization
Drawing Legend:
RLS1 RIM1
Interrupt Status Registers Interrupt Mask Registers
Register Name
RIM2
Register Name
RLS3
RIM3
RLS4
RIM4
RLS5
RIM5
RLS7 RIM7
RIIR
Framers
TLS1
TLS2 TIM2
LSIMR
LLSR
BLSR
BSIM
GFISR1
GFIMR
TIM1
BERTs
GBISR1
GBIMR
Interrupt
TIIR
LIUs
GTCR1.0
GLISR1
TLS3
TIM3
GLIMR
DS26528 Octal T1/E1/J1 Transceiver
System Backplane Interface
DS26528 provides versatile Backplane interface that configured Transmit Receive Frame Elastic Stores Mapping channels into 2.048MHz backplane mode multiple framers share backplane signals Transmit receive channel blocking capability Fractional T1/E1/J1 support Hardware-based (through backplane interface) processor-based signaling Flexible backplane clock providing frequencies 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz Backplane clock frame pulse (TSSYNIO) generator
9.8.1
Elastic Stores
DS26528 contains dual, two-frame elastic stores each framer; receive direction, transmit direction. Both elastic stores fully independent. transmit receive side elastic stores enabled/disabled independently each other. Also, transmit receive elastic store interface either 1.544MHz 2.048/4.096/8.192/16.384MHz backplane without regard backplane rate other elastic store. Since DS26528 common TSYSCLK RSYSCLK eight ports, backplane signals each direction must synchronous ports which elastic stores enabled. However, transmit receive signals required synchronous each other. TIOCR RIOCR settings should identical ports which elastic stores enabled. elastic stores have main purposes. First, they used rate conversion. When DS26528 mode, elastic stores rate convert data stream 2.048MHz backplane. mode elastic store rate convert data stream 1.544MHz backplane. Secondly, they used absorb differences frequency phase between data stream asynchronous (i.e., locked) backplane clock (which 1.544MHz 2.048MHz). this mode, elastic stores will manage rate difference perform controlled slips, deleting repeating frames data order manage difference between network backplane. elastic store enabled while mode, then either CRC4 multiframe boundaries will indicated RMSYNC output controlled RSMS2 control (RIOCR.1). user selects apply 1.544MHz clock RSYSCLK pin, then RBCS registers will determine which channels received data stream will deleted. this mode F-bit location inserted into RSER data one. Also, 1.544MHz applications, RCHBLK output will active Channels through other words, RCBR4 active). two-frame elastic buffer either fills empties, controlled slip will occur. buffer empties, then full frame data will repeated RSER RLS4.5 RLS4.6 bits will one. buffer fills, then full frame data will deleted RLS4.5 RLS4.7 bits will one. elastic stores also used multiplex data streams into higher backplane rates. This Interleave Option (IBO), which discussed Section 9.8.2. registers related Elastic Stores shown following table.
Table 9-2. Registers Related Elastic Store
REGISTER Receive Configuration Register (RIOCR) Receive Elastic Store Control Register (RESCR) Receive Latched Status Register RLS4) Receive Interrupt Mask Register 4(RIM4) Transmit Elastic Store Control Register (TESCR) Transmit Latched Status Register (TLS1) Transmit Interrupt Mask Register TIM1) FRAMER ADDRESSES FUNCTION Sync Clock Selection Receiver Receive Elastic Store Control Receive Elastic Store Empty full status Receive Interrupt Mask Elastic Store Transmit elastic control such minimum mode Transmit Elastic Store Latched Status Transmit Elastic Store Interrupt Mask
Note: addresses shown above Framer Addresses Framers calculated using following: Framer (Framer address 200hex), where Framers
DS26528 Octal T1/E1/J1 Transceiver
9.8.1.1 Elastic Stores Initialization
There elastic store initializations that used improve performance certain applications, Elastic Store Reset Elastic Store Align. Both these involve manipulation elastic store's read write pointers useful primarily synchronous applications (RSYSCLK/TSYSCLK locked RCLK/TCLK respectively). elastic store reset used minimize delay through elastic store. elastic store align used 'center' read/write pointers extent possible.
Table 9-3. Elastic Store Delay After Initialization
INITIALIZATION Receive Elastic Store Reset Transmit Elastic Store Reset Receive Elastic Store Align Transmit Elastic Store Align
RSZS RSZS
REGISTER RESCR.2 TESCR.2 RESCR.3 TESCR.3
DELAY bytes Delay Frame bytes bytes Delay Frame bytes Frame Delay Frames Frame Delay Frames
9.8.1.2 Minimum Delay Mode
Elastic store minimum delay mode used when elastic store's system clock locked network clock (i.e., RCLK locked RSYSCLK receive side TCLK locked TSYSCLK transmit side). RESCR.1 enable receive elastic store minimum delay mode. When enabled elastic stores will forced maximum depth bits instead normal two-frame depth. This feature useful primarily applications that interface 2.048MHz bus. Certain restrictions apply when minimum delay mode used. addition restriction mentioned above, RSYNC must configured output when receive elastic store minimum delay mode TSYNC must configured output when transmit minimum delay mode enabled. this mode SYNC outputs always frame mode (multiframe outputs allowed). typical application RSYSCLK TSYSCLK locked RCLK, RSYNC (frame output mode) connected TSSYNCIO (frame input mode). slip zone select (RSZS RESCR.4) must `1'. slip contention logic framer disabled (since slips cannot occur). power-up after RSYSCLK TSYSCLK signals have locked their respective network clock signals, elastic store reset (RESCR.2) should toggled from zero insure proper operation
9.8.1.3 Additional Receive Elastic Store Information
receive side elastic store enabled, then user must provide either 1.544MHz 2.048MHz clock RSYSCLK pin. higher rate system clock applications, Section 9.8.2. user option either providing frame/multiframe sync RSYNC having RSYNC provide pulse frame/multiframe boundaries. Signaling Reinsertion enabled, robbed-bit signaling data realigned multiframe sync input RSYNC. Otherwise, multiframe sync input RSYNC treated simple frame boundary elastic store. framer will always indicate frame boundaries network side elastic store RFSYNC output whether elastic store enabled not. Multiframe boundaries will always indicated RMSYNC output. elastic store enabled, then RMSYNC will output multiframe boundary backplane side elastic store. When device receiving backplane enabled 2.048MHz operation, RMSYNC signal will output multiframe boundaries delayed through elastic store. When device receiving backplane enabled 1.544MHz operation, RMSYNC signal will output multiframe boundaries delayed through elastic store. user selects apply 2.048MHz clock RSYSCLK pin, then they backplane blank channel select registers (RBCS1-4) determine which channels will have data output RSER forced ones.
9.8.1.4 Receiving Mapped Channels from 2.048MHz Backplane
Setting TSCLKM TIOCR.4 will enable transmit elastic store operate with 2.048MHz backplane time slots frame). this mode user chose which backplane channels TSER will mapped into data stream programming Transmit Blank Channel Select registers (TBCS1-4). logic associated location will force transmit elastic store ignore backplane data that channel. Typically
DS26528 Octal T1/E1/J1 Transceiver user will want program eight channels ignored. default (power-up) configuration will ignore channels that first backplane channels mapped into transmit data stream. example, user desired transmit data from 2.048MHz backplane channels 2-16 18-26, TBCS registers should programmed follows: TBCS1 ignore backplane channel TBCS2 TBCS3 ignore backplane channel TBCS4 ignore backplane channels 27-32
9.8.1.5
Mapping Channels Onto 2.048MHz Backplane
Setting RSCLKM RIOCR.4 will enable receive elastic store operate with 2.048MHz backplane time slots/frame). this mode user chose which backplane channels RSER receive data programming Receive Blank Channel Select registers (RBCS1-4). logic associated location will force RSER high that backplane channel. Typically user will want program eight channels 'blanked.' default (power-up) configuration will blank channels that channels mapped into first channels 2.048MHz backplane. user chooses blank channel (TS0) setting RBCS1.0 then F-bit will passed into RSER. example, RBCS1 RBCS2 RBCS3 RBCS4 Then RSER: channel (MSB) F-bit channel (bits 1-7) ones channels 2-16 channels 1-15 channel ones channels 18-26 channels 16-24 channels 27-32 ones Note that when more sequential channels chosen blanked, receive slip zone select should zero. blank channels distributed (such then RSZS one, which provide lower occurrence slips certain applications. two-frame elastic buffer either fills empties, controlled slip will occur. buffer empties, then full frame data will repeated RSER RLS4.5 RLS4.6 bits will one. buffer fills, then full frame data will deleted RLS4.5 RLS4.7 bits will
9.8.1.6 Receiving Mapped Transmit Channels from 1.544MHz Backplane
user TSCLKM TIOCR.4 enable transmit elastic store operate with 1.544MHz backplane channels frame F-bit). this mode user chose which time slots will have ones data inserted programming Transmit Blank Channel Select registers (E1TBCS1-4). logic associated location will cause elastic store force ones outgoing data that channel. Typically user will want program eight channels 'blanked'. default (power-up) configuration will blank channels that first channels mapped from channels 1.544MHz backplane.
9.8.1.7 Mapping Channels onto 1.544MHz Backplane
user RSCLKM RIOCR.4 enable receive elastic store operate with 1.544MHz backplane channels frame F-bit). this mode user chose which time slots will ignored (not transmitted onto RSER) programming Receive Blank Channel Select registers (RBCS1-4). logic associated location will cause elastic store ignore incoming data that channel. Typically, user will want program eight channels 'ignored'. default (power-up) configuration will ignore channels
DS26528 Octal T1/E1/J1 Transceiver that first channels mapped into channels 1.544MHz backplane. this mode F-bit location RSER always example, user wants ignore time slots (channel (channel 17), RBCS registers would programmed follows: RBCS1 RBCS2 RBCS3 RBCS4
9.8.2
Multiplexer
(Interleaved Operation) multiplexer used conjunction with function located within each framer/formatter block (controlled RIBOC TIBOC registers). When enabled, multiplexer simplifies user interface connecting signals internally. multiplexer eliminates need ganged external wiring tri-state output drivers RSER RSIG pins. This option provides more controlled, cleaner, lower power mode operation. Note that channel block signals TCHBLK RCHBLK output rate selection. Hence 4.096MHz would have channel blocks programmed active rate 4.096MHz). Hence particular blocking channel would active duration channel programmed. DS26528 will also support traditional mode operation allowing complete access individual framers, tri-stating RSER RSIG pins appropriate times external wiring. This mode operation enabled framer associated RIBOC TIBOC registers, while leaving multiplexer disabled (IBOMS0 IBOMS1 Figures show equivalent internal circuit each mode. Table describes function changes each mode multiplexer.
Table 9-4. Registers related Multiplexer
REGISTER Global Transceiver Control Register (GTCR1) Receive Interleave Operation Control Register (RIBOC) Transmit Interleave Operation Control Register (TIBOC) FRAMER ADDRESSES 00F0 FUNCTION This Global Register Framers. used specify Ganged Operation This register used control many Framers corresponding Speed links Receiver. This register used control many Framers corresponding Speed links Transmitter.
188H
Note: addresses shown above Framer Addresses Framers calculated using following: Framer (Framer address 200hex), where Framers
DS26528 Octal T1/E1/J1 Transceiver
Figure 9-3. Multiplexer Equivalent Circuit-4.096MHz
RSER1
RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK
RSIG1 RSYNC1 RSYSCLK TSER1 TSIG1 TSSYNCIO TSYSCLK
Port Backplane Interface
Port Backplane Interface
RSER3 RSIG3 RSYNC3 RSYSCLK TSER3 TSIG3 TSSYNCIO TSYSCLK
Port Backplane Interface
Port Backplane Interface
RSER5 RSIG5 RSYNC5 RSYSCLK TSER5 TSIG5 TSSYNCIO TSYSCLK
Port Backplane Interface
Port Backplane Interface
RSER7 RSIG7 RSYNC7 RSYSCLK TSER7 TSIG7 TSSYNCIO TSYSCLK
Port Backplane Interface
Port Backplane Interface
DS26528 Octal T1/E1/J1 Transceiver
Figure 9-4. Multiplexer Equivalent Circuit-8.192MHz
RSER1
RSIG1
RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSSYNC TSYSCLK TSER TSIG
Port Backplane Interface
RSYNC1 RSYSCLK TSER1 TSIG1 TSSYNCIO TSYSCLK
Port Backplane Interface
Port Backplane Interface
Port Backplane Interface
RSER5
RSIG5
RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK
Port Backplane Interface
RSYNC5 RSYSCLK TSER5 TSIG5 TSSYNCIO TSYSCLK
Port Backplane Interface
Port Backplane Interface
Port Backplane Interface
DS26528 Octal T1/E1/J1 Transceiver
Figure 9-5. Multiplexer Equivalent Circuit-16.384MHz
RSER(1) RSER(2) RSER(3) RSER(4) RSER(5) RSER(6) RSER(7) RSER(8) RIBO_OEB(1-8)
RSER1
RSIG(1) RSIG(2) RSIG(3) RSIG(4) RSIG(5) RSIG(6) RSIG(7) RSIG(8) RIBO_OEB(1-8)
RSIG1
Port Backplane Interface
RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK
RSYNC1 RSYSCLK TSER1 TSIG1 TSSYNCIO TSYSCLK
Port Backplane Interface
Port Backplane Interface
Port Backplane Interface
Port Backplane Interface
Port Backplane Interface
Port Backplane Interface
Port Backplane Interface
DS26528 Octal T1/E1/J1 Transceiver
Table 9-5. RSER Output Definitions
NAME
RSER1 RSER2 RSER3 RSER4 RSER5 RSER6 RSER7 RSER8
NORMAL
Serial Data Port Serial Data Port Serial Data Port Serial Data Port Serial Data Port Serial Data Port Serial Data Port Serial Data Port
4.096MHz
Combined Serial Data Ports Reserved Combined Serial Data Ports Unused Combined Serial Data Ports Unused Combined Serial Data Ports Unused
8.192MHz
Combined Serial Data Ports Unused Unused Unused Combined Serial Data Ports Unused Unused Unused
16.384MHz
Serial Data Ports Unused Unused Unused Unused Unused Unused Unused
Table 9-6. RSIG Output Definitions
NAME
RSIG1 RSIG2 RSIG3 RSIG4 RSIG5 RSIG6 RSIG7 RSIG8
NORMAL
Signaling Data Port Signaling Data Port Signaling Data Port Signaling Data Port Signaling Data Port Signaling Data Port Signaling Data Port Signaling Data Port
4.096MHz
Combined Signaling Data Ports Unused Combined Signaling Data Ports Unused Combined Signaling Data Ports Unused Combined Signaling Data Ports Unused
8.192MHz
Combined Signaling Data Ports Unused Unused Unused Combined Signaling Data Ports Unused Unused Unused
16.384MHz
Signaling Data Ports Unused Unused Unused Unused Unused Unused Unused
DS26528 Octal T1/E1/J1 Transceiver
Table 9-7. TSER Input Definitions
NAME
TSER1 TSER2 TSER3 TSER4 TSER5 TSER6 TSER7 TSER8
NORMAL
Serial Data Port Serial Data Port Serial Data Port Serial Data Port Serial Data Port Serial Data Port Serial Data Port Serial Data Port
4.096MHz
Combined Serial Data Ports Unused Combined Serial Data Ports Unused Combined Serial Data Ports Unused Combined Serial Data Ports Unused
8.192MHz
Combined Serial Data Ports Unused Unused Unused Combined Serial Data Ports Unused Unused Unused
16.384MHz
Serial Data Ports Unused Unused Unused Unused Unused Unused Unused
Table 9-8. TSIG Input Definitions
NAME
TSIG1 TSIG2 TSIG3 TSIG4 TSIG5 TSIG6 TSIG7 TSIG8
NORMAL
Signaling Data Port Signaling Data Port Signaling Data Port Signaling Data Port Signaling Data Port Signaling Data Port Signaling Data Port Signaling Data Port
4.096MHz
Combined Signaling Data Ports Unused Combined Signaling Data Ports Unused Combined Signaling Data Ports Unused Combined Signaling Data Ports Unused
8.192MHz
Combined Signaling Data Ports Unused Unused Unused Combined Signaling Data Ports Unused Unused Unused
16.384MHz
Signaling Data Ports Unused Unused Unused Unused Unused Unused Unused
DS26528 Octal T1/E1/J1 Transceiver
Table 9-9. RSYNC Input Definitions
NAME
RSYNC1 RSYNC2 RSYNC3 RSYNC4 RSYNC5 RSYNC6 RSYNC7 RSYNC8
NORMAL
Frame Pulse port Frame Pulse port Frame Pulse port Frame Pulse port Frame Pulse port Frame Pulse port Frame Pulse port Frame Pulse port
4.096MHz
Frame Pulse Ports Unused Frame Pulse Ports Unused Frame Pulse Ports Unused Frame Pulse Ports Unused
8.192MHz
Frame Pulse Ports Unused Unused Unused Frame Pulse Ports Unused Unused Unused
16.384MHz
Frame Pulse Ports Unused Unused Unused Unused Unused Unused Unused
DS26528 Octal T1/E1/J1 Transceiver
9.8.3
H.100 (CT-Bus) Compatibility
registers used controlling H.100 Backplane RIOCR TIOCR. H.100 Bus) synchronous, bit-serial, transport operating 8.192MHz. H.100 standard also allows compatibility modes operate 2.048MHz, 4.096MHz, 8.192MHz. control H100EN (RIOCR.5), when combined with RSYNCINV TSSYNCINV allows DS26528 accept CT-Bus-compatible frame sync signal (/CT_FRAME) RSYNC TSSYNCIO (input mode) inputs. following rules apply H100EN control bit: H100EN controls sampling point RSYNC (input mode) TSSYNCIO (input Mode) only (the RSYNC output other sync signals affected). H100EN would always used conjunction with receive transmit elastic store buffers. H100EN would typically used with 8.192MHz mode, could also used with 4.096MHz mode 2.048MHz backplane operation. H100EN RIOCR controls both RSYNC TSSYNCIO (i.e., there separate control TSSYNCIO). H100EN does invert expected signal; RSYNCINV (RIOCR) TSSYNCINV (TIOCR) must `high' invert inbound sync signals.
Figure 9-6. RSYNC Input H.100 (Ct-Bus) Mode
RSYNC1
RSYNC2 RSYSCLK
RSER
tbc3
NOTES: RSYNC input mode, normal operation. RSYNC input mode, H100EN RSYNCINV (bit-cell time) 122ns typically. 244ns 488ns also acceptable.
DS26528 Octal T1/E1/J1 Transceiver
Figure 9-7. TSSYNCIO (Input Mode) Input H.100 (CT-Bus) Mode
TSSYNCIO1
TSSYNCIO2 TSYSCLK
TSER
tbc3
NOTES: TSSYNCIO normal operation TSSYNCIO with H100EN TSSYNCINV (bit-cell time) 122ns typically. 244ns 488ns also acceptable.
9.8.4
Transmit Receive Channel Blocking Registers
Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3/RCBR4) Transmit Channel Blocking Registers (TCBR1/TCBR2/TCBR3/TCBR4) control RCHBLK TCHBLK pins respectively. RCHBLK TCHBLK pins user programmable outputs that forced either high during individual channels. These outputs used block clocks USART LAPD controller ISDN-PRI applications. When appropriate bits one, RCHBLK TCHBLK will held high during entire corresponding channel time. When used with (1.544MHz) backplane, only TCBR1 TCBR3 will used. TCBR4 included support (2.048MHz) backplane when elastic store configured rate conversion (Elastic Store).
9.8.5
Transmit Fractional Support (Gapped Clock Mode)
DS26528 programmed output gapped clocks selected channels receive transmit paths simplify connections into USART LAPD controller Fractional T1/E1 ISDN-PRI applications. When gapped clock feature enabled, gated clock output TCHCLK signal. channel selection controlled transmit gapped clock channel select registers (TGCCS1-TGCCS4). transmit path enabled gapped clock mode with TGCLKEN (TESCR.6). Both 56KBps 64KBps channel formats supported determined TESCR.7. When 56KBps mode selected, clock corresponding Data/Control channel omitted (only seven most significant bits channel have clocks).
9.8.6
Receive Fractional Support (Gapped Clock Mode)
DS26528 programmed output gapped clocks selected channels receive transmit paths simplify connections into USART LAPD controller Fractional T1/E1 ISDN-PRI applications. When gapped clock feature enabled, gated clock output RCHCLK signal. channel selection controlled receive gapped clock channel select registers (RGCCS1-RGCCS4). receive path enabled gapped clock mode with RGCLKEN (RESCR.6). Both 56KBps 64KBps channel formats supported determined RESCR.7. When 56KBps mode selected, clock corresponding Data/Control channel omitted (only seven most significant bits channel have clocks).
DS26528 Octal T1/E1/J1 Transceiver
Framers
DS26528 framer cores software selectable receive framer locates frame multiframe boundaries monitors data stream alarms. also used extracting inserting signaling data, data, information. receive side framer decodes AMI, B8ZS line coding, synchronizes data stream, reports alarm information, counts framing/coding errors, provides clock/data frame sync signals backplane interface section. Diagnostic capabilities include loopbacks, 16-bit loop-up loop-down code detection. device contains internal registers host access control device. transmit side, clock data frame sync signals provided framer backplane interface section. framer inserts appropriate synchronization framing patterns, alarm information, calculates inserts codes, provides B8ZS (zero code suppression) line coding. Both transmit receive path have HDLC controller. HDLC controller transmits receives data framer block. HDLC controller assigned time slot, portion time slot, (T1). HDLC controller separate 64-byte FIFO reduce amount processor overhead required manage flow data. backplane interface provides versatile method sending receiving data from host system. Elastic stores provide method interfacing asynchronous systems, converting from T1/E1 network 2.048MHz, 4.096MHz, 8.192MHz 64kHz system backplane. elastic stores also manage slip conditions (asynchronous interface). (Interleave Option) provided allow multiple framers DS26528 share high-speed backplane.
9.9.1
Framing
trunks contain bytes serial voice/data channels bundled with overhead bit, F-bit. F-bit contains fixed pattern receiver delineate frame boundaries. F-bit inserted once frame beginning transmit frame boundary. frames further grouped into bundles frames ESF. framing modes outlined Table 9-10 Table 9-11. Mode, framing Frame ignored Japanese Yellow selected.
DS26528 Octal T1/E1/J1 Transceiver
Table 9-10. Framing Mode
FRAME NUMBER SIGNALING
Table 9-11. Framing Mode
FRAME NUMBER FRAMING CRC6 CRC5 CRC3 CRC4 CRC2 CRC1 SIGNALING
DS26528 Octal T1/E1/J1 Transceiver
Table 9-12. SLC-96 Framing
FRAME NUMBER
SIGNALING
(concentrator bit) (concentrator bit) (concentrator bit) (concentrator bit) (concentrator bit) (concentrator bit) (concentrator bit) (concentrator bit) (concentrator bit) (concentrator bit) (concentrator bit) (spoiler Bit) (Spoiler Bit) (Spoiler Bit) (Maintenance Bit) (Maintenance Bit) (Maintenance Bit) (Alarm Bit)
DS26528 Octal T1/E1/J1 Transceiver
FRAME NUMBER
(Alarm Bit)
SIGNALING
(Switch Bit) (Switch Bit) (Switch Bit) (Switch Bit) 1(Spoiler Bit)
9.9.2
Framing
Framing consists FAS, NFAS detection shown following table.
Table 9-13. FAS/NFAS Framing
CRC-4 FRAME TYPE NFAS NFAS NFAS NFAS NFAS NFAS NFAS NFAS
bits CRC-4 remainder. Alarm bits. Bits Datalink.
DS26528 Octal T1/E1/J1 Transceiver Registers that related setting framing shown following table.
Table 9-14. Registers Related Setting Framer
REGISTER Transmit Master Mode Register (TMMR) Transmit Control Register (TCR1) Transmit Control Register (TCR2) Transmit Control Register (TCR3) Receive Master Mode Register (RMMR) Receive Control Register (RCR1) Receive Control Register (T1RCR2) Receive Control Register (E1RCR2) Receive Latched Status Register (RLS1) Receive Interrupt Mask Register (RIM1) Receive Latched Status Register (RLS2) Receive Interrupt Mask Register (RIM2) Receive Latched Status Register RLS4) Receive Interrupt Mask Register (RIM4) Frames Sync Count Register (FOSCR1) Frames Sync Count Register (FOSCR2) Receive Align Frame Register (E1RAF) Receive Non-Align Frame Register (E1RNAF) Transmit SLC96 Control Register (T1TSLC1) Transmit SLC96 Control Register (T1TSLC2) Transmit SLC96 Control Register (T1TSLC3) Receive SLC96 Control Register (T1RSLC1) Receive SLC96 Control Register 1(T1RSLC2) Receive SLC96 Control Register (T1RSLC3) FRAMER ADDRESSES T1E1 Mode Source F-Bit F-Bit Corruption, Selection SLC96 Mode Selection T1/E1 Selection Receiver Resynchronization Criteria Framer Remote Alarm Criteria Receive Loss Signal Criteria Selection Receive Latched Status Receive Interrupt Mask Receive Latched Status Receive Interrupt Mask Receive Latched Status Receive Interrupt Mask Framer Sync Register Framer Sync Register Byte RNAF Byte Transmit SLC96 Bits Transmit SLC96 Bits Transmit SLC96 Bits Receive SLC96 Bits Receive SLC96 Bits Receive SLC96 Bits FUNCTION
Note: addresses shown above Framer Addresses Framers calculated using following: Framer (Framer address (n-1) 200hex); where Framers
DS26528 Octal T1/E1/J1 Transceiver
9.9.3
Transmit Synchronizer
DS26528 transmitter ability identify frame boundary, well multiframe boundaries within incoming data stream TSER. (TCR3.2) control determines whether transmit synchronizer searches multiframe. Additional control signals transmit synchronizer located TSYNCC Register. latched status TLS3.0 (LOFD) provided indicate that Loss Frame synchronization occurred, real-time (LOF) which high when synchronizer searching frame/multiframe alignment. LOFD enabled cause interrupt condition INTB. Note that when transmit synchronizer used, TSYNC signal should output (TSIO recovered frame sync pulse will output this signal. recovered CRC4 multi-frame sync pulse will output enabled with TIOCR.0 (TSM Other points concerning transmit synchronizer: synchronizer operational when transmit elastic store enabled, including modes. synchronizer does perform CRC6 alignment verification (ESF mode) does verify CRC4 codewords. synchronizer does have ability search multiframe. registers related Transmit Synchronizer shown following table.
Table 9-15. Registers Related Transmit Synchronizer
REGISTER Transmit Synchronizer Control Register (TSYNCC) Transmit Control Register (TCR3) Transmit Latched Status Register (TLS3) Transmit Interrupt Mask Register (TIM3) Transmit Configuration Register (TIOCR) FRAMER ADDRESSES FUNCTION Resynchronization Control Transmit Synchronizer Selects Between Transmit Synchronizer Provides Latched Status Transmit Synchronizer Provides Mask Bits TLS3 Status TSYNC Should Output
Note: addresses shown above Framer Addresses Framers calculated using following: Framer (Framer address (n-1) 200hex); where Framers
DS26528 Octal T1/E1/J1 Transceiver
9.9.4
Signaling
DS26528 supports both software hardware based Signaling. Interrupts generated changes signaling data. DS26528 also equipped with receive signaling freeze loss synchronization (OOF), carrier loss change frame alignment. DS26528 also hardware pins indicate signaling freeze. Flexible signaling support Software hardware based Interrupt generated change signaling data Receive signaling freeze loss frame, loss signal, change frame alignment. Hardware pins carrier loss signaling freeze indication.
Table 9-16. Registers Related Signaling
REGISTER Transmit Signaling Registers (TS1 TS16) Software Signaling Insertion Enable Registers (SSIE1 SSIE4) Transmit Hardware Signaling Channel Select Registers (THSCS1 THSCS4) Receive Signaling Control Register (RSIGC) Receive Signaling All-Ones Insertion Registers (T1RSAOI1 T1RSAOI3) Receive Signaling Registers (RS1 RS16) RSS1 RSS4 RSCSE1 RSCSE4 RLS4 RIM4 RSI1 RSI4 FRAMER ADDRESSES (T1/J1) CAS) 118, 119, 11A, FUNCTION Transmit ABCD Signaling When Enabled, Signaling Inserted Channel Bits Determine which Channels will have Signaling Inserted Hardware Signaling Mode Freeze Control Receive Signaling Registers All-Ones Insertion Mode Only) Receive Signaling Bytes Receive Signaling Change Status Bits Receive Signaling Change State Interrupt Enable Receive Signaling Change State Receive Signaling Change State Interrupt Mask Registers Signaling Reinsertion
1C8, 1C9, 1CA,
(T1/J1) (E1) (T1/J1) (E1)
Note: addresses shown above Framer Addresses Framers calculated using following: Framer (Framer address (n-1) 200hex); where Framers
DS26528 Octal T1/E1/J1 Transceiver
9.9.4.1 Transmit Signaling Operation
There methods provide transmit signaling data. These processor based (i.e., software based) hardware based. Processor-based refers access through transmit signaling registers, -TS16, while hardware based refers using TSIG pins. Both methods used simultaneously.
9.9.4.1.1 Processor-Based Signaling
processor-based mode, signaling data loaded into Transmit Signaling registers (TS1 -TS16) host interface. multiframe boundaries, contents these registers loaded into shift register placement appropriate position outgoing data stream. user utilize Transmit Multiframe Interrupt Latched Status Register (TLS1.2) know when update signaling bits. user need update transmit signaling register which there change state that register. Each Transmit Signaling Register contains Robbed signaling (TCR1.4 mode) TS16 signaling (TCR1.6 mode) time slot that will inserted into outgoing stream. Signaling data sourced from registers per-channel basis utilizing Software Signaling Insertion Enable registers, SSIE1 through SSIE4. framing mode, there four signaling bits channel TS12 contain full multiframe signaling data. framing mode, there only signaling bits channel framing mode, framer uses positions next multiframe. positions become `don't care' mode. mode, TS16 carries signaling information. This information either (Common Channel Signaling) (Channel Associated Signaling) format. time slots referenced different channel number schemes "Channel" numbering, through TS31 labeled channels through "Phone Channel" numbering through TS15 labeled channel through channel TS17 through TS31 labeled channel through channel
TIME SLOT NUMBERING SCHEMES
Channel Phone Channel
9.9.4.1.2
Hardware-Based Signaling
Hardware Based mode, signaling data input TSIG pin. This signaling stream buffered inserted data stream being input TSER pin. Signaling data input Transmit Hardware Signaling Channel Select (THSCS1) function, framer take signaling data presented TSIG insert signaling data into data stream that being input TSER pin. user control which channels have signaling data from TSIG inserted into them per-channel basis. signaling insertion capabilities framer available whether transmit side elastic store enabled disabled. elastic store enabled, backplane clock (TSYSCLK) either 1.544MHz 2.048MHz.
DS26528 Octal T1/E1/J1 Transceiver
9.9.4.2 Receive Signaling Operation
There methods access receive signaling data provide transmit signaling data. These processor based (i.e., software based) hardware based. Processor-based refers access through transmit receive signaling registers, RS1-RS16. Hardware based refers RSIG pin. Both methods used simultaneously.
9.9.4.2.1 Processor-Based Signaling
Signaling information sampled from receive data stream copied into receive signaling registers, through RS16. signaling information these registers always updated multiframe boundaries. This function always enabled.
9.9.4.2.2 Change State
order avoid constantly monitoring receive signaling registers DS26528 programmed alert host when specific channel channels undergo change their signaling state. RSCSE1 through RSCSE4 used select which channels cause change state indication. change state indicated Latched Status Register (RLS4.3). signaling integration enabled then signaling state must constant multiframes before change state indication indicated. user enable toggle upon detection change signaling setting Interrupt Mask RIM4.3. signaling integration mode global cannot enabled channel-by-channel basis. user identity which channels have undergone signaling change state reading Receive Signaling Status (RSS1 through RSS4) registers. information from these registers will tell user which register read signaling data. changes indicated RSS1-RSS4 registers regardless RSCSE1-RSCSE4 registers.
9.9.4.2.3 Hardware-Based Receive Signaling
hardware based signaling signaling data obtained from RSER RSIG pin. RSIG signaling stream output channel channel basis from signaling buffer. robbed TS16 signaling data still present original data stream RSER. signaling buffer provides signaling data RSIG also allows signaling data reinserted into original data stream different alignment that determined multiframe signal from RSYNC pin. this mode, receive elastic store enabled disabled. receive elastic store enabled, then backplane clock (RSYSCLK) either 1.544MHz 2.048MHz. framing mode, ABCD signaling bits output RSIG lower nibble each channel. RSIG data updated once multiframe (3ms ESF, 1.5ms CAS) unless signaling freeze effect. framing mode, signaling bits output twice RSIG lower nibble each channel. Hence, bits contain same data bits respectively, each channel.
9.9.4.2.4 Receive Signaling Reinsertion RSER
this mode, user will provide multiframe sync RSYNC signaling data will reinserted based this alignment. mode, this results copies signaling data RSER data stream. original signaling data based Fs/ESF frame positions realigned data based user supplied multiframe sync applied RSYNC. voice channels this extra copy signaling data little consequence. Reinsertion avoided data channels since this feature activated per-channel basis. reinsertion, elastic store must enabled backplane clock either 1.544MHz 2.048MHz. signaling information cannot reinserted into 1.544MHz backplane. Signaling reinsertion mode enabled, per-channel basis setting Receive Signaling Reinsertion Channel Select high register. channels that have signaling reinserted selected writing RSI1-RSI4 registers. mode, user will generally select channels none reinsertion.
9.9.4.2.5 Force Receive Signaling Ones
mode, user per-channel basis force robbed signaling positions one. This done using T1RSAOI registers (T1RSAOI1 user sets Channel Select RSAOI1-RSAOI3 registers select channels that have signaling forced one.
DS26528 Octal T1/E1/J1 Transceiver
9.9.4.2.6 Receive Signaling Freeze
signaling data four multiframe signaling buffers will frozen known good state upon either loss synchronization (OOF event), carrier loss, change frame alignment. mode, this action meets requirements BellCore TR-TSY-000170 signaling freezing. allow this freeze action occur, RSFE control (RSIGC.1) should high. user force freeze setting RSFF control (RSIGC.2) high. RSIGF output provides hardware indication that freeze effect. four multiframe buffer provides three multiframe delay signaling bits provided RSIG (and RSER Receive Signaling Reinsertion enabled). When freezing enabled (RSFE signaling data will held last known good state until corrupting error condition subsides. When error condition subsides, signaling data will held state least additional (4.5ms framing mode, mode) before being allowed updated with signaling data. Receive Signaling Registers frozen updated during loss sync condition. They will contain most recent signaling information before occurred.
9.9.4.3 Transmit SLC-96 Operation Mode Only)
SLC-96 based transmission scheme, standard pattern robbed make room message fields. SLC-96 multiframe made superframes, hence frames long. 72-frame SLC-96 multiframe, framing bits normal pattern other bits divided into alarm, maintenance, spoiler, concentrator bits well 12-bits normal pattern. Additional SLC-96 information found BellCore document TR-TSY-000008. Registers related Transmit shown following table.
Table 9-17. Registers Related SLC96
REGISTER Transmit (T1TFDL) TSCL Registers (T1TSLC1) Transmit Control Register TCR2) Transmit Latched Status 1(TLS1) Receive Register (T1RSLC1) Receive Latched Status (RLS7) FRAMER ADDRESSES 164, 165, Receive SLC-96 Alignment Event FUNCTION sending Messages Transmit SLC-96 Ft/Fs Bits Registers that Control SLC-96 Overhead Values Transmit Control Data Selection Source Ft/Fs Bits Status Indicating Transmission Data Link Buffer
Note: addresses shown above Framer Addresses Framers calculated using following: Framer (Framer address (n-1) 200hex); where Framers
TFDL register used insert SLC-96 message fields. insert SLC-96 message using TFDL register, user should configure DS26528 shown below: TCR2.6 (TSLC96) Enable Transmit SLC-96 TCR2.7 (TFDLS) Source bits TFDL SLC96 formatter TCR3.2 (TFM) framing Mode TCR1.6 (TFPT) 'pass through' TSER F-bits. DS26528 will automatically insert 12-bit alignment pattern bits SLC96 data link frame. Data from TSLC1-TSLC3 will inserted into remaining locations SLC96 multiframe. status TSLC96 located TLS1.4 will indicate that SLC-96 data link buffer been transmitted that user should write message data into TSLC1-TSLC3. host will have after assertion TLS1.4 write registers TSLC1-TSLC3. data provided these registers, previous values will retransmitted.
DS26528 Octal T1/E1/J1 Transceiver
9.9.4.4 Receive SLC-96 Operation Mode Only)
SLC-96-based transmission scheme, standard pattern robbed make room message fields. SLC-96 multiframe made superframes, hence frames long. 72-frame SLC-96 multiframe, framing bits normal pattern other 36-bits divided into alarm, maintenance, spoiler, concentrator bits well 12-bits normal pattern. Additional SLC-96 information found BellCore document TR-TSY-000008. enable DS26528 synchronize onto SLC-96 pattern, following configuration should used: RCR1.5 (RFM) framing mode cross-couple bits RCR1.3 (SYNCC) T1RCR2.4 (RSLC96) Enable SLC-96 synchronizer RCR1.7 (SYNCT) minimum sync time SLC-96 message bits extracted RSLC1-3 registers. status RSLC96 located RLS7.3 useful retrieving SLC-96 message data. RSLC96 will indicate when framer updated data link registers RSLC1-RSLC3 with latest message data from incoming data stream. Once RSLC96 set, user will have until next RSLC96 interrupt) retrieve most recent message data from RSLC1/2/3 registers. Note that RSLC96 will DS26528 unable detect 12-bit SLC-96 alignment pattern.
DS26528 Octal T1/E1/J1 Transceiver
9.9.5
Datalink
9.9.5.1 Transmit Oriented Code (BOC) Transmit Controller
DS26528 contains generator transmit side detector receive side. function available only mode. registers related Transmit Oriented Code shown following table.
Table 9-18. Registers Related Transmit
REGISTER Transmit Oriented Register (T1TBOC) Transmit HDLC Control Register (THC2) Transmit Control Register 1(TCR1) FRAMER ADDRESSES FUNCTION Transmit Oriented Message Code Register enable Sending Transmit Determines Sourcing F-Bit
Note: addresses shown above Framer Addresses Framers calculated using following: Framer (Framer address (n-1) 200hex); where Framers
Bits through TBOC register contain message transmitted. Setting SBOC (THC2.6) causes transmit controller immediately begin inserting sequence into position. transmit controller automatically provides abort sequence. messages will transmitted long SBOC set. Note that TFPT(TCR1.6) control must 'zero' message overwrite F-bit information being sampled TSER.
Transmit
Write 6-bit code into TBOC register. SBOC THC2
9.9.5.2 Receive Oriented Code (BOC) Controller
DS26528 Framers contains generator transmit side detector receive side. function available only Mode Data link Bits. following table shows registers related Receive operation.
Table 9-19. Registers Related Receive
REGISTER Receive Oriented Control (T1RBOCC) Receive Oriented Control (T1RBOC) Receive Latched Status 7(RLS7) Receive Interrupt Mask (RIM7) FRAMER ADDRESSES FUNCTION Controls Receive Function Receive Oriented Message Indicates Changes Receive Oriented Messages Mask Bits RBOC Generation Interrupts
Note: addresses shown above Framer Addresses Framers calculated using following: Framer (Framer address (n-1) 200hex); where Framers
DS26528 Octal T1/E1/J1 Transceiver mode, DS26528 continuously monitors receive message bits valid message. Detect (BD) status RLS7.0 will once valid message been detected time determined Receive Filter bits RBF0 RBF1 RBOCC register. 6-bit message will available RBOC register. Once user cleared bit, will remain clear until detected same detected following Clear event). Clear (BC) RLS7.1 when valid longer being detected time determined Receive Disintegration bits RBD0 RBD1 RBOCC register. status bits create hardware interrupt INTB signal enabled associated interrupt mask bits RIM7 register.
9.9.5.3 Legacy Transmit
recommended that DS26528's built-in HDLC controllers used most applications requiring access FDL. registers related control Transmit presented following table.
Table 9-20. Registers Related Transmit
REGISTER Transmit (T1TFDL) Transmit Control (TCR2) Transmit Latched Status 2(TLS2) Transmit Interrupt Mask (TIM2) FRAMER ADDRESSES FUNCTION Code Used Insert Transmit Defines Source Transmit Empty Mask TFDL Empty
Note: addresses shown above Framer Addresses Framers calculated using following: Framer (Framer address (n-1) 200hex); where Framers
When enabled with TCR2.7, transmit section will shift into data stream, either framing mode) bits framing mode) contained Transmit register (TFDL). When value written TFDL, will multiplexed serially (LSB first) into proper position outgoing data stream. After full eight bits been shifted out, framer will signal host controller that buffer empty that more data needed setting TLS2.4 one. will also toggle enabled TIM2.4. user update TFDL with value. TFDL updated, value TFDL will transmitted once again. Note that this mode, zero stuffing will applied data. strongly suggested that HDLC controller used messaging applications. framing mode, framer uses TFDL register insert framing pattern. accomplish this TFDL register must programmed `1C'h TCR2.7 should source data from TFDL register) Transmit Register (TFDL) contains Facility Data Link (FDL) information that inserted byte basis into outgoing data stream. transmitted first. mode, only lower bits used.
DS26528 Octal T1/E1/J1 Transceiver
9.9.5.4 Legacy Receive
recommended that DS26528's built-in HDLC controllers used most applications requiring access FDL. registers related Receive shown following table.
Table 9-21. Registers Related Receive
REGISTER Receive (T1RFDL) Receive Latched Status 7(RLS7) Receive Interrupt Mask 7(RIM7) FRAMER ADDRESSES FUNCTION Code Used Insert Transmit Receive Full this Register Mask RFDL Full
Note: addresses shown above Framer Addresses Framers calculated using following: Framer (Framer address (n-1) 200hex); where Framers
receive section, recovered bits bits shifted bit-by-bit into Receive register (RFDL). Since RFDL bits length, will fill every times 250ms). framer will signal external controller that buffer filled RLS7.2 bit. enabled RIM7.2, INTB will toggle indicating that buffer filled needs read. user read this data before lost. Note that zero de-stuffing applied data provided through RFDL register. Receive Register (RFDL) reports incoming Facility Data Link (FDL) incoming bits. received first. framing mode, RFDL updates multiframe boundaries reports only bits.
9.9.6
Datalink
FRAMER ADDRESSES
registers related Datalink shown following table: REGISTER E1RAF E1RNAF E1RsiAF E1RSiNAF E1RSa4 RSA8 E1TAF E1TNAF E1TSiAF E1TSiNAF E1TSa4 TSA8 E1TSACR FUNCTION Receive Frame Alignment Register Receive Non-Frame Alignment Register Receive Bits Frame Alignment Frames Receive Bits Non-Frame Alignment Frames Receive Bits Transmit Align Frame Register Transmit Non-Align Frame Register Transmit Bits Frame Alignment Frames Transmit Bits Non-Frame Alignment Frames Transmit Transmit Source3 Control
Note: addresses shown above Framer Addresses Framers calculated using following: Framer (Framer address (n-1) 200hex); where Framers
DS26528 Octal T1/E1/J1 Transceiver
9.9.6.1 Additional Receive Receive Operation Mode)
DS26528, when operated mode, provides access both bits methods. first involves using internal E1RAF/E1RNAF E1TAF/E1TNAF registers. second method involves expanded version first method.
9.9.6.1.1 Internal Register Scheme Based Double-Frame (Method
receive side, E1RAF E1RNAF registers will always report data received locations. E1RAFand E1RNAF registers updated align frame boundaries. setting Receive Align Frame Latched Status Register (RLS2.0) will indicate that contents RNAF have been updated. host RLS2.0 know when read E1RAF E1RNAF registers. host 250ms retrieve data before lost.
9.9.6.1.2 Internal Register Scheme Based CRC4 Multiframe
receive side, there eight registers (E1RsiAF, E1RSiNAF, E1RRA, E1RSa4 E1RSa8) that report bits they received. These registers updated with setting Receive CRC4 Multiframe Latched Status Register (RLS2.1). host RLS2.1 know when read these registers. user retrieve data before lost. following register descriptions additional information.
9.9.6.2 Internal Register Scheme Based CRC4 Multiframe
transmit side there eight registers (E1TSiAF, E1TSiNAF, E1TRA, E1TSa4 E1TSa8) that Transmit Control Register (E1TSACR), programmed insert both data. Data sampled from these registers with setting Transmit Multiframe Status Register (TLS1.3). host TLS1.3 know when update these registers. update data else data will retransmitted. register descriptions below.
9.9.7
Maintenance Alarms
DS26528 provides extensive functions alarm detection generation. also provides diagnostic functions monitoring performance sending diagnostic information: Real-time latched status bits, interrupts interrupt mask transmitter receiver detection detection generation Violation detection Error counters Monitoring Milliwatt generation detection Slip Buffer Status Transmit Receive
DS26528 Octal T1/E1/J1 Transceiver Some Registers related Maintenance Alarms follows:
Table 9-22. Registers Related Maintenance Alarms
REGISTER Receive Real-Time Status Register (RRTS1) Receive Interrupt Mask 1(RIM1) Receive Latched Status Register (RLS2) Receive Real-Time Status Register (RRTS3) Receive Latched Status Register (RLS3) Receive Interrupt Mask Register (RIM3) Receive Interrupt Mask Register (RIM4) Latched Status (RLS7) Interrupt Mask (RIM7) Latched Status (TLS1) Latched Status (SYNC)(TLS3) Monitor (RDS0M) Error Count Configuration (ERCNT) Line Code Violation Count Register (LCVCR1) Line Code Violation Count Register (LCVCR2) Path Code Violation Count Register (PCVCR1) Path Code Violation Count Register (PCVCR2) Frames Sync Count Register (FOSCR1) Frames Sync Count Register (FOSCR2) FRAMER ADDRESSES FUNCTION Real-Time Receive Status Real-Time Interrupt Mask Real-Time Latched Status Real-Time Receive Status Real-Time Latched Status Real-Time Interrupt Mask Real-Time Interrupt Mask Real-Time Latched Status Real-Time Interrupt Mask Loss Transmit Clock Status, TPDV, etc. Loss Frame Status Receive Monitor Configuration Error Counters Line Code Violation Counter Line Code Violation Counter Receive Path Code Violation Counter Receive Path Code Violation Counter Receive Frame Sync Counter Receive Frame Sync Counter
Note: addresses shown above Framer Addresses Framers calculated using following: Framer (Framer address (n-1) 200hex); where Framers
DS26528 Octal T1/E1/J1 Transceiver
9.9.7.1 Status Information Operation
When particular event occurred occurring), appropriate these registers will one. Status bits operate either latched real-time fashion. Some latched bits enabled generate hardware interrupt INTB signal. Real-Time Bits Some status bits operate real-time fashion. These bits read-only indicate present state alarm condition. Real-time bits will remain stable, valid during host read operation. current value internal status signals read time from real-time status registers without changing latched status register bits Latched Bits When event alarm occurs latched one, will remain until cleared user. These bits typically respond `change-of-state' alarm, condition, event; operate read-thenwrite fashion. user should read value desired status bit, then write that particular location order clear latched value (write locations cleared). Once cleared, will again until event occurred again. Mask Bits Some alarms events either masked unmasked from interrupt Interrupt Mask Registers (RIMx). When unmasked, INTB signal will forced when enabled event condition occurs. INTB will allowed return high other unmasked interrupts present) when user reads then clears (with write) alarm that caused interrupt occur. Note that latched status INTB will clear even alarm still present. Note that some conditions have multiple status indications. example, Receive Loss Frame (RLOF) provides following indications: Real-time indication that receiver synchronized with incoming data stream. Read-only that remains high long condition present. Latched indication that receiver loss synchronization since last cleared. will clear when written user, even condition still present (rising edge detect RRTS1.0). Latched indication that receiver reacquired synchronization since last cleared. will clear when written user, even condition still present (falling edge detect RRTS1.0).
RRTS1.0 (RLOF)
RLS1.0 (RLOFD)
RLS1.4 (RLOFC)
DS26528 Octal T1/E1/J1 Transceiver
Table 9-23. Alarm Criteria
ALARM (Blue Alarm) (see note below) (Yellow Alarm) mode (T1RCR2.0 12th F-bit mode (T1RCR2.0 this mode also referred "Japanese Yellow Alarm") mode Loss Signal (this alarm also referred Receive Carrier Loss (RCL)) CRITERIA when over window, less zeros received when consecutive channels zero least occurrences when 12th framing consecutive occurrences when consecutive patterns 00FF appear when consecutive zeros received CLEAR CRITERIA when over window, more zeros received when consecutive channels zero less than occurrences when 12th framing zero consecutive occurrences when less patterns 00FF possible appear when more ones possible positions received starting with first received
NOTES: definition Alarm Indication Signal (Blue Alarm) unframed ones signal. detectors should able operate properly presence 10E-3 error rate they should falsely trigger framed ones signal. alarm criteria DS26528 been achieve this performance. recommended that RAIS qualified with RLOF bit. following terms equivalent: RAIS Blue Alarm RLOS RLOF Loss Frame (conventionally RLOS Dallas Semiconductor devices) RRAI Yellow Alarm
9.9.8
Automatic Alarm Generation
device programmed automatically transmit Remote Alarm. When automatic generation enabled (TCR2.6 device monitors receive side framer determine following conditions present/ loss receive frame synchronization, alarm (all one's) reception, loss receive carrier signal). more) above conditions present, then framer will either force AIS. When automatic generation enabled (TCR2.5 framer monitors receive side determine following conditions present/ loss receive frame synchronization, alarm (all one's) reception, loss receive carrier signal) CRC4 multiframe synchronization cannot found within 128ms synchronization CRC4 enabled). more) above conditions present, then framer will transmit alarm. generation conforms G.706 specifications. Note: illegal state have both automatic generation automatic Remote Alarm generation enabled same time.
9.9.8.1 Receive AIS-CI RAI-CI Detection
AIS-CI repetitive pattern 1.26 seconds. consists 1.11 seconds unframed ones pattern 0.15 seconds ones modified AIS-CI signature. AIS-CI signature repetitive pattern 6176 bits length which, first numbered bits 3088, 3474 5790 logical zeros other bits pattern logical ones (T1.403). AIS-CI unframed pattern, defined framing formats. RAIS-CI when AIS-CI pattern been detected RAIS (RRTS1.2) set. RAIS-CI latched that should cleared host when read. RAIS-CI will continue approximately every seconds that condition present. host will need `poll' bit, conjunction with normal indicators determine when condition cleared.
DS26528 Octal T1/E1/J1 Transceiver RAI-CI repetitive pattern within data link with period 1.08 seconds. consists sequentially interleaving 0.99 seconds "00000000 11111111" (right-to-left with "00111110 11111111". RRAICI when oriented code "00111110 11111111" detected while RRAI (RRTS1.3) set. RRAICI detector uses receive filter bits (RBF0 RBF1) located RBOCC determine integration time RAI-CI detection. Like RAIS-CI, RRAI-CI latched should cleared host when read. RRAI-CI will continue approximately every seconds that condition present. host will need `poll' bit, conjunction with normal indicators determine when condition cleared. useful enable 200ms integration time with RAIIE control (T1RCR2.1) networks that utilize RAI-CI.
9.9.8.2 Receive Side Digital Milliwatt Code Generation
Receive side digital milliwatt code generation involves using Receive Digital Milliwatt Registers (RDMR1/2/3) determine which channels line going backplane should overwritten with digital milliwatt pattern. digital milliwatt code 8-byte repeating pattern that represents 1kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E). Each RDMRx registers, represents particular channel. one, then receive data that channel will replaced with digital milliwatt code. zero, replacement occurs.
9.9.9
Error Count Registers
DS26528 contains four counters that used accumulate line coding errors, path errors synchronization errors. Counter update options include second boundaries, 42ms mode only), 62.5ms mode only) manually. Error Counter Configuration Register (ERCNT). When updated automatically, user interrupt from timer determine when read these registers. four counters will saturate their respective maximum counts they will rollover (note: only Line Code Violation Count Register potential over-flow error would have exceed 10E-2 before this would occur). DS26528 share one-second timer from port across ports. DS26528 error/performance counters configured update shared one-second source, separate manual update signal input. ERCNT register more information. allowing multiple framer cores synchronously latch their counters, host software streamlined read process performance information from multiple spans more controlled manner.
9.9.9.1 Line Code Violation Count Register (LCVCR)
Either bipolar violations code violations counted. Bipolar violations defined consecutive marks same polarity. mode, B8ZS mode receive side, then B8ZS codewords counted BPVs. mode, HDB3 mode receive side, then HDB3 codewords counted BPVs. ERCNT.0 set, then counts code violations defined O.161. Code violations defined consecutive bipolar violations same polarity. most applications, framer should programmed count BPVs when receiving code count when receiving B8ZS HDB3 code. This counter increments times disabled loss sync conditions. counter saturates 65,535 will rollover. error rate line would have greater than 10E-2 before would saturate. following table details exactly what LCVCRs count.
Table 9-24. Line Code Violation Counting Options
COUNT EXCESSIVE ZEROS? (ERCNT.0) B8ZS ENABLED? (RCR1.6) WHAT COUNTED LCVCR1, LCVCR2 BPVs BPVs consecutive zeros BPVs (B8ZS/HDB3 codewords counted) BPVs consecutive zeros
DS26528 Octal T1/E1/J1 Transceiver
Table 9-25. Line Code Violation Counting Options
CODE VIOLATION SELECT (ERCNT.0) WHAT COUNTED LCVCRs BPVs
9.9.9.2 Path Code Violation Count Register (PCVCR)
operation, Path Code Violation Count Register records either CRC6 errors. When receive side framer operate framing mode, PCVCR will record errors CRC6 codewords. When operate framing mode, PCVCR will count errors framing position. ERCNT.2 bit, framer programmed also report errors framing position. PCVCR will disabled during receive loss synchronization (RLOF conditions. Table 9-26 detailed description exactly what errors PCVCR counts operation. operation, Path Code Violation Count register records CRC4 errors. Since maximum CRC4 count second period 1000, this counter cannot saturate. counter disabled during loss sync either CRC4 level; will continue count loss multiframe sync occur

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