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H8/3834 Series
H8/3837 HD6433837, HD6433837S, HD64473837 H8/3836 HD6433836, HD6433836S H8/3835 HD6433835, HD6433835S H8/3834 HD6433834, HD6433834S, HD6473834 H8/3833 HD6433833, HD6433833S H8/3832 HD6433832S Hardware Manual
ADE-602-054D Rev. 3/5/03 Hitachi, Ltd. MC-Setsu
Notice
When using this document, keep following mind: This document may, wholly partially, subject change without notice. rights reserved: permitted reproduce duplicate, form, whole part this document without Hitachi's permission. Hitachi will held responsible damage user that result from accidents other reasons during operation user's unit according this document. Circuitry other examples described herein meant merely indicate characteristics performance Hitachi's semiconductor products. Hitachi assumes responsibility intellectual property claims other problems that result from applications based examples described herein. license granted implication otherwise under patents other rights third party Hitachi, Ltd. MEDICAL APPLICATIONS: Hitachi's products authorized MEDICAL APPLICATIONS without written consent appropriate officer Hitachi's sales company. Such includes, limited life support systems. Buyers Hitachi's products requested notify relevant Hitachi sales offices when planning products MEDICAL APPLICATIONS.
Preface
H8/300L Series single-chip microcomputers high-speed H8/300L core, with many necessary peripheral functions on-chip. H8/300L instruction compatible with H8/300 CPU. H8/3834 Series system-on-a-chip architecture that includes such peripheral functions controller/driver, five types timers, 14-bit PWM, three-channel serial communication interface, converter. This makes ideal systems requiring display. This manual describes hardware H8/3834 Series. details H8/3834 Series instruction set, refer H8/300L Series Programming Manual. Note: terms H8/3834, H8/3834S, H8/3834 Series used text refer products shown below. H8/3834: HD6433837, HD6433836, HD6433835, HD6433834, HD6433833, HD6473837, HD6473834 HD6433837S, HD6433836S, HD6433835S, HD6433834S, HD6433833S, HD6433832S
H8/3834S:
H8/3834 Series: products, including H8/3834 H8/3834S
Contents
Section
Overview Overview Internal Block Diagram Arrangement Functions 1.3.1 Arrangement 1.3.2 Functions. CPU. Overview 2.1.1 Features 2.1.2 Address Space 2.1.3 Register Configuration Register Descriptions. 2.2.1 General Registers 2.2.2 Control Registers. 2.2.3 Initial Register Values Data Formats 2.3.1 Data Formats General Registers. 2.3.2 Memory Data Formats Addressing Modes. 2.4.1 Addressing Modes. 2.4.2 Effective Address Calculation. Instruction 2.5.1 Data Transfer Instructions 2.5.2 Arithmetic Operations 2.5.3 Logic Operations 2.5.4 Shift Operations 2.5.5 Manipulations. 2.5.6 Branching Instructions 2.5.7 System Control Instructions. 2.5.8 Block Data Transfer Instruction. Basic Operational Timing 2.6.1 Access On-Chip Memory (RAM, ROM). 2.6.2 Access On-Chip Peripheral Modules. States. 2.7.1 Overview 2.7.2 Program Execution State 2.7.3 Program Halt State 2.7.4 Exception-Handling State
Section
Memory Map. 2.8.1 Memory Map. 2.8.2 Address Relocation Application Notes. 2.9.1 Notes Data Access. 2.9.2 Notes Manipulation 2.9.3 Notes EEPMOV Instruction
Section
Exception Handling Overview Reset 3.2.1 Overview 3.2.2 Reset Sequence. 3.2.3 Interrupt Immediately after Reset Interrupts 3.3.1 Overview 3.3.2 Interrupt Control Registers. 3.3.3 External Interrupts. 3.3.4 Internal Interrupts. 3.3.5 Interrupt Operations 3.3.6 Interrupt Response Time Application Notes. 3.4.1 Notes Stack Area 3.4.2 Notes Rewriting Port Mode Registers.
Overview 4.1.1 Block Diagram 4.1.2 System Clock Subclock. System Clock Generator. Subclock Generator Prescalers. Note Oscillators
Section
Clock Pulse Generators.
Section
Power-Down Modes Overview 5.1.1 System Control Registers. Sleep Mode. 5.2.1 Transition Sleep Mode 5.2.2 Clearing Sleep Mode Standby Mode 5.3.1 Transition Standby Mode. 5.3.2 Clearing Standby Mode
5.3.3 Oscillator Settling Time after Standby Mode Cleared 5.3.4 Transition Standby Mode Port States Watch Mode 5.4.1 Transition Watch Mode 5.4.2 Clearing Watch Mode 5.4.3 Oscillator Settling Time after Watch Mode Cleared Subsleep Mode 5.5.1 Transition Subsleep Mode 5.5.2 Clearing Subsleep Mode Subactive Mode. 5.6.1 Transition Subactive Mode 5.6.2 Clearing Subactive Mode. 5.6.3 Operating Frequency Subactive Mode. Active (medium-speed) Mode. 5.7.1 Transition Active (medium-speed) Mode 5.7.2 Clearing Active (medium-speed) Mode. 5.7.3 Operating Frequency Active (medium-speed) Mode. Direct Transfer. 5.8.1 Direct Transfer Overview. 5.8.2 Calculation Direct Transfer Time before Transition
Section
Overview 6.1.1 Block Diagram H8/3834 PROM Mode 6.2.1 Setting PROM Mode. 6.2.2 Socket Adapter Arrangement Memory Map. H8/3834 Programming 6.3.1 Writing Verifying 6.3.2 Programming Precautions H8/3837 PROM Mode 6.4.1 Setting PROM Mode. 6.4.2 Socket Adapter Arrangement Memory Map. H8/3837 Programming 6.5.1 Writing Verifying 6.5.2 Programming Precautions Reliability Programmed Data
Section
Overview 7.1.1 Block Diagram Ports
Section
Overview Port 8.2.1 Overview 8.2.2 Register Configuration Description. 8.2.3 Functions. 8.2.4 States Port 8.3.1 Overview 8.3.2 Register Configuration Description. 8.3.3 Functions. 8.3.4 States Port 8.4.1 Overview 8.4.2 Register Configuration Description. 8.4.3 Functions. 8.4.4 States 8.4.5 Input Pull-Up Port 8.5.1 Overview 8.5.2 Register Configuration Description. 8.5.3 Functions. 8.5.4 States Port 8.6.1 Overview 8.6.2 Register Configuration Description. 8.6.3 Functions. 8.6.4 States 8.6.5 Input Pull-Up Port 8.7.1 Overview 8.7.2 Register Configuration Description. 8.7.3 Functions. 8.7.4 States 8.7.5 Input Pull-Up Port 8.8.1 Overview 8.8.2 Register Configuration Description. 8.8.3 Functions. 8.8.4 States Port 8.9.1 Overview 8.9.2 Register Configuration Description. 8.9.3 Functions.
8.9.4 States 8.10 Port 8.10.1 Overview 8.10.2 Register Configuration Description. 8.10.3 Functions. 8.10.4 States 8.11 Port 8.11.1 Overview 8.11.2 Register Configuration Description. 8.11.3 Functions. 8.11.4 States 8.12 Port 8.12.1 Overview 8.12.2 Register Configuration Description. 8.13 Port 8.13.1 Overview 8.13.2 Register Configuration Description.
Section
Timers Overview Timer 9.2.1 Overview 9.2.2 Register Descriptions 9.2.3 Timer Operation 9.2.4 Timer Operation States. Timer 9.3.1 Overview 9.3.2 Register Descriptions 9.3.3 Timer Operation 9.3.4 Timer Operation States. Timer 9.4.1 Overview 9.4.2 Register Descriptions 9.4.3 Timer Operation 9.4.4 Timer Operation States. Timer 9.5.1 Overview 9.5.2 Register Descriptions 9.5.3 Interface with CPU. 9.5.4 Timer Operation 9.5.5 Application Notes. Timer 9.6.1 Overview
9.6.2 9.6.3 9.6.4 9.6.5 9.6.6
Register Descriptions Noise Canceller Circuit Timer Operation Application Notes. Sample Timer Application
Section Serial Communication Interface
10.1 Overview 10.2 SCI1. 10.2.1 Overview 10.2.2 Register Descriptions 10.2.3 Operation 10.2.4 Interrupts 10.2.5 Application Notes. 10.3 SCI2. 10.3.1 Overview 10.3.2 Register Descriptions 10.3.3 Operation 10.3.4 Interrupts 10.3.5 Application Notes. 10.4 SCI3. 10.4.1 Overview 10.4.2 Register Descriptions 10.4.3 Operation 10.4.4 Operation Asynchronous Mode 10.4.5 Operation Synchronous Mode 10.4.6 Multiprocessor Communication Function 10.4.7 Interrupts 10.4.8 Application Notes.
Section 14-Bit
11.1 Overview 11.1.1 Features 11.1.2 Block Diagram 11.1.3 Configuration 11.1.4 Register Configuration 11.2 Register Descriptions. 11.2.1 Control Register (PWCR). 11.2.2 Data Registers (PWDRU, PWDRL). 11.3 Operation
Section Converter
12.1 Overview
12.2
12.3
12.4 12.5 12.6
12.1.1 Features 12.1.2 Block Diagram 12.1.3 Configuration 12.1.4 Register Configuration. Register Descriptions. 12.2.1 Result Register (ADRR). 12.2.2 Mode Register (AMR) 12.2.3 Start Register (ADSR). Operation 12.3.1 Conversion Operation. 12.3.2 Start Conversion External Trigger Input. Interrupts Typical Application Notes.
Section Controller/Driver
13.1 Overview 13.1.1 Features 13.1.2 Block Diagram 13.1.3 Configuration 13.1.4 Register Configuration 13.2 Register Descriptions. 13.2.1 Port Control Register (LPCR). 13.2.2 Control Register (LCR). 13.3 Operation 13.3.1 Settings Prior Display 13.3.2 Relation Display 13.3.3 Connection HD66100. 13.3.4 Operation Power-Down Modes 13.3.5 Boosting Driver Power Supply
Section Electrical Characteristics
14.1 H8/3832S, H8/3833S, H8/3834S, H8/3835S, H8/3836S H8/3837S Absolute Maximum Ratings (Standard Specifications) 14.2 H8/3832S, H8/3833S H8/3834S Electrical Characteristics (Standard Specifications). 14.2.1 Power Supply Voltage Operating Range. 14.2.2 Characteristics 14.2.3 Characteristics 14.2.4 Converter Characteristics 14.2.5 Characteristics 14.3 H8/3835S, H8/3836S H8/3837S Electrical Characteristics (Standard Specifications).
14.4 14.5
14.6
14.7 14.8
14.9
14.10 14.11
14.3.1 Power Supply Voltage Operating Range. 14.3.2 Characteristics 14.3.3 Characteristics 14.3.4 Converter Characteristics 14.3.5 Characteristics H8/3832S, H8/3833S, H8/3834S, H8/3835S, H8/3836S H8/3837S Absolute Maximum Ratings (Wide Temperature Range (I-Spec) Version). H8/3832S, H8/3833S H8/3834S Electrical Characteristics (Wide Temperature Range (I-Spec) Version) 14.5.1 Power Supply Voltage Operating Range. 14.5.2 Characteristics 14.5.3 Characteristics 14.5.4 Converter Characteristics 14.5.5 Characteristics H8/3835S, H8/3836S H8/3837S Electrical Characteristics (Wide Temperature Range (I-Spec) Version) 14.6.1 Power Supply Voltage Operating Range. 14.6.2 Characteristics 14.6.3 Characteristics 14.6.4 Converter Characteristics 14.6.5 Characteristics H8/3833, H8/3834, H8/3835, H8/3836, H8/3837 (Standard Specification) Absolute Maximum Ratings. H8/3833 H8/3834 Electrical Characteristics (Standard Specifications). 14.8.1 Power Supply Voltage Operating Range.388 14.8.2 Characteristics 14.8.3 Characteristics 14.8.4 Converter Characteristics 14.8.5 Characteristics H8/3835 H8/3836 H8/3837 (Standard Specifications) Electrical Characteristics. 14.9.1 Power Supply Voltage Operating Range. 14.9.2 Characteristics 14.9.3 Characteristics 14.9.4 Converter Characteristics 14.9.5 Characteristics H8/3833, H8/3834, H8/3835, H8/3836, H8/3837 Absolute Maximum Ratings (Wide Temperature Range (I-Spec) Version) H8/3833 H8/3834 Electrical Characteristics (Wide Temperature Range (I-Spec) Version). 14.11.1 Power Supply Voltage Operating Range. 14.11.2 Characteristics 14.11.3 Characteristics
viii
14.11.4 Converter Characteristics 14.11.5 Characteristics 14.12 H8/3835, H8/3836, H8/3837 Electrical Characteristics (Wide Temperature Range (I-Spec) Version) 14.12.1 Power Supply Voltage Operating Range. 14.12.2 Characteristics 14.12.3 Characteristics 14.12.4 Converter Characteristics 14.12.5 Characteristics 14.13 Operation Timing 14.14 Output Load Circuit.
Appendix Instruction
Instructions Operation Code Number Execution States.
Appendix On-Chip Registers
Registers Registers
Appendix Port Block Diagrams.
C.10 C.11 C.12 Block Diagram Port Block Diagram Port Block Diagram Port Block Diagram Port Block Diagram Port Block Diagram Port Block Diagram Port Block Diagram Port Block Diagram Port Block Diagram Port Block Diagram Port Block Diagram Port
Appendix Port States Different Processing States Appendix List Products Codes Appendix Package Dimensions
Section Overview
Overview
H8/300L Series series single-chip microcomputers (MCU: microcomputer unit), built around high-speed H8/300L equipped with peripheral system functions on-chip. Within H8/300L Series, H8/3834 Series features on-chip liquid crystal display (LCD) controller/driver. Other on-chip peripheral functions include five timers, 14-bit pulse width modulator (PWM), three serial communication interface channels, analog-to-digital (A/D) converter. Together these functions make H8/3834 Series ideally suited embedded control systems requiring display. On-chip memory kbytes kbyte H8/3832S, kbytes kbyte H8/3833(S), kbytes kbyte H8/3834(S), kbytes kbytes H8/3835(S), kbytes kbytes H8/3836(S), kbytes kbytes H8/3837(S). H8/3834 H8/3837 both include ZTATversion*, featuring user-programmable onchip PROM. Table summarizes features H8/3834 Series. Note: ZTAT trademark Hitachi, Ltd. Table
Item
Features
Description High-speed H8/300L General-register architecture General registers: Sixteen 8-bit registers (can used eight 16-bit registers) Operating speed Max. operating speed: Add/subtract: (operating MHz) Multiply/divide: (operating MHz) 32.768 subclock Instruction compatible with H8/300 Instruction length bytes bytes Basic arithmetic operations between registers instruction data transfer between memory registers
Table
Item
Features (cont)
Description Typical instructions Multiply bits bits) Divide bits bits) accumulator Register-indirect designation position external interrupt pins: IRQ4 WKP0 internal interrupt sources System clock pulse generator: Subclock pulse generator: 32.768 Sleep mode Standby mode Watch mode Subsleep mode Subactive mode Active (medium-speed) mode H8/3832S: H8/3833(S): H8/3834(S): H8/3835(S): H8/3836(S): H8/3837(S): pins: Input pins: Timer 8-bit timer Count-up timer with selection eight internal clock signals divided from system clock four clock signals divided from watch clock 16-kbyte ROM, 1-kbyte 24-kbyte ROM, 1-kbyte 32-kbyte ROM, 1-kbyte 40-kbyte ROM, 2-kbyte 48-kbyte ROM, 2-kbyte 60-kbyte ROM, 2-kbyte
Interrupts
interrupt sources
Clock pulse generators on-chip clock pulse generators
Power-down modes
power-down modes
Memory
Large on-chip memory
ports
port pins
Timers
Five on-chip timers
Note: defined section Clock Pulse Generators.
Table
Item Timers
Features (cont)
Description Timer 8-bit timer Count-up timer with selection seven internal clock signals event input from external Auto-reloading Timer 8-bit timer Count-up/count-down timer with selection seven internal clock signals event input from external Auto-reloading Timer 16-bit timer used independent 8-bit timers. Count-up timer with selection four internal clock signals event input from external Compare-match function with toggle output Timer 8-bit timer Count-up timer with selection four internal clock signals Input capture function with built-in noise canceller circuit SCI1: synchronous serial interface Choice 8-bit 16-bit data transfer SCI2: 8-bit synchronous serial interface Automatic transfer 32-byte data segments SCI3: 8-bit synchronous asynchronous serial interface Built-in function multiprocessor communication
Serial communication interface
Three channels chip
14-bit
Pulse-division output reduced ripple used 14-bit converter connecting external low-pass filter. Successive approximations using resistance ladder resolution: bits 12-channel analog input port Conversion time: channel Choice four duty cycles (static, 1/2, 1/3, 1/4) Segments expanded externally Segment pins switched general-purpose ports groups four
converter
controller/driver
segment pins common pins
Table
Item
Features (cont)
Description
Product Code Mask Version HD6433832SH HD6433832SF HD6433832SX HD6433833H HD6433833SH HD6433833F HD6433833SF HD6433833X HD6433833SX HD6433834H HD6433834SH HD6433834F HD6433834SF HD6433834X HD6433834SX HD6433835H HD6433835SH HD6433835F HD6433835SF HD6433835X HD6433835SX HD6433836H HD6433836SH HD6433836F HD6433836SF HD6433836X HD6433836SX HD6433837H HD6433837SH HD6433837F HD6433837SF HD6433837X HD6433837SX HD6433832SD HD6433832SE HD6433832SL HD6433833D HD6433833SD HD6433833E HD6433833SE HD6433833L HD6433833SL HD6433834D HD6433834SD HD6433834E HD6433834SE HD6433834L HD6433834SL HD6433835D HD6433835SD HD6433835E HD6433835SE HD6433835L HD6433835SL HD6433836D HD6433836SD HD6433836E HD6433836SE HD6433836L HD6433836SL HD6433837D HD6433837SD HD6433837E HD6433837SE HD6433837L HD6433837SL ZTATVersion HD6473834H HD6473834F HD6473834X HD6473837H HD6473837F HD6473837X HD6473834D HD6473834E HD6473837D HD6473837E HD6473837L Package 100-pin (FP-100B) 100-pin (FP-100A) 100-pin TQFP (TFP-100B) 100-pin (FP-100B) 100-pin (FP-100A) 100-pin TQFP (TFP-100B) 100-pin (FP-100B) 100-pin (FP-100A) 100-pin TQFP (TFP-100B) 100-pin (FP-100B) 100-pin (FP-100A) 100-pin TQFP (TFP-100B) 100-pin (FP-100B) 100-pin (FP-100A) 100-pin TQFP (TFP-100B) 100-pin (FP-100B) 100-pin (FP-100A) 100-pin TQFP (TFP-100B) 100-pin (FP-100B) 100-pin (FP-100A) 100-pin TQFP (TFP-100B) 100-pin (FP-100B) 100-pin (FP-100A) 100-pin TQFP (TFP-100B) 100-pin (FP-100B) 100-pin (FP-100A) 100-pin TQFP (TFP-100B) 100-pin (FP-100B) 100-pin (FP-100A) 100-pin TQFP (TFP-100B) 100-pin (FP-100B) 100-pin (FP-100A) 100-pin TQFP (TFP-100B) 100-pin (FP-100B) 100-pin (FP-100A) 100-pin TQFP (TFP-100B) ROM: kbytes RAM: kbytes (I-spec) ROM: kbytes RAM: kbytes (I-spec) ROM: kbytes RAM: kbytes (I-spec) ROM: kbytes RAM: kbyte (I-spec) ROM: kbytes RAM: kbyte (I-spec) ROM: kbytes RAM: kbyte (I-spec) ROM: kbytes RAM: kbytes ROM: kbytes RAM: kbytes ROM: kbytes RAM: kbytes ROM: kbytes RAM: kbyte ROM/RAM Size ROM: kbytes RAM: kbyte ROM: kbytes RAM: kbyte
Product lineup
Internal Block Diagram
Figure shows block diagram H8/3834 Series.
OSC1 OSC2 TEST
System clock oscillator
Subclock oscillator
Data (upper)
Address
driver power supply
H8/300L
P10/TMOW P11/TMOFL P12/TMOFH P13/TMIG P14/PWM P15/IRQ1/TMIB P16/IRQ2/TMIC P17/IRQ3/TMIF P20/IRQ4/ADTRG P21/UD P30/SCK1 P31/SI1 P32/SO1 P33/SCK2 P34/SI2 P35/SO2 P36/STRB P37/CS
Data (lower)
PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1
Port
P97/SEG40/CL1 P96/SEG39/CL2 P95/SEG38/DO P94/SEG37/M P93/SEG36 P92/SEG35 P91/SEG34 P90/SEG33 P87/SEG32 P86/SEG31 P85/SEG30 P84/SEG29 P83/SEG28 P82/SEG27 P81/SEG26 P80/SEG25 P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 P73/SEG20 P72/SEG19 P71/SEG18 P70/SEG17 P67/SEG16 P66/SEG15 P65/SEG14 P64/SEG13 P63/SEG12 P62/SEG11 P61/SEG10 P60/SEG9
Port
Timer
controller
Timer
SCI1
Port
Timer
SCI2
Timer P40/SCK3 P41/RXD P42/TXD P43/IRQ0 Port
SCI3
Timer
14-bit
P50/WKP0/SEG1 P51/WKP1/SEG2 P52/WKP2/SEG3 P53/WKP3/SEG4 P54/WKP4/SEG5 P55/WKP5/SEG6 P56/WKP6/SEG7 P57/WKP7/SEG8
converter Port
Port AVCC AVSS PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7
Port PC0/AN8 PC1/AN9 PC2/AN10 PC3/AN11
Figure Block Diagram
Port
Port
Port
Port
Port
1.3.1
Arrangement Functions
Arrangement
arrangement H8/3834 Series shown figures 1.3.
P17/IRQ3/TMIF P16/IRQ2/TMIC P15/IRQ1/TMIB
P12/TMOFH
P11/TMOFL
PC2/AN10
P43/IRQ0
P42/TXD
PC1/AN9
PC0/AN8
PB7/AN7
PB6/AN6
PB5/AN5
PB4/AN4
PB3/AN3
PB2/AN2
PB1/AN1
PB0/AN0
AVCC
P10/TMOW
P13/TMIG
P40/SCK3
P41/RXD
P14/PWM
PC3/AN11 AVSS TEST OSC1 OSC2 P20/IRQ4/ADTRG P21/UD P30/SCK1 P31/SI1 P32/SO1 P33/SCK2 P34/SI2 P35/SO2 P36/STRB
P97/SEG40/CL1 P96/SEG39/CL2 P95/SEG38/DO P94/SEG37/M P93/SEG36 P92/SEG35 P91/SEG34 P90/SEG33 P87/SEG32 P86/SEG31 P85/SEG30 P84/SEG29 P83/SEG28 P82/SEG27 P81/SEG26 P80/SEG25 P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 P73/SEG20 P72/SEG19 P71/SEG18 P70/SEG17 P67/SEG16
5051 P50/WKP0/SEG1 P51/WKP1/SEG2 P52/WKP2/SEG3 P53/WKP3/SEG4 P54/WKP4/SEG5 P55/WKP5/SEG6 P56/WKP6/SEG7 P57/WKP7/SEG8 PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 P61/SEG10 P62/SEG11 P63/SEG12 P64/SEG13 P65/SEG14 P66/SEG15 P60/SEG9 P37/CS
Figure Arrangement (FP-100B, TFP-100B: View)
P16/IRQ2/TMIC
P17/IRQ3/TMIF
P15/IRQ1/TMIB
P12/TMOFH
PC0/AN8 PC1/AN9 PC2/AN10 PC3/AN11 AVSS TEST OSC1 OSC2 P20/IRQ4/ADTRG P21/UD P30/SCK1 P31/SI1 P32/SO1 P33/SCK2 P34/SI2 P35/SO2 P36/STRB P37/CS P50/WKP0/SEG1 P51/WKP1/SEG2 P52/WKP2/SEG3 P53/WKP3/SEG4 P54/WKP4/SEG5 P55/WKP5/SEG6 P56/WKP6/SEG7 P57/WKP7/SEG8 PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 P61/SEG10 P62/SEG11 P63/SEG12 P60/SEG9 P10/TMOW P97/SEG40/CL1 P96/SEG39/CL2 P95/SEG38/DO P94/SEG37/M P93/SEG36 P92/SEG35 P91/SEG34 P90/SEG33 P87/SEG32 P86/SEG31 P85/SEG30 P84/SEG29 P83/SEG28 P82/SEG27 P81/SEG26 P80/SEG25 P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 P73/SEG20 P72/SEG19 P71/SEG18 P70/SEG17 P67/SEG16 P66/SEG15 P65/SEG14 P64/SEG13
Figure Arrangement (FP-100A: View)
P11/TMOFL
P13/TMIG
P40/SCK3
P43/IRQ0
P41/RXD
P42/TXD
PB7/AN7
PB6/AN6
PB5/AN5
PB4/AN4
PB3/AN3
PB2/AN2
PB1/AN1
PB0/AN0
AVCC
P14/PWM
1.3.2
Functions
Table outlines functions H8/3834 Series. Table Functions
Type Symbol FP-100B TFP-100B FP-100A Input Name Functions Power supply: pins should connected system power supply Ground: pins should connected system power supply Analog power supply: This power supply converter. When converter used, connect this system power supply Analog ground: This converter ground pin. should connected system power supply power supply: These power supply pins controller/ driver. built-in resistor divider provided power supply, these pins normally left open. Power supply conditions Clock pins Input This connects crystal ceramic oscillator, used input external clock. section Clock Pulse Generators, typical connection diagram. This connects 32.768-kHz crystal oscillator. section Clock Pulse Generators, typical connection diagram.
Power source pins
Input
AVCC
Input
AVSS
Input
Input
Output
Input Output
Table
Functions (cont)
Type System control
Symbol TEST
FP-100B TFP-100B FP-100A
Input Input Input
Name Functions Reset: When this driven low, chip reset Mode: This controls system clock oscillation reset state Test: This test pin, application systems. should connected External interrupt request These input pins external interrupts which there choice between rising falling edge sensing Wakeup interrupt request These input pins external interrupts that detected falling edge Clock output: This output waveforms generated timer output circuit Timer event counter input: This event input input timer counter Timer event counter input: This event input input timer counter Timer up/down select: This selects whether timer counter isused down-counting. high level selects up-counting, level down-counting. Timer event counter input: This event input input timer counter Timer output: This output waveforms generated timer output compare function
Interrupt pins
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4
Input
Input
Timer pins
TMOW
Output
TMIB
Input
TMIC
Input
Input
TMIF
Input
TMOFL
Output
Table
Functions (cont)
Type Timer pins
Symbol TMOFH
FP-100B TFP-100B FP-100A
Output
Name Functions Timer output: This output waveforms generated timer output compare function Timer capture input: This input timer input capture function 14-bit output: This output waveforms generated 14-bit Port This 8-bit input port Port This 4-bit input port Port (bit This 1-bit input port Port (bits This 3-bit port. Input output designated each means port control register (PCR4). Port This 4-bit port. Input output designated each means port control register (PCRA). Port This 8-bit port. Input output designated each means port control register (PCR1). Port This 8-bit port. Input output designated each means port control register (PCR2). Port This 8-bit port. Input output designated each means port control register (PCR3). Port This 8-bit port. Input output designated each means port control register (PCR5).
TMIG
Input
14-bit ports
Output
Input Input Input
Table
Functions (cont)
Type ports
Symbol
FP-100B TFP-100B FP-100A
Name Functions Port This 8-bit port. Input output designated each means port control register (PCR6). Port This 8-bit port. Input output designated each means port control register (PCR7). Port This 8-bit port. Input output designated each means port control register (PCR8). Port This 8-bit port. Input output designated each means port control register (PCR9). SCI1 receive data input: This SCI1 data input SCI1 send data output: This SCI1 data output SCI1 clock This SCI1 clock SCI2 receive data input: This SCI2 data input SCI2 send data output: This SCI2 data output SCI2 clock This SCI2 clock SCI2 chip select input: This controls start SCI2 transfers SCI2 strobe output: This outputs strobe pulse each time byte data transferred SCI3 receive data input: This SCI3 data input
Serial com- munication interface (SCI) STRB
Input Output Input Output Input Output
Input
Table
Functions (cont)
Type
Symbol
FP-100B TFP-100B FP-100A
Output Input
Name Functions SCI3 send data output: This SCI3 data output SCI3 clock This SCI3 clock Analog input channels These analog data input channels converter converter trigger input: This external trigger input converter common output: These common output pins segment output: These segment output pins latch clock: This display data latch clock output external segment expansion shift clock: This display data shift clock output external segment expansion serial data output: This serial display data output external segment expansion alternating signal output: This alternating signal output external segment expansion
Serial com- munication interface (SCI) converter
ADTRG
Input
controller/ driver
COM4 COM1 SEG40 SEG1
Output
Output Output
Output
Output
Output
Section
Overview
H8/300L sixteen 8-bit general registers, which also paired eight 16-bit registers. concise, optimized instruction designed high-speed operation. 2.1.1 Features
Features H8/300L listed below. General-register architecture Sixteen 8-bit general registers, also usable eight 16-bit general registers Instruction with basic instructions, including: Multiply divide instructions Powerful bit-manipulation instructions Eight addressing modes Register direct Register indirect Register indirect with displacement Register indirect with post-increment pre-decrement Absolute address Immediate Program-counter relative Memory indirect 64-kbyte address space High-speed operation frequently used instructions executed four states High-speed arithmetic logic operations 16-bit register-register subtract: 8-bit multiply: 8-bit divide: Note: These values MHz. Low-power operation modes SLEEP instruction transfer low-power operation
2.1.2
Address Space
H8/300L supports address space kbytes storing program code data. 2.8, Memory Map, details memory map. 2.1.3 Register Configuration
Figure shows register structure H8/300L CPU. There groups registers: general registers control registers.
General registers (Rn) (SP) Stack Pointer
Control registers (CR) UHUNZ Program Counter CCR: Condition Code Register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask User User
Figure Registers
2.2.1
Register Descriptions
General Registers
general registers used both data registers address registers. When used data registers, they accessed 16-bit registers R7), high bytes (R0H R7H) bytes (R0L R7L) accessed separately 8-bit registers. When used address registers, general registers accessed 16-bit registers R7). also functions stack pointer (SP), used implicitly hardware exception processing subroutine calls. When functions stack pointer, indicated figure 2.2, (R7) points stack.
Lower address side [H'0000]
Unused area (R7) Stack area
Upper address side [H'FFFF]
Figure Stack Pointer 2.2.2 Control Registers
control registers include 16-bit program counter (PC) 8-bit condition code register (CCR). Program Counter (PC): This 16-bit register indicates address next instruction will execute. instructions fetched bits word) time, least significant ignored (always regarded Condition Code Register (CCR): This 8-bit register contains internal status information, including interrupt mask half-carry (H), negative (N), zero (Z), overflow (V), carry flags. These bits read written software (using LDC, STC, ANDC, ORC, XORC instructions). flags used branching conditions conditional branching (Bcc) instructions.
7-Interrupt Mask (I): When this interrupts masked. This automatically start exception handling. interrupt mask read written software. further details, section 3.3, Interrupts. 6-User (U): used freely user. 5-Half-Carry Flag (H): When ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, NEG.B instruction executed, this flag there carry borrow cleared otherwise. flag used implicitly instructions. When ADD.W, SUB.W, CMP.W instruction executed, flag there carry borrow cleared otherwise. 4-User (U): used freely user. 3-Negative Flag (N): Indicates most significant (sign bit) result instruction. 2-Zero Flag (Z): indicate zero result, cleared indicate non-zero result. 1-Overflow Flag (V): when arithmetic overflow occurs, cleared other times. 0-Carry Flag (C): when operation execution generates carry, cleared otherwise. Used instructions, indicate carry Subtract instructions, indicate borrow Shift rotate instructions carry flag also used accumulator manipulation instructions. Some instructions leave some flag bits unchanged. Refer H8/300L Series Programming Manual action each instruction flag bits.
2.2.3
Initial Register Values
When reset, program counter (PC) initialized value stored address H'0000 vector table, other bits general registers initialized. particular, stack pointer (R7) initialized. prevent program crashes stack pointer should initialized software, first instruction executed after reset.
Data Formats
H8/300L process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, 16-bit (word) data. manipulation instructions operate 1-bit data specified byte operand arithmetic logic instructions except ADDS SUBS operate byte data. MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU bits bits), DIVXU bits bits) instructions operate word data. instructions perform decimal arithmetic adjustments byte data packed form. Each nibble byte treated decimal digit.
2.3.1
Data Formats General Registers
general register data formats shown figure 2.3.
Data Type Register
Data Format
1-bit data
don't care
1-bit data
don't care
Byte data
don't care
Byte data
don't care
Word data
Upper digit
Lower digit
4-bit data
don't care
Upper digit
Lower digit
4-bit data
don't care
Notation: RnH: Upper byte general register RnL: Lower byte general register MSB: Most significant LSB: Least significant
Figure Register Data Formats
2.3.2
Memory Data Formats
Figure indicates data formats memory. access H8/300L CPU, word data stored memory must always begin even address. word access least significant address regarded address specified, access performed preceding even address. This rule affects MOV.W instruction, also applies instruction fetching.
Data Type Address Data Format
1-bit data Byte data
Address Address Even address address Even address address Even address address
Word data
Upper bits Lower bits
Byte data (CCR) stack
CCR*
Word data stack
CCR: Condition code register Note: Ignored return
Figure Memory Data Formats When stack accessed using address register, word access should always performed. CCR, same value stored upper bits lower bits word data. return, lower bits ignored.
2.4.1
Addressing Modes
Addressing Modes
H8/300L supports eight addressing modes listed table 2.1. Each instruction uses subset these addressing modes. Table
Addressing Modes
Address Modes Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Symbol @(d:16, @Rn+ @-Rn @aa:8 @aa:16 #xx:8 #xx:16 @(d:8, @@aa:8
Absolute address Immediate Program-counter relative Memory indirect
Register Direct-Rn: register field instruction specifies 16-bit general register containing operand. Only MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU bits bits), DIVXU bits bits) instructions have 16-bit operands. Register Indirect-@Rn: register field instruction specifies 16-bit general register containing address operand memory. Register Indirect with Displacement-@(d:16, Rn): instruction second word (bytes containing displacement which added contents specified general register obtain operand address memory. This mode used only instructions. MOV.W instruction, resulting address must even.
Register Indirect with Post-Increment Pre-Decrement-@Rn+ @-Rn: Register indirect with post-increment-@Rn+ @Rn+ mode used with instructions that load registers from memory. register field instruction specifies 16-bit general register containing address operand. After operand accessed, register incremented MOV.B MOV.W. MOV.W, original contents 16-bit general register must even. Register indirect with pre-decrement-@-Rn @-Rn mode used with instructions that store register contents memory. register field instruction specifies 16-bit general register which decremented obtain address operand memory. register retains decremented value. size decrement MOV.B MOV.W. MOV.W, original contents register must even. Absolute Address-@aa:8 @aa:16: instruction specifies absolute address operand memory. absolute address bits long (@aa:8) bits long (@aa:16). MOV.B manipulation instructions 8-bit absolute addresses. MOV.B, MOV.W, JMP, instructions 16-bit absolute addresses. 8-bit absolute address, upper bits assumed (H'FF). address range H'FF00 H'FFFF (65280 65535). Immediate-#xx:8 #xx:16: instruction contains 8-bit operand (#xx:8) second byte, 16-bit operand (#xx:16) third fourth bytes. Only MOV.W instructions contain 16-bit immediate values. ADDS SUBS instructions implicitly contain value immediate data. Some manipulation instructions contain 3-bit immediate data second fourth byte instruction, specifying number. Program-Counter Relative-@(d:8, PC): This mode used instructions. 8-bit displacement byte instruction code sign-extended bits added program counter contents generate branch destination address. possible branching range -126 +128 bytes (-63 words) from current address. displacement should even number.
Memory Indirect-@@aa:8: This mode used instructions. second byte instruction code specifies 8-bit absolute address. word located this address contains branch destination address. upper bits absolute address assumed (H'00), address range from H'0000 H'00FF 255). Note that with H8/300L Series, lower address area also used vector area. 3.3, Interrupts, details vector area. address specified branch destination operand address MOV.W instruction, least significant regarded causing word access performed address preceding specified address. 2.3.2, Memory Data Formats, further information. 2.4.2 Effective Address Calculation
Table shows effective addresses calculated each addressing modes. Arithmetic logic instructions register direct addressing (1). ADD.B, ADDX, SUBX, CMP.B, AND, instructions also immediate addressing (6). Data transfer instructions addressing modes except program-counter relative memory indirect (8). manipulation instructions register direct (1), register indirect (2), absolute addressing (8bit) specify byte operand, 3-bit immediate addressing specify position that byte. BSET, BCLR, BNOT, BTST instructions also register direct addressing specify position.
Table
Effective Address Calculation
Effective Address Calculation Method Effective Address (EA)
Addressing Mode Instruction Format
Register direct,
Operand contents registers indicated rm/rn
Contents bits) register indicated
Register indirect,
Contents bits) register indicated
Register indirect with displacement, @(d:16,
disp
disp
Register indirect with post-increment, @Rn+
Contents bits) register indicated
Register indirect with pre-decrement, @-Rn
Contents bits) register indicated
Incremented decremented operand byte size, word size
Table
Effective Address Calculation (cont)
Effective Address Calculation Method Effective Address (EA)
Addressing Mode Instruction Format Absolute address @aa:8
H'FF
@aa:16
Immediate #xx:8
#xx:16
Operand 2-byte immediate data
Program-counter relative @(d:8,
contents
Sign extension
disp
disp
Table
Effective Address Calculation (cont)
Effective Address Calculation Method Effective Address (EA)
Addressing Mode Instruction Format
Memory indirect, @@aa:8
H'00
Memory contents bits)
Notation: Register field Operation field disp: Displacement IMM: Immediate data abs: Absolute address
Instruction
H8/300L Series total instructions, which grouped function table 2.3. Table
Function Data transfer Arithmetic operations Logic operations Shift manipulation Branch System control Block data transfer
Instruction
Instructions MOV, PUSH* POP*
Number Total:
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, AND, XOR, SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Bcc* JMP, BSR, JSR, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, EEPMOV
Notes: PUSH equivalent MOV.W @-SP. equivalent MOV.W @SP+, machine language also same. generic term conditional branch instructions.
functions instructions shown tables 2.11. meaning operation symbols used tables follows.
Notation
(EAd), <EAd> (EAs), <EAs> #IMM disp General register (destination) General register (source) General register Destination operand Source operand Condition code register (negative) flag (zero) flag (overflow) flag (carry) flag Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division logical logical Exclusive logical Move Logical negation (logical complement) 3-bit length 8-bit length 16-bit length Contents operand indicated effective address
2.5.1
Data Transfer Instructions
Table describes data transfer instructions. Figure shows their object code formats. Table
Instruction
Data Transfer Instructions
Size* Function (EAs) (EAd) Moves data between general registers between general register memory, moves immediate data general register. @Rn, @(d:16, Rn), @aa:16, #xx:16, @-Rn, @Rn+ addressing modes available byte word data. @aa:8 addressing mode available byte data only. @-R7 @R7+ modes require word operands. specify byte size these modes.
@SP+ Pops 16-bit general register from stack. Equivalent MOV.W @SP+,
PUSH
@-SP Pushes 16-bit general register onto stack. Equivalent MOV.W @-SP.
Note: Size: Operand size Byte Word
Certain precautions required data access. 2.9.1, Notes Data Access, details.
RmRn
@RmRn
disp
@(d:16, Rm)Rn
@Rm+Rn, @-Rm
@aa:8Rn
@aa:16Rn
#xx:8Rn
#xx:16Rn
Notation: Operation field Register field disp: Displacement abs: Absolute address IMM: Immediate data
PUSH, @SP+ @-SP
Figure Data Transfer Instruction Codes
2.5.2
Arithmetic Operations
Table describes arithmetic instructions. Table
Instruction
Arithmetic Instructions
Size* Function #IMM Performs addition subtraction data general registers, addition immediate data data general register. Immediate data cannot subtracted from data general register. Word data added subtracted only when both words general registers. #IMM Performs addition subtraction with carry borrow byte data general registers, addition subtraction immediate data data general register. Increments decrements general register Adds subtracts immediate data from data general register. immediate data must decimal adjust Decimal-adjusts (adjusts packed 4-bit BCD) addition subtraction result general register referring Performs 8-bit 8-bit unsigned multiplication data general registers, providing 16-bit result
ADDX SUBX
ADDS SUBS MULXU
DIVXU
Performs 16-bit 8-bit unsigned division data general registers, providing 8-bit quotient 8-bit remainder
#IMM Compares data general register with data another general register with immediate data, result stored CCR. Word data compared only between general registers.
Obtains two's complement (arithmetic complement) data general register
Note: Size: Operand size Byte Word
2.5.3
Logic Operations
Table describes four instructions that perform logic operations. Table
Instruction
Logic Operation Instructions
Size* Function #IMM Performs logical operation general register another general register immediate data
#IMM Performs logical operation general register another general register immediate data
#IMM Performs logical exclusive operation general register another general register immediate data
Obtains one's complement (logical complement) general register contents
Note: Size: Operand size Byte
2.5.4
Shift Operations
Table describes eight shift instructions. Table
Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR
Shift Instructions
Size* Function shift Performs arithmetic shift operation general register contents shift Performs logical shift operation general register contents rotate Rotates general register contents rotate through carry Rotates general register contents through (carry)
Notes: Size: Operand size Byte
Figure shows instruction code format arithmetic, logic, shift instructions.
ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG,
MULXU, DIVXU
ADD, ADDX, SUBX, (#XX:8)
AND, (Rm)
AND, (#xx:8)
Notation: Operation field Register field IMM: Immediate data
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
Figure Arithmetic, Logic, Shift Instruction Codes
2.5.5
Manipulations
Table describes bit-manipulation instructions. Figure shows their object code formats. Table
Instruction BSET
Bit-Manipulation Instructions
Size* Function (<bit-No.> <EAd>) Sets specified general register memory operand. number specified 3-bit immediate data lower three bits general register.
BCLR
(<bit-No.> <EAd>) Clears specified general register memory operand. number specified 3-bit immediate data lower three bits general register.
BNOT
(<bit-No.> <EAd>) (<bit-No.> <EAd>) Inverts specified general register memory operand. number specified 3-bit immediate data lower three bits general register.
BTST
(<bit-No.> <EAd>) Tests specified general register memory operand sets clears flag accordingly. number specified 3-bit immediate data lower three bits general register.
BAND
(<bit-No.> <EAd>) ANDs flag with specified general register memory operand, stores result flag.
BIAND
(<bit-No.> <EAd>)] ANDs flag with inverse specified general register memory operand, stores result flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) flag with specified general register memory operand, stores result flag.
BIOR
(<bit-No.> <EAd>)] flag with inverse specified general register memory operand, stores result flag. number specified 3-bit immediate data.
Note: Size: Operand size Byte
Table
Instruction BXOR
Bit-Manipulation Instructions (cont)
Size* Function (<bit-No.> <EAd>) XORs flag with specified general register memory operand, stores result flag.
BIXOR
[~(<bit-No.> <EAd>)] XORs flag with inverse specified general register memory operand, stores result flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Copies specified general register memory operand flag.
BILD
(<bit-No.> <EAd>) Copies inverse specified general register memory operand flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Copies flag specified general register memory operand.
BIST
(<bit-No.> <EAd>) Copies inverse flag specified general register memory operand. number specified 3-bit immediate data.
Note: Size: Operand size Byte
Certain precautions required manipulation. 2.9.2, Notes Manipulation, details.
BSET, BCLR, BNOT, BTST
Operand: register direct (Rn) No.: immediate (#xx:3) Operand: register direct (Rn) No.: register direct (Rm)
Operand: register indirect (@Rn) No.:
immediate (#xx:3)
Operand: register indirect (@Rn) No.:
register direct (Rm)
Operand: absolute (@aa:8) No.:
immediate (#xx:3)
Operand: absolute (@aa:8) No.: register direct (Rm)
BAND, BOR, BXOR, BLD,
Operand: register direct (Rn) No.: immediate (#xx:3)
Operand: register indirect (@Rn) No.:
immediate (#xx:3)
Operand: absolute (@aa:8) No.: immediate (#xx:3)
Notation: Operation field Register field abs: Absolute address IMM: Immediate data
Figure Manipulation Instruction Codes
BIAND, BIOR, BIXOR, BILD, BIST
Operand: register direct (Rn) No.: immediate (#xx:3)
Operand: register indirect (@Rn) No.:
immediate (#xx:3)
Operand: absolute (@aa:8) No.: immediate (#xx:3)
Notation: Operation field Register field abs: Absolute address IMM: Immediate data
Figure Manipulation Instruction Codes (cont)
2.5.6
Branching Instructions
Table describes branching instructions. Figure shows their object code formats. Table
Instruction
Branching Instructions
Size Function Branches designated address specified condition true. branching conditions given below. Mnemonic (BT) (BF) (BHS) (BLO) Description Always (true) Never (false) High same Carry clear (high same) Carry (low) equal Equal Overflow clear Overflow Plus Minus Greater equal Less than Greater than Less equal Condition Always Never CZ=0 CZ=1 NV=0 NV=1
Branches unconditionally specified address Branches subroutine specified address Branches subroutine specified address Returns from subroutine
disp
(@Rm)
(@aa:16)
(@@aa:8)
disp
(@Rm)
(@aa:16)
(@@aa:8)
Notation: Operation field Condition field Register field disp: Displacement abs: Absolute address
Figure Branching Instruction Codes
2.5.7
System Control Instructions
Table 2.10 describes system control instructions. Figure shows their object code formats. Table 2.10 System Control Instructions
Instruction SLEEP Size* Function Returns from exception-handling routine Causes transition from active mode power-down mode. section Power-Down Modes, details CCR, #IMM Moves immediate data general register contents condition code register Copies condition code register specified general register ANDC #IMM Logically ANDs condition code register with immediate data #IMM Logically condition code register with immediate data XORC #IMM Logically exclusive-ORs condition code register with immediate data Only increments program counter Note: Size: Operand size Byte
RTE, SLEEP,
LDC, (Rn)
Notation: Operation field Register field IMM: Immediate data
ANDC, ORC, XORC, (#xx:8)
Figure System Control Instruction Codes
2.5.8
Block Data Transfer Instruction
Table 2.11 describes block data transfer instruction. Figure 2.10 shows object code format. Table 2.11 Block Data Transfer Instruction
Instruction EEPMOV Size Function then repeat until else next; Block transfer instruction. Transfers number bytes specified R4L, from locations starting address specified locations starting address specified completion transfer, next instruction executed. @R5+ @R6+
Certain precautions required using EEPMOV instruction. 2.9.3, Notes EEPMOV Instruction, details.
Notation: Operation field
Figure 2.10 Block Data Transfer Instruction Code
Basic Operational Timing
operation synchronized system clock subclock (SUB). details these clock signals section Clock Pulse Generators. period from rising edge next rising edge called state. cycle consists states three states. cycle differs depending whether access on-chip memory on-chip peripheral modules. 2.6.1 Access On-Chip Memory (RAM, ROM)
Access on-chip memory takes place states. data width bits, allowing access byte word size. Figure 2.11 shows on-chip memory access cycle.
cycle state state
Internal address
Address
Internal read signal Internal data (read access)
Read data
Internal write signal Internal data (write access)
Write data
Figure 2.11 On-Chip Memory Access Cycle
2.6.2
Access On-Chip Peripheral Modules
On-chip peripheral modules accessed states three states. data width bits, access byte size only. This means that accessing word data, instructions must used. Figures 2.12 2.13 show on-chip peripheral module access cycle. Two-State Access On-Chip Peripheral Modules
cycle state state
Internal address
Address
Internal read signal Internal data (read access)
Read data
Internal write signal Internal data (write access)
Write data
Figure 2.12 On-Chip Peripheral Module Access Cycle (2-State Access)
Three-State Access On-Chip Peripheral Modules
cycle state state state
Internal address Internal read signal Internal data (read access) Internal write signal Internal data (write access) Write data Read data
Address
Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access)
2.7.1
States
Overview
There four states: reset state, program execution state, program halt state, exception-handling state. program execution state includes active (high-speed mediumspeed) mode subactive mode. program halt state there sleep mode, standby mode, watch mode, sub-sleep mode. These states shown figure 2.14. Figure 2.15 shows state transitions.
state
Reset state initialized. Program execution state
Active (high speed) mode executes successive program instructions high speed, synchronized system clock Active (medium speed) mode executes successive program instructions reduced speed, synchronized system clock Subactive mode executes successive program instructions reduced speed, synchronized subclock
Low-power modes
Program halt state state which some chip functions stopped conserve power
Sleep mode
Standby mode
Watch mode
Subsleep mode
Exceptionhandling state transient state entered when changes processing flow reset interrupt exception handling source. Note: section Power-Down Modes, details modes their transitions.
Figure 2.14 Operation States
Reset cleared Reset state Reset occurs Exception-handling state
Reset occurs
Reset occurs
Interrupt source
Exception- Exceptionhandling handling request complete
Program halt state SLEEP instruction executed
Program execution state
Figure 2.15 State Transitions 2.7.2 Program Execution State
program execution state executes program instructions sequence. There three modes this state, active modes (high speed medium speed) subactive mode. Operation synchronized with system clock active mode (high speed medium speed), with subclock subactive mode. section Power-Down Modes details these modes. 2.7.3 Program Halt State
program halt state there four modes: sleep mode, standby mode, watch mode, subsleep mode. section Power-Down Modes details these modes. 2.7.4 Exception-Handling State
exception-handling state transient state occurring when exception handling started reset interrupt changes normal processing flow. exception handling caused interrupt, (R7) referenced values saved stack. details interrupt handling, section Exception Handling.
2.8.1
Memory
Memory
Figure 2.16 shows H8/3832 memory map. Figure 2.17 shows H8/3833 memory map. Figure 2.18 shows H8/3834 memory map. Figure 2.19 shows H8/3835 memory map. Figure 2.20 shows H8/3836 memory map. Figure 2.21 shows H8/3837 memory map.
H'0000 Interrupt vector area H'0029 H'002A On-chip H'3FFF kbytes (16,384 bytes)
Reserved
H'F740 RAM* bytes) H'F77F
Reserved H'FB80 On-chip H'FF7F H'FF80 H'FF9F H'FFA0 Internal registers bytes) H'FFFF Note: addresses addresses after reset. 32-byte serial data buffer 1,024 bytes
Figure 2.16 H8/3832 Memory
H'0000 Interrupt vector area H'0029 H'002A kbytes (24,576 bytes) On-chip H'5FFF
Reserved
H'F740 RAM* bytes) H'F77F
Reserved H'FB80 On-chip H'FF7F H'FF80 H'FF9F H'FFA0 Internal registers bytes) H'FFFF Note: addresses addresses after reset. 32-byte serial data buffer 1,024 bytes
Figure 2.17 H8/3833 Memory
H'0000 Interrupt vector area H'0029 H'002A kbytes (32,768 bytes) On-chip
H'7FFF
Reserved
H'F740 bytes) H'F77F
Reserved H'FB80 On-chip H'FF7F H'FF80 H'FF9F H'FFA0 Internal registers bytes) H'FFFF Note: addresses addresses after reset. 32-byte serial data buffer 1,024 bytes
Figure 2.18 H8/3834 Memory
H'0000 Interrupt vector area H'0029 H'002A kbytes (40,960 bytes) On-chip
H'9FFF
Reserved
H'F740 bytes) H'F77F H'F780
On-chip
2,048 bytes
H'FF7F H'FF80 32-byte serial data buffer H'FF9F H'FFA0 Internal registers bytes) H'FFFF Note: addresses addresses after reset.
Figure 2.19 H8/3835 Memory
H'0000 Interrupt vector area H'0029 H'002A kbytes (49,152 bytes) On-chip
H'BFFF Reserved H'F740 bytes) H'F77F H'F780
On-chip
2,048 bytes
H'FF7F H'FF80 32-byte serial data buffer H'FF9F H'FFA0 Internal registers bytes) H'FFFF Note: addresses addresses after reset.
Figure 2.20 H8/3836 Memory
H'0000 Interrupt vector area H'0029 H'002A
kbytes (60,928 bytes) On-chip
H'EDFF Reserved H'F740 bytes) H'F77F H'F780
On-chip
2,048 bytes
H'FF7F H'FF80 32-byte serial data buffer H'FF9F H'FFA0 Internal registers bytes) H'FFFF Note: addresses addresses after reset.
Figure 2.21 H8/3837 Memory
2.8.2
Address Relocation
After reset, area located addresses H'F740 H'F77F. However, this area relocated setting relocation register (RLCTR) bits. relocation register explained below. relocation register (RLCTR: H'FFCF)
Initial value Read/Write RLCT1 RLCT0
RLCTR 8-bit read/write register that selects address space. Upon reset, RLCTR initialized H'00. Bits Reserved Bits Bits reserved; they always read cannot modified. Bits relocation select (RLCT1, RLCT0) Bits select address space.
RLCT1 RLCT0 Description H'F740 toH'F77F H'F940 H'F97F*
(initial value)
H'FB40 H'FB7F*2 H'FD40 H'FD7F*1,
Notes: devices with 1,024-byte RAM, RLCT1 on-chip addresses H'FB80 H'FD7F become inaccessible. devices with 2,048-byte RAM, RLCT1 value except these onchip addresses become inaccessible.
2.9.1
Application Notes
Notes Data Access
Access Empty Areas: address space H8/300L includes empty areas addition RAM, registers, areas available user. these empty areas mistakenly accessed application program, following results will occur. Data transfer from empty area transferred data will lost. This action also cause misoperate. Data transfer from empty area Unpredictable data transferred. Access Internal Registers: Internal data transfer from on-chip modules other than areas makes 8-bit data width. word access attempted these areas, following results will occur. Word access from register area Upper byte: Will written register. Lower byte: Transferred data will lost. Word access from register Upper byte: Will written upper part register. Lower byte: Unpredictable data will written lower part register. Byte size instructions should therefore used when transferring data from registers other than on-chip areas. Figure 2.22 shows data size number states which on-chip peripheral modules accessed.
Access Word Byte States H'0000 H'0029 H'002A Interrupt vector area bytes)
kbytes On-chip
H'7FFF*2
Reserved
H'F740 bytes) H'F77F
Reserved
H'FB80*3 On-chip H'FF7F H'FF80 H'FF9F H'FFA0 Internal registers bytes) H'FFFF H'FFA8 H'FFAD 32-byte serial data buffer 1,024 bytes*3
Notes: above example description H8/3834. indicated addresses area initial values after system reset. H8/3832 kbytes on-chip ROM, ending address H'3FFF. H8/3833 kbytes on-chip ROM, ending address H'5FFF. H8/3835 kbytes on-chip ROM, ending address H'9FFF. H8/3836 kbytes on-chip ROM, ending address H'BFFF. H8/3837 kbytes on-chip ROM, ending address H'EDFF. H8/3832 H8/3833 have 1,024 bytes on-chip starting address H8/3834. H8/3835, H8/3836, H8/3837 each have 2,048 bytes on-chip RAM, their starting address H'F780.
Figure 2.22 Data Size Number States Access from On-Chip Peripheral Modules
2.9.2
Notes Manipulation
BSET, BCLR, BNOT, BST, BIST instructions read byte data, modify data, then write data byte again. Special care required when using these instructions cases where registers assigned same address, case registers that include writeonly bits, when instruction accesses I/O.
Order Operation Read Modify Write Operation Read byte data designated address Modify designated read data Write altered byte data designated address
Manipulation Registers Assigned Aame Address Example Timer load register timer count manipulation Figure 2.23 shows example which timer registers share same address. When manipulation instruction accesses timer load register timer counter reloadable timer, since these registers share same address, following operations take place.
Order Operation Read Modify Write Operation Timer counter data read (one byte) modifies (sets resets) designated instruction altered byte data written timer load register
timer counter counting, value read necessarily same value timer load register. result, bits other than intended timer load register modified timer counter value.
Count clock Timer counter Reload Timer load register Read Write
Internal
Figure 2.23 Timer Configuration Example
Example When BSET instruction executed port Here BSET instruction executed designating port designated input pins, with low-level signal input high-level signal remaining pins, P30, output pins output low-level signals. this example, BSET instruction used change high-level output. Prior executing BSET]
Input/output state PCR3 PDR3 Input level Input High level Output level Output level Output level Output level Output level Output level
BSET instruction executed] BSET @PDR3 BSET instruction executed designating port
After executing BSET]
Input/output state PCR3 PDR3 Input level Input High level Output level Output level Output level Output level Output level Output High level
Explanation BSET operates] When BSET instruction executed, first reads port Since input pins, reads states (low-level high-level input). output pins, reads value PDR3. this example PDR3 value H'80, value read H'40. Next, sets read data changing PDR3 data H'41. Finally, writes this value (H'41) PDR3, completing execution BSET.
result this operation, PDR3 becomes outputs high-level signal. However, bits PDR3 with different values. avoid this problem, store copy PDR3 data work area memory. Perform manipulation data work area, then write this data PDR3. Prior executing BSET] MOV. MOV. MOV. #80, R0L, R0L,
Input/output state PCR3 PDR3 RAM0 Input level
@RAM0 @PDR3
Input High level
PDR3 value (H'80) written work area memory (RAM0) well PDR3.
Output level
Output level
Output level
Output level
Output level
Output level
BSET instruction executed] BSET @RAM0 BSET instruction executed designating PDR3 work area (RAM0).
After executing BSET] MOV. MOV. @RAM0, R0L, @PDR3
Input/output state PCR3 PDR3 RAM0 Input level Input High level
work area (RAM0) value written PDR3.
Output level
Output level
Output level
Output level
Output level
Output High level
Manipulation Register Containing Write-Only Example When BCLR instruction executed PCR3 port this example, port control register PCR3 accessed BCLR instruction. examples above, input pins, with low-level signal input high-level signal P36. remaining pins, P30, output pins that output low-level signals. this example, BCLR instruction used change input port. assumed that high-level signal will input this input pin. Prior executing BCLR]
Input/output state PCR3 PDR3 Input level Input High level Output level Output level Output level Output level Output level Output level
BCLR instruction executed] BCLR @PCR3 BCLR instruction executed designating PCR3.
After executing BCLR]
Input/output state PCR3 PDR3 Output level Output High level Output level Output level Output level Output level Output level Input High level
Explanation BCLR operates] When BCLR instruction executed, first reads PCR3. Since PCR3 write-only register, reads value H'FF, even though PCR3 value actually H'3F. Next, clears read data changing data H'FE. Finally, this value (H'FE) written PCR3 BCLR instruction execution ends.
result this operation, PCR3 becomes making input port. However, bits PCR3 change that change from input pins output pins. avoid this problem, store copy PCR3 data work area memory. Perform manipulation data work area, then write this data PCR3. Prior executing BCLR] MOV. MOV. MOV. #3F, R0L, R0L,
Input/output state PCR3 PDR3 RAM0 Input level
@RAM0 @PCR3
Input High level
PCR3 value (H'3F) written work area memory (RAM0) well PCR3.
Output level
Output level
Output level
Output level
Output level
Output level
BCLR instruction executed] BCLR @RAM0 BCLR instruction executed designating PCR3 work area (RAM0).
After executing BCLR] MOV. MOV. @RAM0, R0L, @PCR3
Input/output state PCR3 PDR3 RAM0 Input level Input High level
work area (RAM0) value written PCR3.
Output level
Output level
Output level
Output level
Output level
Output High level
Table 2.12 lists registers that share same address, table 2.13 lists registers that contain write-only bits.
Table 2.12 Registers with shared addresses
Register Name Timer counter timer load register Timer counter timer load register Port data register Port data register Port data register Port data register Port data register Port data register Port data register Port data register Port data register Port data register Abbreviation TCB/TLB TCC/TLC PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA Address H'FFB3 H'FFB5 H'FFD4 H'FFD5 H'FFD6 H'FFD7 H'FFD8 H'FFD9 H'FFDA H'FFDB H'FFDC H'FFDD
Note: These port registers used also input.
Table 2.13 Registers with write-only bits
Register Name Port control register Port control register Port control register Port control register Port control register Port control register Port control register Port control register Port control register Port control register Timer control register control register data register data register Abbreviation PCR1 PCR2 PCR3 PCR4 PCR5 PCR6 PCR7 PCR8 PCR9 PCRA TCRF PWCR PWDRU PWDRL Address H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FFEA H'FFEB H'FFEC H'FFED H'FFB6 H'FFD0 H'FFD1 H'FFD2
2.9.3
Notes EEPMOV Instruction
EEPMOV instruction block data transfer instruction. moves number bytes specified from address specified address specified
When setting make sure that final destination address R4L) does exceed H'FFFF. value must change from H'FFFF H'0000 during execution instruction.
H'FFFF allowed
Section Exception Handling
Overview
Exception handling performed H8/3834 Series when reset interrupt occurs. Table shows priorities these types exception handling. Table
Priority High
Exception Handling Types Priorities
Exception Source Reset Interrupt Time Start Exception Handling Exception handling starts soon reset state cleared When interrupt requested, exception handling starts after execution present instruction exception handling progress completed
3.2.1
Reset
Overview
reset highest-priority exception. internal state registers onchip peripheral modules initialized. 3.2.2 Reset Sequence
soon goes low, processing stopped H8/3834 enters reset state. make sure chip reset properly, observe following precautions. power Hold until clock pulse generator output stabilizes. Resetting during operation: Hold least system clock cycles. high level, reset exception handling begins when held given period, then returned high level. low, however, when held given period then returned high level, reset cleared immediately. First must from high, then after 8,192 clock cycles reset cleared reset exception handling begins.
Reset exception handling takes place follows. internal state registers on-chip peripheral modules initialized, with condition code register (CCR) loaded from reset exception handling vector address (H'0000 H'0001), after which program starts executing from address indicated When system power turned off, should held low. Figures show reset sequence.
Reset cleared Program initial instruction prefetch Vector fetch Internal processing High
Internal address Internal read signal Internal write signal Internal data (16-bit)
Reset exception handling vector address (H'0000) Program start address First instruction program
Figure Reset Sequence (when High)
Reset cleared Vector fetch Internal processing Program initial instruction prefetch
8,192 clock cycles Internal address Internal read signal Internal write signal Internal data (16-bit)
Reset exception handling vector address (H'0000) Program start address First instruction program
Figure Reset Sequence (when Low) 3.2.3 Interrupt Immediately after Reset
After reset, interrupt were accepted before stack pointer (SP: initialized, would pushed onto stack correctly, resulting program runaway. prevent this, immediately after reset exception handling interrupts masked. this reason, initial program instruction always executed immediately after reset. This instruction should initialize stack pointer (e.g. MOV.W #xx: SP).
3.3.1
Interrupts
Overview
interrupt sources include external interrupts (WKP0 WKP7, IRQ0 IRQ4), internal interrupts from on-chip peripheral modules. Table shows interrupt sources, their priorities, their vector addresses. When more than interrupt requested, interrupt with highest priority processed. interrupts have following features: Both internal external interrupts masked CCR. When this interrupt request flags interrupts accepted. external interrupt pins IRQ0 IRQ4 each independently either rising edge sensing falling edge sensing. Table
Priority High
Interrupt Sources Priorities
Interrupt Source IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 WKP6 SCI1 Timer Timer Interrupt Reset IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 SCI1 transfer complete Timer overflow Timer overflow Timer overflow underflow H'0014 H'0015 H'0016 H'0017 H'0018 H'0019 H'001A H'001B Vector Number Vector Address H'0000 H'0001 H'0008 H'0009 H'000A H'000B H'000C H'000D H'000E H'000F H'0010 H'0011 H'0012 H'0013
Timer
Table
Priority High
Interrupt Sources Priorities (cont)
Interrupt Source Timer Interrupt Timer compare match Timer overflow Timer Timer compare match Timer overflow Timer Timer input capture Timer overflow SCI2 SCI2 transfer complete SCI2 transfer abort SCI3 SCI3 transmit SCI3 transmit data empty SCI3 receive data full SCI3 overrun error SCI3 framing error SCI3 parity error converter conversion Direct transfer H'0026 H'0027 H'0028 H'0029 H'0024 H'0025 H'0022 H'0023 H'0020 H'0021 H'001E H'001F Vector Number Vector Address H'001C H'001D
(SLEEP instruction executed)
Note: Vector addresses H'0002 H'0007 reserved cannot used.
3.3.2
Interrupt Control Registers
Table lists registers that control interrupts. Table Interrupt Control Registers
Abbreviation IEGR IENR1 IENR2 IRR1 IRR2 IWPR R/W* R/W* R/W* Initial Value H'E0 H'00 H'00 H'20 H'00 H'00 Address H'FFF2 H'FFF3 H'FFF4 H'FFF6 H'FFF7 H'FFF9
Register Name edge select register Interrupt enable register Interrupt enable register Interrupt request register Interrupt request register Wakeup interrupt request register
Note: Write enabled only writing clear flag.
Edge Select Register (IEGR)
Initial value Read/Write IEG4 IEG3 IEG2 IEG1 IEG0
IEGR 8-bit read/write register, used designate whether pins IRQ0 IRQ4 rising edge sensing falling edge sensing. Bits 5-Reserved Bits: Bits reserved; they always read cannot modified. 4-IRQ4 Edge Select (IEG4): selects input sensing IRQ4/ADTRG.
IEG4 Description Falling edge IRQ4/ADTRG input detected Rising edge IRQ4/ADTRG input detected (initial value)
3-IRQ3 Edge Select (IEG3): selects input sensing IRQ3/TMIF.
IEG3 Description Falling edge IRQ3/TMIF input detected Rising edge IRQ3/TMIF input detected (initial value)
2-IRQ2 Edge Select (IEG2): selects input sensing IRQ2/TMIC.
IEG2 Description Falling edge IRQ2/TMIC input detected Rising edge IRQ2/TMIC input detected (initial value)
1-IRQ1 Edge Select (IEG1): selects input sensing IRQ1/TMIB.
IEG1 Description Falling edge IRQ1/TMIB input detected Rising edge IRQ1/TMIB input detected (initial value)
0-IRQ0 Edge Select (IEG0): selects input sensing IRQ0.
IEG0 Description Falling edge IRQ0 input detected Rising edge IRQ0 input detected (initial value)
Interrupt Enable Register (IENR1)
IENTA Initial value Read/Write IENS1 IENWP IEN4 IEN3 IEN2 IEN1 IEN0
IENR1 8-bit read/write register that enables disables interrupt requests. 7-Timer Interrupt Enable (IENTA): enables disables timer overflow interrupt requests.
IENTA Description Disables timer interrupts Enables timer interrupts (initial value)
6-SCI1 Interrupt Enable (IENS1): enables disables SCI1 transfer complete interrupt requests.
IENS1 Description Disables SCI1 interrupts Enables SCI1 interrupts (initial value)
5-Wakeup Interrupt Enable (IENWP): enables disables WKP7 WKP0 interrupt requests.
IENWP Description Disables interrupt requests from Enables interrupt requests from (initial value)
Bits 0-IRQ4 IRQ0 Interrupt Enable (IEN4 IEN0): Bits enable disable IRQ4 IRQ0 interrupt requests.
IENn Description Disables interrupt request IRQn Enables interrupt request IRQn (initial value)
Interrupt Enable Register (IENR2)
IENDT Initial value Read/Write IENAD IENS2 IENTG IENTFH IENTFL IENTC IENTB
IENR2 8-bit read/write register that enables disables interrupt requests. 7-Direct Transfer Interrupt Enable (IENDT): enables disables direct transfer interrupt requests.
IENDT Description Disables direct transfer interrupt requests Enables direct transfer interrupt requests (initial value)
6-A/D Converter Interrupt Enable (IENAD): enables disables converter interrupt requests.
IENAD Description Disables converter interrupt requests Enables converter interrupt requests (initial value)
5-SCI2 Interrupt Enable (IENS2): enables disables SCI2 transfer complete transfer abort interrupt requests.
IENS2 Description Disables SCI2 interrupts Enables SCI2 interrupts (initial value)
4-Timer Interrupt Enable (IENTG): enables disables timer input capture overflow interrupt requests.
IENTG Description Disables timer interrupts Enables timer interrupts (initial value)
3-Timer Interrupt Enable (IENTFH): enables disables timer compare match overflow interrupt requests.
IENTFH Description Disables timer interrupts Enables timer interrupts (initial value)
2-Timer Interrupt Enable (IENTFL): enables disables timer compare match overflow interrupt requests.
IENTFL Description Disables timer interrupts Enables timer interrupts (initial value)
1-Timer Interrupt Enable (IENTC): enables disables timer overflow underflow interrupt requests.
IENTC Description Disables timer interrupts Enables timer interrupts (initial value)
0-Timer Interrupt Enable (IENTB): enables disables timer overflow underflow interrupt requests.
IENTB Description Disables timer interrupts Enables timer interrupts (initial value)
SCI3 interrupt control covered 10.4.2, description serial control register
Interrupt request register (IRR1)
IRRTA Initial value Read/Write R/W* IRRS1 R/W* IRRI4 R/W* IRRI3 R/W* IRRI2 R/W* IRRI1 R/W* IRRI0 R/W*
Note: Only write flag clearing possible.
IRR1 8-bit read/write register, which corresponding when timer SCI1, IRQ0 interrupt requested. flags cleared automatically when interrupt accepted. necessary write clear each flag. 7-Timer Interrupt Request Flag (IRRTA)
IRRTA Description Clearing conditions: When IRRTA cleared writing (initial value)
Setting conditions: When timer counter value overflows (goes from H'FF H'00)
6-SCI1 Interrupt Request Flag (IRRS1)
IRRS1 Description Clearing conditions: When IRRS1 cleared writing Setting conditions: When SCI1 transfer completed (initial value)
5-Reserved Bit: reserved; always read cannot modified. Bits 0-IRQ4 IRQ0 Interrupt Request Flags (IRRI4 IRRI0)
IRRIn Description Clearing conditions: When IRRIn cleared writing IRRIn (initial value)
Setting conditions: IRRIn when IRQn interrupt input, designated signal edge detected
Interrupt Request Register (IRR2)
IRRDT Initial value Read/Write R/W* IRRAD R/W* IRRS2 R/W* IRRTG R/W* IRRTFH R/W* IRRTFL R/W* IRRTC R/W* IRRTB R/W*
Note: Only write flag clearing possible.
IRR2 8-bit read/write register, which corresponding when direct transfer, converter, SCI2, timer timer timer timer timer interrupt requested. flags cleared automatically when interrupt accepted. necessary write clear each flag. 7-Direct Transfer Interrupt Request Flag (IRRDT)
IRRDT Description Clearing conditions: When IRRDT cleared writing (initial value)
Setting conditions: When DTON direct transfer made immediately after SLEEP instruction executed
6-A/D Converter Interrupt Request Flag (IRRAD)
IRRAD Description Clearing conditions: When IRRAD cleared writing Setting conditions: When conversion completed ADSF reset (initial value)
5-SCI2 Interrupt Request Flag (IRRS2)
IRRS2 Description Clearing conditions: When IRRS2 cleared writing Setting conditions: When SCI2 transfer completed aborted (initial value)
4-Timer Interrupt Request Flag (IRRTG)
IRRTG Description Clearing conditions: When IRRTG cleared writing (initial value)
Setting conditions: When TMIG TMIG input designated signal edge detected
3-Timer Interrupt Request Flag (IRRTFH)
IRRTFH Description Clearing conditions: When IRRTFH cleared writing (initial value)
Setting conditions: When counter matches output compare register 8-bit timer mode, when 16-bit counter (TCFL, TCFH) matches output compare register (OCRFL, OCRFH) 16-bit timer mode
2-Timer Interrupt Request Flag (IRRTFL)
IRRTFL Description Clearing conditions: When IRRTFL cleared writing (initial value)
Setting conditions: When counter matches output compare register 8-bit timer mode
1-Timer Interrupt Request Flag (IRRTC)
IRRTC Description Clearing conditions: When IRRTC cleared writing (initial value)
Setting conditions: When timer counter value overflows (goes from H'FF H'00) underflows (goes from H'00 H'FF)
0-Timer Interrupt Request Flag (IRRTB)
IRRTB Description Clearing conditions: When IRRTB cleared writing (initial value)
Setting conditions: When timer counter value overflows (goes from H'FF H'00)
Wakeup Interrupt Request Register (IWPR)
IWPF7 Initial value Read/Write R/W* IWPF6 R/W* IWPF5 R/W* IWPF4 R/W* IWPF3 R/W* IWPF2 R/W* IWPF1 R/W* IWPF0 R/W*
Note: Only write flag clearing possible.
IWPR 8-bit read/write register, which corresponding when pins WKP0 wakeup input receives falling edge input. flags cleared automatically when interrupt accepted. necessary write clear each flag.
Bits 0-Wakeup Interrupt Request Flags (WKPF7 WKPF0)
IWPFn Description Clearing conditions: When IWPFn cleared writing IWPFn Setting conditions: IWPFn when wakeup interrupt input, falling edge input detected
3.3.3
External Interrupts
There external interrupts, WKP0 WKP7 IRQ4. Interrupts WKP0 WKP7: Interrupts WKP7 requested falling edge inputs pins WKP0 WKP7. When these pins designated WKP0 WKP7 pins port mode register (PMR5) falling edge input detected, corresponding wakeup interrupt request register (IWPR) requesting interrupt. Wakeup interrupt requests disabled clearing IENWP IENR1 also possible mask interrupts setting
When interrupt exception handling request received interrupts WKP0 WKP7, vector number interrupts WKP0 WKP7 Since eight interrupts assigned same vector number, interrupt source must determined exception handling routine. Interrupts IRQ0 IRQ4: Interrupts IRQ0 IRQ4 requested into pins inputs IRQ0 IRQ4. These interrupts detected either rising edge sensing falling edge sensing, depending settings bits IEG0 IEG4 edge select register (IEGR). When these pins designated pins IRQ0 IRQ4 port mode registers (PMR1 PMR2) designated edge input, corresponding IRR1 requesting interrupt. Interrupts IRQ0 IRQ4 disabled clearing bits IEN0 IEN4 IENR1 interrupts masked setting When IRQ4 interrupt exception handling initiated, Vector numbers assigned interrupts IRQ0 IRQ4. order priority from IRQ0 (high) IRQ4 (low). Table gives details. 3.3.4 Internal Interrupts
There internal interrupts that requested on-chip peripheral modules. When peripheral module requests interrupt, corresponding IRR1 IRR2 Individual interrupt requests disabled clearing corresponding IENR1 IENR2 interrupts masked setting When internal interrupt request accepted, Vector numbers assigned these interrupts. Table shows order priority interrupts from on-chip peripheral modules. 3.3.5 Interrupt Operations
Interrupts controlled interrupt controller. Figure shows block diagram interrupt controller. Figure shows flow interrupt acceptance. Interrupt operation described follows. When interrupt condition while interrupt enable register interrupt request signal sent interrupt controller. When interrupt controller receives interrupt request, sets interrupt request flag. From among interrupts with interrupt request flags interrupt controller selects interrupt request with highest priority holds others pending. (Refer table list interrupt priorities.) interrupt controller checks CCR. selected interrupt request accepted; interrupt request held pending.
interrupt accepted, after processing current instruction completed, both pushed onto stack. state stack this time shown figure 3.5. value pushed onto stack address first instruction executed upon return from interrupt handling. masking further interrupts. vector address corresponding accepted interrupt generated, interrupt handling routine located address indicated contents vector address executed. Notes: When disabling interrupts clearing bits interrupt enable register, when clearing bits interrupt request register, always while interrupts masked above clear operations performed while result conflict arises between clear instruction interrupt request, exception processing interrupt will executed after clear instruction been executed.
Interrupt controller
External internal interrupts
Priority decision logic
Interrupt request
External interrupts internal interrupt enable signals
(CPU)
Figure Block Diagram Interrupt Controller
Program execution state
IRRIO IENO
IRRI1 IEN1
IRRI2 IEN2
IRRDT IENDT
contents saved contents saved Branch interrupt handling routine
Notation: Program counter CCR: Condition code register
Figure Flow Interrupt Acceptance
(R7) Stack area
(R7)
CCR* Even address
Prior start interrupt exception handling
saved stack
After completion interrupt exception handling
Notation: PCH: Upper bits program counter (PC) PCL: Lower bits program counter (PC) CCR: Condition code register Stack pointer Notes: shows address first instruction executed upon return from interrupt handling routine. Register contents must always saved restored word access, starting from even-numbered address. Ignored return from interrupt.
Figure Stack State after Completion Interrupt Exception Handling Figure shows typical interrupt sequence where program area on-chip stack area on-chip RAM.
Interrupt accepted Instruction prefetch Internal processing Stack access Vector fetch Prefetch instruction Internal interrupt-handling routine processing (10)
Interrupt level decision wait instruction
Interrupt request signal
Internal address
Internal read signal
Internal write signal
Figure Interrupt Sequence
Internal data bits)
Instruction prefetch address (Instruction executed. Address saved contents, becoming return address.) (2)(4) Instruction code (not executed) Instruction prefetch address (Instruction executed.) Vector address Starting address interrupt-handling routine (contents vector address) (10) First instruction interrupt-handling routine
3.3.6
Interrupt Response Time
Table shows number wait states after interrupt request flag until first instruction interrupt handler executed. Table
Item Waiting time completion executing instruction* Saving stack Vector fetch Instruction fetch Internal processing Total Note: including EEPMOV instruction.
Interrupt Wait States
States
3.4.1
Application Notes
Notes Stack Area
When word data accessed H8/3834 Series, least significant address regarded Access stack always takes place word size, stack pointer (SP: should never indicate address. PUSH (MOV.W @-SP) (MOV.W @SP+, save restore register values. Setting address cause program crash. example shown figure 3.7.
H'FEFC H'FEFD H'FEFF
instruction H'FEFF
MOV. R1L, @-R7 Contents lost
Stack accessed beyond
Notation: PCH: Upper byte program counter PCL: Lower byte program counter R1L: General register Stack pointer
Figure Operation when Address When contents saved stack during interrupt exception handling restored when executed, this also takes place word size. Both upper lower bytes word data saved stack; return, even address contents restored while address contents ignored. 3.4.2 Notes Rewriting Port Mode Registers
When port mode register rewritten switch functions external interrupt pins, following points should observed. When external interrupt function switched rewriting port mode register that controls these pins (IRQ4 IRQ0, WKP7 WKP0), interrupt request flag time function switched, even valid interrupt input pin. sure clear interrupt request flag after switching functions. Table shows conditions under which interrupt request flags this way.
Table
Conditions under which Interrupt Request Flag
Conditions IRRI3 IRRI2 IRRI1 IRRI0 When PMR2 IRQ4 changed from while IRQ4 IEGR IEG4 When PMR2 IRQ4 changed from while IRQ4 IEGR IEG4 When PMR1 IRQ3 changed from while IRQ3 IEGR IEG3 When PMR1 IRQ3 changed from while IRQ3 IEGR IEG3 When PMR1 IRQ2 changed from while IRQ2 IEGR IEG2 When PMR1 IRQ2 changed from while IRQ2 IEGR IEG2 When PMR1 IRQ1 changed from while IRQ1 IEGR IEG1 When PMR1 IRQ1 changed from while IRQ1 IEGR IEG1 When PMR2 IRQ0 changed from while IRQ0 IEGR IEG0 When PMR2 IRQ0 changed from while IRQ0 IEGR IEG0
Interrupt Request Flags IRR1 IRRI4
IWPR
IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0
When PMR5 WKP7 changed from while When PMR5 WKP6 changed from while When PMR5 WKP5 changed from while When PMR5 WKP4 changed from while When PMR5 WKP3 changed from while When PMR5 WKP2 changed from while When PMR5 WKP1 changed from while When PMR5 WKP0 changed from while
Figure shows procedure setting port mode register clearing interrupt request flag. When switching function, mask interrupt before setting port mode register. After accessing port mode register, execute least instruction (e.g., NOP), then clear interrupt request flag from instruction clear flag executed immediately after port mode register access without executing intervening instruction, flag will cleared. alternative method avoid setting interrupt request flags when functions switched keeping pins high level that conditions table occur.
Interrupts masked. (Another possibility disable relevant interrupt interrupt enable register
port mode register Execute instruction Clear interrupt request flag After setting port mode register bit, first execute least instruction (e.g., NOP), then clear interrupt request flag
Interrupt mask cleared
Figure Port Mode Register Setting Interrupt Request Flag Clearing Procedure
Section Clock Pulse Generators
Overview
Clock oscillator circuitry (CPG: clock pulse generator) provided on-chip, including both system clock pulse generator subclock pulse generator. system clock pulse generator consists system clock oscillator system clock dividers. subclock pulse generator consists subclock oscillator circuit subclock divider. 4.1.1 Block Diagram
Figure shows block diagram clock pulse generators.
System clock oscillator
System clock divider (1/2)
(fOSC System clock pulse generator
System clock divider (1/8)
Prescaler bits)
/8192
Subclock oscillator
Subclock divider (1/2, 1/4, 1/8)
Subclock pulse generator
Prescaler bits)
/128
Figure Block Diagram Clock Pulse Generators 4.1.2 System Clock Subclock
basic clock signals that drive on-chip peripheral modules SUB. Four clock signals have names: system clock, subclock, oscillator clock, watch clock. clock signals available peripheral modules /16, /32, /64, /128, /256, /512, /1024, /2048, /4096, /8192, W/2, W/4, W/8, W/16, W/32, W/64, W/128. clock requirements differ from module another.
System Clock Generator
Clock pulse supplied system clock divider either connecting crystal ceramic oscillator, providing external clock input. Connecting Crystal Oscillator: Figure shows typical method connecting crystal oscillator.
±20% ±20%
Figure Typical Connection Crystal Oscillator Figure shows equivalent circuit crystal oscillator. oscillator having characteristics given table should used.
Figure Equivalent Circuit Crystal Oscillator Table Crystal Oscillator Parameters
Frequency (MHz) (max) (max)
Connecting Ceramic Oscillator: Figure shows typical method connecting ceramic oscillator.
±20% ±10% ±10% Ceramic oscillator: Murata
Figure Typical Connection Ceramic Oscillator Notes Board Design: When generating clock pulses connecting crystal ceramic oscillator, careful attention following points. Avoid running signal lines close oscillator circuit, since oscillator adversely affected induction currents. (See figure 4.5.) board should designed that oscillator load capacitors located close possible pins OSC1 OSC2.
avoided
Signal Signal
Figure Board Design Oscillator Circuit
External Clock Input Method: Connect external clock signal OSC1, leave OSC2 open. Figure shows typical connection.
External clock input
Open
Figure External Clock Input (Example)
Frequency Duty cycle Oscillator Clock OSC)
Subclock Generator
Connecting 32.768-kHz Crystal Oscillator: Clock pulses supplied subclock divider connecting 32.768-kHz crystal oscillator, shown figure 4.7. Following same connection precautions mentioned section 4.2.3, Notes Board Design.
(typ.)
Figure Typical Connection 32.768-kHz Crystal Oscillator
Figure shows equivalent circuit 32.768-kHz crystal oscillator.
32.768 Crystal oscillator: MX38T (Nihon Denpa Kogyo)
Figure Equivalent Circuit 32.768-kHz Crystal Oscillator Inputting external clock (H8/3832S, H8/3833S, H8/3834S, H8/3835S, H8/3836S, H8/3837S only) Circuit configuration external clock input pin. should left open. example connection this case shown figure 4.9.
External clock input
Open
Figure Example Connection when Inputting External Clock
External clock Input square waveform pin. When using CPU, timer timer timer LCD, with subclock clock selected, stop clock supply pin.
Figure 4.10 External Subclock Timing characteristics timing external clock input shown table 4.2. Table Characteristics Timing
AVCC AVSS -20°C 75°C, unless otherwise specified, including subactive mode)
Applicable Symbol Test Conditions Values Unit Notes Figure 4.10
Item Input high voltage Input voltage External subclock rise time External subclock fall time
-0.3 -0.3 12.0 12.0 32.768
+0.3
Figure 4.10
External subclock oscillation frequency External subclock high width External subclock width
Figure 4.10
Connection when Using Subclock: When subclock used, connect leave open, shown figure 4.9.
Open
Figure Connection when Using Subclock
Prescalers
H8/3834 Series equipped with on-chip prescalers having different input clocks (prescaler prescaler Prescaler 13-bit counter using system clock input clock. prescaled outputs provide internal clock signals on-chip peripheral modules. Prescaler 5-bit counter using 32.768-kHz signal divided (W/4) input clock. prescaled outputs used timer time base timekeeping. Prescaler (PSS): Prescaler 13-bit counter using system clock input clock. incremented once clock period. Prescaler initialized H'0000 reset, starts counting exit from reset state. standby mode, watch mode, subactive mode, subsleep mode, system clock pulse generator stops. Prescaler also stops initialized H'0000. cannot read write prescaler output from prescaler shared timer timer timer timer timer SCI1, SCI2, SCI3, converter, controller, 14-bit PWM. divider ratio separately each on-chip peripheral function. active (medium-speed) mode clock input prescaler OSC/16. Prescaler (PSW): Prescaler 5-bit counter using 32.768 signal divided (W/4) input clock. Prescaler initialized H'00 reset, starts counting exit from reset state. Even standby mode, watch mode, subactive mode, subsleep mode, prescaler continues functioning long clock signals supplied pins
Prescaler reset setting bits TMA3 TMA2 timer mode register (TMA). Output from prescaler used drive timer which case timer functions time base timekeeping.
Note Oscillators
Oscillator characteristics both masked ZTATversions closely related board design should carefully evaluated user, referring examples shown this section. Oscillator circuit constants will differ depending oscillator element, stray capacitance interconnecting circuit, other factors. Suitable constants should determined consultation with oscillator element manufacturer. Design circuit that oscillator element never receives voltages exceeding maximum rating.
Section Power-Down Modes
Overview
H8/3834 Series seven modes operation after reset. These include power-down modes, which power dissipation significantly reduced. Table gives summary seven operation modes. Table Operation Modes
Description runs system clock, executing program instructions high speed runs system clock, executing program instructions reduced speed runs subclock, executing program instructions reduced speed halts. On-chip peripheral modules continue operate system clock. halts. Timer timer timer controller/driver continue operate subclock. halts. time-base function timer controller/driver continue operate subclock. on-chip peripheral modules stop operating
Operating Mode Active (high-speed) mode Active (medium-speed) mode Subactive mode Sleep mode Subsleep mode Watch mode Standby mode
above operating modes except active (high-speed) mode referred power-down modes. this section active modes (high-speed medium-speed) referred collectively active mode. Figure shows transitions among these operation modes. Table indicates internal states each mode.
Program execution state Reset state LSON MSON Program halt state
Program halt state
Active (high-speed) mode
LSON MSON Active (medium-speed) mode
SSBY TMA3
Watch mode
Standby mode
SSBY TMA3 LSON
SSBY LSON
Sleep mode
LSON TMA3
SLEEP instruction
SSBY LSON TMA3
Subactive mode
Subsleep mode
Transition caused exception handling
Power-down mode
transition between different modes cannot made occur simply because interrupt request generated. Make sure that interrupt accepted interrupt handling performed. Details mode transition conditions given explanations each mode, sections through 5.8. Notes: Timer interrupt, interrupt, interrupts Timer interrupt, timer interrupt, timer interrupt, interrupts, WKP0 WKP7 interrupts interrupts interrupt, interrupt, WKP0 WKP7 interrupts
Figure Operation Mode Transition Diagram
Table
Internal State Each Operation Mode
Active Mode
Function Subclock oscillator operation Registers External interrupts IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 WKP0 WKP1 WKP2 WKP3 WKP4 WKP5 WKP6 WKP7 Peripheral Timer module Timer functions Timer Timer Timer SCI1 SCI2 SCI3 Notes:
High Speed Functions
Medium Speed Functions Functions Functions
Sleep Mode Functions Functions Halted Retained
Watch Mode Halted Functions Halted Retained
Subactive Subsleep Mode Mode Halted Functions Functions Halted Functions Halted Retained
Standby Mode Halted Functions Halted Retained Retained*1
System clock oscillator Functions Instructions Functions
Functions
Functions
Functions
Functions Retained*6
Functions
Functions
Functions Retained*6
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions*5 Functions*5 Functions*5 Retained Retained Retained Retained Functions/ Functions/ Retained*2 Retained*2 Retained Retained Functions/ Functions/ Retained*3 Retained*3
Functions
Functions
Functions
Retained Reset
Retained Reset Retained Retained
Retained Reset Retained Retained
Retained Reset Retained Retained
Functions Functions Functions
Functions Functions Functions
Retained Functions Functions
Retained Retained
Functions/ Functions/ Functions/ Retained Retained*4 Retained*4 Retained*4
Register contents held; high-impedance output. Functions only external clock internal clock selected; otherwise halted retained. Functions only internal clock selected; otherwise halted retained. Functions only internal clock selected; otherwise halted retained. Functions when timekeeping time-base function selected. External interrupt requests ignored. interrupt request register contents affected.
5.1.1
System Control Registers
operation mode selected using system control registers described table 5.3. Table
Name System control register System control register
System Control Register
Abbreviation SYSCR1 SYSCR2 Initial Value H'07 H'E0 Address H'FFF0 H'FFF1
System Control Register (SYSCR1)
SSBY Initial value Read/Write STS2 STS1 STS0 LSON
SYSCR1 8-bit read/write register control power-down modes. 7-Software Standby (SSBY): This designates transition standby mode watch mode.
SSBY Description When SLEEP instruction executed active mode, transition made sleep mode (initial value) When SLEEP instruction executed subactive mode, transition made subsleep mode. When SLEEP instruction executed active mode, transition made standby mode watch mode. When SLEEP instruction executed subactive mode, transition made watch mode.
Bits 4-Standby Timer Select (STS2 STS0): These bits designate time peripheral modules wait stable clock operation after exiting from standby mode watch mode active mode interrupt. designation should made according clock frequency that waiting time least
STS2
STS1
STS0
Description Wait time 8,192 states Wait time 16,384 states Wait time 32,768 states Wait time 65,536 states Wait time 131,072 states (initial value)
Note: Don't care
3-Low Speed Flag (LSON): This chooses system clock subclock (SUB) operating clock when watch mode cleared. resulting operation mode depends combination other control bits interrupt input.
LSON Description operates system clock operates subclock (SUB) (initial value)
Bits 0-Reserved Bits: These bits reserved; they always read cannot modified. System Control Register (SYSCR2)
Initial value Read/Write NESEL DTON MSON
SYSCR2 8-bit read/write register power-down mode control. Bits 5-Reserved Bits: These bits reserved; they always read cannot modified. 4-Noise Elimination Sampling Frequency Select (NESEL): This selects frequency which watch clock signal generated subclock pulse generator sampled, relation oscillator clock (OSC) generated system clock pulse generator. When MHz, clear NESEL
NESEL Description Sampling rate OSC/16 Sampling rate OSC/4 (initial value)
3-Direct Transfer Flag (DTON): This designates whether make direct transitions among active (high-speed), active (medium-speed) subactive mode when SLEEP instruction executed. mode which transition made after SLEEP instruction executed depends combination this other control bits.
DTON Description When SLEEP instruction executed active mode, transition made standby mode, watch mode, sleep mode. (initial value) When SLEEP instruction executed subactive mode, transition made watch mode subsleep mode. When SLEEP instruction executed active (high-speed) mode, direct transition made active (medium-speed) mode SSBY MSON LSON subactive mode SSBY TMA3 LSON When SLEEP instruction executed active (medium-speed) mode, direct transition made active (high-speed) mode SSBY MSON LSON subactive mode SSBY TMA3 LSON When SLEEP instruction executed subactive mode, direct transition made active (high-speed) mode SSBY TMA3 LSON MSON active (medium-speed) mode SSBY TMA3 LSON MSON
2-Medium Speed Flag (MSON): After standby, watch, sleep mode cleared, this selects active (high-speed) active (medium-speed) mode.
MSON Description Operation active (high-speed) mode Operation active (medium-speed) mode (initial value)
Bits 0-Subactive Mode Clock Select (SA1 SA0): These bits select clock rate (W/2, W/4, W/8) subactive mode. cannot modified subactive mode.
Note: Don't care Description
(initial value)
5.2.1
Sleep Mode
Transition Sleep Mode
system goes from active mode sleep mode when SLEEP instruction executed while SSBY LSON bits system control register (SYSCR1) cleared sleep mode operation halted on-chip peripheral functions other than operational. register contents retained. 5.2.2 Clearing Sleep Mode
Sleep mode cleared interrupt (timer timer timer timer timer IRQ0 IRQ4, WKP0 WKP7, SCI1, SCI2, SCI3, converter) input pin. Clearing Interrupt: When interrupt requested, sleep mode cleared interrupt exception handling starts. Operation resumes active (high-speed) mode MSON SYSCR2, active (medium-speed) mode MSON Sleep mode cleared condition code register (CCR) particular interrupt disabled interrupt enable register. Clearing Input: When goes low, goes into reset state sleep mode cleared.
5.3.1
Standby Mode
Transition Standby Mode
system goes from active mode standby mode when SLEEP instruction executed while SSBY SYSCR1 LSON cleared TMA3 timer register (TMA) cleared standby mode clock pulse generator stops, on-chip peripheral modules stop functioning. long minimum required voltage applied, contents registers some on-chip peripheral registers, data on-chip RAM, retained. Data on-chip will retained long specified data retention voltage supplied. ports high-impedance state.
5.3.2
Clearing Standby Mode
Standby mode cleared interrupt (IRQ0, IRQ1, WKP0 WKP7) input pin. Clearing Interrupt: When interrupt requested, system clock pulse generator starts. After time bits STS2-STS0 SYSCR1 elapsed, stable system clock signal supplied entire chip, standby mode cleared, interrupt exception handling starts. Operation resumes active (high-speed) mode MSON SYSCR2, active (mediumspeed) mode MSON Standby mode cleared particular interrupt disabled interrupt enable register. Clearing Input: When goes low, system clock pulse generator starts. After pulse generator output stabilized, driven high, starts reset exception handling. Since system clock signals supplied entire chip soon system clock pulse generator starts functioning, should kept level until pulse generator output stabilizes. 5.3.3 Oscillator Settling Time after Standby Mode Cleared
Bits STS2 STS0 SYSCR1 should follows. When Crystal Oscillator Used table below gives settings various operating frequencies. bits STS2 STS0 waiting time least Table
STS2
Clock Frequency Settling Time (Times
STS1 STS0 Waiting Time 8,192 states 16,384 states 32,768 states 65,536 states 131,072 states 13.1 26.2 16.4 32.8 16.4 32.8 65.5 16.4 32.8 65.5 131.1 16.4 32.8 65.5 131.1 262.1
Note: Don't care
When External Clock Used values set. Normally minimum time (STS2 STS1 STS0 should set.
5.3.4
Transition Standby Mode Port States
system goes from active (high-speed medium-speed) mode standby mode when SLEEP instruction executed while SSBY SYSCR1 LSON cleared TMA3 cleared Port pins (except those with their pull-up turned enter high-impedance state when transition standby mode made. This timing shown figure 5.2.
Internal data
SLEEP instruction fetch
Next instruction fetch SLEEP instruction execution Internal processing
Port pins
Output Active (high-speed medium-speed) mode
High-impedance Standby mode
Figure Transition Standby Mode Port States
5.4.1
Watch Mode
Transition Watch Mode
system goes from active subactive mode watch mode when SLEEP instruction executed while SSBY SYSCR1 TMA3 watch mode, operation on-chip peripheral modules other than timer controller halted. controller selected operate halt. long minimum required voltage applied, contents registers some registers onchip peripheral modules, on-chip contents, retained. ports keep same states before transition.
5.4.2
Clearing Watch Mode
Watch mode cleared interrupt (timer WKP0 WKP7) input pin. Clearing Interrupt: Watch mode cleared when interrupt requested. mode which transition made depends settings LSON SYSCR1 MSON SYSCR2. both LSON MSON cleared transition active (high-speed) mode; LSON MSON transition active (medium-speed) mode; LSON transition subactive mode. When transition active mode, after time SYSCR1 bits STS2-STS0 elapsed, stable clock signal supplied entire chip, interrupt exception handling starts. Watch mode cleared particular interrupt disabled interrupt enable register. Clearing Input: Clearing same standby mode; 5.3.2, Clearing Standby Mode. 5.4.3 Oscillator Settling Time after Watch Mode Cleared
waiting time same standby mode; 5.3.3, Oscillator Settling Time after Standby Mode Cleared.
5.5.1
Subsleep Mode
Transition Subsleep Mode
system goes from subactive mode subsleep mode when SLEEP instruction executed while SSBY SYSCR1 cleared LSON SYSCR1 TMA3 subsleep mode, operation on-chip peripheral modules other than timer timer timer controller halted. long minimum required voltage applied, contents registers some registers on-chip peripheral modules, on-chip contents, retained. ports keep same states before transition.
5.5.2
Clearing Subsleep Mode
Subsleep mode cleared interrupt (timer timer timer IRQ0 IRQ4, WKP0 WKP7) input pin. Clearing Interrupt: When interrupt requested, subsleep mode cleared interrupt exception handling starts. Subsleep mode cleared particular interrupt disabled interrupt enable register. Clearing Input: Clearing same standby mode; 5.3.2, Clearing Standby Mode.
5.6.1
Subactive Mode
Transition Subactive Mode
Subactive mode entered from watch mode timer IRQ0, WKP0 WKP7 interrupt requested while LSON SYSCR1 From subsleep mode, subactive mode entered timer timer timer IRQ4, WKP0 WKP7 interrupt requested. transition subactive mode does take place particular interrupt disabled interrupt enable register. 5.6.2 Clearing Subactive Mode
Subactive mode cleared SLEEP instruction input pin. Clearing SLEEP Instruction: SLEEP instruction executed while SSBY SYSCR1 TMA3 subactive mode cleared watch mode entered. SLEEP instruction executed while SSBY LSON SYSCR1 TMA3 TMA, subsleep mode entered. Direct transfer active mode also possible; 5.8, Direct Transfer, below. Clearing Pin: Clearing same standby mode; Clearing section 5.3.2, Clearing Standby Mode. 5.6.3 Operating Frequency Subactive Mode
operating frequency subactive mode bits SYSCR2. choices W/2, W/4, W/8.
5.7.1
Active (medium-speed) Mode
Transition Active (medium-speed) Mode
MSON SYSCR2 while LSON SYSCR1 cleared transition active (medium-speed) mode results from IRQ0, IRQ1, WKP0 WKP7 interrupts standby mode, timer IRQ0, WKP0 WKP7 interrupts watch mode, interrupt sleep mode. transition active (medium-speed) mode does take place particular interrupt disabled interrupt enable register. 5.7.2 Clearing Active (medium-speed) Mode
Active (medium-speed) mode cleared SLEEP instruction input pin. Clearing SLEEP Instruction: transition standby mode takes place SLEEP instruction executed while SSBY SYSCR1 LSON SYSCR1 cleared TMA3 cleared system goes watch mode SSBY SYSCR1 TMA3 when SLEEP instruction executed. Sleep mode entered both SSBY LSON cleared when SLEEP instruction executed. Direct transfer active (high-speed) mode subactive mode also possible. 5.8, Direct Transfer, below details. Clearing Pin: When goes low, enters reset state active (medium-speed) mode cleared. 5.7.3 Operating Frequency Active (medium-speed) Mode
active (medium-speed) mode, clocked frequency active (high-speed) mode.
5.8.1
Direct Transfer
Direct Transfer Overview
execute programs three modes: active (high-speed) mode, active (m
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