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Renesas Technology Corp.
Hitachi Single-Chip Microcomputer
H8/3437 Series
H8/3437
HD6473437, HD6433437
H8/3436
HD6433436
H8/3434
HD6473434, HD6433434
H8/3437W
HD6433437W
H8/3436W
HD6433436W
H8/3434W
HD6433434W
H8/3437F-ZTATHD64F3437
H8/3437SF-ZTATHD64F3437S HD64F3434
H8/3434F-ZTATHardware Manual
ADE-602-077F Rev. 3/14/02 Hitachi, Ltd.
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
General Precautions Handling Product
Treatment Pins Note: connect anything pins. (not connected) pins either connected internal circuitry they used test pins reduce noise. something connected pins, operation guaranteed. Treatment Unused Input Pins Note: unused input pins high level. Generally, input pins CMOS products high-impedance input pins. unused pins their open states, intermediate levels induced noise vicinity, passthrough current flows internally, malfunction occur. Processing before Initialization Note: When power first supplied, product's state undefined. states internal circuits undefined until full power supplied throughout chip level input reset pin. During period where states undefined, register settings output state each also undefined. Design your system that does malfunction because processing while this undefined state. those products which have reset function, reset immediately after power supply been turned Prohibition Access Undefined Reserved Addresses Note: Access undefined reserved addresses prohibited. undefined reserved addresses used expand functions, test registers have been allocated these addresses. access these registers; system's operation guaranteed they accessed.
Preface
H8/3437 Series high-performance single-chip microcomputer that integrates peripheral functions necessary system configuration with H8/300 featuring 32-bit internal architecture core. On-chip peripheral functions include ROM, RAM, four kinds timers, serial communication interface (SCI), host interface (HIF), keyboard controller, converter, converter, ports, enabling H8/3437 Series used microcontroller embedding high-speed control systems. Flash memory (F-ZTATTM*), PROM (ZTAT®*), mask available on-chip ROM, enabling users respond quickly flexibly changing application specifications demands transition from initial full-fledged volume production. Note: F-ZTAT trademark Hitachi, Ltd. ZTAT registered trademark Hitachi, Ltd. Intended Readership: This manual intended users undertaking design application system using H8/3437 Series microcomputer. Readers using this manual require basic knowledge electrical circuits, logic circuits, microcomputers. Purpose: purpose this manual give users understanding hardware functions electrical characteristics H8/3437 Series. Details execution instructions found H8/300 Series Programming Manual, which should read conjunction with present manual.
Using this Manual: overall understanding H8/3437 Series' functions Follow Table Contents. This manual broadly divided into sections CPU, system control functions, peripheral functions, electrical characteristics. detailed understanding functions Refer separate publication H8/300 Series Programming Manual. detailed description register's function when register name known. Information addresses, contents, initialization summarized Appendix Internal Register. Note notation: Bits shown high-to-low order from left right. Related Material: latest information available Site. Please make sure that have most up-to-date information available.
User's Manuals H8/3437 Series:
Manual Title H8/3437 Series Hardware Manual H8/300 Series Programming Manual This manual ADE-602-025
Users manuals development tools:
Manual Title C/C++ Compiler, Assembler, Optimized Linkage Editor User's Manual Simulator Debugger Users Manual Hitachi Debugging Interface Users Manual Hitachi Embedded Workshop Users Manual H8S, H8/300 Series Hitachi Embedded Workshop, Hitachi Debugging Interface Users Manual ADE-702-247 ADE-702-282 ADE-702-161 ADE-702-201 ADE-702-231
Notes S-Mask Model (Single-Power-Supply Specification)
There versions H8/3437F with on-chip flash memory: dual-power-supply version single-power-supply (S-mask) version. Points noted when using H8/3437F singlepower-supply S-mask model given below.
Notes Voltage Application
must applied S-mask model (single-power-supply specification), this permanently damage device. flash memory programming power supply S-mask model (single-power-supply specification) VCC. programming power supply dual-power-supply model FVPP single-power-supply model (S-mask model) does have FVPP pin. Also, boot mode, applied dual-power-supply model, application necessary single-power-supply model (S-mask model). maximum rating +0.3 Applying voltage excess maximum rating will permanently damage device. select HN28F101 programmer setting S-mask model (single-power-supply specification). this setting made mistake, will applied STBY pin, possibly causing permanent damage device. When using PROM programmer program on-chip flash memory S-mask model (single-power-supply specification), PROM programmer that supports Hitachi microcomputer devices with 64-kbyte on-chip flash memory. Also, only specified socket adapter. Using wrong PROM programmer socket adapter damage device. following PROM programmers support S-mask model (single-power-supply specification). DATA I/O: UNISITE, 2900, 3900, etc. Minato: 1892, 1891, 1890, etc.
Product Type Names Markings
Table shows examples product type names markings H8/3437F (dual-powersupply specification) H8/3437SF (single-power-supply specification), differences flash memory programming power supply. Table Differences H8/3437F H8/3437F S-Mask Model Markings
Dual-Power-Supply Model: H8/3437F Product type name Sample markings HD64F3437F16/TF16 Single-Power-Supply Model: H8/3437F S-Mask Model HD64F3437SF16/TF16
H8/3437
64F3437F16
JAPAN
H8/3437
64F3437F16
JAPAN
printed above type name Flash memory programming power supply power supply (12.0 ±0.6 power supply (5.0 ±10%)
Differences S-Mask Model
Table shows differences between H8/3437F (dual-power-supply specification) H8/3437SF (single-power-supply specification). Table
Item Program/ erase voltage
Differences between H8/3437F H8/3437F S-Mask Model
Dual-Power-Supply Model: H8/3437F must applied from off-chip (12.0 ±0.6 Dual function power supply STBY function Writer mode On-board Boot mode User programming mode Writer mode Boot mode User programming mode 32-byte-unit programming Single-Power-Supply Model: H8/3437F S-Mask Model application required single-power-supply programming (5.0 ±10%) programming control (See section these modes)
(FWE) function Programming modes
Operating modes allowing on-board programming On-board programming unit Programming with PROM programmer
(See section these modes)
1-byte-unit programming
Select Hitachi stand-alone flash memory HN28F101 setting
Special programming mode setting required. PROM programmer that supports Hitachi microcomputer device types with 64-kbyte on-chip flash memory. (128-byte-unit fast page programming)
Setting level
Boot mode setting method User program mode setting method
Reset release after FVPP /STBY application
Reset release after above settings application Control bits software
Item Programming mode timing
Dual-Power-Supply Model: H8/3437F
tMDS tMDS: 4tcyc (min.)
Single-Power-Supply Model: H8/3437F S-Mask Model
tMDS MD1, P92, P91, tMDS: 4tcyc (min.)
Prewrite processing Programming processing register configuration Memory (block configuration)
Required before erasing Block corresponding programming address must EBR1/EBR2 registers before programming EBR1, EBR2
required Settings left required
EBR2
(128 bytes) (128 bytes) (128 bytes) (128 bytes) (512 bytes) kbyte) kbyte) kbyte) kbytes) kbytes LB1(8 kbytes)
kbyte) kbyte) kbyte) kbyte)
kbytes)
kbytes
kbytes)
kbytes)
kbytes)
kbytes)
kbytes) kbytes) kbytes) kbytes) kbytes)
Reset during operation
Drive least system clock cycles (RES pulse width tRESW min. 10tcyc)
Drive least system clock cycles (RES pulse width tRESW min. 20tcyc)
Item MDCR
Dual-Power-Supply Model: H8/3437F
MDS1 MDS0
Single-Power-Supply Model: H8/3437F S-Mask Model
EXPE MDS1 MDS0
Expanded mode enable (EXPE) WSCR
RAMS RAM0 CKDBL WMS1WMS0 CKDBL FLSHE WMS1 WMS0
Flash memory control register enable (FLSHE) FLMCR1
Flash write enable (FWE) Software write enable (SWE) FLMCR2
FLER
Flash memory error (FLER) Erase setup (ESU) Program setup (PSU) EBR1
This address used.
EBR2
Erase block register (EBR2) kbyte): H'0000 H'03FF kbyte): H'0400 H'07FF kbyte): H'0800 H'0BFF kbyte): H'0C00 H'0FFF kbytes): H'1000 H'7FFF kbytes): H'8000 H'BFFF kbytes): H'C000 H'EF7F kbytes): H'EF00 H'F77F Details concerning flash memory Electrical characteristics Registers section (Dual-PowerSupply 60-Kbyte Flash Memory Version) section Electrical Characteristics Appendix Registers section (Single-PowerSupply 60-Kbyte Flash Memory Version) section Electrical Characteristics Appendix Registers
Table shows differences development environments H8/3437F (dual-power-supply specification) H8/3437SF (single-power-supply specification). Table
Item
H8/3437F H8/3437F S-Mask Model Development Environments
Dual-Power-Supply Model: H8/3437F Single-Power-Supply Model: H8/3437F S-Mask Model Hitachi HS3008EPI60H Hitachi HS3437ECH61H Minato DATA Hitachi HS0008EASF3H Hitachi HS6400FWIW2SF
E6000 Emulator Hitachi emulator unit HS3008EPI60H User cable Programming socket adapter Adapter board Windows interface software Hitachi HS3437ECH61H Hitachi HS3434ESHF1H Hitachi HS0008EASF1H/2H Hitachi HS6400FWIW2SF
Table shows differences settings H8/3437F (dual-power-supply specification) H8/3437SF (single-power-supply specification). Table
Item Boot mode
FVPP/STBY (GND)
H8/3437F H8/3437F S-Mask Model Settings
Dual-Power-Supply Model: H8/3437F
H8/3437F
Single-Power-Supply Model: H8/3437F S-Mask Model
H8/3437SF
User programming mode
H8/3437F
There state transitions states. Transitions should implemented means register settings software.
FVPP/STBY
List Items Revised Added This Version
Section Notes S-Mask Model (Single-Power-Supply Specification) Overview Page Item Table Differences H8/3437F H8/3437F SMask Model Markings Table Features Description (see Manual details) Single-Power-Supply Model: H8/3437F Smask model sample marking amended "Other features" specifications amended. H8/3434F-ZTAT amended "Series Lineup" specifications. Notes deleted 1.3.1 Arrangement Figure Arrangement (FP-100B, TFP-100B, View) Rotated degrees left, that bottom left. Added Figure 12.5 Sample Flowchart Flowchart amended. Transmitting Serial Data Procedure description added. Descriptions deleted Note Issuance Retransmission Start Condition Note Issuance Stop Condition Countermeasure Additional Note Precautions when Clearing IRIC Flag when Using Wait Function 15.6 Application Notes 18.3.2 Notes Programming 19.6.1 Writer Mode Setting Figure 15.10 Example Analog Input Circuit Figure amended description added. Description amended Added
6.2.2 Oscillator Circuit (H8/3437SF) 12.3.2 Asynchronous Mode Section Interface [Option] 13.4 Application Notes
Section 21.1.7 Flash Memory Operating Modes
Page
Item Figure 21.2 Flash Memory Related State Transitions Figure 21.3 Boot Mode
Description (see Manual details) "SWE" amended "FLSHE". Procedure amended.
Figure 21.4 User Procedure amended. Programming Mode (Example) Note description added. Area Allocation Boot Mode Figure 21.9 Areas Boot Mode Notes Boot Mode Description amended. Amended description amended. Entire description amended. Note description added. Figure 21.22 Status Read Mode Timing Waveforms Table 21.19 Status Read Mode Return Codes Note amended
21.2.3 Erase Block Register (EBR2) 21.3.1 Boot Mode
21.4 21.4.4 21.5.1 Writer Mode Setting 21.5.3 Operation Writer Mode
21.6 Flash Memory Programming Erasing Precautions
Program with specified Description amended. voltage timing Table 21.22 Area Accessed FLSHE mode Each Mode with FLSHE amended FLSHE description deleted.
22.3.5 Application Note Electrical Characteristics
Heading number amended Entire description newly added.
23.3 Electrical Characteristics (H8/3437SF Low-Voltage Version) Function Control Register Transfer Rate Select
Table amended note added
Contents
Section
Overview. Overview. Block Diagram Assignments Functions 1.3.1 Arrangement 1.3.2 Functions
Section
Overview. 2.1.1 Features 2.1.2 Address Space. 2.1.3 Register Configuration. Register Descriptions 2.2.1 General Registers. 2.2.2 Control Registers 2.2.3 Initial Register Values Data Formats. 2.3.1 Data Formats General Registers 2.3.2 Memory Data Formats. Addressing Modes. 2.4.1 Addressing Mode. 2.4.2 Calculation Effective Address. Instruction 2.5.1 Data Transfer Instructions 2.5.2 Arithmetic Operations 2.5.3 Logic Operations 2.5.4 Shift Operations 2.5.5 Manipulations. 2.5.6 Branching Instructions. 2.5.7 System Control Instructions. 2.5.8 Block Data Transfer Instruction. States 2.6.1 Overview. 2.6.2 Program Execution State 2.6.3 Exception-Handling State 2.6.4 Power-Down State Access Timing Cycle 2.7.1 Access On-Chip Memory (RAM ROM). 2.7.2 Access On-Chip Register Field External Devices
Section
Operating Modes Address Space Overview. 3.1.1 Mode Selection 3.1.2 Mode System Control Registers System Control Register (SYSCR). Mode Control Register (MDCR) Address Space Each Operating Mode Exception Handling Overview. Reset. 4.2.1 Overview. 4.2.2 Reset Sequence 4.2.3 Disabling Interrupts after Reset. Interrupts 4.3.1 Overview. 4.3.2 Interrupt-Related Registers 4.3.3 External Interrupts 4.3.4 Internal Interrupts. 4.3.5 Interrupt Handling 4.3.6 Interrupt Response Time. 4.3.7 Precaution Note Stack Handling
Section
Section
Wait-State Controller Overview. 5.1.1 Features 5.1.2 Block Diagram. 5.1.3 Input/Output Pins. 5.1.4 Register Configuration. Register Description. 5.2.1 Wait-State Control Register (WSCR). Wait Modes.
Section
Clock Pulse Generator
Overview. 6.1.1 Block Diagram. 6.1.2 Wait-State Control Register (WSCR). Oscillator Circuit. 6.2.1 Oscillator (Generic Device). 6.2.2 Oscillator Circuit (H8/3437S). Duty Adjustment Circuit. Prescaler
Section
Ports Overview. Port 7.2.1 Overview. 7.2.2 Register Configuration Descriptions. 7.2.3 Functions Each Mode 7.2.4 Input Pull-Up Transistors. Port 7.3.1 Overview. 7.3.2 Register Configuration Descriptions. 7.3.3 Functions Each Mode 7.3.4 Input Pull-Up Transistors. Port 7.4.1 Overview. 7.4.2 Register Configuration Descriptions. 7.4.3 Functions Each Mode 7.4.4 Input Pull-Up Transistors. Port 7.5.1 Overview. 7.5.2 Register Configuration Descriptions. 7.5.3 Functions Port 7.6.1 Overview. 7.6.2 Register Configuration Descriptions. 7.6.3 Functions Port 7.7.1 Overview. 7.7.2 Register Configuration Descriptions. 7.7.3 Functions 7.7.4 Input Pull-Up Transistors. Port 7.8.1 Overview. 7.8.2 Register Configuration Descriptions. Port 7.9.1 Overview. 7.9.2 Register Configuration Descriptions. 7.9.3 Functions 7.10 Port 7.10.1 Overview. 7.10.2 Register Configuration Descriptions. 7.10.3 Functions 7.11 Port 7.11.1 Overview.
7.11.2 Register Configuration Descriptions. 7.11.3 Functions Each Mode 7.11.4 Input Pull-Up Transistors. 7.12 Port 7.12.1 Overview. 7.12.2 Register Configuration Descriptions. 7.12.3 Functions Each Mode 7.12.4 Input Pull-Up Transistors.
Section
16-Bit Free-Running Timer Overview. 8.1.1 Features 8.1.2 Block Diagram. 8.1.3 Input Output Pins 8.1.4 Register Configuration. Register Descriptions 8.2.1 Free-Running Counter (FRC) 8.2.2 Output Compare Registers (OCRA OCRB). 8.2.3 Input Capture Registers (ICRA ICRD). 8.2.4 Timer Interrupt Enable Register (TIER). 8.2.5 Timer Control/Status Register (TCSR) 8.2.6 Timer Control Register (TCR). 8.2.7 Timer Output Compare Control Register (TOCR) Interface. Operation. 8.4.1 Increment Timing 8.4.2 Output Compare Timing 8.4.3 Clear Timing 8.4.4 Input Capture Timing. 8.4.5 Timing Input Capture Flag (ICF) Setting 8.4.6 Setting Output Compare Flags (OCFA OCFB) 8.4.7 Setting Overflow Flag (OVF) Interrupts Sample Application. Application Notes 8-Bit Timers. Overview. 9.1.1 Features 9.1.2 Block Diagram. 9.1.3 Input Output Pins 9.1.4 Register Configuration.
Section
Register Descriptions 9.2.1 Timer Counter (TCNT). 9.2.2 Time Constant Registers (TCORA TCORB) 9.2.3 Timer Control Register (TCR). 9.2.4 Timer Control/Status Register (TCSR) 9.2.5 Serial/Timer Control Register (STCR) Operation. 9.3.1 TCNT Increment Timing. 9.3.2 Compare-Match Timing. 9.3.3 External Reset TCNT 9.3.4 Setting TCSR Overflow Flag (OVF). Interrupts Sample Application. Application Notes 9.6.1 Contention between TCNT Write Clear 9.6.2 Contention between TCNT Write Increment. 9.6.3 Contention between TCOR Write Compare-Match 9.6.4 Contention between Compare-Match Compare-Match 9.6.5 Increment Caused Changing Internal Clock Source.
Section Timers
10.1 Overview. 10.1.1 Features 10.1.2 Block Diagram. 10.1.3 Input Output Pins 10.1.4 Register Configuration. 10.2 Register Descriptions 10.2.1 Timer Counter (TCNT). 10.2.2 Duty Register (DTR) 10.2.3 Timer Control Register (TCR). 10.3 Operation. 10.3.1 Timer Increment. 10.3.2 Operation. 10.4 Application Notes
Section Watchdog Timer.
11.1 Overview. 11.1.1 Features 11.1.2 Block Diagram. 11.1.3 Output 11.1.4 Register Configuration. 11.2 Register Descriptions 11.2.1 Timer Counter (TCNT).
11.2.2 Timer Control/Status Register (TCSR) 11.2.3 System Control Register (SYSCR). 11.2.4 Register Access. 11.3 Operation. 11.3.1 Watchdog Timer Mode 11.3.2 Interval Timer Mode 11.3.3 Setting Overflow Flag. 11.3.4 RESO Signal Output Timing. 11.4 Application Notes 11.4.1 Contention between TCNT Write Increment. 11.4.2 Changing Clock Select Bits (CKS2 CKS0). 11.4.3 Recovery from Software Standby Mode 11.4.4 Switching between Watchdog Timer Mode Interval Timer Mode. 11.4.5 System Reset RESO Signal 11.4.6 Detection Program Runaway.
Section Serial Communication Interface
12.1 Overview. 12.1.1 Features 12.1.2 Block Diagram. 12.1.3 Input Output Pins 12.1.4 Register Configuration. 12.2 Register Descriptions 12.2.1 Receive Shift Register (RSR) 12.2.2 Receive Data Register (RDR). 12.2.3 Transmit Shift Register (TSR). 12.2.4 Transmit Data Register (TDR). 12.2.5 Serial Mode Register (SMR) 12.2.6 Serial Control Register (SCR) 12.2.7 Serial Status Register (SSR) 12.2.8 Rate Register (BRR) 12.2.9 Serial/Timer Control Register (STCR). 12.3 Operation. 12.3.1 Overview. 12.3.2 Asynchronous Mode 12.3.3 Synchronous Mode 12.4 Interrupts 12.5 Application Notes
Section Interface [Option]
13.1 Overview. 13.1.1 Features 13.1.2 Block Diagram.
13.1.3 Input/Output Pins. 13.1.4 Register Configuration. 13.2 Register Descriptions 13.2.1 Data Register (ICDR). 13.2.2 Slave Address Register (SAR). 13.2.3 Mode Register (ICMR). 13.2.4 Control Register (ICCR). 13.2.5 Status Register (ICSR) 13.2.6 Serial/Timer Control Register (STCR) 13.3 Operation. 13.3.1 Data Format 13.3.2 Master Transmit Operation 13.3.3 Master Receive Operation 13.3.4 Slave Transmit Operation 13.3.5 Slave Receive Operation. 13.3.6 IRIC Timing Control 13.3.7 Noise Canceler. 13.3.8 Sample Flowcharts. 13.4 Application Notes
Section Host Interface
14.1 Overview. 14.1.1 Block Diagram. 14.1.2 Input Output Pins 14.1.3 Register Configuration. 14.2 Register Descriptions 14.2.1 System Control Register (SYSCR). 14.2.2 Host Interface Control Register (HICR) 14.2.3 Input Data Register (IDR1). 14.2.4 Output Data Register (ODR1) 14.2.5 Status Register (STR1) 14.2.6 Input Data Register (IDR2). 14.2.7 Output Data Register (ODR2) 14.2.8 Status Register (STR2) 14.2.9 Serial/Timer Control Register (STCR) 14.3 Operation. 14.3.1 Host Interface Operation. 14.3.2 Control States. 14.3.3 Gate. 14.4 Interrupts 14.4.1 IBF1, IBF2. 14.4.2 HIRQ11, HIRQ1, HIRQ12. 14.5 Application Note.
Section Converter.
15.1 Overview. 15.1.1 Features 15.1.2 Block Diagram. 15.1.3 Input Pins 15.1.4 Register Configuration. 15.2 Register Descriptions 15.2.1 Data Registers (ADDRA ADDRD). 15.2.2 Control/Status Register (ADCSR) 15.2.3 Control Register (ADCR) 15.3 Interface. 15.4 Operation. 15.4.1 Single Mode (SCAN 15.4.2 Scan Mode (SCAN 15.4.3 Input Sampling Conversion Time 15.4.4 External Trigger Input Timing. 15.5 Interrupts 15.6 Application Notes
Section Converter.
16.1 Overview. 16.1.1 Features 16.1.2 Block Diagram. 16.1.3 Input Output Pins 16.1.4 Register Configuration. 16.2 Register Descriptions 16.2.1 Data Registers (DADR0, DADR1). 16.2.2 Control Register (DACR) 16.3 Operation.
Section RAM.
17.1 Overview. 17.1.1 Block Diagram. 17.1.2 Enable (RAME) System Control Register (SYSCR) 17.2 Operation. 17.2.1 Expanded Modes (Modes 17.2.2 Single-Chip Mode (Mode
Section (Mask Version/ZTAT Version)
18.1 Overview. 18.1.1 Block Diagram. 18.2 Writer Mode (H8/3437, H8/3434) 18.2.1 Writer Mode Setup.
viii
18.2.2 Socket Adapter Assignments Memory Map. 18.3 PROM Programming 18.3.1 Programming Verification 18.3.2 Notes Programming 18.3.3 Reliability Programmed Data
Section (32-kbyte Dual-Power-Supply Flash Memory Version)
19.1 Flash Memory Overview 19.1.1 Flash Memory Operating Principle 19.1.2 Mode Programming Flash Memory Address Space 19.1.3 Features. 19.1.4 Block Diagram. 19.1.5 Input/Output Pins. 19.1.6 Register Configuration. 19.2 Flash Memory Register Descriptions. 19.2.1 Flash Memory Control Register (FLMCR) 19.2.2 Erase Block Register (EBR1) 19.2.3 Erase Block Register (EBR2) 19.2.4 Wait-State Control Register (WSCR). 19.3 On-Board Programming Modes. 19.3.1 Boot Mode 19.3.2 User Programming Mode. 19.4 Programming Erasing Flash Memory 19.4.1 Program Mode 19.4.2 Program-Verify Mode 19.4.3 Programming Flowchart Sample Program. 19.4.4 Erase Mode 19.4.5 Erase-Verify Mode. 19.4.6 Erasing Flowchart Sample Program 19.4.7 Prewrite Verify Mode 19.4.8 Protect Modes 19.4.9 Interrupt Handling during Flash Memory Programming Erasing. 19.5 Flash Memory Emulation 19.6 Flash Memory Writer Mode (H8/3434F) 19.6.1 Writer Mode Setting 19.6.2 Socket Adapter Memory Map. 19.6.3 Operation Writer Mode. 19.7 Flash Memory Programming Erasing Precautions.
Section (60-kbyte Dual-Power-Supply Flash Memory Version)
20.1 Flash Memory Overview 20.1.1 Flash Memory Operating Principle 20.1.2 Mode Programming Flash Memory Address Space
20.2
20.3
20.4
20.5 20.6
20.7
20.1.3 Features 20.1.4 Block Diagram. 20.1.5 Input/Output Pins. 20.1.6 Register Configuration. Flash Memory Register Descriptions. 20.2.1 Flash Memory Control Register (FLMCR) 20.2.2 Erase Block Register (EBR1) 20.2.3 Erase Block Register (EBR2) 20.2.4 Wait-State Control Register (WSCR). On-Board Programming Modes. 20.3.1 Boot Mode 20.3.2 User Programming Mode. Programming Erasing Flash Memory 20.4.1 Program Mode 20.4.2 Program-Verify Mode 20.4.3 Programming Flowchart Sample Program. 20.4.4 Erase Mode 20.4.5 Erase-Verify Mode. 20.4.6 Erasing Flowchart Sample Program 20.4.7 Prewrite Verify Mode 20.4.8 Protect Modes 20.4.9 Interrupt Handling during Flash Memory Programming Erasing. Flash Memory Emulation Flash Memory Writer Mode (H8/3437F) 20.6.1 Writer Mode Setting 20.6.2 Socket Adapter Memory Map. 20.6.3 Operation Writer Mode Flash Memory Programming Erasing Precautions.
Section (60-kbyte Single-Power-Supply Flash Memory Version).
21.1 Flash Memory Overview 21.1.1 Mode Settings Space. 21.1.2 Features 21.1.3 Block Diagram. 21.1.4 Input/Output Pins. 21.1.5 Register Configuration. 21.1.6 Mode Control Register (MDCR) 21.1.7 Flash Memory Operating Modes 21.2 Flash Memory Register Descriptions. 21.2.1 Flash Memory Control Register (FLMCR1) 21.2.2 Flash Memory Control Register (FLMCR2) 21.2.3 Erase Block Register (EBR2) 21.2.4 Wait-State Control Register (WSCR).
21.3 On-Board Programming Modes. 21.3.1 Boot Mode 21.3.2 User Programming Mode. 21.4 Programming/Erasing Flash Memory. 21.4.1 Program Mode 21.4.2 Program-Verify Mode 21.4.3 Erase Mode 21.4.4 Erase-Verify Mode. 21.4.5 Protect Modes 21.4.6 Interrupt Handling during Flash Memory Programming Erasing. 21.5 Flash Memory Writer Mode (H8/3437SF) 21.5.1 Writer Mode Setting 21.5.2 Socket Adapter Memory Map. 21.5.3 Operation Writer Mode 21.6 Flash Memory Programming Erasing Precautions.
Section Power-Down State
22.1 Overview. 22.1.1 System Control Register (SYSCR). 22.2 Sleep Mode 22.2.1 Transition Sleep Mode. 22.2.2 Exit from Sleep Mode. 22.3 Software Standby Mode. 22.3.1 Transition Software Standby Mode. 22.3.2 Exit from Software Standby Mode 22.3.3 Clock Settling Time Exit from Software Standby Mode. 22.3.4 Sample Application Software Standby Mode 22.3.5 Application Note. 22.4 Hardware Standby Mode 22.4.1 Transition Hardware Standby Mode. 22.4.2 Recovery from Hardware Standby Mode 22.4.3 Timing Relationships.
Section Electrical Specifications.
23.1 Absolute Maximum Ratings 23.2 Electrical Characteristics. 23.2.1 Characteristics 23.2.2 Characteristics 23.2.3 Converter Characteristics. 23.2.4 Converter Characteristics. 23.2.5 Flash Memory Characteristics (H8/3437SF Only) 23.3 Absolute Maximum Ratings (H8/3437SF Low-Voltage Version) 23.4 Electrical Characteristics (H8/3437SF Low-Voltage Version).
23.4.1 Characteristics 23.4.2 Characteristics 23.4.3 Converter Characteristics. 23.4.4 Converter Characteristics. 23.4.5 Flash Memory Characteristics 23.5 Operational Timing. 23.5.1 Timing 23.5.2 Control Signal Timing 23.5.3 16-Bit Free-Running Timer Timing. 23.5.4 8-Bit Timer Timing. 23.5.5 Pulse Width Modulation Timer Timing. 23.5.6 Serial Communication Interface Timing 23.5.7 Port Timing. 23.5.8 Host Interface Timing 23.5.9 Timing (Option) 23.5.10 Reset Output Timing. 23.5.11 External Clock Output Timing.
Appendix Instruction Set.
Instruction List Operation Code Map. Number States Required Execution
Appendix Internal Register
Addresses Function
Appendix Port Block Diagrams
C.10 C.11 Port Block Diagram Port Block Diagram Port Block Diagram Port Block Diagrams Port Block Diagrams Port Block Diagrams Port Block Diagrams Port Block Diagrams Port Block Diagrams Port Block Diagram. Port Block Diagram.
Appendix Port States Each Processing State
Appendix Appendix
Timing Transition Recovery from Hardware Standby Mode. Option Lists
Appendix Product Code Lineup Appendix Package Dimensions
xiii
Section Overview
Overview
H8/3437 Series single-chip microcomputers features H8/300 core complement on-chip supporting modules implementing variety system functions. H8/300 high-speed processor with architecture featuring powerful bitmanipulation instructions, ideally suited realtime control applications. on-chip supporting modules implement peripheral functions needed system configurations. These include ROM, RAM, four types timers 16-bit free-running timer, 8-bit timers, timers, watchdog timer), serial communication interface (SCI), interface [option], host interface (HIF), converter, converter, ports. H8/3437 Series operate single-chip mode expanded modes, depending requirements application. Besides mask-ROM versions H8/3437 Series, there ZTATTM*1 versions with on-chip PROM, F-ZTATTM*2 version with on-chip flash memory. F-ZTATversion programmed reprogrammed on-board application systems. Notes: ZTAT(zero turn-around time) trademark Hitachi, Ltd. F-ZTAT(flexible-ZTAT) trademark Hitachi, Ltd. guaranteed voltage range different F-ZTAT version.
Version AVCC General Version
Table lists features H8/3437 Series.
Table
Item
Features
Specification Two-way general register configuration Eight 16-bit registers, Sixteen 8-bit registers High-speed operation Maximum clock rate clock): 16-bit register-register add/subtract: MHz), MHz), MHz) 8-bit multiply: MHz), 1167 MHz), 1400 MHz) 8-bit divide: MHz), 1167 MHz), 1400 MHz) Streamlined, concise instruction Instruction length: bytes Register-register arithmetic logic operations instruction data transfer between registers memory Instruction features Multiply instruction bits bits) Divide instruction bits bits) Bit-accumulator instructions Register-indirect specification positions
Memory
H8/3437: 60-kbyte ROM; 2-kbyte H8/3436: 48-kbyte ROM; 2-kbyte H8/3434: 32-kbyte ROM; 1-kbyte 16-bit free-running counter (can also count external events) output-compare lines Four input capture lines (can buffered)
16-bit free-running timer channel) 8-bit timer channels) timer channels) Watchdog timer (WDT) channel)
Each channel 8-bit up-counter (can also count external events) time constant registers Duty cycle from 100% Resolution: 1/250 Overflow generate reset interrupt Also usable interval timer
Item
Specification Asynchronous synchronous mode (selectable) Full duplex: transmit receive simultaneously On-chip baud rate generator Conforms Philips interface Includes single master mode slave mode 8-bit host interface port Three host interrupt requests (HIRQ HIRQ11, HIRQ12) Regular fast gate output register sets, each with data registers status register Controls matrix-scan keyboard providing keyboard scan function with wake-up interrupts sense ports 10-bit resolution Eight channels: single scan mode (selectable) Start conversion externally triggered Sample-and-hold function 8-bit resolution channels input/output lines which drive LEDs) input-only lines Nine external interrupt lines: NMI, IRQ0 IRQ7 on-chip interrupt sources Three selectable wait modes Expanded mode with on-chip disabled (mode Expanded mode with on-chip disabled (mode Single-chip mode (mode Sleep mode Software standby mode Hardware standby mode On-chip clock pulse generator
Serial communication interface (SCI) channels) interface channel) [option] Host interface (HIF)
Keyboard controller converter
converter ports Interrupts Wait control Operating modes
Power-down modes
Other features
Item Series lineup
Specification
Part Number Product Name H8/3437 F-ZTAT Version MHz) Version MHz) HD64F3437F16 HD64F3437FLH16 HD64F3437TF16 HD64F3437TFLH16 HD64F3437SF16 HD64F3437STF16 H8/3437 ZTAT HD6473437F16 HD6473437TF16 H8/3437 HD6433437F16 HD6433437F12 HD6433437TF16 HD6433437TF12 H8/3436 HD6433436F16 HD6433436F12 HD6433436TF16 HD6433436TF12 H8/3434 F-ZTAT HD64F3434F16 HD64F3434FLH16 HD64F3434TF16 HD64F3434TFLH16 H8/3434 ZTAT HD6473434F16 HD6473434TF16 H8/3434 HD6433434F16 HD6433434F12 HD6433434TF16 HD6433434TF12 Version MHz) HD64F3437F16 HD64F3437FLH16 HD64F3437TF16 HD64F3437TFLH16 HD64F3437SF16 HD64F3437STF16 HD6473437F16 HD6473437TF16 HD6433437VF10 HD6433437VTF10 HD6433436VF10 HD6433436VTF10 HD64F3434F16 HD64F3434FLH16 HD64F3434TF16 HD64F3434TFLH16 HD6473434F16 HD6473434TF16 HD6433434VF10 HD6433434VTF10 Package 100-pin (FP-100B) 100-pin TQFP (TFP-100B) 100-pin (FP-100B) 100-pin TQFP (TFP-100B) 100-pin (FP-100B) 100-pin TQFP (TFP-100B) 100-pin (FP-100B) 100-pin TQFP (TFP-100B) 100-pin (FP-100B) 100-pin TQFP (TFP-100B) 100-pin (FP-100B) 100-pin TQFP (TFP-100B) 100-pin (FP-100B) 100-pin TQFP (TFP-100B) 100-pin (FP-100B) 100-pin TQFP (TFP-100B) Mask Flash memory (dual-powersupply product) Mask Mask Flash memory (dual-powersupply product)
Flash memory (single-powersupply product)
PROM
PROM
interface available option. Please note following points regarding this option. mask versions, chips featuring interface include part number. Example: HD6433437WTF, HD6433434WF, etc.
Block Diagram
Figure shows block diagram H8/3437 Series.
XTAL EXTAL PA0/KEYIN8 PA1/KEYIN9 PA2/KEYIN10 PA3/KEYIN11 PA4/KEYIN12 PA5/KEYIN13 PA6/KEYIN14 PA7/KEYIN15 P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 KEYIN0/P60/FTCI KEYIN1/P61/FTOA KEYIN2/P62/FTIA KEYIN3/P63/FTIB KEYIN4/P64/FTIC KEYIN5/P65/FTID KEYIN6/P66/FTOB/IRQ6 KEYIN7/P67/IRQ7 Clock pulse generator RESO STBY VCCB H8/300 Data (high) Address Port
Data (low)
Port
Watchdog timer 16-bit free-running timer
Host interface
Serial communication interface channels) interface channel) [option]
Port
(flash memory, PROM, H8/3437: kbytes mask ROM) H8/3436: kbytes H8/3437: kbytes H8/3436: kbytes H8/3434: kbyte H8/3434: kbytes
PB0/XDB0 PB1/XDB1 PB2/XDB2 PB3/XDB3 PB4/XDB4 PB5/XDB5 PB6/XDB6 PB7/XDB7 P90/ADTRG/ECS2/IRQ2 P91/IRQ1/EIOW P92/IRQ0 P93/RD P94/WR P95/AS P97/WAIT/SDA P30/D0/HDB0 P31/D1/HDB1 P32/D2/HDB2 P33/D3/HDB3 P34/D4/HDB4 P35/D5/HDB5 P36/D6/HDB6 P37/D7/HDB7 P80/HA0 P81/GA20 P82/CS1 P83/IOR P84/TxD1/IRQ3/IOW P85/RxD1/IRQ4/CS2 P86/SCK1/IRQ5/SCL
Port
Port
8-bit timer channels)
10-bit converter channels) 8-bit converter channels)
Port
Port
Port
Port
P40/TMCI0 P41/TMO0 P42/TMRI0 HIRQ11/P43/TMCI1 HIRQ1/P44/TMO1 HIRQ12/P45/TMRI1 P46/PW0 P47/PW1
P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 AVref AVCC AVSS
Memory Sizes H8/3437 kbytes kbytes H8/3436 kbytes kbytes H8/3434 kbytes kbyte
Figure Block Diagram
P50/TxD0 P51/RxD0 P52/SCK0
Port
timer channels)
Port
1.3.1
Assignments Functions
Arrangement
Figure shows arrangement FP-100B TFP-100B packages.
P14/A4 P15/A5 P16/A6 P17/A7 PB4/XDB4 PB5/XDB5 P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 PB6/XDB6 PB7/XDB7 P47/PW1 P46/PW0 P45/TMRI1/HIRQ12 P44/TMO1/HIRQ1 P43/TMCI1/HIRQ11 P42/TMRI0
Note: S-mask model (single-power-supply model), functions only STBY pin.
Figure Arrangement (FP-100B, TFP-100B, View)
XTAL EXTAL VCCB FVPP*/STBY KEYIN15/PA7 KEYIN14/PA6 SCK0/P52 RxD0/P51 TxD0/P50 SDA/WAIT/P97 AS/P95 WR/P94 KEYIN13/PA5 KEYIN12/PA4 RD/P93 IRQ0/P92 EIOW/IRQ1/P91 ADTRG/ECS2/IRQ2/P90
A3/P13 A2/P12 A1/P11 A0/P10 XDB3/PB3 XDB2/PB2 D0/HDB0/P30 D1/HDB1/P31 D2/HDB2/P32 D3/HDB3/P33 D4/HDB4/P34 D5/HDB5/P35 D6/HDB6/P36 D7/HDB7/P37 XDB1/PB1 XDB0/PB0 HA0/P80 GA20/P81 CS1/P82 IOR/P83 IOW/TxD1/IRQ3/P84 CS2/RxD1/IRQ4/P85 SCL/SCK1/IRQ5/P86 RESO
FP-100B, TFP-100B (top view)
P41/TMO0 P40/TMCI0 PA0/KEYIN8 PA1/KEYIN9 AVSS P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 AVCC AVref P67/KEYIN7/IRQ7 P66/KEYIN6/IRQ6/FTOB P65/KEYIN5/FTID P64/KEYIN4/FTIC PA2/KEYIN10 PA3/KEYIN11 P63/KEYIN3/FTIB P62/KEYIN2/FTIA P61/KEYIN1/FTOA P60/KEYIN0/FTCI
1.3.2
Functions
Assignments Each Operating Mode: Table lists assignments pins FP-100B TFP-100B packages each operating mode. Table
FP-100B, TFP-100B
Assignments Each Operating Mode
Expanded Modes Single-Chip Mode Mode Mode XTAL EXTAL VCCB STBY PA7/KEYIN15 PA6/KEYIN14 P52/SCK0 P51/RxD0 P50/TxD0 Mode XTAL EXTAL VCCB STBY/FVPP PA7/KEYIN15 PA6/KEYIN14 P52/SCK0 P51/RxD0 P50/TxD0 Disabled XTAL EXTAL VCCB STBY/FVPP PA7/KEYIN15 PA6/KEYIN14 P52/SCK0 P51/RxD0 P50/TxD0 Enabled XTAL EXTAL VCCB STBY/FVPP PA7/KEYIN15 PA6/KEYIN14 P52/SCK0 P51/RxD0 P50/TxD0 P97/SDA PA5/KEYIN13 PA4/KEYIN12 P92/IRQ0 Flash EPROM Memory Writer Writer Mode Mode XTAL EXTAL
P97/WAIT/SDA P97/WAIT/SDA P97/SDA PA5/KEYIN13 PA4/KEYIN12 P92/IRQ0 PA5/KEYIN13 PA4/KEYIN12 P92/IRQ0 PA5/KEYIN13 PA4/KEYIN12 P92/IRQ0
FP-100B, TFP-100B
Expanded Modes
Single-Chip Mode Mode
Mode
Mode
Disabled
Enabled
Flash EPROM Memory Writer Writer Mode Mode EA15 EA16
P91/IRQ1 when disabled STAC STCR; EIOW/IRQ1 when enabled STAC STCR P90/IRQ2/ADTRG when disabled STAC STCR; ECS2/IRQ2 when enabled STAC STCR P60/FTCI/ KEYIN0 P61/FTOA/ KEYIN1 P62/FTIA/ KEYIN2 P63/FTIB/ KEYIN3 PA3/KEYIN11 PA2/KEYIN10 P64/FTIC/ KEYIN4 P65/FTID/ KEYIN5 P66/FTOB/ IRQ6/KEYIN6 P67/IRQ7/ KEYIN7 AVref AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P60/FTCI/ KEYIN0 P61/FTOA/ KEYIN1 P62/FTIA/ KEYIN2 P63/FTIB/ KEYIN3 PA3/KEYIN11 PA2/KEYIN10 P64/FTIC/ KEYIN4 P65/FTID/ KEYIN5 P66/FTOB/ IRQ6/KEYIN6 P67/IRQ7/ KEYIN7 AVref AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P60/FTCI/ KEYIN0 P61/FTOA/ KEYIN1 P62/FTIA/ KEYIN2 P63/FTIB/ KEYIN3 PA3/KEYIN11 PA2/KEYIN10 P64/FTIC/ KEYIN4 P65/FTID/ KEYIN5 P66/FTOB/ IRQ6/KEYIN6 P67/IRQ7/ KEYIN7 AVref AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P60/FTCI/ KEYIN0 P61/FTOA/ KEYIN1 P62/FTIA/ KEYIN2 P63/FTIB/ KEYIN3 PA3/KEYIN11 PA2/KEYIN10 P64/FTIC/ KEYIN4 P65/FTID/ KEYIN5 P66/FTOB/ IRQ6/KEYIN6 P67/IRQ7/ KEYIN7 AVref AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0
FP-100B, TFP-100B
Expanded Modes
Single-Chip Mode Mode
Mode P77/AN7/DA1 AVSS PA1/KEYIN9 PA0/KEYIN8 P40/TMCI0 P41/TMO0 P42/TMRI0 P43/TMCI1/ HIRQ11*1 P44/TMO1/ HIRQ1*1 P45/TMRI1/ HIRQ12*1 P46/PW0 P47/PW1 PB7/XDB7 PB6/XDB6 PB5/XDB5 PB4/XDB4
Mode P77/AN7/DA1 AVSS PA1/KEYIN9 PA0/KEYIN8 P40/TMCI0 P41/TMO0 P42/TMRI0 P43/TMCI1/ HIRQ11*1 P44/TMO1/ HIRQ1*1 P45/TMRI1/ HIRQ12*1 P46/PW0 P47/PW1 PB7/XDB7 PB6/XDB6 P27/A P26/A P25/A P24/A P23/A P22/A P21/A P20/A PB5/XDB5 PB4/XDB4
Disabled P77/AN7/DA1 AVSS PA1/KEYIN9 PA0/KEYIN8 P40/TMCI0 P41/TMO0 P42/TMRI0 P43/TMCI1 P44/TMO1 P45/TMRI1 P46/PW0 P47/PW1
Enabled P77/AN7/DA1 AVSS PA1/KEYIN9 PA0/KEYIN8 P40/TMCI0 P41/TMO0 P42/TMRI0 HIRQ11/TMCI1 HIRQ1/TMO1 HIRQ12/TMRI1 P46/PW0 P47/PW1
Flash EPROM Memory Writer Writer Mode Mode EA14 EA13 EA12 EA11 EA10
FP-100B, TFP-100B
Expanded Modes
Single-Chip Mode Mode
Mode PB3/XDB3 PB2/XDB2 PB1/XDB1 PB0/XDB0 P80/HA0
Mode P17/A P16/A P15/A P14/A P13/A P12/A P11/A P10/A PB3/XDB3 PB2/XDB2 PB1/XDB1 PB0/XDB0 P80/HA0
Disabled
Enabled HDB0 HDB1 HDB2 HDB3 HDB4 HDB5 HDB6 HDB7 P81/GA
Flash EPROM Memory Writer Writer Mode Mode
P81/GA P82/CS
P81/GA P82/CS
P83/IOR
P83/IOR
FP-100B, TFP-100B
Expanded Modes
Single-Chip Mode Mode
Mode
Mode
Disabled
Enabled
Flash EPROM Memory Writer Writer Mode Mode
P84/IRQ3/TxD1 when disabled STAC STCR; IOW/IRQ3 when enabled STAC STCR P85/IRQ4/RxD1 when disabled STAC STCR; 2/IRQ4 when enabled STAC STCR P86/SCK1/ IRQ5/SCL RESO P86/SCK1/ IRQ5/SCL RESO P86/SCK1/ IRQ5/SCL RESO P86/SCK1/ IRQ5/SCL RESO
Note: Pins marked should left unconnected. details writer mode, refer 18.2, Writer Mode, 19.6, Flash Memory Writer Mode (H8/3434F), 20.6, Flash Memory Writer Mode (H8/3437F) 21.5, Flash Memory Writer Mode (H8/3437SF). this chip, except S-mask model (single-power-supply specification), same used STBY FVPP When this driven low, transition made hardware standby mode. This occurs only normal operating modes (modes also when programming flash memory with PROM writer. When using PROM programmer program dual-power-supply flash memory, therefore, PROM programmer specifications should provide this held level except when programming (FVPP Differs mode depending whether host interface enabled disabled. XDB6 only used when host interface enabled.
Functions: Table gives concise description function each pin. Table Functions
Type Power Symbol FP-100B, TFP-100B Name Function Power: Connected power supply. Connect both pins system power supply. buffer power supply: Power supply input/output buffers pins P97, Ground: Connected ground Connect pins system ground Crystal: Connected crystal oscillator. crystal frequency should same desired system clock frequency. external clock input EXTAL pin, reverse-phase clock should input XTAL pin. External crystal: Connected crystal oscillator external clock. frequency external clock should same desired system clock frequency. section 6.2, Oscillator Circuit, examples connections crystal external clock. System clock: Supplies system clock peripheral devices. Reset: input causes chip reset. Reset output: Outputs reset signal external devices. Standby: transition hardware standby mode power-down state) occurs when input received STBY pin. Address bus: Address output pins. Data bus: 8-bit bidirectional data bus.
VCCB
Clock XTAL
EXTAL
System control RESO STBY
Address Data
Type control Symbol WAIT FP-100B, TFP-100B Name Function Wait: Requests insert wait states into cycle when external address accessed. Read: Goes indicate that reading external address. Write: Goes indicate that writing external address. Address strobe: Goes indicate that there valid address address bus. Nonmaskable interrupt: Highest-priority interrupt request. NMIEG system control register (SYSCR) determines whether interrupt recognized rising falling edge input. Interrupt request Maskable interrupt request pins. Mode: Input pins setting mode operating mode according table below. Mode Mode Mode Description Illegal setting Expanded mode with on-chip disabled Expanded mode with on-chip enabled Single-chip mode
Interrupt signals
IRQ0 IRQ7 Operating mode control
Mode
Mode
Note: H8/3437SF (S-mask model, single-power-supply on-chip flash memory version), settings used when boot mode set. details, section 21.3, On-Board Programming Modes. change mode settings while chip operating.
Type 16-bit freerunning timer (FRT) Symbol FTOA FTOB FTCI FP-100B, TFP-100B Name Function output compare Output pins controlled comparators free-running timer. counter clock input: Input external clock signal free-running timer. input capture Input capture pins free-running timer. 8-bit timer output (channels Compare-match output pins 8-bit timers. 8-bit timer counter clock input (channels External clock input pins 8bit timer counters. 8-bit timer counter reset input (channels high input these pins resets 8-bit timer counters. timer output (channels Pulse-width modulation timer output pins. Transmit data (channels Data output pins serial communication interface. Receive data (channels Data input pins serial communication interface. Serial clock (channels Input/output pins serial clock. Host interface data bus: 8-bit bidirectional which host processor accesses host interface. Chip select Input pins selecting host interface channels read: Read strobe input host interface. write: Write strobe input host interface.
FTIA FTID 8-bit timer TMO0 TMO1 TMCI0 TMCI1 TMRI0 TMRI1 timer Serial communication interface (SCI) TxD0 TxD1 RxD0 RxD1 Host interface (HIF) HDB0 HDB7
Type Host interface (HIF) Symbol GA20 HIRQ1 HIRQ11 HIRQ12 Keyboard control KEYIN0 KEYIN15 FP-100B, TFP-100B Name Function Command/data: Input indicating data access command access. Gate gate control signal output pin. Host interrupts Output pins interrupt request signals host processor. Keyboard input: Input pins from matrix keyboard. (Keyboard scan signals normally output from P27, allowing maximum matrix. number keys further increased other output ports.) Host interface data bus: 8-bit bidirectional which host processor accesses host interface. Host chip select Input selecting host interface channel write: Write strobe input host interface. Analog input: Analog signal input pins converter. trigger: External trigger input starting converter. Analog output: Analog signal output pins converter. Analog reference voltage: Reference voltage converters. converters used, connect AVCC system power supply. Analog ground: Ground converters. Connect system ground Analog reference voltage: Analog reference voltage input pins converters.
Host interface (expanded modes) Host interface enabled when STAC STCR) converter
EIOW ADTRG
converter converters
AVCC
AVSS
AVref
Type Symbol FP-100B, TFP-100B Name Function Programming power supply on-board programming: Connect flash memory programming power supply (+12 clock I/O: Input/output clock. Power supplied buffer power supply CCB. Features drive function. data I/O: Input/output data. Power supplied buffer power supply CCB. Features drive function. Port 8-bit input/output port with programmable input pull-ups driving capability. direction each selected port data direction register (P1DDR). Port 8-bit input/output port with programmable input pull-ups driving capability. direction each selected port data direction register (P2DDR). Port 8-bit input/output port with programmable input pull-ups. direction each selected port data direction register (P3DDR). Port 8-bit input/output port. direction each selected port data direction register (P4DDR). Port 3-bit input/output port. direction each selected port data direction register (P5DDR). Port 8-bit input/output port with programming input pull-ups. direction each selected port data direction register (P6DDR). Port 8-bit input port. Port 7-bit input/output port. direction each selected port data direction register (P8DDR). powered buffer power supply CCB.
Flash memory [H8/3434, H8/3437 F-ZTAT] interface [option]
ports
Type ports Symbol FP-100B, TFP-100B Name Function Port 8-bit input/output port. direction each (except selected port data direction register (P9DDR). powered buffer power supply CCB. Port 8-bit input/output port with programming input pull-ups. direction each selected port data direction register (PADDR). powered buffer power supply CCB. Features drive function. Port 8-bit input/output port with programming input pull-ups. direction each selected port data direction register (PBDDR).
Note: this chip, except S-mask model (single-power-supply specification), same used STBY FVPP When this driven low, transition made hardware standby mode. This occurs only normal operating modes (modes also when programming flash memory with PROM writer. When using PROM programmer program dual-power-supply flash memory, therefore, PROM programmer specifications should provide this held level except when programming (FVPP
Section
Overview
H8/300 fast central processing unit with eight 16-bit general registers (also configurable eight-bit registers) concise instruction designed high-speed operation. 2.1.1 Features
main features H8/300 listed below. Two-way register configuration Sixteen 8-bit general registers, Eight 16-bit general registers Instruction with basic instructions, including: Multiply divide instructions Powerful bit-manipulation instructions Eight addressing modes Register direct (Rn) Register indirect (@Rn) Register indirect with displacement (@(d:16, Rn)) Register indirect with post-increment pre-decrement (@Rn+ @-Rn) Absolute address (@aa:8 @aa:16) Immediate (#xx:8 #xx:16) PC-relative (@(d:8, PC)) Memory indirect (@@aa:8) Maximum 64-kbyte address space High-speed operation frequently-used instructions executed four states Maximum clock rate clock): 16-bit register-register subtract: MHz), MHz), MHz) 8-bit multiply: MHz), 1167 MHz), 1400 MHz) 8-bit divide: MHz), 1167 MHz), 1400 MHz) Power-down mode SLEEP instruction
2.1.2
Address Space
H8/300 supports address space with maximum size kbytes program code data combined. memory differs depending mode (mode details, section 3.4, Address Space Each Operating Mode. 2.1.3 Register Configuration
Figure shows internal register structure H8/300 CPU. There groups registers: general registers control registers.
General registers (Rn) (SP) Stack pointer
Control registers UHUNZ Program counter CCR: Condition code register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask User User
Figure Registers
2.2.1
Register Descriptions
General Registers
general registers used both data registers address registers. When used address registers, general registers accessed 16-bit registers R7). When used data registers, they accessed 16-bit registers, high bytes accessed separately 8-bit registers (R0H R7L). also functions stack pointer, used implicitly hardware processing interrupts subroutine calls. assembly-language coding, also denoted letters indicated figure 2.2, (SP) points stack.
Unused area (R7) Stack area
Figure Stack Pointer 2.2.2 Control Registers
control registers include 16-bit program counter (PC) 8-bit condition code register (CCR). Program Counter (PC): This 16-bit register indicates address next instruction will execute. Each instruction accessed bits word), least significant ignored (always regarded Condition Code Register (CCR): This 8-bit register contains internal status information, including carry (C), overflow (V), zero (Z), negative (N), half-carry flags interrupt mask (I). 7-Interrupt Mask (I): When this interrupts except masked. This automatically reset start interrupt handling. 6-User (U): This written read software (using LDC, STC, ANDC, ORC, XORC instructions).
5-Half-Carry Flag (H): This flag when ADD.B, ADDX.B, SUB.B, SUBX.B, NEG.B, CMP.B instruction causes carry borrow cleared otherwise. Similarly, when ADD.W, SUB.W, CMP.W instruction causes carry borrow cleared otherwise. used implicitly instructions. 4-User (U): This written read software (using LDC, STC, ANDC, ORC, XORC instructions). 3-Negative Flag (N): This flag indicates most significant (sign bit) result instruction. 2-Zero Flag (Z): This flag indicate zero result cleared indicate nonzero result. 1-Overflow Flag (V): This flag when arithmetic overflow occurs, cleared other times. 0-Carry Flag (C): This flag used subtract instructions, indicate carry borrow most significant result Shift rotate instructions, store value shifted most significant least significant manipulation load instructions, accumulator LDC, STC, ANDC, ORC, XORC instructions enable load store CCR, clear selected bits logic operations. flags used conditional branching instructions (BCC). action each instruction flag bits, H8/300 Series Programming Manual. 2.2.3 Initial Register Values
When reset, program counter (PC) loaded from vector table interrupt mask other bits general registers initialized. particular, stack pointer (R7) initialized. stack pointer should initialized software, first instruction executed after reset.
Data Formats
H8/300 process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, 16-bit (word) data. manipulation instructions operate 1-bit data specified byte operand. arithmetic logic instructions except ADDS SUBS operate byte data. instruction perform decimal arithmetic adjustments byte data packed form. Each nibble byte treated decimal digit. MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU bits bits), DIVXU bits bits) instructions operate word data.
2.3.1
Data Formats General Registers
Data sizes above stored general registers shown figure 2.3.
Data Type Register
Data Format
1-bit data
Don't care
1-bit data
Don't care
Byte data
Don't care
Byte data
Don't care
Word data
Upper digit
Lower digit
4-bit data
Don't care
Upper digit
Lower digit
4-bit data
Don't care
Legend: RnH: Upper digit general register RnL: Lower digit general register MSB: Most significant LSB: Least significant
Figure Register Data Formats
2.3.2
Memory Data Formats
Figure indicates data formats memory. Word data stored memory must always begin even address. word access least significant address regarded address specified, address error occurs access performed preceding even address. This rule affects MOV.W instructions branching instructions, implies that only even addresses should stored vector table.
Data Type Address Data Format
1-bit data Byte data
Address Address Even address address Even address address Even address address
Word data
Upper bits Lower bits
Byte data (CCR) stack
CCR*
Word data stack
Note: Ignored return Legend: CCR: Condition code register
Figure Memory Data Formats When stack addressed register must always accessed word time. When pushed stack, identical copies pushed make complete word. When they restored, lower byte ignored.
2.4.1
Addressing Modes
Addressing Mode
H8/300 supports eight addressing modes. Each instruction uses subset these addressing modes. Table
Addressing Modes
Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Symbol @(d:16, @Rn+ @-Rn @aa:8 @aa:16 #xx:8 #xx:16 @(d:8, @@aa:8
Absolute address Immediate Program-counter-relative Memory indirect
Register Direct-Rn: register field instruction specifies 16-bit general register containing operand. most cases general register accessed 8-bit register. Only MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU bits bits), DIVXU bits bits) instructions have 16-bit operands. Register Indirect-@Rn: register field instruction specifies 16-bit general register containing address operand. Register Indirect with Displacement-@(d:16, Rn): This mode, which used only instructions, similar register indirect instruction second word (bytes which added contents specified general register obtain operand address. MOV.W instruction, resulting address must even. Register Indirect with Post-Increment Pre-Decrement-@Rn+ @-Rn: Register indirect with Post-Increment-@Rn+ @Rn+ mode used with instructions that load registers from memory. similar register indirect mode, 16-bit general register specified register field instruction incremented after operand accessed. size increment depending size operand: MOV.B; MOV.W. MOV.W, original contents 16-bit general register must even.
Register Indirect with Pre-Decrement-@-Rn @-Rn mode used with instructions that store register contents memory. similar register indirect mode, 16-bit general register specified register field instruction decremented before operand accessed. size decrement depending size operand: MOV.B; MOV.W. MOV.W, original contents 16-bit general register must even. Absolute Address-@aa:8 @aa:16: instruction specifies absolute address operand memory. MOV.B instruction uses 8-bit absolute address form H'FFxx. upper bits assumed possible address range H'FF00 H'FFFF (65280 65535). MOV.B, MOV.W, JMP, instructions 16-bit absolute addresses. Immediate-#xx:8 #xx:16: instruction contains 8-bit operand second byte, 16-bit operand third fourth bytes. Only MOV.W instructions contain 16-bit immediate values. ADDS SUBS instructions implicitly contain value immediate data. Some manipulation instructions contain 3-bit immediate data (#xx:3) second fourth byte instruction, specifying number. Program-Counter-Relative-@(d:8, PC): This mode used generate branch addresses instructions. 8-bit value byte instruction code added sign-extended value program counter contents. result must even number. possible branching range -126 +128 bytes (-63 words) from current address. Memory Indirect-@@aa:8: This mode used instructions. second byte instruction code specifies 8-bit absolute address from H'0000 H'00FF 255). word located this address contains branch address. upper bits absolute address (H'00), thus branch address limited values from (H'0000 H'00FF). Note that some addresses this range also used vector table. Refer section 3.4, Address Space Each Operating Mode. address specified branch destination operand address MOV.W instruction, least significant regarded causing word access performed address preceding specified address. section 2.3.2, Memory Data Formats, further information.
2.4.2
Calculation Effective Address
Table shows H8/300 calculates effective addresses each addressing mode. Arithmetic, logic, shift instructions register direct addressing (1). ADD.B, ADDX.B, SUBX.B, CMP.B, AND.B, OR.B, XOR.B instructions also immediate addressing (6). instruction uses addressing modes except program-counter relative memory indirect (8). manipulation instructions register direct (1), register indirect (2), 8-bit absolute addressing identify byte operand, 3-bit immediate addressing identify within byte. BSET, BCLR, BNOT, BTST instructions also register direct addressing identify bit.
Table
Effective Address Calculation
Effective Address Calculation Effective Address
Addressing Mode Instruction Format Register direct,
regm regm regn
regn
Operands contained registers regm regn
Register indirect,
16-bit register contents
Register indirect with displacement, @(d:16,
16-bit register contents
disp
disp
Register indirect with post-increment, @Rn+
16-bit register contents
Register indirect with pre-decrement, @-Rn
16-bit register contents
Note: byte operand, word operand
Addressing Mode Instruction Format Absolute address @aa:8
Effective Address Calculation
Effective Address
H'FF
@aa:16
Immediate #xx:8
Operand 2-byte immediate data
#xx:16
PC-relative @(d:8,
contents
Sign extension
disp
disp
Addressing Mode Instruction Format Memory indirect, @@aa:8
Effective Address Calculation
Effective Address
H'00
Memory contents bits) Legend: reg: General register Operation code disp: Displacement IMM: Immediate data abs: Absolute address
Instruction
H8/300 types instructions, which classified function table 2.3. Table
Function Data transfer Arithmetic operations Logic operations Shift manipulation Branch System control Block data transfer
Instruction Classification
Instructions MOV, MOVTPE MOVFPE PUSH
Types Total
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, AND, XOR, SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Bcc*2, JMP, BSR, JSR, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, EEPMOV
Notes: PUSH equivalent MOV.W @-SP. equivalent MOV.W @SP+, conditional branch instruction which represents condition code. supported H8/3437 Series.
following sections give concise summary instructions each category, indicate patterns their object code. notation used defined next. Operation Notation
(EAd) (EAs) #imm #xx:3 #xx:8 #xx:16 disp General register (destination) General register (source) General register Destination operand Source operand Stack pointer Program counter Condition code register (negative) flag (zero) flag (overflow) flag (carry) flag Immediate data 3-bit immediate data 8-bit immediate data 16-bit immediate data Displacement Addition Subtraction Multiplication Division logical logical Exclusive logical Move
2.5.1
Data Transfer Instructions
Table describes data transfer instructions. Figure shows their object code formats. Table
Instruction
Data Transfer Instructions
Size* Function (EAs) (EAd) Moves data between general registers between general register memory, moves immediate data general register. @Rn, @(d:16, Rn), @aa:16, #xx:8 #xx:16, @-Rn, @Rn+ addressing modes available byte word data. @aa:8 addressing mode available byte data only. @-R7 @R7+ modes require word operands. specify byte size these modes.
MOVTPE MOVFPE PUSH
supported H8/3437 Series. supported H8/3437 Series. @-SP Pushes 16-bit general register onto stack. Equivalent MOV.W @-SP.
@SP+ Pops 16-bit general register from stack. Equivalent MOV.W @SP+,
Note: Size: Operand size Byte Word
RmRn
@RmRn
disp
@(d:16, Rm)Rn
@Rm+Rn, Rn@-Rm
@aa:8Rn
@aa:16Rn
#xx:8Rn
#xx:16Rn
MOVFPE, MOVTPE
Legend: Operation field Register field disp: Displacement Absolute address abs: IMM: Immediate data
POP, PUSH
Figure Data Transfer Instruction Codes
2.5.2
Arithmetic Operations
Table describes arithmetic instructions. figure section 2.5.4, Shift Operations, their object codes. Table
Instruction
Arithmetic Instructions
Size* Function #imm Performs addition subtraction data general registers, addition immediate data data general register. Immediate data cannot subtracted from data general register. Word data added subtracted only when both words general registers. #imm Performs addition subtraction with carry borrow byte data general registers, addition subtraction immediate data data general register. Increments decrements general register. #imm Adds subtracts immediate data from data general register. immediate data must decimal adjust Decimal-adjusts (adjusts packed BCD) addition subtraction result general register referring CCR. Performs 8-bit 8-bit unsigned multiplication data general registers, providing 16-bit result.
ADDX SUBX
ADDS SUBS MULXU
DIVXU
Performs 16-bit 8-bit unsigned division data general registers, providing 8-bit quotient 8-bit remainder.
#imm Compares data general register with data another general register with immediate data. Word data compared only between general registers.
Obtains two's complement (arithmetic complement) data general register.
Note: Size: Operand size Byte Word
2.5.3
Logic Operations
Table describes four instructions that perform logic operations. figure section 2.5.4, Shift Operations, their object codes. Table
Instruction
Logic Operation Instructions
Size* Function #imm Performs logical operation general register another general register immediate data.
#imm Performs logical operation general register another general register immediate data.
#imm Performs logical exclusive operation general register another general register immediate data.
(Rd) (Rd) Obtains one's complement (logical complement) general register contents.
Note: Size: Operand size Byte
2.5.4
Shift Operations
Table describes eight shift instructions. Figure shows object code formats arithmetic, logic, shift instructions. Table
Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: Size: Operand size Byte
Shift Instructions
Size* Function shift Performs arithmetic shift operation general register contents. shift Performs logical shift operation general register contents. rotate Rotates general register contents. rotate through carry Rotates general register contents through (carry) bit.
ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG,
MULXU, DIVXU
ADD, ADDX, SUBX, (#xx:8)
AND, (Rm)
AND, (#xx:8)
Legend: Operation field Register field IMM: Immediate data
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
Figure Arithmetic, Logic, Shift Instruction Codes
2.5.5
Manipulations
Table describes bit-manipulation instructions. Figure shows their object code formats. Table
Instruction BSET
Bit-Manipulation Instructions
Size* Function (<bit no.> <EAd>) Sets specified general register memory specified number, given 3-bit immediate data lower three bits general register.
BCLR
(<bit no.> <EAd>) Clears specified general register memory specified number, given 3-bit immediate data lower three bits general register.
BNOT
(<bit no.> <EAd>) (<bit no.> <EAd>) Inverts specified general register memory. specified number, given 3-bit immediate data lower three bits general register.
BTST
(<bit no.> <EAd>) Tests specified general register memory sets clears flag accordingly. specified number, given 3-bit immediate data lower three bits general register.
BAND
(<bit no.> <EAd>) ANDs flag with specified general register memory. (<bit no.> <EAd>)] ANDs flag with inverse specified general register memory. number specified 3-bit immediate data. (<bit no.> <EAd>) flag with specified general register memory. (<bit no.> <EAd>)] flag with inverse specified general register memory. number specified 3-bit immediate data. (<bit no.> <EAd>) XORs flag with specified general register memory.
BIAND
BIOR
BXOR
Note: Size: Operand size Byte
Instruction BIXOR
Size*
Function [(<bit no.> <EAd>)] XORs flag with inverse specified general register memory. number specified 3-bit immediate data. (<bit no.> <EAd>) Copies specified general register memory flag. (<bit no.> <EAd>) Copies inverse specified general register memory flag. number specified 3-bit immediate data. (<bit no.> <EAd>) Copies flag specified general register memory. (<bit no.> <EAd>) Copies inverse flag specified general register memory. number specified 3-bit immediate data.
BILD
BIST
Note: Size: Operand size Byte
Notes Manipulation Instructions: BSET, BCLR, BNOT, BST, BIST readmodify-write instructions. They read byte data, modify byte, then write byte back. Care required when these instructions applied registers with write-only bits port registers.
Step Read Modify Write Description Read data byte specified address Modify data byte Write modified data byte back specified address
Example BCLR executed clear port data direction register (P4DDR) under following conditions. Input pin, Input pin, high Output pins, intended purpose this BCLR instruction switch from output input.
Before Execution BCLR Instruction
Input/output state Input Input High Output Output Output Output Output Output
Execution BCLR Instruction BCLR @P4DDR clear data direction register
After Execution BCLR Instruction
Input/output state Output Output High Output Output Output Output Output Input High
Explanation: execute BCLR instruction, begins reading P4DDR. Since P4DDR write-only register, read H'FF, even though true value H'3F. Next clears read data, changing value H'FE. Finally, writes this value (H'FE) back P4DDR complete BCLR instruction. result, P40DDR cleared making input pin. addition, P47DDR P46DDR making output pins.
BSET, BCLR, BNOT, BTST
Operand: register direct (Rn) no.: immediate (#xx:3) Operand: register direct (Rn) no.: register direct (Rm)
Operand: register indirect (@Rn) no.:
immediate (#xx:3)
Operand: register indirect (@Rn) no.:
register direct (Rm)
Operand: absolute (@aa:8) no.:
immediate (#xx:3)
Operand: absolute (@aa:8) no.: register direct (Rm)
BAND, BOR, BXOR, BLD,
Operand: register direct (Rn) no.: immediate (#xx:3)
Operand: register indirect (@Rn) no.:
immediate (#xx:3)
Operand: absolute (@aa:8) no.: immediate (#xx:3)
Legend: Operation field Register field abs: Absolute address IMM: Immediate data
Figure Manipulation Instruction Codes
BIAND, BIOR, BIXOR, BILD, BIST
Operand: register direct (Rn) no.: immediate (#xx:3)
Operand: register indirect (@Rn) no.:
immediate (#xx:3)
Operand: absolute (@aa:8) no.: immediate (#xx:3)
Legend: Operation field Register field abs: Absolute address IMM: Immediate data
Figure Manipulation Instruction Codes (cont)
2.5.6
Branching Instructions
Table describes branching instructions. Figure shows their object code formats. Table
Instruction
Branching Instructions
Size Function Branches condition true. Mnemonic (BT) (BF) (BHS) (BLO) field 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Always (true) Never (false) High same Carry clear (High same) Carry (low) equal Equal Overflow clear Overflow Plus Minus Greater equal Less than Greater than Less equal Condition Always Never CZ=0 CZ=1 NV=0 NV=1
Branches unconditionally specified address. Branches subroutine specified address. Branches subroutine specified displacement from current address. Returns from subroutine.
disp
(@Rm)
(@aa:16)
(@@aa:8)
disp
(@Rm)
(@aa:16)
(@@aa:8)
Legend: Operation field Condition field Register field disp: Displacement abs: Absolute address
Figure Branching Instruction Codes
2.5.7
System Control Instructions
Table 2.10 describes system control instructions. Figure shows their object code formats. Table 2.10 System Control Instructions
Instruction SLEEP Size* Function Returns from exception-handling routine. Causes transition power-down state. CCR, #imm Moves immediate data general register contents condition code register. Copies condition code register specified general register. ANDC #imm Logically ANDs condition code register with immediate data. #imm Logically condition code register with immediate data. XORC #imm Logically exclusive-ORs condition code register with immediate data. Only increments program counter. Note: Size: Operand size Byte
RTE, SLEEP,
LDC, (Rn)
Legend: Operation field Register field IMM: Immediate data
ANDC, ORC, XORC, (#xx:8)
Figure System Control Instruction Codes
2.5.8
Block Data Transfer Instruction
Table 2.11 describes EEPMOV instruction. Figure 2.10 shows object code format. Table 2.11 Block Data Transfer Instruction/EEPROM Write Operation
Instruction EEPMOV Size Function then repeat until else next; Moves data block according parameters general registers R4L, R4L: size block (bytes) starting source address starting destination address Execution next instruction starts soon block transfer completed. @R5+ @R6+
Legend: Operation field
Figure 2.10 Block Data Transfer Instruction/EEPROM Write Operation Code
Notes EEPMOV Instruction EEPMOV instruction block data transfer instruction. moves number bytes specified from address specified address specified
When setting make sure that final destination address R4L) does exceed H'FFFF. value must change from H'FFFF H'0000 during execution instruction.
H'FFFF allowed
2.6.1
States
Overview
three states: program execution state, exception-handling state, power-down state. power-down state further divided into three modes: sleep mode, software standby mode, hardware standby mode. Figure 2.11 summarizes these states, figure 2.12 shows state transitions.
State
Program execution state executes successive program instructions. Exception-handling state transient state triggered reset interrupt. executes hardware sequence that includes loading program counter from vector table. Power-down state state which some chip functions stopped conserve power. Sleep mode Software standby mode Hardware standby mode
Figure 2.11 Operating States
Exception handling request Exceptionhandling state
Program execution state Exception handing Interrupt request
SLEEP instruction with SSBY SLEEP instruction
Sleep mode
NMI, IRQ0 IRQ2 IRQ6
Software standby mode
Reset state
STBY
Hardware standby mode Power-down state
Notes: transition reset state occurs when goes low, except when chip hardware standby mode. transition from state hardware standby mode occurs when STBY goes low.
Figure 2.12 State Transitions 2.6.2 Program Execution State
this state executes program instructions. 2.6.3 Exception-Handling State
exception-handling state transient state that occurs when reset interrupted changes normal processing flow. interrupt exception handling, references stack pointer (R7) saves program counter condition code register stack. further details section Exception Handling.
2.6.4
Power-Down State
power-down state includes three modes: sleep mode, software standby mode, hardware standby mode. Sleep Mode: entered when SLEEP instruction executed. halts, register contents remain unchanged on-chip supporting modules continue function. Software Standby Mode: entered SLEEP instruction executed while SSBY (Software Standby) system control register (SYSCR) set. on-chip supporting modules halt. on-chip supporting modules initialized, contents on-chip registers remain unchanged long specified voltage supplied. port outputs also remain unchanged. Hardware Standby Mode: entered when input STBY goes low. chip functions halt, including port output. on-chip supporting modules initialized, onchip contents held. section Power-Down State, further information.
Access Timing Cycle
driven system clock period from rising edge system clock next referred "state." Memory access performed two- three-state cycle. On-chip memory, on-chip supporting modules, external devices accessed different cycles described below. 2.7.1 Access On-Chip Memory (RAM ROM)
On-chip accessed cycle states designated Either byte word data accessed, 16-bit data bus. Figure 2.13 shows on-chip memory access cycle. Figure 2.14 shows associated states.
cycle
state
state
Internal address
Address
Internal read signal Read data
Internal data (read)
Internal write signal
Internal data (write)
Write data
Figure 2.13 On-Chip Memory Access Cycle
cycle
state
state
Address
Address
High High High Data bus: high impedance state
Figure 2.14 States during On-Chip Memory Access Cycle
2.7.2
Access On-Chip Register Field External Devices
on-chip supporting module registers external devices accessed cycle consisting three states: Only byte data accessed cycle, 8-bit data bus. Access word data instruction codes requires consecutive cycles (six states). Figure 2.15 shows access cycle on-chip register field. Figure 2.16 shows associated states. Figures 2.17 show read write access timing external devices.
cycle
state Internal address Internal read signal Internal data (read) Internal write signal Internal data (write)
state
state
Address
Read data
Write data
Figure 2.15 On-Chip Register Field Access Cycle
cycle
state
state
state
Address
Address
High High High Data bus: high impedance state
Figure 2.16 States during On-Chip Register Field Access Cycle
Read cycle
state
state
state
Address
Address
High Data
Read data
Figure 2.17 External Device Access Timing (Read)
Write cycle
state
state
state
Address
Address
High
Data
Write data
Figure 2.17 External Device Access Timing (Write)
Section Operating Modes Address Space
3.1.1
Overview
Mode Selection
H8/3437 Series operates three modes numbered mode selected inputs mode pins (MD1 table 3.1. Table
Mode Mode Mode Mode Mode
Operating Modes
High High High High Address Space Expanded Expanded Single-chip On-Chip Disabled Enabled Enabled On-Chip Enabled* Enabled* Enabled
Note: RAME system control register (SYSCR) cleared off-chip memory accessed instead.
Modes expanded modes that permit access off-chip memory peripheral devices. maximum address space supported these externally expanded modes kbytes. mode (single-chip mode), only on-chip on-chip register field used. ports available general-purpose input output. Mode inoperative H8/3437 Series. Avoid setting mode pins mode change mode settings while chip operating. 3.1.2 Mode System Control Registers
Table lists registers related chip's operating mode: system control register (SYSCR) mode control register (MDCR). mode control register indicates inputs mode pins Table
Name System control register Mode control register
Mode System Control Registers
Abbreviation SYSCR MDCR Read/Write Address H'FFC4 H'FFC5
System Control Register (SYSCR)
SSBY STS2 STS1 STS0 XRST NMIEG RAME
Initial value Read/Write
system control register (SYSCR) 8-bit register that controls operation chip. 7-Software Standby (SSBY): Enables transition software standby mode. details, section Power-Down State. recovery from software standby mode external interrupt, SSBY remains cleared writing
SSBY Description SLEEP instruction causes transition sleep mode. (Initial value)
SLEEP instruction causes transition software standby mode.
Bits 4-Standby Timer Select (STS2 STS0): These bits select clock settling time when chip recovers from software standby mode external interrupt. During selected time on-chip supporting modules continue stand These bits should according clock frequency that settling time least specific settings, section 22.3.3, Clock Settling Time Exit from Software Standby Mode. ZTAT Mask Versions
STS2 STS1 STS0 Description Settling time 8,192 states Settling time 16,384 states Settling time 32,768 states Settling time 65,536 states Settling time 131,072 states Unused (Initial value)
F-ZTAT Version
STS2 STS1 STS0 Description Settling time 8,192 states Settling time 16,384 states Settling time 32,768 states Settling time 65,536 states Settling time 131,072 states Settling time 1,024 states Unused (Initial value)
Note: When 1,024 states (STS2 STS0 101) selected, following points should noted. period exceeding (e.g. specified when selecting 8-bit timer, timer, watchdog timer clock, counter timer will count normally when 1,024 states specified settling time. avoid this problem, value just before transition software standby mode (before executing SLEEP instruction), re-set value STS2 STS0 value from directly after software standby mode cleared interrupt.
3-External Reset (XRST): Indicates source reset. reset generated input external reset signal, watchdog timer overflow when watchdog timer used. XRST read-only bit. external reset, cleared watchdog timer overflow.
XRST Description Reset caused watchdog timer overflow. Reset caused external input. (Initial value)
2-NMI Edge (NMIEG): Selects valid edge input.
NMIEG Description interrupt requested falling edge input. interrupt requested rising edge input. (Initial value)
1-Host Interface Enable (HIE): Enables disables host interface function. When enabled, host interface processes host-slave data transfers, operating slave mode.
Description host interface disabled. host interface enabled (slave mode). (Initial value)
0-RAM Enable (RAME): Enables disables on-chip RAM. RAME initialized reset, initialized software standby mode.
RAME Description on-chip disabled. on-chip enabled. (Initial value)
Mode Control Register (MDCR)
EXPE
MDS1
MDS0
Initial value Read/Write
R/W*2
Notes: H8/3437SF (S-mask model, single-power-supply on-chip flash memory version) only. Otherwise, this reserved that always read Determined mode pins (MD1 MD0).
mode control register (MDCR) 8-bit register that indicates operating mode chip. 7-Expanded Mode Enable (EXPE): Functions only H8/3437SF (S-mask model, single-power-supply on-chip flash memory version). details, section 21.1.6, Mode Control Register (MDCR). models other than H8/3437SF, this reserved that cannot modified always read Bits 5-Reserved: These bits cannot modified always read Bits 3-Reserved: These bits cannot modified always read 2-Reserved: This cannot modified always read Bits 0-Mode Select (MDS1 MDS0): These bits indicate values mode pins (MD1 MD0), thereby indicating current operating mode chip. MDS1 corresponds MDS0 MD0. These bits read written. When mode control register read, levels mode pins (MD1 latched these bits.
Address Space Each Operating Mode
Figures show memory maps H8/3437, H8/3436, H8/3434 modes
Mode Expanded Mode without On-Chip H'0000 Vector table H'004B H'004C H'004B H'004C H'0000 Vector table H'004B H'004C Mode Expanded Mode with On-Chip H'0000 Vector table Mode Single-Chip Mode
On-chip 61,312 bytes On-chip 63,360 bytes
External address space
H'EF7F H'EF80 External address space H'F77F H'F780 On-chip RAM*, 2,048 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF H'F77F H'F780 On-chip RAM*, 2,048 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF H'FF7F H'FF88 H'FFFF H'FF7F H'FF80 On-chip RAM, 2,048 bytes
On-chip register field
Note: External memory accessed these addresses when RAME system control register (SYSCR) cleared
Figure H8/3437 Address Space
Mode Expanded Mode without On-Chip H'0000 Vector table H'004B H'004C H'004B H'004C H'0000
Mode Expanded Mode with On-Chip H'0000 Vector table H'004B H'004C
Mode Single-Chip Mode
Vector table
On-chip 49,152 bytes
On-chip 49,152 bytes
External address space
H'BFFF H'C000 Reserved*1 H'EF7F H'EF80 External address space H'F77F H'F780 On-chip 2,048 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF H'F77F H'F780 On-chip 2,048 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF
H'BFFF H'C000
Reserved*1
H'F77F H'F780 On-chip 2,048 bytes H'FF7F H'FF88 On-chip register field H'FFFF
Notes: access reserved areas. External memory accessed these addresses when RAME system control register (SYSCR) cleared
Figure H8/3436 Address Space
Mode Expanded Mode without On-Chip H'0000 Vector table H'004B H'004C H'004B H'004C H'0000
Mode Expanded Mode with On-Chip H'0000 Vector table H'004B H'004C
Mode Single-Chip Mode
Vector table
On-chip 32,768 bytes
On-chip 32,768 bytes
External address space
H'7FFF H'8000
H'7FFF H'8000
Reserved*1 H'EF7F H'EF80 External address space H'F77F H'F780 Reserved*1, H'FB7F H'FB80 On-chip 1,024 bytes H'FB7F H'FB80 H'F77F H'F780 Reserved*1, On-chip 1,024 bytes H'FB80 H'FF7F H'FF88 On-chip register field H'FFFF H'F77F H'F780 Reserved*1 On-chip 1,024 bytes Reserved*1
H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF
H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF
Notes: access reserved areas. External memory accessed these addresses when RAME system control register (SYSCR) cleared
Figure H8/3434 Address Space
Section Exception Handling
Overview
H8/3437 Series recognizes kinds exceptions: interrupts reset. Table indicates their priority timing their hardware exception-handling sequence. Table
Priority High
Hardware Exception-Handling Sequences Priority
Type Exception Reset Interrupt Detection Timing Synchronized with clock instruction execution* Timing Exception-Handling Sequence hardware exception-handling sequence begins soon changes from high. When interrupt requested, hardware exception-handling sequence begins current instruction, current hardware exception-handling sequence.
Note: detected after ANDC, ORC, XORC, instructions.
4.2.1
Reset
Overview
reset highest exception-handling priority. When goes when there watchdog timer reset (when reset option selected watchdog timer overflow), current processing stops chip enters reset state. internal state registers on-chip supporting modules initialized. reset exception-handling sequence starts when returns from high, watchdog reset pulse. 4.2.2 Reset Sequence
reset state begins when goes watchdog reset generated. ensure correct resetting, power-on should held least reset during operation, should held least system clock cycles. watchdog reset pulse width always system clocks. states during reset, appendix States.
following sequence carried when reset exception handling begins. internal state registers on-chip supporting modules initialized, condition code register (CCR) loads program counter with first word vector table (stored addresses H'0000 H'0001) starts program execution. should held when power switched off, well when power switched Figure indicates timing reset sequence modes Figure indicates timing mode
Vector fetch
RES/watchdog timer reset (internal) Internal address Internal read signal Internal write signal Internal data bits) Reset vector address (H'0000) Starting address program First instruction program
Internal Instruction processing prefetch
Figure Reset Sequence (Mode Program Stored On-Chip ROM)
Vector fetch
Internal processing
Instruction prefetch
RES/watchdog timer reset (internal)
Figure Reset Sequence (Mode
bits)
(1), (2), (5), (6),
Reset vector address: H'0000, H'0001 Starting address program (contents reset vector): upper byte, lower byte Starting address program: (4), First instruction program: first byte, second byte
4.2.3
Disabling Interrupts after Reset
After reset, interrupt were accepted before initialization stack pointer (SP: R7), program counter condition code register might saved correctly, leading program crash. prevent this, interrupts, including NMI, disabled immediately after reset. first program instruction therefore always executed. This instruction should initialize stack pointer (example: MOV.W #xx:16, SP). After reset exception handling, order initialize contents CCR, manipulation instruction executed before instruction initialize stack pointer. Immediately after execution manipulation instruction, interrupts including disabled. next instruction initialize stack pointer.
4.3.1
Interrupts
Overview
interrupt sources include nine external sources from input pins (NMI, IRQ0 IRQ7, KEYIN0 KEYIN15), internal sources on-chip supporting modules. Table lists interrupt sources priority order gives their vector addresses. When more interrupts requested, interrupt with highest priority served first. features these interrupts are: highest priority always accepted. internal external interrupts except masked CCR. When interrupts other than accepted. IRQ0 IRQ7 sensed falling edge input signal, level-sensed. type sensing selected each interrupt individually. edge-sensed, either rising falling edge selected. interrupts individually vectored. software interrupt-handling routine does have determine what type interrupt occurred. IRQ6 multiplexed with external sources (KEYIN0 KEYIN15). KEYIN0 KEYIN15 masked individually user software. watchdog timer generate either overflow interrupt, depending needs application. details, section Watchdog Timer.
Table
Interrupts
ICIA (Input capture ICIB (Input capture ICIC (Input capture ICID (Input capture OCIA (Output compare OCIB (Output compare FOVI (Overflow) CMI0A (Compare-match CMI0B (Compare-match OVI0 (Overflow) CMI1A (Compare-match CMI1B (Compare-match OVI1 (Overflow) IBF1 (IDR1 receive end) IBF2 (IDR2 receive end) ERI0 (Receive error) RXI0 (Receive end) TXI0 (TDR empty) TEI0 (TSR empty) ERI1 (Receive error) RXI1 (Receive end) TXI1 (TDR empty) TEI1 (TSR empty) (Conversion end) WOVF (WDT overflow) IICI (Transfer end) Vector Table Address H'0006 H'0007 H'0008 H'0009 H'000A H'000B H'000C H'000D H'000E H'000F H'0010 H'0011 H'0012 H'0013 H'0014 H'0015 H'0016 H'0017 H'0018 H'0019 H'001A H'001B H'001C H'001D H'001E H'001F H'0020 H'0021 H'0022 H'0023 H'0024 H'0025 H'0026 H'0027 H'0028 H'0029 H'002A H'002B H'002C H'002D H'002E H'002F H'0030 H'0031 H'0032 H'0033 H'0034 H'0035 H'0036 H'0037 H'0038 H'0039 H'003A H'003B H'003C H'003D H'003E H'003F H'0040 H'0041 H'0042 H'0043 H'0044 H'0045 H'0046 H'0047 H'0048 H'0049 H'004A H'004B Priority High
Interrupt source IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 16-bit free-running timer
8-bit timer
8-bit timer
Host interface Serial communication interface Serial communication interface converter Watchdog timer interface
Notes: H'0000 H'0001 contain reset vector. H'0002 H'0005 reserved H8/3437 Series available user.
4.3.2
Interrupt-Related Registers
interrupt-related registers system control register (SYSCR), sense control register (ISCR), enable register (IER), keyboard matrix interrupt mask registers (KMIMR KMIMRA). Table
Name System control register sense control register enable register Keyboard matrix interrupt mask register Keyboard matrix interrupt mask register
Registers Read Interrupt Controller
Abbreviation SYSCR ISCR KMIMR KMIMRA Read/Write Address H'FFC4 H'FFC6 H'FFC7 H'FFF1 H'FFF3
System Control Register (SYSCR)
SSBY Initial value Read/Write STS2 STS1 STS0 XRST NMIEG RAME
valid edge line controlled (NMIEG) system control register. 2-NMI Edge (NMIEG): Determines whether nonmaskable interrupt generated falling rising edge input signal.
NMIEG Description interrupt generated falling edge NMI. interrupt generated rising edge NMI. (Initial state)
section 3.2, System Control Register, information other SYSCR bits. Sense Control Register (ISCR)
IRQ7SC IRQ6SC IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC Initial value Read/Write
Bits 0-IRQ7 IRQ0 Sense Control (IRQ7SC IRQ0SC): These bits determine whether IRQ7 IRQ0 level-sensed sensed falling edge.
Bits IRQ7SC IRQ0SC Description interrupt generated when IRQ7 IRQ0 inputs low. (Initial state) interrupt generated falling edge IRQ7 IRQ0 inputs.
Enable Register (IER)
IRQ7E Initial value IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
Bits 0-IRQ7 IRQ0 Enable (IRQ7E IRQ0E): These bits enable disable IRQ7 IRQ0 interrupts individually.
Bits IRQ7E IRQ0E Description IRQ7 interrupt requests disabled. IRQ7 interrupt requests enabled. (Initial state)
When edge sensing selected setting bits IRQ7SC IRQ0SC possible interrupt-handling routine executed even though corresponding enable (IRQ7E IRQ0E) cleared interrupt disabled. interrupt requested while enable (IRQ7E IRQ0E) request will held pending until served. enable cleared while request still pending, request will remain pending, although requests will recognized. interrupt mask cleared interrupt-handling routine executed even though enable execution interrupt-handling routines under these conditions desired, avoided using following procedure disable clear interrupt requests. CCR, masking interrupts. Note that automatically when execution jumps interrupt vector. Clear desired bits from IRQ7E IRQ0E disable interrupt requests. Clear corresponding IRQ7SC IRQ0SC bits then them again. Pending IRQn interrupt requests cleared when CCR, IRQnSC IRQnE
Keyboard Matrix Interrupt Mask Register (KMIMR) control interrupts from matrix keyboard key-sense input pins KEYIN0 KEYIN15, there keyboard matrix interrupt mask registers, KMIMR KMIMRA. Bits KMIMR7 KMIMR0 KMIMR correspond key-sense inputs KEYIN7 KEYIN0. Bits KMIMR15 KMIMR8 KMIMRA correspond key-sense inputs KEYIN15 KEYIN8. Initially, KMIMR6 that corresponds IRQ6/KEYIN6 interrupt-enabled state, other interrupt mask bits interrupt-disabled state. KMIMR 8-bit readable/writable register used keyboard matrix scanning sensing. This register initializes state which only input IRQ6 enabled. enable keysense input interrupts from more pins during keyboard scanning sensing, clear corresponding mask bits
KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0 Initial value Read/Write
Bits 0-Keyboard Matrix Interrupt Mask (KMIMR7 KMIMR0): These bits control key-sense input interrupt requests KEYIN7 KEYIN0.
Bits KMIMR7 KMIMR0 Description Key-sense input interrupt request enabled. Key-sense input interrupt request disabled. (Initial value)*
Note: Except KMIMR6, which initially
KMIMR9
KMIMR8
KMIMR15 KMIMR14 KMIMR13 KMIMR12 KMIMR11 KMIMR10
Initial value Read/Write
Bits 0-Keyboard Matrix Interrupt Mask (KMIMR15 KMIMR8): These bits control key-sense input interrupt requests KEYIN15 KEYIN8.
Bits KMIMR15 KMIMR8 Description Key-sense input interrupt request enabled. Key-sense input interrupt request disabled. (Initial value)
Figure shows relationship between IRQ6 interrupt, KMIMR, KMIMRA.
KMIMR0 P60/KEYIN0
IRQ6 internal signal
KMIMR6 P66/KEYIN6/IRQ6 KMIMR7 P67/KEYIN7 Edge/level select enable/ disable control IRQ6E IRQ6SC
IRQ6 interrupt
KMIMR8 PA0/KEYIN8
KMIMR15 PA7/KEYIN15
Initial values given parentheses
Figure KMIMR, KMIMRA, IRQ6 Interrupt
4.3.3
External Interrupts
nine external interrupts IRQ0 IRQ7. NMI, IRQ1, IRQ2, IRQ6 used recover from software standby mode. NMI: nonmaskable interrupt generated rising falling edge input signal regardless whether (interrupt mask) CCR. valid edge selected NMIEG system control register. vector number hardware exception-handling sequence IRQ0 IRQ7: These interrupt signals level-sensed sensed falling edge input, selected ISCR bits IRQ0SC IRQ7SC. These interrupts masked collectively CCR, enabled disabled individually setting clearing bits IRQ0E IRQ7E enable register. IRQ6 input signal logically ORed internally with sense input signals. When KEYIN0 KEYIN15 pins PA7) used sense input, corresponding KMIMR bits should cleared enable corresponding sense input interrupts. KMIMR bits corresponding unused sense inputs should disable interrupts. sense interrupts combined into single IRQ6 interrupt. When these interrupts accepted, IRQ0 IRQ7 have interrupt vector numbers They prioritized order from IRQ7 (low) IRQ0 (high). details, table 4.2. Interrupts IRQ7 depend whether pins IRQ0 IRQ7 input output pins. When using external interrupts IRQ0 IRQ7, clear corresponding bits these pins input state, these pins input output pins timers, serial communication interface, interface, host interface, converter. 4.3.4 Internal Interrupts
Twenty-six internal interrupts requested on-chip supporting modules. Each interrupt source vector number, interrupt-handling routine does have determine which interrupt occurred. internal interrupts masked when When these interrupts accepted, mask further interrupts (except NMI). vector numbers priority order, table 4.2.
4.3.5
Interrupt Handling
Interrupts controlled interrupt controller that arbitrates between simultaneous interrupt requests, commands start hardware interrupt exception-handling sequence, furnishes necessary vector number. Figure shows block diagram interrupt controller.
interrupt IRQ0 flag IRQ0E IRQ0 interrupt Priority decision
Interrupt controller
Interrupt request
Vector number
IRIC IEIC
IICI interrupt
(CCR)
Note: edge-sensed interrupts, these gates change circuit shown below. IRQ0 edge IRQ0E IRQ0 flag
IRQ0 interrupt
Figure Block Diagram Interrupt Controller interrupts interrupts from on-chip supporting modules (except reset selected watchdog timer overflow) have corresponding enable bits. When enable cleared interrupt signal sent interrupt controller, interrupt ignored. These interrupts also masked setting CPU's interrupt mask Accordingly, these interrupts accepted only when their enable cleared nonmaskable interrupt (NMI) always accepted, except reset state hardware standby mode.
When another enabled interrupt requested, interrupt controller transfers interrupt request indicates corresponding vector number. (When more interrupts requested, interrupt controller selects vector number interrupt with highest priority.) When notified interrupt request, current instruction current hardware exception-handling sequence, starts hardware exception-handling sequence interrupt latches vector number. Figure flowchart interrupt (and reset) operations. Figure shows interrupt timing sequence case which software interrupt-handling routine on-chip stack on-chip RAM. interrupt request sent interrupt controller when interrupt occurs, when interrupt occurs input line on-chip supporting module provided enable that interrupt interrupt controller checks accepts interrupt request cleared only requests accepted; other interrupt requests remain pending. Among accepted interrupt requests, interrupt controller selects request with highest priority passes CPU. Other interrupt requests remain pending. When receives interrupt request, waits until completion current instruction hardware exception-handling sequence, then starts hardware exceptionhandling sequence interrupt latches interrupt vector number. hardware exception-handling sequence, first pushes onto stack. figure 4.6. stacked indicates address first instruction that will executed return from software interrupt-handling routine. Next masking further interrupts except NMI. vector address corresponding vector number generated, vector table entry this vector address loaded into program counter, execution branches software interrupt-handling routine address indicated that entry.
Program execution
Interrupt requested? NMI?
IRQ0? IRQ1? IICI? Pending
Latch vector
Save
Reset
Save
Read vector address
Branch software interrupt-handling routine
Figure Hardware Interrupt-Handling Sequence
(R7) Stack area
SP(R7)
CCR*
(upper byte)
(lower byte) Even address
Before interrupt accepted
Pushed onto stack
After interrupt accepted
Program counter CCR: Condition code register Stack pointer Notes: contains address first instruction executed after return. Registers must saved restored word access even address. Ignored return.
Figure Usage Stack Interrupt Handling comprised byte, when saved stack, treated word data. During interrupt processing, identical bytes data saved stack create word data. When instruction executed restore value from stack, byte located even address loaded into CCR, byte located address ignored.
Interrupt accepted Interrupt priority decision. Wait Instruction Internal instruction. prefetch processing Interrupt request signal Vector fetch
Stack
Instruction prefetch (first instruction Internal interrupt-handling process- routine)
Internal address
Internal read signal Internal write signal
Internal 16-bit data
(10)
(10)
Instruction prefetch address (Pushed stack. Instruction executed return from interrupt-handling routine.) Instruction code (Not executed) Instruction prefetch address (Not executed) SP-2 SP-4 Address vector table entry Vector table entry (address first instruction interrupt-handling routine) First instruction interrupt-handling routine
Figure Timing Interrupt Sequence
4.3.6
Interrupt Response Time
Table indicates number states that elapse from interrupt request signal until first instruction software interrupt-handling routine executed. Since on-chip memory accessed bits time, very fast interrupt service obtained placing interrupt-handling routines on-chip stack on-chip RAM. Table Number States before Interrupt Service
Number States Reason Wait Interrupt priority decision Wait completion current instruction*1 Save Fetch vector Fetch instruction Internal processing Total On-Chip Memory
External Memory 12*2 12*2
Notes: These values apply current instruction EEPMOV. wait states inserted external memory access, number wait states. internal interrupts.
4.3.7
Precaution
Note that following type contention occur interrupt handling. When software clears enable interrupt disable interrupt, interrupt becomes disabled after execution clearing instruction. enable cleared BCLR instruction, example, interrupt requested during execution that instruction, instant when instruction ends interrupt still enabled, after execution instruction, hardware exception-handling sequence executed interrupt. higher-priority interrupt requested same time, however, hardware exception-handling sequence executed higher-priority interrupt interrupt that disabled ignored. Similar considerations apply when interrupt request flag cleared Figure shows example which OCIAE cleared
write cycle TIER Internal address TIER address
OCIA interrupt handling
Internal write signal OCIAE OCFA OCIA interrupt signal
Figure Contention between Interrupt Disabling Instruction above contention does occur enable flag cleared while interrupt mask
Note Stack Handling
word access, least significant address always assumed stack always accessed word access. Care should taken keep even value stack pointer (general register R7). PUSH MOV.W @-SP MOV.W @SP+, instructions push registers stack. Setting stack pointer value cause programs crash. Figure shows example damage caused when stack pointer contains address.
H'FECC H'FECD
H'FECF
instruction
MOV.B R1L, @-R7
H'FECF
improperly stored beyond stack
lost
PCH: PCL: R1L:
Upper byte program counter Lower byte program counter General register Stack pointer
Figure Example Damage Caused Setting Address
Section Wait-State Controller
Overview
H8/3437 Series on-chip wait-state controller that enables insertion wait states into cycles interfacing low-speed external devices. 5.1.1 Features
Features wait-state controller listed below. Three selectable wait modes: programmable wait mode, auto-wait mode, wait mode Automatic insertion zero three wait states 5.1.2 Block Diagram
Figure shows block diagram wait-state controller.
Internal data
WAIT
Wait-state controller (WSC) WSCR
Wait request signal
Legend: WSCR: Wait-state control register
Figure Block Diagram Wait-State Controller
5.1.3
Input/Output Pins
Table summarizes wait-state controller's input pin. Table
Name Wait
Wait-State Controller Pins
Abbreviation WAIT Input Function Wait request signal access external addresses
5.1.4
Register Configuration
Table summarizes wait-state controller's register. Table
Address H'FFC2
Register Configuration
Name Wait-state control register Abbreviation WSCR Initial Value H'08
5.2.1
Register Description
Wait-State Control Register (WSCR)
WSCR 8-bit readable/writable register that selects wait mode wait-state controller (WSC) specifies number wait states. also controls area setting dual-powersupply flash memory, selection/non-selection single-power-supply flash memory control registers, frequency division clock signals supplied supporting modules.
RAMS Initial value Read/Write
RAM0
WMS1
WMS0
CKDBL FLSHE
Notes: These bits valid only H8/3437F H8/3434F (dual-power-supply on-chip flash memory versions). This valid only H8/3437SF (S-mask model, single-power-supply on-chip flash memory version).
WSCR initialized H'08 reset hardware standby mode. initialized software standby mode.
7-RAM Select (RAMS) 6-RAM Area Select (RAM0) Bits select area emulation dual-power-supply flash memory updates. details, flash memory description section ROM. 5-Clock Double (CKDBL): Controls frequency division clock signals supplied supporting modules. details, section Clock Pulse Generator. 4-Flash Memory Control Register Enable (FLSHE): Controls selection/non-selection single-power-supply flash memory control registers. details, description flash memory section ROM. models other than H8/3437SF, this reserved, written read; initial value Bits 2-Wait Mode Select (WMS1/0): These bits select wait mode.
WMS1 WMS0 Description Programmable wait mode wait states inserted wait-state controller wait mode auto-wait mode (Initial value)
Bits 0-Wait Count (WC1/0): These bits select number wait states inserted access external address areas.
Description wait states inserted wait-state controller state inserted states inserted states inserted (Initial value)
Wait Modes
Programmable Wait Mode: number wait states selected bits inserted accesses external addresses. Figure shows timing when wait count (WC1
Address
External address
Read access Data Read data
Write access Data Write data
Figure Programmable Wait Mode
Wait Mode: accesses external addresses, number wait states (TW) selected bits inserted. WAIT fall system clock last these wait states, additional wait state inserted. WAIT remains low, wait states continue inserted until WAIT signal goes high. wait mode useful inserting four more wait states, inserting different numbers wait states different external devices. Figure shows timing when wait count (WC1 additional wait state inserted WAIT input.
Inserted wait count Inserted WAIT signal
WAIT Address Read data Data Write access Data Note: Arrows indicate time sampling WAIT pin. Write data External address
Read access
Figure Wait Mode
Auto-Wait Mode: WAIT low, number wait states (TW) selected bits inserted. auto-wait mode, WAIT fall system clock state, number wait states selected bits inserted. additional wait states inserted even WAIT remains low. auto-wait mode used easy interface low-speed memory, simply routing chip select signal WAIT pin. Figure shows timing when wait count
WAIT
Address
External address
External address
Read access Data Read data Read data
Write access Data Write data Write data
Note: Arrows indicate time sampling WAIT pin.
Figure Auto-Wait Mode
Section Clock Pulse Generator
Overview
H8/3437 Series built-in clock pulse generator (CPG) consisting oscillator circuit, duty adjustment circuit, divider prescaler that generates clock signals on-chip supporting modules. 6.1.1 Block Diagram
Figure shows block diagram clock pulse generator.
XTAL EXTAL
Oscillator circuit
Duty adjustment circuit
(system clock)
(for supporting modules) Prescaler
Frequency divider (1/2) CKDBL
Figure Block Diagram Clock Pulse Generator Input external clock signal EXTAL pin, connect crystal resonator XTAL EXTAL pins. system clock frequency will same input frequency. This same system clock frequency supplied timers other supporting modules, divided two. selection made software, controlling CKDBL bit.
6.1.2
Wait-State Control Register (WSCR)
WSCR 8-bit readable/writable register that controls frequency division clock signals supplied supporting modules. also controls wait state controller wait settings, area setting dual-power-supply flash memory, selection/non-selection single-power-supply flash memory control registers. WSCR initialized H'08 reset hardware standby mode. initialized software standby mode.
RAMS Initial value Read/Write
RAM0
WMS1
WMS0
CKDBL FLSHE
Notes: These bits valid only H8/3437F H8/3434F (dual-power-supply on-chip flash memory versions). This valid only H8/3437SF (S-mask model, single-power-supply on-chip flash memory version).
7-RAM Select (RAMS) 6-RAM Area Select (RAM0) Bits select area emulation dual-power-supply flash memory updates. details, flash memory description section ROM. 5-Clock Double (CKDBL): Controls frequency division clock signals supplied supporting modules.
CKDBL Description undivided system clock supplied clock supporting modules. (Initial value) system clock divided supplied clock supporting modules.
4-Flash Memory Control Register Enable (FLSHE): Controls selection/non-selection single-power-supply flash memory control registers. details, description flash memory section ROM. models other than H8/3437SF, this reserved, written read; initial value Bits 2-Wait Mode Select (WMS1/0) Bits 0-Wait Count (WC1/0) These bits control wait-state insertion. details, section Wait-State Controller.
6.2.1
Oscillator Circuit
Oscillator (Generic Device)
external crystal connected across EXTAL XTAL pins, on-chip oscillator circuit generates system clock signal. Alternatively, external clock signal applied EXTAL pin. Connecting External Crystal Circuit Configuration: external crystal connected example figure 6.2. Table indicates appropriate damping resistance AT-cut parallel resonance crystal should used.
EXTAL
XTAL
Figure Connection Crystal Oscillator (Example) Table Damping Resistance
Frequency (MHz)
Crystal Oscillator: Figure shows equivalent circuit crystal resonator. crystal resonator should have characteristics listed table 6.2.
XTAL EXTAL
AT-cut parallel resonating crystal
Figure Equivalent Circuit External Crystal Table External Crystal Parameters
Frequency (MHz) (pF)
crystal with same frequency desired system clock frequency Note Board Design: When external crystal connected, other signal lines should kept away from crystal circuit prevent induction from interfering with correct oscillation. figure 6.4. crystal load capacitors should placed close possible XTAL EXTAL pins.
allowed
Signal
Signal
XTAL
E
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