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Cautions
Keep safety first your circuit designs! Renesas Technology Corporation puts maximum effort into making semiconductor products better more reliable, there always possibility that trouble occur with them. Trouble with semiconductors lead personal injury, fire property damage. Remember give consideration safety when making your circuit designs, with appropriate measures such placement substitutive, auxiliary circuits, (ii) nonflammable material (iii) prevention against malfunction mishap. Notes regarding these materials These materials intended reference assist customers selection Renesas Technology Corporation product best suited customer's application; they convey license under intellectual property rights, other rights, belonging Renesas Technology Corporation third party. Renesas Technology Corporation assumes responsibility damage, infringement third-party's rights, originating product data, diagrams, charts, programs, algorithms, circuit application examples contained these materials. information contained these materials, including product data, diagrams, charts, programs algorithms represents information products time publication these materials, subject change Renesas Technology Corporation without notice product improvements other reasons. therefore recommended that customers contact Renesas Technology Corporation authorized Renesas Technology Corporation product distributor latest product information before purchasing product listed herein. information described here contain technical inaccuracies typographical errors. Renesas Technology Corporation assumes responsibility damage, liability, other loss rising from these inaccuracies errors. Please also attention information published Renesas Technology Corporation various means, including Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). When using information contained these materials, including product data, diagrams, charts, programs, algorithms, please sure evaluate information total system before making final decision applicability information products. Renesas Technology Corporation assumes responsibility damage, liability other loss resulting from information contained herein. Renesas Technology Corporation semiconductors designed manufactured device system that used under circumstances which human life potentially stake. Please contact Renesas Technology Corporation authorized Renesas Technology Corporation product distributor when considering product contained herein specific purposes, such apparatus systems transportation, vehicular, medical, aerospace, nuclear, undersea repeater use. prior written approval Renesas Technology Corporation necessary reprint reproduce whole part these materials. these products technologies subject Japanese export control restrictions, they must exported under license from Japanese government cannot imported into country other than approved destination. diversion reexport contrary export control laws regulations Japan and/or country destination prohibited. Please contact Renesas Technology Corporation further details these materials products contained therein.
Hitachi 16-Bit Single-Chip Microcomputer
H8S/2140B Series
H8S/2161B HD64F2161BV, HD6432161BV, HD6432161BVW H8S/2160B HD64F2160BV, HD6432160BV, HD6432160BVW H8S/2141B F-ZTATHD64F2141BV H8S/2140B F-ZTATHD64F2140BV H8S/2145B F-ZTATHD64F2145BV H8S/2148B F-ZTATHD64F2148BV, HD64F2148B
Hardware Manual
ADE-602-274A Rev. 08/01/02 Hitachi, Ltd.
Cautions
Hitachi neither warrants grants licenses rights Hitachi's third party's patent, copyright, trademark, other intellectual property rights information contained this document. Hitachi bears responsibility problems that arise with third party's rights, including intellectual property rights, connection with information contained this document. Products product specifications subject change without notice. Confirm that have received latest product standards specifications before final design, purchase use. Hitachi makes every attempt ensure that products high quality reliability. However, contact Hitachi's sales office before using product application that demands especially high quality reliability where failure malfunction directly threaten human life cause risk bodily injury, such aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment medical equipment life support. Design your application that product used within ranges guaranteed Hitachi particularly maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions other characteristics. Hitachi bears responsibility failure damage when used beyond guaranteed ranges. Even within guaranteed ranges, consider normally foreseeable failure rates failure modes semiconductor devices employ systemic measures such fail-safes, that equipment incorporating Hitachi product does cause bodily injury, fire other consequential damage operation Hitachi product. This product designed radiation resistant. permitted reproduce duplicate, form, whole part this document without written approval from Hitachi. Contact Hitachi's sales office questions regarding this document Hitachi semiconductor products.
Rev. 2.0, 08/02, page xxxviii
General Precautions Handling Product
Treatment Pins Note: connect anything pins. (not connected) pins either connected internal circuitry used test pins reduce noise. something connected pins, operation guaranteed. Treatment Unused Input Pins Note: unused input pins high level. Generally, input pins CMOS products high-impedance input pins. unused pins their open states, intermediate levels induced noise vicinity, passthrough current flows internally, malfunction occur. Processing before Initialization Note: When power first supplied, product's state undefined. states internal circuits undefined until full power supplied throughout chip level input reset pin. During period where states undefined, register settings output state each also undefined. Design your system that does malfunction because processing while this undefined state. those products which have reset function, reset immediately after power supply been turned Prohibition Access Undefined Reserved Addresses Note: Access undefined reserved addresses prohibited. undefined reserved addresses used expand functions, test registers have been allocated these addresses. access these registers; system's operation guaranteed they accessed.
Rev. 2.0, 08/02, page xxxviii
Configuration This Manual
This manual comprises following items: General Precautions Handling Product Configuration This Manual Preface Contents Overview Description Functional Modules System-Control Modules On-Chip Peripheral Modules configuration functional description each module differs according module. However, generic style includes following items: Feature Input/Output iii) Register Description Operation Usage Note When designing application system that includes this LSI, take notes into account. Each section includes notes relation descriptions given, usage notes given, required, final part each section. List Registers Electrical Characteristics Appendix Main Revisions Additions this Edition (only revised versions) list revisions summary points that have been revised added earlier versions. This does include revised contents. details, actual locations this manual. Index
Rev. 2.0, 08/02, page xxxviii
Preface
H8S/2140B Series microcomputers (MCUs) made H8S/2000 employing Hitachi's original architecture their cores, peripheral functions required configure system. H8S/2000 internal 32-bit configuration, sixteen 16-bit general registers, simple optimized instruction high-speed operation. H8S/2000 handle 16-Mbyte linear address space. This equipped with data transfer controller (DTC) master, ROM, RAM, 8-bit timer (PWM), 14-bit timer (PWMX), 16-bit free-running timer (FRT), 8-bit timer (TMR), timer connection, watchdog timer (WDT), serial communication interface (SCI), keyboard buffer controller, host interface X-bus interface (XBS), host interface interface (LPC), 8-bit converter, 10-bit converter, ports on-chip peripheral modules required system configuration. interface (IIC) also included optional interface. high-functionality controller also provided, enabling fast easy connection DRAM other kinds memory. flash memory (F-ZTAT version available this LSI's ROM. This provides flexibility reprogrammed time cope with situations from early stages mass production full-scale mass production. This particularly applicable application devices with specifications that will most probably change. Note: F-ZTAT
trademark Hitachi, Ltd.
Target Users: This manual written users will using H8S/2140B Series design application systems. Target users expected understand fundamentals electrical circuits, logical circuits, microcomputers. Objective: This manual written explain hardware functions electrical characteristics H8S/2140B Series target users. Refer H8S/2600 Series, H8S/2000 Series Programming Manual detailed description instruction set.
Notes reading this manual: order understand overall functions chip Read manual according contents. This manual roughly categorized into parts CPU, system control functions, peripheral functions electrical characteristics. order understand details CPU's functions
Rev. 2.0, 08/02, page xxxviii
Read H8S/2600 Series, H8S/2000 Series Programming Manual. order understand details register when name known Read index that final part manual find page number entry register. addresses, bits, initial values registers summarized section List Registers. Rules: Register name: following notation used cases when same similar function, e.g. serial communication interface, implemented more than channel: XXX_N (XXX register name channel number) left right. Binary B'xxxx, hexadecimal H'xxxx, decimal xxxx. overbar added low-active signal: [[[[
order: Number notation: Signal notation: Related Manuals:
latest versions related manuals available from site. Please ensure have latest versions documents require.
H8S/2140B Series manuals:
Manual Title H8S/2140B Series Hardware Manual H8S/2600 Series, H8S/2000 Series Programming Manual This manual ADE-602-083
User's manuals development tools:
Manual Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual H8S, H8/300 Series Simulator/Debugger User's Manual H8S, H8/300 Series Hitachi Embedded Workshop, Hitachi Debugging Interface Tutorial Hitachi Embedded Workshop User's Manual ADE-702-247 ADE-702-282 ADE-702-231 ADE-702-201
Rev. 2.0, 08/02, page xxxviii
Contents
Section Overview
Features Block Diagram Arrangement Functions 1.3.1 Arrangement 1.3.2 Functions Each Operating Mode.7 1.3.3 Functions.18
Section
Features 2.1.1 Differences between H8S/2600 H8S/2000 CPU.28 2.1.2 Differences from H8/300 CPU.28 2.1.3 Differences from H8/300H Operating Modes 2.2.1 Normal Mode 2.2.2 Advanced Mode Address Space Register Configuration 2.4.1 General Registers 2.4.2 Program Counter (PC).36 2.4.3 Extended Control Register (EXR).36 2.4.4 Condition-Code Register (CCR) 2.4.5 Initial Register Values Data Formats 2.5.1 General Register Data Formats 2.5.2 Memory Data Formats Instruction 2.6.1 Table Instructions Classified Function.42 2.6.2 Basic Instruction Formats.51 Addressing Modes Effective Address Calculation 2.7.1 Register Direct-Rn 2.7.2 Register Indirect-@ERn 2.7.3 Register Indirect with Displacement-@(d:16, ERn) @(d:32, ERn) 2.7.4 Register Indirect with Post-Increment Pre-Decrement-@ERn+ @-ERn 2.7.5 Absolute Address-@aa:8, @aa:16, @aa:24, @aa:32 2.7.6 Immediate-#xx:8, #xx:16, #xx:32 2.7.7 Program-Counter Relative-@(d:8, @(d:16, 2.7.8 Memory Indirect-@@aa:8.55 2.7.9 Effective Address Calculation.56
Rev. 2.0, 08/02, page xxxviii
Processing States Usage Notes.60 2.9.1 Note Instruction Usage 2.9.2 Note STM/LDM Instruction Usage.60 2.9.3 Note Manipulation Instructions.60 2.9.4 EEPMOV Instruction
Section Operating Modes.
Operating Mode Selection.63 Register Descriptions 3.2.1 Mode Control Register (MDCR).64 3.2.2 System Control Register (SYSCR) 3.2.3 Serial Timer Control Register (STCR).67 Operating Mode Descriptions 3.3.1 Mode 3.3.2 Mode 3.3.3 Mode 3.3.4 Functions Each Operating Mode Address Each Operating Mode
Section Exception Handling.
Exception Handling Types Priority Exception Sources Exception Vector Table Reset.81 4.3.1 Reset Exception Handling.81 4.3.2 Interrupts after Reset 4.3.3 On-Chip Peripheral Modules after Reset Cancelled Interrupt Exception Handling Trap Instruction Exception Handling Stack Status after Exception Handling Usage Note
Section Interrupt Controller
Features Input/Output Pins Register Descriptions 5.3.1 Interrupt Control Registers (ICRA ICRC).88 5.3.2 Address Break Control Register (ABRKCR).89 5.3.3 Break Address Registers (BARA BARC) 5.3.4 Sense Control Registers (ISCRH, ISCRL) 5.3.5 Enable Register (IER) 5.3.6 Status Register (ISR)
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Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) Wake-Up Event Interrupt Mask Register (WUEMRB).92 Interrupt Sources 5.4.1 External Interrupts.94 5.4.2 Internal Interrupts.96 Interrupt Exception Handling Vector Table Interrupt Control Modes Interrupt Operation 5.6.1 Interrupt Control Mode 5.6.2 Interrupt Control Mode .101 5.6.3 Interrupt Exception Handling Sequence.103 5.6.4 Interrupt Response Times.105 5.6.5 Activation Interrupt .106 Address Break .107 5.7.1 Features .107 5.7.2 Block Diagram .108 5.7.3 Operation.108 5.7.4 Usage Notes.109 Usage Notes.111 5.8.1 Conflict between Interrupt Generation Disabling.111 5.8.2 Instructions that Disable Interrupts .111 5.8.3 Interrupts during Execution EEPMOV Instruction .112 5.8.4 Setting Product Incorporating DTC.112 5.8.5 Status Register (ISR) .112
5.3.7
Section Controller.113
Features .113 Input/Output Pins .114 Register Descriptions.114 6.3.1 Control Register (BCR).115 6.3.2 Wait State Control Register (WSCR).116 Control .117 6.4.1 Specifications .117 6.4.2 Advanced Mode .118 6.4.3 Normal Mode .118 6.4.4 Select Signals .119 Basic Interface.120 6.5.1 Data Size Data Alignment .120 6.5.2 Valid Strobes .121 6.5.3 Basic Operation Timing .122 6.5.4 Wait Control.130 Burst Interface .131 6.6.1 Basic Operation Timing .131 6.6.2 Wait Control.132
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Idle Cycle .133 Arbitration.134 6.8.1 Priority Masters .134 6.8.2 Transfer Timing .134
Section Data Transfer Controller (DTC).
Features .135 Register Descriptions .136 7.2.1 Mode Register (MRA).137 7.2.2 Mode Register (MRB) .138 7.2.3 Source Address Register (SAR) .138 7.2.4 Destination Address Register (DAR) .138 7.2.5 Transfer Count Register (CRA).138 7.2.6 Transfer Count Register (CRB) .139 7.2.7 Enable Registers (DTCER) .139 7.2.8 Vector Register (DTVECR) .140 Activation Sources .140 Location Register Information Vector Table.141 Operation.144 7.5.1 Normal Mode .145 7.5.2 Repeat Mode .145 7.5.3 Block Transfer Mode .146 7.5.4 Chain Transfer.147 7.5.5 Interrupts .148 7.5.6 Operation Timing .149 7.5.7 Number Execution States.150 Procedures Using .151 7.6.1 Activation Interrupt .151 7.6.2 Activation Software .151 Examples .152 7.7.1 Normal Mode .152 7.7.2 Software Activation .153 Usage Notes.154 7.8.1 Module Stop Mode Setting .154 7.8.2 On-Chip RAM.154 7.8.3 DTCE Setting .154 7.8.4 Setting Required Entering Subactive Mode Watch Mode .154 7.8.5 Activation Interrupt Sources SCI, IIC, LPC, Converter .154
Section Ports
Overview .155 Port .160 8.2.1 Port Data Direction Register (P1DDR) .160
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8.2.2 Port Data Register (P1DR) .161 8.2.3 Port Pull-Up Control Register (P1PCR) .161 8.2.4 Functions.162 8.2.5 Port Input Pull-Up MOS.162 Port .163 8.3.1 Port Data Direction Register (P2DDR) .163 8.3.2 Port Data Register (P2DR) .164 8.3.3 Port Pull-Up Control Register (P2PCR) .164 8.3.4 Functions.165 8.3.5 Port Input Pull-Up MOS.166 Port .167 8.4.1 Port Data Direction Register (P3DDR) .167 8.4.2 Port Data Register (P3DR) .167 8.4.3 Port Pull-Up Control Register (P3PCR) .168 8.4.4 Functions.168 8.4.5 Port Input Pull-Up MOS.169 Port .169 8.5.1 Port Data Direction Register (P4DDR) .170 8.5.2 Port Data Register (P4DR) .170 8.5.3 Functions.171 Port .174 8.6.1 Port Data Direction Register (P5DDR) .174 8.6.2 Port Data Register (P5DR) .175 8.6.3 Functions.175 Port .176 8.7.1 Port Data Direction Register (P6DDR) .176 8.7.2 Port Data Register (P6DR) .177 8.7.3 Port Pull-Up Control Register (KMPCR) .177 8.7.4 Functions.177 8.7.5 Port Input Pull-Up MOS.180 Port .180 8.8.1 Port Input Data Register (P7PIN).181 8.8.2 Functions.181 Port .182 8.9.1 Port Data Direction Register (P8DDR) .182 8.9.2 Port Data Register (P8DR) .183 8.9.3 Functions.183 8.10 Port .186 8.10.1 Port Data Direction Register (P9DDR) .187 8.10.2 Port Data Register (P9DR) .188 8.10.3 Functions.188 8.11 Port .191 8.11.1 Port Data Direction Register (PADDR) .192
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8.12
8.13 8.14
8.15
8.16
8.11.2 Port Output Data Register (PAODR) .192 8.11.3 Port Input Data Register (PAPIN) .193 8.11.4 Functions.193 8.11.5 Port Input Pull-Up MOS.197 Port .198 8.12.1 Port Data Direction Register (PBDDR).198 8.12.2 Port Output Data Register (PBODR).199 8.12.3 Port Input Data Register (PBPIN) .199 8.12.4 Functions.200 8.12.5 Port Input Pull-Up MOS.202 Additional Overview H8S/2160B H8S/2161B .203 Ports .204 8.14.1 Port Port Data Direction Registers (PCDDR, PDDDR).205 8.14.2 Port Port Output Data Registers (PCODR, PDODR).206 8.14.3 Port Port Input Data Registers (PCPIN, PDPIN) .207 8.14.4 Port Port Nch-OD Control Register (PCNOCR, PDNOCR).208 8.14.5 Functions.208 8.14.6 Input Pull-Up Ports D.209 Ports F.209 8.15.1 Port Port Data Direction Registers (PEDDR, PFDDR) .210 8.15.2 Port Port Output Data Registers (PEODR, PFODR) .211 8.15.3 Port Port Input Data Registers (PEPIN, PFPIN) .212 8.15.4 Port Port Nch-OD Control Register (PENOCR, PFNOCR) .213 8.15.5 Functions.213 8.15.6 Input Pull-Up Ports .214 Port .214 8.16.1 Port Data Direction Register (PGDDR) .214 8.16.2 Port Output Data Register (PGODR) .215 8.16.3 Port Input Data Register (PGPIN) .215 8.16.4 Port Nch-OD Control Register (PGNOCR) .216 8.16.5 Functions.216
Section 8-Bit Timer (PWM)
Features .217 Input/Output Pin.219 Register Descriptions .219 9.3.1 Register Select (PWSL) .220 9.3.2 Data Registers (PWDR0 PWDR15) .222 9.3.3 Data Polarity Registers (PWDPRA, PWDPRB).222 9.3.4 Output Enable Registers (PWOERA, PWOERB) .223 9.3.5 Peripheral Clock Select Register (PCSR).224 Operation.225 Usage Note .226
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9.5.1
Module Stop Mode Setting.226
Section 14-Bit Timer (PWMX).227
10.1 Features .227 10.2 Input/Output Pins .228 10.3 Register Descriptions.228 10.3.1 (D/A) Counters (DACNTH, DACNTL) .228 10.3.2 (D/A) Data Registers (DADRA, DADRB).230 10.3.3 (D/A) Control Register (DACR).232 10.4 Master Interface .233 10.5 Operation.234 10.6 Usage Note .240 10.6.1 Module Stop Mode Setting.240
Section 16-Bit Free-Running Timer (FRT) .241
11.1 Features .241 11.2 Input/Output Pins .243 11.3 Register Descriptions.243 11.3.1 Free-Running Counter (FRC).244 11.3.2 Output Compare Registers (OCRA, OCRB).244 11.3.3 Input Capture Registers (ICRA ICRD).244 11.3.4 Output Compare Registers (OCRAR, OCRAF).245 11.3.5 Output Compare Register (OCRDM) .245 11.3.6 Timer Interrupt Enable Register (TIER) .246 11.3.7 Timer Control/Status Register (TCSR) .247 11.3.8 Timer Control Register (TCR) .250 11.3.9 Timer Output Compare Control Register (TOCR).251 11.4 Operation.253 11.4.1 Pulse Output .253 11.5 Operation Timing .253 11.5.1 Increment Timing .253 11.5.2 Output Compare Output Timing .254 11.5.3 Clear Timing .255 11.5.4 Input Capture Input Timing.255 11.5.5 Buffered Input Capture Input Timing.256 11.5.6 Timing Input Capture Flag (ICF) Setting.257 11.5.7 Timing Output Compare Flag (OCF) setting .258 11.5.8 Timing Overflow Flag Setting.258 11.5.9 Automatic Addition Timing .259 11.5.10 Mask Signal Generation Timing .259 11.6 Interrupt Sources .260 11.7 Usage Notes.261 11.7.1 Conflict between Write Clear.261
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11.7.2 11.7.3 11.7.4 11.7.5
Conflict between Write Increment .262 Conflict between Write Compare-Match .262 Switching Internal Clock Operation .264 Module Stop Mode Setting .266
Section 8-Bit Timer (TMR)
12.1 Features .267 12.2 Input/Output Pins .270 12.3 Register Descriptions .270 12.3.1 Timer Counter (TCNT) .271 12.3.2 Time Constant Register (TCORA) .271 12.3.3 Time Constant Register (TCORB) .271 12.3.4 Timer Control Register (TCR) .272 12.3.5 Timer Control/Status Register (TCSR) .275 12.3.6 Input Capture Register (TICR).281 12.3.7 Time Constant Register (TCORC) .281 12.3.8 Input Capture Registers (TICRR, TICRF).281 12.3.9 Timer Input Select Register (TISR) .282 12.4 Operation.282 12.4.1 Pulse Output .282 12.5 Operation Timing .283 12.5.1 TCNT Count Timing.283 12.5.2 Timing CMFA CMFB Setting Compare-Match .284 12.5.3 Timing Timer Output Compare-Match .284 12.5.4 Timing Counter Clear Compare-Match .285 12.5.5 TCNT External Reset Timing .285 12.5.6 Timing Overflow Flag (OVF) Setting.286 12.6 Operation with Cascaded Connection .286 12.6.1 16-Bit Count Mode .286 12.6.2 Compare-Match Count Mode.287 12.7 Input Capture Operation.287 12.8 Interrupt Sources .290 12.9 Usage Notes.291 12.9.1 Conflict between TCNT Write Clear.291 12.9.2 Conflict between TCNT Write Increment .292 12.9.3 Conflict between TCOR Write Compare-Match .293 12.9.4 Conflict between Compare-Matches B.294 12.9.5 Switching Internal Clocks TCNT Operation.294 12.9.6 Mode Setting with Cascaded Connection .296 12.9.7 Module Stop Mode Setting .296
Section Timer Connection.
13.1 Features .297
Rev. 2.0, 08/02, page xxxviii
13.2 Input/Output Pins .299 13.3 Register Descriptions.299 13.3.1 Timer Connection Register (TCONRI).300 13.3.2 Timer Connection Register (TCONRO).303 13.3.3 Timer Connection Register (TCONRS) .305 13.3.4 Edge Sense Register (SEDGR) .307 13.4 Operation.309 13.4.1 Decoding (PDC Signal Generation).309 13.4.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation).310 13.4.3 Measurement 8-Bit Timer Divided Waveform Period.312 13.4.4 Modification Signal.314 13.4.5 Signal Fall Modification Synchronization.316 13.4.6 Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation) .317 13.4.7 HSYNCO Output .320 13.4.8 VSYNCO Output .321 13.4.9 CBLANK Output .322 13.5 Usage Note .323 13.5.1 Module Stop Mode Setting.323
Section Watchdog Timer (WDT) .325
14.1 Features .325 14.2 Input/Output Pins .327 14.3 Register Descriptions.327 14.3.1 Timer Counter (TCNT) .327 14.3.2 Timer Control/Status Register (TCSR) .328 14.4 Operation.332 14.4.1 Watchdog Timer Mode .332 14.4.2 Interval Timer Mode .334 14.4.3 5(62 Signal Output Timing.335 14.5 Interrupt Sources .335 14.6 Usage Notes.336 14.6.1 Notes Register Access .336 14.6.2 Conflict between Timer Counter (TCNT) Write Increment .337 14.6.3 Changing Values CKS2 CKS0 Bits .337 14.6.4 Switching between Watchdog Timer Mode Interval Timer Mode .337 14.6.5 System Reset 5(62 Signal .338 14.6.6 Counter Values during Transitions between High-Speed, Sub-Active, Watch Modes .338
Section Serial Communication Interface (SCI IrDA).339
15.1 Features .339 15.2 Input/Output Pins .341
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15.3 Register Descriptions .341 15.3.1 Receive Shift Register (RSR).342 15.3.2 Receive Data Register (RDR) .342 15.3.3 Transmit Data Register (TDR) .342 15.3.4 Transmit Shift Register (TSR) .342 15.3.5 Serial Mode Register (SMR).343 15.3.6 Serial Control Register (SCR).345 15.3.7 Serial Status Register (SSR).347 15.3.8 Serial Interface Mode Register (SCMR) .349 15.3.9 Rate Register (BRR).350 15.3.10 Keyboard Comparator Control Register (KBCOMP) .356 15.4 Operation Asynchronous Mode.357 15.4.1 Data Transfer Format .357 15.4.2 Receive Data Sampling Timing Reception Margin Asynchronous Mode .359 15.4.3 Clock .360 15.4.4 Initialization (Asynchronous Mode) .361 15.4.5 Data Transmission (Asynchronous Mode).362 15.4.6 Serial Data Reception (Asynchronous Mode) .364 15.5 Multiprocessor Communication Function .368 15.5.1 Multiprocessor Serial Data Transmission .370 15.5.2 Multiprocessor Serial Data Reception.371 15.6 Operation Clocked Synchronous Mode .374 15.6.1 Clock .374 15.6.2 Initialization (Clocked Synchronous Mode) .375 15.6.3 Serial Data Transmission (Clocked Synchronous Mode).376 15.6.4 Serial Data Reception (Clocked Synchronous Mode).378 15.6.5 Simultaneous Serial Data Transmission Reception (Clocked Synchronous Mode) .380 15.7 IrDA Operation .382 15.8 Interrupt Sources .385 15.9 Usage Notes.386 15.9.1 Module Stop Mode Setting .386 15.9.2 Break Detection Processing.386 15.9.3 Mark State Break Detection .386 15.9.4 Receive Error Flags Transmit Operations (Clocked Synchronous Mode Only) .386 15.9.5 Relation between Writing TDRE Flag .386 15.9.6 Restrictions Using .387 15.9.7 Operations during Mode Transitions.387 15.9.8 Notes Switching from Pins Port Pins.391
Rev. 2.0, 08/02, page xxxviii
Section Interface (IIC) (Optional) .393
16.1 Features .393 16.2 Input/Output Pins .396 16.3 Register Descriptions.397 16.3.1 Data Register (ICDR).397 16.3.2 Slave Address Register (SAR) .398 16.3.3 Second Slave Address Register (SARX).399 16.3.4 Mode Register (ICMR) .401 16.3.5 Control Register (ICCR) .404 16.3.6 Status Register (ICSR) .414 16.3.7 Switch Register (DDCSWR) .418 16.3.8 Extended Control Register (ICXR) .420 16.4 Operation.424 16.4.1 Data Format.424 16.4.2 Initialization .426 16.4.3 Master Transmit Operation .426 16.4.4 Master Receive Operation .430 16.4.5 Slave Receive Operation .437 16.4.6 Slave Transmit Operation.444 16.4.7 IRIC Setting Timing Control.446 16.4.8 Automatic Switching from Formatless Mode Format.449 16.4.9 Operation Using .450 16.4.10 Noise Canceler .451 16.4.11 Initialization Internal State.452 16.5 Interrupt Sources .454 16.6 Usage Notes.454 16.6.1 Module Stop Mode Setting.463
Section Keyboard Buffer Controller.465
17.1 Features .465 17.2 Input/Output Pins .466 17.3 Register Descriptions.467 17.3.1 Keyboard Control Register (KBCRH).467 17.3.2 Keyboard Control Register (KBCRL) .469 17.3.3 Keyboard Data Buffer Register (KBBR).470 17.4 Operation.471 17.4.1 Receive Operation .471 17.4.2 Transmit Operation .472 17.4.3 Receive Abort.475 17.4.4 KCLKI Read Timing .477 17.4.5 KCLKO Write Timing .477 17.4.6 Setting Timing KCLK Control .478 17.4.7 Receive Timing .479
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17.4.8 KCLK Fall Interrupt Operation.480 17.5 Usage Notes.481 17.5.1 KBIOE Setting KCLK Falling Edge Detection.481 17.5.2 Module Stop Mode Setting .481
Section Host Interface X-Bus Interface (XBS)
18.1 Features .483 18.2 Input/Output Pins .485 18.3 Register Descriptions .486 18.3.1 System Control Register (SYSCR2) .486 18.3.2 Host Interface Control Register (HICR) Host Interface Control Register (HICR2).488 18.3.3 Input Data Register (IDR) .491 18.3.4 Output Data Register (ODR).491 18.3.5 Status Register (STR).492 18.4 Operation.493 18.4.1 Host Interface Activation .493 18.4.2 Control States .495 18.4.3 Gate .495 18.4.4 Host Interface Shutdown Function .497 18.5 Interrupt Sources .499 18.5.1 IBF1, IBF2, IBF3, IBF4 .499 18.5.2 HIRQ11, HIRQ1, HIRQ12, HIRQ3, HIRQ4 .499 18.6 Usage Notes.501 18.6.1 Note Host Interface .501 18.6.2 Module Stop Mode Setting .501
Section Host Interface Interface (LPC).
19.1 Features .503 19.2 Input/Output Pins .505 19.3 Register Descriptions .506 19.3.1 Host Interface Control Registers (HICR0, HICR1).507 19.3.2 Host Interface Control Registers (HICR2, HICR3).514 19.3.3 Channel Address Register (LADR3) .517 19.3.4 Input Data Registers (IDR1 IDR3).518 19.3.5 Output Data Registers (ODR1 ODR3).519 19.3.6 Bidirectional Data Registers (TWR0 TWR15) .529 19.3.7 Status Registers (STR1 STR3).520 19.3.8 SERIRQ Control Registers (SIRQCR0, SIRQCR1).527 19.3.9 Host Interface Select Register (HISEL) .535 19.4 Operation.536 19.4.1 Host Interface Activation .536 19.4.2 Cycles .537
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19.4.3 Gate .539 19.4.4 Host Interface Shutdown Function (LPCPD) .542 19.4.5 Host Interface Serialized Interrupt Operation (SERIRQ).546 19.4.6 Host Interface Clock Start Request (CLKRUN) .548 19.5 Interrupt Sources .548 19.5.1 IBFI1, IBFI2, IBFI3, ERRI.548 19.5.2 SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, HIRQ12 .549 19.6 Usage Notes.551 19.6.1 Module Stop Mode Setting.551 19.6.2 Notes Using Host Interface .551
Section Converter .553
20.1 Features .553 20.2 Input/Output Pins .554 20.3 Register Descriptions.554 20.3.1 Data Registers (DADR0, DADR1).554 20.3.2 Control Register (DACR).555 20.4 Operation.556 20.5 Usage Note .557 20.5.1 Module Stop Mode Setting.557
Section Converter .559
21.1 Features .559 21.2 Input/Output Pins .561 21.3 Register Descriptions.562 21.3.1 Data Registers (ADDRA ADDRD) .562 21.3.2 Control/Status Register (ADCSR).563 21.3.3 Control Register (ADCR).564 21.3.4 Keyboard Comparator Control Register (KBCOMP) .565 21.4 Operation.566 21.4.1 Single Mode .566 21.4.2 Scan Mode.566 21.4.3 Input Sampling Conversion Time.568 21.4.4 External Trigger Input Timing .569 21.5 Interrupt Sources .569 21.6 Conversion Accuracy Definitions.570 21.7 Usage Notes.572 21.7.1 Permissible Signal Source Impedance.572 21.7.2 Influences Absolute Accuracy.572 21.7.3 Setting Range Analog Power Supply Other Pins .573 21.7.4 Notes Board Design .573 21.7.5 Notes Noise Countermeasures.573 21.7.6 Module Stop Mode Setting.574
Rev. 2.0, 08/02, page xxxviii
Section RAM. Section ROM.
23.1 Features .577 23.2 Mode Transitions.579 23.3 Block Configuration.582 23.3.1 Block Configuration 64-Kbyte Flash Memory .582 23.3.2 Block Configuration 128-Kbyte Flash Memory .583 23.3.3 Block Configuration 256-Kbyte Flash Memory .584 23.4 Input/Output Pins .585 23.5 Register Descriptions .585 23.5.1 Flash Memory Control Register (FLMCR1) .586 23.5.2 Flash Memory Control Register (FLMCR2) .587 23.5.3 Erase Block Registers (EBR1, EBR2).587 23.6 Operating Modes .591 23.7 On-Board Programming Modes .591 23.7.1 Boot Mode.592 23.7.2 User Program Mode .596 23.8 Flash Memory Programming/Erasing .598 23.8.1 Program/Program-Verify .598 23.8.2 Erase/Erase-Verify .600 23.9 Program/Erase Protection.602 23.9.1 Hardware Protection.602 23.9.2 Software Protection .602 23.9.3 Error Protection.602 23.10 Interrupts during Flash Memory Programming/Erasing.603 23.11 Programmer Mode.604 23.12 Usage Notes.604
Section Masked Section Clock Pulse Generator.
25.1 Oscillator .610 25.1.1 Connecting Crystal Resonator.610 25.1.2 External Clock Input Method .611 25.2 Duty Correction Circuit.613 25.3 Medium-Speed Clock Divider.613 25.4 Master Clock Select Circuit .614 25.5 Subclock Input Circuit .614 25.6 Subclock Waveform Forming Circuit .614 25.7 Clock Select Circuit.615 25.8 Processing Pins.615 25.9 Usage Notes.616
Rev. 2.0, 08/02, page xxxviii
25.9.1 Note Resonator.616 25.9.2 Notes Board Design .616
Section Power-Down Modes .617
26.1 Register Descriptions.617 26.1.1 Standby Control Register (SBYCR).618 26.1.2 Low-Power Control Register (LPWRCR).620 26.1.3 Module Stop Control Registers (MSTPCRH, MSTPCRL) .621 26.2 Mode Transitions States.622 26.3 Medium-Speed Mode .625 26.4 Sleep Mode.626 26.5 Software Standby Mode .627 26.6 Hardware Standby Mode.628 26.7 Watch Mode .629 26.8 Subsleep Mode .630 26.9 Subactive Mode.631 26.10 Module Stop Mode.632 26.11 Direct Transitions .632 26.12 Usage Notes.633 26.12.1 Port Status .633 26.12.2 Current Consumption when Waiting Oscillation Stabilization.633 26.12.3 Module Stop Mode.633
Section List Registers.635
27.1 27.2 27.3 27.4 Register Addresses (Address Order) .635 Register Bits .646 Register States Each Operating Mode.655 Register Select Conditions .664
Section Electrical Characteristics .677
28.1 Electrical Characteristics H8S/2140B, H8S/2141B, H8S/2160B, H8S/2161B .677 28.1.1 Absolute Maximum Ratings.677 28.1.2 Characteristics.678 28.1.3 Characteristics.686 28.1.4 Conversion Characteristics .694 28.1.5 Conversion Characteristics .695 28.1.6 Flash Memory Characteristics.696 28.1.7 Usage Note .698 28.2 Electrical Characteristics H8S/2145B H8S/2148B .699 28.2.1 Absolute Maximum Ratings.699 28.2.2 Characteristics.701 28.2.3 Characteristics.719 28.2.4 Conversion Characteristics .730
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28.2.5 Conversion Characteristics.732 28.2.6 Flash Memory Characteristics.733 28.2.7 Usage Notes .735 28.3 Timing Chart .736 28.3.1 Clock Timing .736 28.3.2 Control Signal Timing.738 28.3.3 Timing.739 28.3.4 On-Chip Peripheral Module Timing .743
Appendix Port States Each Processing State Appendix Product Codes Appendix Package Dimensions Main Revisions Additions this Edition Index
Rev. 2.0, 08/02, page xxii xxxviii
Figures
Section Figure Figure Figure Figure Overview Internal Block Diagram H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B Internal Block Diagram H8S/2160B H8S/2161B Arrangement H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B Arrangement H8S/2160B H8S/2161B
Section Figure Exception Vector Table (Normal Mode) Figure Stack Structure Normal Mode Figure Exception Vector Table (Advanced Mode) Figure Stack Structure Advanced Mode Figure Memory Figure Internal Registers Figure Usage General Registers.35 Figure Stack Figure General Register Data Formats Figure General Register Data Formats Figure 2.10 Memory Data Formats Figure 2.11 Instruction Formats (Examples).52 Figure 2.12 Branch Address Specification Memory Indirect Addressing Mode Figure 2.13 State Transitions Section Figure Figure Figure Figure Figure Figure Figure Section Figure Figure Figure Operating Modes Address H8S/2140B H8S/2160B Address H8S/2140B H8S/2160B Address H8S/2141B H8S/2161B Address H8S/2141B H8S/2161B Address H8S/2145BV Address H8S/2145BV Address H8S/2148B (1).77 Exception Handling Reset Sequence (Mode Stack Status after Exception Handling Operation when Value
Section Interrupt Controller Figure Block Diagram Interrupt Controller Figure Relationship between Interrupts IRQ7 IRQ6, Interrupts KIN15 KIN0, Interrupts WUE7 WUE0, Registers KMIMR, KMIMRA, WUEMRB Figure Block Diagram Interrupts IRQ7 IRQ0 Figure Flowchart Procedure Interrupt Acceptance Interrupt Control Mode .100
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Figure State Transition Interrupt Control Mode 1.101 Figure Flowchart Procedure Interrupt Acceptance Interrupt Control Mode .103 Figure Interrupt Exception Handling .104 Figure Interrupt Controller .106 Figure Address Break Block Diagram .108 Figure 5.10 Address Break Timing Example.110 Figure 5.11 Conflict between Interrupt Generation Disabling .111 Section Controller Figure Block Diagram Controller .113 Figure Signal Output Timing.119 Figure Access Sizes Data Alignment Control (8-Bit Access Space).120 Figure Access Sizes Data Alignment Control (16-bit Access Space) .121 Figure Timing 8-Bit, 2-State Access Space.122 Figure Timing 8-Bit, 3-State Access Space.123 Figure Timing 16-Bit, 2-State Access Space (Even Byte Access) .124 Figure Timing 16-Bit, 2-State Access Space (Odd Byte Access) .125 Figure Timing 16-Bit, 2-State Access Space (Word Access).126 Figure 6.10 Timing 16-Bit, 3-State Access Space (Even Byte Access) .127 Figure 6.11 Timing 16-Bit, 3-State Access Space (Odd Byte Access) .128 Figure 6.12 Timing 16-Bit, 3-State Access Space (Word Access).129 Figure 6.13 Example Wait State Insertion Timing (Pin Wait Mode) .131 Figure 6.14 Access Timing Example Burst Space (AST BRSTS1 .132 Figure 6.15 Access Timing Example Burst Space (AST BRSTS1 .132 Figure 6.16 Examples Idle Cycle Operation.133 Section Data Transfer Controller (DTC) Figure Block Diagram DTC.136 Figure Block Diagram Activation Source Control.141 Figure Register Information Location Address Space .142 Figure Operation Flowchart .144 Figure Memory Mapping Normal Mode.145 Figure Memory Mapping Repeat Mode.146 Figure Memory Mapping Block Transfer Mode.147 Figure Chain Transfer Operation .148 Figure Operation Timing (Example Normal Mode Repeat Mode).149 Figure 7.10 Operation Timing (Example Block Transfer Mode, with Block Size 2).149 Figure 7.11 Operation Timing (Example Chain Transfer).149 Section 8-Bit Timer (PWM) Figure Block Diagram Timer .218 Figure Example Additional Pulse Timing (when Upper Bits PWDR 1000) .226
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Section Figure 10.1 Figure 10.2 Figure 10.3 Figure 10.4 Figure 10.5 Figure 10.6
14-Bit Timer (PWMX) (D/A) Block Diagram.227 Operation Output Waveform DADR corresponds .236 Output Waveform DADR corresponds TH).237 Data Register Configuration when .237 Output Waveform when DADR H'0207 .238
Section 16-Bit Free-Running Timer (FRT) Figure 11.1 Block Diagram 16-Bit Free-Running Timer.242 Figure 11.2 Example Pulse Output .253 Figure 11.3 Increment Timing with Internal Clock Source .253 Figure 11.4 Increment Timing with External Clock Source .254 Figure 11.5 Timing Output Compare Output.254 Figure 11.6 Clearing Compare-Match Signal.255 Figure 11.7 Input Capture Input Signal Timing (Usual Case) .255 Figure 11.8 Input Capture Input Signal Timing (When ICRA ICRD Read) .256 Figure 11.9 Buffered Input Capture Timing .256 Figure 11.10 Buffered Input Capture Timing (BUFEA 1).257 Figure 11.11 Timing Input Capture Flag (ICFA, ICFB, ICFC, ICFD) Setting .257 Figure 11.12 Timing Output Compare Flag (OCFA OCFB) Setting .258 Figure 11.13 Timing Overflow Flag (OVF) Setting .258 Figure 11.14 OCRA Automatic Addition Timing.259 Figure 11.15 Timing Input Capture Mask Signal Setting .259 Figure 11.16 Timing Input Capture Mask Signal Clearing.260 Figure 11.17 Write-Clear Conflict.261 Figure 11.18 Write-Increment Conflict .262 Figure 11.19 Conflict between Write Compare-Match (When Automatic Addition Function Used).263 Figure 11.20 Conflict between OCRAR/OCRAF Write Compare-Match (When Automatic Addition Function Used).264 Section 8-Bit Timer (TMR) Figure 12.1 Block Diagram 8-Bit Timers (TMR_0 TMR_1).268 Figure 12.2 Block Diagram 8-Bit Timers (TMR_Y TMR_X).269 Figure 12.3 Pulse Output Example .282 Figure 12.4 Count Timing Internal Clock Input .283 Figure 12.5 Count Timing External Clock Input (Both Edges).283 Figure 12.6 Timing Setting Compare-Match.284 Figure 12.7 Timing Toggled Timer Output Compare-Match Signal .284 Figure 12.8 Timing Counter Clear Compare-Match.285 Figure 12.9 Timing Counter Clear External Reset Input .285 Figure 12.10 Timing Flag Setting .286 Figure 12.11 Timing Input Capture Operation .288
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Figure 12.12 Timing Input Capture Signal (Input capture signal input during TICRR TICRF read).288 Figure 12.13 Input Capture Signal Selection .289 Figure 12.14 Conflict between TCNT Write Clear .291 Figure 12.15 Conflict between TCNT Write Increment.292 Figure 12.16 Conflict between TCOR Write Compare-Match.293 Section Figure 13.1 Figure 13.2 Figure 13.3 Figure 13.4 Figure 13.5 Figure 13.6 Figure 13.7 Figure 13.8 Figure 13.9 Section Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 Figure 14.5 Figure 14.6 Figure 14.7 Figure 14.8 Timer Connection Block Diagram Timer Connection .298 Timing Chart Decoding .310 Timing Chart Clamp Waveform Generation (CL1 Signals).311 Timing Chart Clamp Waveform Generation (CL3 Signal) .311 Timing Chart Measurement Signal Signal Divided Waveform Periods.314 Modification Timing Chart.315 Fall Modification Synchronization Timing Chart.317 Signal/IHG Signal/CL4 Signal Timing Chart.319 CBLANK Output Waveform Generation .322 Watchdog Timer (WDT) Block Diagram .326 Watchdog Timer Mode (RST/10, Operation .333 Interval Timer Mode Operation .334 Flag Timing Output Timing 5(62 signal.335 Writing TCNT TCSR (WDT_0) .336 Conflict between TCNT Write Increment.337 Sample Circuit Resetting System 5(62 Signal.338
Section Serial Communication Interface (SCI IrDA) Figure 15.1 Block Diagram .340 Figure 15.2 Data Format Asynchronous Communication (Example with 8-Bit Data, Parity, Stop Bits).357 Figure 15.3 Receive Data Sampling Timing Asynchronous Mode.359 Figure 15.4 Relation between Output Clock Transmit Data Phase (Asynchronous Mode).360 Figure 15.5 Sample Initialization Flowchart.361 Figure 15.6 Example Transmit Operation Asynchronous Mode (Example with 8-Bit Data, Parity, Stop Bit) .362 Figure 15.7 Sample Serial Transmission Flowchart.363 Figure 15.8 Example Receive Operation Asynchronous Mode (Example with 8-Bit Data, Parity, Stop Bit) .364 Figure 15.9 Sample Serial Reception Flowchart .366 Figure 15.9 Sample Serial Reception Flowchart .367
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Figure 15.10 Example Communication Using Multiprocessor Format (Transmission Data H'AA Receiving Station .369 Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart.370 Figure 15.12 Example Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, Stop Bit).371 Figure 15.13 Sample Multiprocessor Serial Reception Flowchart .372 Figure 15.13 Sample Multiprocessor Serial Reception Flowchart .373 Figure 15.14 Data Format Clocked Synchronous Communication (LSB-First) .374 Figure 15.15 Sample Initialization Flowchart.375 Figure 15.16 Example Transmit Operation Clocked Synchronous Mode .376 Figure 15.17 Sample Serial Transmission Flowchart.377 Figure 15.18 Example Receive Operation Clocked Synchronous Mode.378 Figure 15.19 Sample Serial Reception Flowchart.379 Figure 15.20 Sample Flowchart Simultaneous Serial Transmission Reception.381 Figure 15.21 IrDA Block Diagram .382 Figure 15.22 IrDA Transmission Reception.383 Figure 15.23 Example Transmission using Clocked Synchronous Mode.387 Figure 15.24 Sample Flowchart Mode Transition during Transmission .388 Figure 15.25 States during Transmission Asynchronous Mode (Internal Clock) .389 Figure 15.26 States during Transmission Clocked Synchronous Mode (Internal Clock) .389 Figure 15.27 Sample Flowchart Mode Transition during Reception.390 Figure 15.28 Switching from Pins Port Pins .391 Figure 15.29 Prevention Pulse Output Switching from Pins Port Pins .391 Section Interface (IIC) (Optional) Figure 16.1 Block Diagram Interface .395 Figure 16.2 Interface Connections (Example: This Master) .396 Figure 16.3 Data Format Format).424 Figure 16.4 Data Format (Formatless) (IIC_0 Only) .424 Figure 16.5 Data Format (Serial Format).425 Figure 16.6 Timing .425 Figure 16.7 Sample Flowchart Initialization .426 Figure 16.8 Sample Flowchart Operations Master Transmit Mode .427 Figure 16.9 Example Operation Timing Master Transmit Mode (MLS WAIT .429 Figure 16.10 Example Stop Condition Issuance Operation Timing Master Transmit Mode (MLS WAIT .429 Figure 16.11 Sample Flowchart Operations Master Receive Mode (HNDS .430 Figure 16.12 Example Operation Timing Master Receive Mode (MLS WAIT HNDS .432 Figure 16.13 Example Stop Condition Issuance Operation Timing Master Receive Mode (MLS WAIT HNDS 1).432
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Figure 16.14 Sample Flowchart Operations Master Receive Mode (receiving multiple bytes) (WAIT .433 Figure 16.15 Sample Flowchart Operations Master Receive Mode (receiving single byte) (WAIT .434 Figure 16.16 Example Master Receive Mode Operation Timing (MLS ACKB WAIT 1).436 Figure 16.17 Example Stop Condition Issuance Timing Master Receive Mode (MLS ACKB WAIT 1).437 Figure 16.18 Sample Flowchart Operations Slave Receive Mode (HNDS 1).438 Figure 16.19 Example Slave Receive Mode Operation Timing (MLS HNDS= 1).440 Figure 16.20 Example Slave Receive Mode Operation Timing (MLS HNDS= 1).440 Figure 16.21 Sample Flowchart Operations Slave Receive Mode (HNDS 0).441 Figure 16.22 Example Slave Receive Mode Operation Timing (MLS ACKB 0).443 Figure 16.23 Example Slave Receive Mode Operation Timing (MLS ACKB 0).443 Figure 16.24 Sample Flowchart Slave Transmit Mode .444 Figure 16.25 Example Slave Transmit Mode Operation Timing (MLS 0).446 Figure 16.26 IRIC Setting Timing Control (1).447 Figure 16.27 IRIC Setting Timing Control (2).448 Figure 16.28 IRIC Setting Timing Control (3).449 Figure 16.29 Block Diagram Noise Canceler .452 Figure 16.30 Notes Reading Master Receive Data .458 Figure 16.31 Flowchart Start Condition Issuance Instruction Retransmission Timing .459 Figure 16.32 Stop Condition Issuance Timing.460 Figure 16.33 IRIC Flag Clearing Timing When WAIT 1.460 Figure 16.34 ICDR Read ICCR Access Timing Slave Transmit Mode .461 Figure 16.35 Timing Slave Mode .462 Section Keyboard Buffer Controller Figure 17.1 Block Diagram Keyboard Buffer Controller .465 Figure 17.2 Keyboard Buffer Controller Connection.466 Figure 17.3 Sample Receive Processing Flowchart .471 Figure 17.4 Receive Timing.472 Figure 17.5 Sample Transmit Processing Flowchart .473 Figure 17.5 Sample Transmit Processing Flowchart .474 Figure 17.6 Transmit Timing .474 Figure 17.7 Sample Receive Abort Processing Flowchart .475 Figure 17.7 Sample Receive Abort Processing Flowchart .476 Figure 17.8 Receive Abort Transmit Start (Transmission/Reception Switchover) Timing.476 Figure 17.9 KCLKI Read Timing .477 Figure 17.10 KCLKO Write Timing .477 Figure 17.11 Setting KCLK Automatic Inhibit Generation Timing.478 Figure 17.12 Receive Counter KBBR Data Load Timing.479
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Figure 17.13 Example KCLK Input Fall Interrupt Operation.480 Figure 17.14 KBIOE Setting KCLK Falling Edge Detection Timing.481 Section Figure 18.1 Figure 18.2 Figure 18.3 Section Figure 19.1 Figure 19.2 Figure 19.3 Figure 19.4 Figure 19.5 Figure 19.6 Figure 19.7 Figure 19.8 Host Interface X-Bus Interface (XBS) Block Diagram XBS.484 GA20 Output .496 HIRQ Output Flowchart (Example Channels 2).500 Host Interface Interface (LPC) Block Diagram .504 Typical /)5$0( Timing .538 Abort Mechanism .538 GA20 Output .540 Power-Down State Termination Timing.545 SERIRQ Timing .546 Clock Start Request Timing.548 HIRQ Flowchart (Example Channel .551
Section Converter Figure 20.1 Block Diagram Converter.553 Figure 20.2 Converter Operation Example .556 Section Converter Figure 21.1 Block Diagram Converter.560 Figure 21.2 Example Converter Operation (Scan Mode, Channels Selected) .567 Figure 21.3 Conversion Timing .568 Figure 21.4 External Trigger Input Timing.569 Figure 21.5 Conversion Accuracy Definitions .571 Figure 21.6 Conversion Accuracy Definitions .571 Figure 21.7 Example Analog Input Circuit.572 Figure 21.8 Example Analog Input Protection Circuit .574 Figure 21.9 Equivalent Circuit Analog Input .574 Section Figure 23.1 Block Diagram Flash Memory .578 Figure 23.2 Flash Memory State Transitions .579 Figure 23.3 Boot Mode .580 Figure 23.4 User Program Mode (Example) .581 Figure 23.5 64-Kbyte Flash Memory Block Configuration .582 Figure 23.6 128-Kbyte Flash Memory Block Configuration .583 Figure 23.7 256-Kbyte Flash Memory Block Configuration .584 Figure 23.8 On-Chip Area Boot Mode .595 Figure 23.9 Code Area.596 Figure 23.10 Programming/Erasing Flowchart Example User Program Mode .597 Figure 23.11 Program/Program-Verify Flowchart.599
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Figure 23.12 Erase/Erase-Verify Flowchart.601 Figure 23.13 Memory Programmer Mode .604 Section Masked Figure 24.1 Block Diagram 128-Kbyte Masked (HD6432161BV) .607 Figure 24.2 Block Diagram 64-Kbyte Masked (HD6432160BV) .607 Section Figure 25.1 Figure 25.2 Figure 25.3 Figure 25.4 Figure 25.5 Figure 25.6 Figure 25.7 Figure 25.8 Figure 25.9 Section Figure 26.1 Figure 26.2 Figure 26.3 Figure 26.4 Clock Pulse Generator Block Diagram Clock Pulse Generator.609 Typical Connection Crystal Resonator .610 Equivalent Circuit Crystal Resonator .610 Example External Clock Input .611 External Clock Input Timing .612 Timing External Clock Output Stabilization Delay Time .613 Subclock Input Timing Processing Pins .615 Note Board Design Oscillator Circuit Section.616 Power-Down Modes Mode Transition Diagram.623 Medium-Speed Mode Timing.626 Application Example Software Standby Mode.628 Hardware Standby Mode Timing.629
Section Electrical Characteristics Figure 28.1 Darlington Pair Drive Circuit (Example).684 Figure 28.2 Drive Circuit (Example).685 Figure 28.3 Output Load Circuit .686 Figure 28.4 Connection Capacitor .698 Figure 28.5 Connection Capacitor .736 Figure 28.6 System Clock Timing .736 Figure 28.7 Oscillation Settling Timing.737 Figure 28.8 Oscillation Setting Timing (Exiting Software Standby Mode).737 Figure 28.9 Reset Input Timing .738 Figure 28.10 Interrupt Input Timing .738 Figure 28.11 Basic Timing (Two-State Access) .739 Figure 28.12 Basic Timing (Three-State Access) .740 Figure 28.13 Basic Timing (Three-State Access with Wait State).741 Figure 28.14 Burst Access Timing (Two-State Access) .742 Figure 28.15 Burst Access Timing (One-State Access) .742 Figure 28.16 Port Input/Output Timing .743 Figure 28.17 Input/Output Timing.743 Figure 28.18 Clock Input Timing .744 Figure 28.19 8-Bit Timer Output Timing.744 Figure 28.20 8-Bit Timer Clock Input Timing.744
Rev. 2.0, 08/02, page xxxviii
Figure 28.21 Figure 28.22 Figure 28.23 Figure 28.24 Figure 28.25 Figure 28.26 Figure 28.27 Figure 28.28 Figure 28.29 Figure 28.30 Figure 28.31
8-Bit Timer Reset Input Timing .744 PWM, PWMX Output Timing.745 Clock Input Timing.745 Input/Output Timing (Synchronous Mode) .745 Converter External Trigger Input Timing .745 Output Timing (5(62).746 Host Interface (XBS) Timing.746 Keyboard Buffer Controller Timing .747 Interface Input/Output Timing.748 Host Interface (LPC) Timing .748 Tester Measurement Condition.749
Appendix Package Dimensions Figure Package Dimensions (FP-100B) .754 Figure Package Dimensions (TFP-100B).755 Figure Package Dimensions (TFP-144).756
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Tables
Section Overview Table Functions H8S/2141B, H8S/2140B, H8S/2145B, H8S/2148B Each Operating Mode Table Functions H8S/2160B H8S/2161B Each Operating Mode Table Functions.18 Section Table Table Table Table Table Table Table Table Table Table Table Table 2.10 Table 2.11 Table 2.12 Table 2.13 Table 2.13 Instruction Classification. Operation Notation.42 Data Transfer Instructions.43 Arithmetic Operations Instructions (1).44 Arithmetic Operations Instructions (2).45 Logic Operations Instructions Shift Instructions Manipulation Instructions Manipulation Instructions Branch Instructions System Control Instructions Block Data Transfer Instructions Addressing Modes.52 Absolute Address Access Ranges Effective Address Calculation Effective Address Calculation
Section Operating Modes Table Operating Mode Selection.63 Table Functions Each Mode Section Exception Handling Table Exception Types Priority Table Exception Handling Vector Table.80 Table Status after Trap Instruction Exception Handling.83 Section Interrupt Controller Table Configuration Table Correspondence between Interrupt Source Table Interrupt Sources, Vector Addresses, Interrupt Priorities.97 Table Interrupt Control Modes.99 Table Interrupt Response Times.105 Table Number States Interrupt Handling Routine Execution Status.105 Section Controller Table Configuration .114
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Table Table Table Table
Specifications Basic Interface .118 Address Range Signal Output .119 Data Buses Used Valid Strobes .121 States Idle Cycle .133
Section Data Transfer Controller (DTC) Table Interrupt Sources, Vector Addresses, Corresponding DTCEs.143 Table Register Functions Normal Mode .145 Table Register Functions Repeat Mode .146 Table Register Functions Block Transfer Mode .147 Table Execution Status.150 Table Number States Required Each Execution Status.150 Section Table Table Table Table Table Table Table Table Table Table 8.10 Ports Port Functions H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B .156 Input Pull-Up States (Port .162 Input Pull-Up States (Port .166 Input Pull-Up States (Port .169 Input Pull-Up States (Port .180 Input Pull-Up States (Port .197 Input Pull-Up States (Port B).203 H8S/2160B, H8S/2161B Additional Port Functions.204 Input Pull-Up States (Port port D).209 Input Pull-Up States (Port port F).214
Section 8-Bit Timer (PWM) Table Configuration .219 Table Internal Clock Selection .221 Table Resolution, Conversion Period Carrier Frequency when MHz.222 Table Duty Cycle Basic Pulse.225 Table Position Pulses Added Basic Pulses.226 Section 14-Bit Timer (PWMX) Table 10.1 Configuration .228 Table 10.2 Read Write Access Methods 16-Bit Registers .234 Table 10.3 Settings Operation (Examples when MHz) .235 Table 10.4 Position Pulse Added Basic Pulse (CFS .239 Section 16-Bit Free-Running Timer (FRT) Table 11.1 Configuration .243 Table 11.2 Interrupt Sources.260 Table 11.3 Switching Internal Clock Operation .265 Section 8-Bit Timer (TMR) Table 12.1 Configuration .270 Table 12.2 Clock Input TCNT Count Condition .273
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Table 12.3 Table 12.4 Table 12.5 Table 12.6
Input Capture Signal Selection.289 Interrupt Sources 8-Bit Timers TMR_0, TMR_1, TMR_Y, TMR_X.290 Timer Output Priorities .294 Switching Internal Clocks TCNT Operation .295
Section Timer Connection Table 13.1 Configuration .299 Table 13.2 Synchronization Signal Connection Enable .302 Table 13.3 Registers Accessible TMR_X/TMR_Y.306 Table 13.4 Examples Settings .309 Table 13.5 Examples TCORB (Pulse Width Threshold) Settings .309 Table 13.6 Examples TCSR Settings.313 Table 13.7 Examples TCR, TCSR, TOCR, OCRDM Settings .315 Table 13.8 Examples TCR, TCSR, TCORB Settings .316 Table 13.9 Examples OCRAR, OCRAF, TCORA, TCORB, TCR, TCSR Settings .318 Table 13.10 HSYNCO Output Modes .320 Table 13.11 VSYNCO Output Modes .321 Section Watchdog Timer (WDT) Table 14.1 Configuration .327 Table 14.2 Interrupt Source.335 Section Serial Communication Interface (SCI IrDA) Table 15.1 Configuration .341 Table 15.2 Relationships between Setting Rate .350 Table 15.3 Settings Various Rates (Asynchronous Mode) .351 Table 15.4 Maximum Rate Each Frequency (Asynchronous Mode).354 Table 15.5 Maximum Rate with External Clock Input (Asynchronous Mode).354 Table 15.6 Settings Various Rates (Clocked Synchronous Mode) .355 Table 15.7 Maximum Rate with External Clock Input (Clocked Synchronous Mode).355 Table 15.8 Serial Transfer Formats (Asynchronous Mode) .358 Table 15.9 Status Flags Receive Data Handling.365 Table 15.10 IrCKS2 IrCKS0 Settings .384 Table 15.11 Interrupt Sources .385 Section Interface (IIC) (Optional) Table 16.1 Configuration .396 Table 16.2 Communication Format.400 Table 16.3 Transfer Rate .403 Table 16.4 Flags Transfer States (Master Mode) .410 Table 16.5 Flags Transfer States (Slave Mode).412 Table 16.6 Data Format Symbols.425 Table 16.7 Examples Operation Using .451 Table 16.8 Interrupt Sources.454 Table 16.9 Timing (SCL Outputs).455
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Table 16.10 Table 16.11
Permissible Rise Time (tsr) Values .455 Timing (with Maximum Influence tSr/tSf) .457
Section Keyboard Buffer Controller Table 17.1 Configuration .466 Section Host Interface X-Bus Interface (XBS) Table 18.1 Configuration Table 18.2 Set/Clear Timing Flags.493 Table 18.3 Host Interface Channel Selection Operation .494 Table 18.4 Host Interface Operations from Host, Slave Operation.495 Table 18.5 GA20 (P81) Set/Clear Timing.496 Table 18.6 Fast Gate Output Signal.497 Table 18.7 Scope Shutdown.498 Table 18.8 Input Buffer Full Interrupts .499 Table 18.9 HIRQ Setting/Clearing Conditions .500 Section Host Interface Interface (LPC) Table 19.1 Configuration .505 Table 19.2 Register Selection.518 Table 19.3 GA20 (P81) Set/Clear Timing.539 Table 19.4 Fast Gate Output Signals .541 Table 19.5 Scope Host Interface Shutdown.543 Table 19.6 Scope Initialization Each Host Interface Mode .544 Table 19.7 Receive Complete Interrupts Error Interrupt .548 Table 19.8 HIRQ Setting Clearing Conditions.550 Section Converter Table 20.1 Configuration .554 Table 20.2 Channel Enable.555 Section Converter Table 21.1 Configuration .561 Table 21.2 Analog Input Channels Corresponding ADDR Registers.562 Table 21.3 Conversion Time (Single Mode) .569 Section Table 23.1 Differences between Boot Mode User Program Mode.579 Table 23.2 Configuration .585 Table 23.3 Operating Modes .591 Table 23.4 On-Board Programming Mode Settings.591 Table 23.5 Boot Mode Operation.594 Table 23.6 System Clock Frequencies which Automatic Adjustment Rate Possible.595 Section Clock Pulse Generator Table 25.1 Damping Resistance Values.610
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Table 25.2 Table 25.3 Table 25.4 Table 25.5
Crystal Resonator Parameters .611 External Clock Input Conditions.612 External Clock Output Stabilization Delay Time.613 Subclock Input Conditions .614
Section Power-Down Modes Table 26.1 Operating Frequency Wait Time .619 Table 26.2 Internal States Each Mode.624 Section Electrical Characteristics Table 28.1 Absolute Maximum Ratings.677 Table 28.2 Characteristics .678 Table 28.2 Characteristics .681 Table 28.2 Characteristics When Function Used .683 Table 28.3 Permissible Output Currents .684 Table 28.4 Drive Characteristics.685 Table 28.5 Clock Timing .687 Table 28.6 Control Signal Timing.688 Table 28.7 Timing (Normal Mode) .689 Table 28.7 Timing (Advanced Mode) .690 Table 28.8 Timing On-Chip Peripheral Modules .691 Table 28.8 Timing On-Chip Peripheral Modules .692 Table 28.9 Keyboard Buffer Controller Timing.693 Table 28.10 Timing.693 Table 28.11 Module Timing .694 Table 28.12 Conversion Characteristics (AN7 Input: 134/266-State Conversion) .694 Table 28.13 Conversion Characteristics (CIN15 CIN0 Input: 134/266-State Conversion) .695 Table 28.14 Conversion Characteristics .695 Table 28.15 Flash Memory Characteristics.696 Table 28.16 Absolute Maximum Ratings.699 Table 28.17 Characteristics .701 Table 28.17 Characteristics .703 Table 28.17 Characteristics .705 Table 28.17 Characteristics .708 Table 28.17 Characteristics .710 Table 28.17 Characteristics .713 Table 28.17 Characteristics (3-V Version H8S/2145BV) When Function Used .715 Table 28.18 Permissible Output Currents .716 Table 28.19 Drive Characteristics.718 Table 28.20 Clock Timing .719 Table 28.21 Control Signal Timing.720
Rev. 2.0, 08/02, page xxxvii xxxviii
Table 28.22 Table 28.22 Table 28.23 Table 28.23 Table 28.24 Table 28.25 Table 28.26 Table 28.27 Table 28.28 Table 28.29 Table 28.30
Timing (Normal Mode) .721 Timing (Advanced Mode) .723 Timing On-Chip Peripheral Modules .725 Timing On-Chip Peripheral Modules .727 Keyboard Buffer Controller Timing.728 Timing.728 Module Timing (For H8S/2145B Only) .729 Conversion Characteristics (AN7 Input: 134/266-State Conversion) .730 Conversion Characteristics (CIN15 CIN0 Input: 134/266-State Conversion) .731 Conversion Characteristics .732 Flash Memory Characteristics (Operation Range Programming/Erasing) .733
Appendix Table Port States Each Processing State .751
Rev. 2.0, 08/02, page xxxviii xxxviii
Section Overview
Features
High-speed H8S/2000 central processing unit with internal 16-bit architecture Upward-compatible with H8/300 H8/300H CPUs object level Sixteen 16-bit general registers basic instructions Various peripheral functions Data transfer controller (DTC) 8-bit timer (PWM) 14-bit timer (PWMX) 16-bit free-running timer (FRT) 8-bit timer (TMR) Timer connection Watchdog timer (WDT) Asynchronous clocked synchronous serial communication interface (SCI,IrDA) interface (IIC) Keyboard buffer controller Host interface X-BUS interface (XBS) Host interface interface (LPC) 8-bit converter 10-bit converter Clock pulse generator
Rev. 2.0, 08/02, page
On-chip memory
F-ZTAT Version Model HD64F2161BV* HD64F2160BV* HD64F2141BV* HD64F2140BV* HD64F2145BV* HD64F2148BV* HD64F2148B Masked Version HD6432161BV* HD6432160BV* HD6432161BVW* HD6432160BVW* Note:* version product kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes Under development Under development Remarks
General ports pins: (H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B) pins: (H8S/2160B H8S/2161B) Input-only pins: Supports various power-down states Compact package
Product H8S/2161B, H8S/2160B H8S/2141B, H8S/2140B H8S/2145B, H8S/2148B Package TQFP-144 QFP-100B TQFP-100B Code TFP-144 FP-100B TFP-100B Body Size 18.0 18.0 16.0 16.0 Pitch
Rev. 2.0, 08/02, page
Block Diagram
Clock pulse generator
Internal data
controller
H8S/2000
Internal address
XTAL EXTAL VCCB
PA7/A23/ PA6/A22/ PA5/A21/ PA4/A20/ PA3/A19/ PA2/A18/ PA1/A17/ PA0/A16/
/CIN15/PS2CD /CIN14/PS2CC /CIN13/PS2BD /CIN12/PS2BC /CIN11/PS2AD /CIN10/PS2AC /CIN9 /CIN8
Port
P97/ /SDA0 P95/ P94/ P93/ P92/ P91/ P90/ /CLAMPO /VFBACKI /VSYNCI/TMIY /VSYNCO /HFBACKI/TMIX
Interrup controller
(Flash memory)
P27/A15/PW15/CBLANK P26/A14/PW14 P25/A13/PW13 P24/A12/PW12 P23/A11/PW11 P22/A10/PW10 P21/A9/PW9 P20/A8/PW8 P17/A7/PW7 P16/A6/PW6 P15/A5/PW5 P14/A4/PW4 P13/A3/PW3 P12/A2/PW2 P11/A1/PW1 P10/A0/PW0 P37/D15/HDB7/SERIRQ* P36/D14/HDB6/LCLK* P35/D13/HDB5/ P34/D12/HDB4/ P33/D11/HDB3/LAD3* P32/D10/HDB2/LAD2* P31/D9/HDB1/LAD1* P30/D8/HDB0/LAD0* PB7/D7/ PB6/D6/ PB5/D5/ PB4/D4/ PB3/D3/ PB2/D2/ PB1/D1/ PB0/D0/ */HIRQ4/LSCI* */HIRQ3/
Port
channels
P67/TMOX/CIN7/ P66/FTOB/CIN6/ P65/FTID/CIN5/ P64/FTIC/CIN4/ P63/FTIB/CIN3/ P62/FTIA/CIN2/ P61/FTOA/CIN1/ P60/FTCI/CIN0/
Keyboard buffer controller channels
Port
16-bit
8-bit
14-bit
P47/PWX1 P46/PWX0 P45/TMRI1/HIRQ12/CSYNCI P44/TMO1/HIRQ1/HSYNCO P43/TMCI1/HIRQ11/HSYNCI P42/TMRI0/SCK2/SDA1 P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD
Port
8-bit timer channels Timer connection
Host interfaces (LPC*, XBS)
10-bit converter
8-bit converter
P52/SCK0/SCL0 P51/RxD0 P50/TxD0
Port
channels
Port
Port
AVref AVCC AVSS
Note:* function
function supported H8S/2148B.
Figure Internal Block Diagram H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B
P86/ /SCK1/SCL1 /RxD1 P85/ P84/ /TxD1 P83/ P82/HIFSD/ /GA20 P81/ P80/HA0/
P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0
Rev. 2.0, 08/02, page
Port
channels (IrDA channel)
Port
Port
Port
PA7/A23/ PA6/A22/ PA5/A21/
/CIN15/PS2CD /CIN14/PS2CC /CIN13/PS2BD /CIN12/PS2BC /CIN11/PS2AD /CIN10/PS2AC /CIN9 /CIN8
Port
PA4/A20/ PA3/A19/ PA2/A18/ PA1/A17/ PA0/A16/
XTAL EXTAL VCCB
Clock pulse generator
Internal data
controller
H8S/2000
Internal address
P27/A15/PW15/CBLANK P26/A14/PW14
Port
P25/A13/PW13 P24/A12/PW12 P23/A11/PW11 P22/A10/PW10 P21/A9/PW9 P20/A8/PW8 P17/A7/PW7 P16/A6/PW6
P97/ /SDA0 P95/ P94/ P93/ P92/ P91/ P90/ /CLAMPO /VFBACKI /VSYNCI/TMIY /VSYNCO /HFBACKI/TMIX
Interrupt controller
Port
(Flash memory, Masked ROM) channels
Port
P15/A5/PW5 P14/A4/PW4 P13/A3/PW3 P12/A2/PW2 P11/A1/PW1 P10/A0/PW0 P37/D15/HDB7/SERIRQ P36/D14/HDB6/LCLK P35/D13/HDB5/
P67/TMOX/CIN7/ P66/FTOB/CIN6/ P65/FTID/CIN5/ P64/FTIC/CIN4/ P63/FTIB/CIN3/ P62/FTIA/CIN2/ P61/FTOA/CIN1/ P60/FTCI/CIN0/ P47/PWX1
Keyboard buffer controller channels
Port
Port
P34/D12/HDB4/ P33/D11/HDB3/LAD3 P32/D10/HDB2/LAD2 P31/D9/HDB1/LAD1
16-bit
8-bit
14-bit
P30/D8/HDB0/LAD0 PB7/D7/
P46/PWX0 P45/TMRI1/HIRQ12/CSYNCI P44/TMO1/HIRQ1/HSYNCO P43/TMCI1/HIRQ11/HSYNCI P42/TMRI0/SCK2/SDA1 P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD
Port
Port
8-bit timer channels Timer connection
Host interfaces (LPC, XBS)
PB6/D6/ PB5/D5/ PB4/D4/ PB3/D3/ PB2/D2/ PB1/D1/ PB0/D0/ /HIRQ4/LSCI /HIRQ3/
10-bit converter
channels (IrDA channel)
8-bit converter
AVref AVCC AVSS
P77/AN7/DA1 P76/AN6/DA0 P75/AN5
/SCK1/SCL1 /RxD1
P74/AN4 P73/AN3 P72/AN2
Figure Internal Block Diagram H8S/2160B H8S/2161B
Rev. 2.0, 08/02, page
P82/HIFSD/ P81/ /GA20 P80/HA0/
P86/ P85/ P84/
P83/
P71/AN1 P70/AN0
/TxD1
Port
Port
Port
Port
Port
Port
Port
P52/SCK0/SCL0 P51/RxD0 P50/TxD0
Port
channels
1.3.1
Arrangement Functions
Arrangement
P45/TMRI1/HIRQ12/CSYNCI P43/TMCI1/HIRQ11/HSYNCI P44/TMO1/HIRQ1/HSYNCO
P27/A15/PW15/CBLANK
P14/A4/PW4
P15/A5/PW5
P16/A6/PW6
P17/A7/PW7
PB4/D4/
P13/A3/PW3 P12/A2/PW2 P11/A1/PW1 P10/A0/PW0 PB3/D3/ PB2/D2/
XTAL
P42/TMRI0/SCK2/SDA1
P22/A10/PW10
P23/A11/PW11
P24/A12/PW12
P25/A13/PW13
P26/A14/PW14
P20/A8/PW8
P21/A9/PW9
P47/PWX1 P46/PWX0 PB7/D7/
PB5/D5/
PB6/D6/
P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD PA0/A16/CIN8/ PA1/A17/CIN9/ AVSS P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 AVCC AVref P67/TMOX/CIN7/ P66/FTOB/CIN6/ P65/FTID/CIN5/ P64/FTIC/CIN4/ PA2/A18/CIN10/ PA3/A19/CIN11/ P63/FTIB/CIN3/ P62/FTIA/CIN2/ P61/FTOA/CIN1/ P60/FTCI/CIN0/ /CLAMPO /PS2AC /PS2AD /VFBACKI /VSYNCI/TMIY /VSYNCO /HFBACKI/TMIX
FP-100B TFP-100B (Top view)
EXTAL
P30/D8 /HDB0/LAD0* P31/D9 /HDB1/LAD1* P32/D10/HDB2/LAD2* P33/D11/HDB3/LAD3* P34/D12/HDB4/ P35/D13/HDB5/
P36/D14/HDB6/LCLK* P37/D15/HDB7/SERIRQ* PB1/D1/ PB0/D0/ */HIRQ4/LSCI* */HIRQ3/ P80/HA0/ P81/ P82/HIFSD/ P83/ P84/ P85/ P86/ /TxD1 /RxD1 /GA20
/SCK1/SCL1
VCCB
/SDA0 P96/ /EXCL /PS2BD /PS2CD /PS2CC P52/SCK0/SCL0 P51/RxD0 P50/TxD0 /PS2BC
P92/ P91/
P97/
P95/
P94/
P93/
PA7/A23/CIN15/
PA6/A22/CIN14/
PA5/A21/CIN13/
PA4/A20/CIN12/
Note:* function
function supported H8S/2148B.
Figure Arrangement H8S/2140B, H8S/2141B, H8S/2145B, H8S/2148B
Rev. 2.0, 08/02, page
P90/
/VSYNCI/TMIY P62/FTIA/CIN2/
P27/A15/PW15/CBLANK
P67/TMOX/CIN7/
P66/FTOB/CIN6/
/VFBACKI
P61/FTOA/CIN1/
P65/FTID/CIN5/
P64/FTIC/CIN4/
P60/FTCI/CIN0/
P63/FTIB/CIN3/
P22/A10/PW10
P23/A11/PW11
P24/A12/PW12
P25/A13/PW13
P26/A14/PW14
/HFBACKI/TMIX
/CLAMPO
/VSYNCO
P77/AN7/DA1
P76/AN6/DA0
P13/A3/PW3
P14/A4/PW4
P15/A5/PW5
P16/A6/PW6
P17/A7/PW7
P20/A8/PW8
P21/A9/PW9
P12/A2/PW2 P11/A1/PW1 P10/A0/PW0 PB7/D7/ PB6/D6/ PB5/D5/ PB4/D4/ PB3/D3/ PB2/D2/ PB1/D1/HIRQ4/ PB0/D0/HIRQ3/ /LSCI
P75/AN5
AVCC
AVref
P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 AVSS PA0/A16/CIN8/ PA1/A17/CIN9/ PA2/A18/CIN10/ PA3/A19/CIN11/ PA4/A20/CIN12/ /PS2AC /PS2AD /PS2BC
P30/D8/HDB0/LAD0 P31/D9/HDB1/LAD1 P32/D10/HDB2/LAD2 P33/D11/HDB3/LAD3 P34/D12/HDB4/ P35/D13/HDB5/ P36/D14/HDB6/LCLK P37/D15/HDB7/SERIRQ P80/HA0/ P81/ P82/HIFSD/ P83/ P84/ P85/ P86/ /TxD1 /RxD1 /GA20
TFP-144 (Top view)
/SCK1/SCL1
P40/TMCI0/TxD2/IrTxD P41/TMO0/RxD2/IrRxD P42/TMRI0/SCK2/SDA1 XTAL EXTAL
/SDA0
/PS2CD
P96/ EXCL
/PS2CC PA6/A22/CIN14/
/PS2BD PA5/A21/CIN13/
P51/ RxD0
P44/TMO1/HIRQ1/HSYNCO
P43/TMCI1/HIRQ11/HSYNCI
P45/TMRI1/HIRQ12/CSYNCI
P52/SCK0/SCL0
P46/PWX0
P47/PWX1
P50/TxD0
P92/
P91/
P97/
P95/
P94/
P93/
Figure Arrangement H8S/2160B H8S/2161B
Rev. 2.0, 08/02, page
PA7/A23/CIN15/
P90/
VCCB
1.3.2 Table
Functions Each Operating Mode Functions H8S/2141B, H8S/2140B, H8S/2145B, H8S/2148B Each Operating Mode
Name
FP-100B TFP-100B Mode XTAL EXTAL VCCB 67%<
Extended Modes Mode Mode (EXPE XTAL EXTAL VCCB 67%< PA7/A23/CIN15/ .,148/PS2CD PA6/A22/CIN14/ .,147/PS2CC P52/SCK0/SCL0 P51/RxD0 P50/TxD0 P97/:$,7/SDA0 $6/,26 PA5/A21/CIN13/ .,146/PS2BD PA4/A20/CIN12/ .,145/PS2BC
Single-Chip Modes Mode Mode (EXPE XTAL EXTAL VCCB 67%< PA7/CIN15/.,148/ PS2CD PA6/CIN14/.,147/ PS2CC P52/SCK0/SCL0 P51/RxD0 P50/TxD0 P97/SDA0 P95/&64 P94/,2: PA5/CIN13/.,146/ PS2BD PA4/CIN12/.,145/ PS2BC
Flash Memory Programmer Mode XTAL EXTAL FA17 FA16 FA15
PA7/CIN15/.,148/ PS2CD PA6/CIN14/.,147/ PS2CC P52/SCK0/SCL0 P51/RxD0 P50/TxD0 P97/:$,7/SDA0 $6/,26 PA5/CIN13/.,146/ PS2BD PA4/CIN12/.,145/ PS2BC
Rev. 2.0, 08/02, page
Name FP-100B TFP-100B Mode P92/,543 P91/,544 P90//:5/,545/ $'75* P60/FTCI/CIN0/ .,13/HFBACKI/ TMIX P61/FTOA/CIN1/ .,14/VSYNCO Extended Modes Mode Mode (EXPE P92/,543 P91/,544 P90//:5/,545/ $'75* P60/FTCI/CIN0/ .,13/HFBACKI/ TMIX P61/FTOA/CIN1/ .,14/VSYNCO Single-Chip Modes Mode Mode (EXPE P93/,25 P92/,543 P91/,544 P90/(&65/,545/ $'75* P60/FTCI/CIN0/ .,13/HFBACKI/ TMIX P61/FTOA/CIN1/ .,14/VSYNCO P62/FTIA/CIN2/ .,15/VSYNCI/TMIY P63/FTIB/CIN3/ .,16/VFBACKI PA3/CIN11/.,144/ PS2AD PA2/CIN10/.,143/ PS2AC P64/FTIC/CIN4/ .,17/CLAMPO P65/FTID/CIN5/ .,18 P66/FTOB/CIN6/ .,19/,549 P67/TMOX/CIN7/ .,1:/,54: AVref AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 Flash Memory Programmer Mode
P62/FTIA/CIN2/ P62/FTIA/CIN2/ .,15/VSYNCI/TMIY .,15/VSYNCI/TMIY P63/FTIB/CIN3/ .,16/VFBACKI PA3/CIN11/.,144/ PS2AD PA2/CIN10/.,143/ PS2AC P64/FTIC/CIN4/ .,17/CLAMPO P65/FTID/CIN5/ .,18 P66/FTOB/CIN6/ .,19/,549 P67/TMOX/CIN7/ .,1:/,54: AVref AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3 P63/FTIB/CIN3/ .,16/VFBACKI PA3/A19/CIN11/ .,144/PS2AD PA2/A18/CIN10/ .,143/PS2AC P64/FTIC/CIN4/ .,17/CLAMPO P65/FTID/CIN5/ .,18 P66/FTOB/CIN6/ .,19/,549 P67/TMOX/CIN7/ .,1:/,54: AVref AVCC P70/AN0 P71/AN1 P72/AN2 P73/AN3
Rev. 2.0, 08/02, page
Name FP-100B TFP-100B Mode P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVSS PA1/CIN9/.,1< PA0/CIN8/.,1; P40/TMCI0/TxD2/ IrTxD P41/TMO0/RxD2/ IrRxD P42/TMRI0/SCK2/ SDA1 P43/TMCI1/ HSYNCI P44/TMO1/ HSYNCO P45/TMRI1/ CSYNCI P46/PWX0 P47/PWX1 PB7/D7/:8(:* PB6/D6/:8(9* Extended Modes Mode Mode (EXPE P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVSS PA1/A17/CIN9/.,1< PA0/A16/CIN8/.,1; P40/TMCI0/TxD2/ IrTxD P41/TMO0/RxD2/ IrRxD P42/TMRI0/SCK2/ SDA1 P43/TMCI1/ HSYNCI P44/TMO1/ HSYNCO P45/TMRI1/ CSYNCI P46/PWX0 P47/PWX1 PB7/D7/:8(:* PB6/D6/:8(9* P27/A15/PW15/ CBLANK P26/A14/PW14 P25/A13/PW13 P24/A12/PW12 P23/A11/PW11 Single-Chip Modes Mode Mode (EXPE P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVSS PA1/CIN9/.,1< PA0/CIN8/.,1; P40/TMCI0/TxD2/ IrTxD P41/TMO0/RxD2/ IrRxD P42/TMRI0/SCK2/ SDA1 P43/TMCI1/HIRQ11/ HSYNCI P44/TMO1/HIRQ1/ HSYNCO P45/TMRI1/HIRQ12/ CSYNCI P46/PWX0 P47/PWX1 PB7/:8(:* PB6/:8(9* P27/PW15/ CBLANK P26/PW14 P25/PW13 P24/PW12 P23/PW11 Flash Memory Programmer Mode FA14 FA13 FA12 FA11
Rev. 2.0, 08/02, page
Name FP-100B TFP-100B Mode PB5/D5/:8(8* PB4/D4/:8(7* PB3/D3/:8(6* PB2/D2/:8(5* PB1/D1/:8(4* PB0/D0/:8(3* Extended Modes Mode Mode (EXPE P22/A10/PW10 P21/A9/PW9 P20/A8/PW8 PB5/D5/:8(8* PB4/D4/:8(7* P17/A7/PW7 P16/A6/PW6 P15/A5/PW5 P14/A4/PW4 P13/A3/PW3 P12/A2/PW2 P11/A1/PW1 P10/A0/PW0 PB3/D3/:8(6* PB2/D2/:8(5* PB1/D1/:8(4* PB0/D0/:8(3* Single-Chip Modes Mode Mode (EXPE P22/PW10 P21/PW9 P20/PW8 PB5/:8(8* PB4/:8(7* P17/PW7 P16/PW6 P15/PW5 P14/PW4 P13/PW3 P12/PW2 P11/PW1 P10/PW0 PB3/:8(6*/&67 PB2/:8(5*/&66 P30/HDB0/LAD0* P31/HDB1/LAD1* P32/HDB2/LAD2* P33/HDB3/LAD3* P34/HDB4/ /)5$0(* P35/HDB5/ /5(6(7* P36/HDB6/LCLK* Flash Memory Programmer Mode FA10
P37/HDB7/SERIRQ* PB1/HIRQ4/:8(4*/ LSCI* PB0/HIRQ3/:8(3*/ /60,*
Rev. 2.0, 08/02, page
Name FP-100B TFP-100B Mode P84/,546/TxD1 P85/,547/RxD1 P86/,548/SCK1/ SCL1 5(62 Extended Modes Mode Mode (EXPE P84/,546/TxD1 P85/,544/RxD1 P86/,548/SCK1/ SCL1 5(62 Single-Chip Modes Mode Mode (EXPE P80/HA0/30(* P81/&65/GA20 P82/HIFSD/ &/.581* P83//3&3'* P84/,546/TxD1 P85/,547/RxD1 P86/,548/SCK1/ SCL1 5(62 Flash Memory Programmer Mode
Note:* means VCCB drive means NMOS pushpull/open-drain drive. function function supported H8S/2148B.
Rev. 2.0, 08/02, page
Table
Functions H8S/2160B H8S/2161B Each Operating Mode
Name
TFP-144 Mode P43/TMCI1/ HSYNCI P44/TMO1/ HSYNCO P45/TMRI1/ CSYNCI P46/PWX0 P47/PWX1 67%<
Extended modes Mode Mode (EXPE P43/TMCI1/ HSYNCI P44/TMO1/ HSYNCO P45/TMRI1/ CSYNCI P46/PWX0 P47/PWX1 67%< P52/SCK0/SCL0 P51/RxD0 P50/TxD0 P97/:$,7/SDA0 $6/,26 P92/,543 P91/,544 P90//:5/,545/ $'75*
Single-Chip Modes Mode Mode (EXPE P43/TMCI1/HIRQ11/ HSYNCI P44/TMO1/HIRQ1/ HSYNCO P45/TMRI1/HIRQ12/ CSYNCI P46/PWX0 P47/PWX1 67%< P52/SCK0/SCL0 P51/RxD0 P50/TxD0 P97/SDA0 P95/&64 P94/,2: P93/,25 P92/,543 P91/,544 P90/,545/$'75*/ (&65
Flash Memory Programmer Mode FA18 FA17 FA16 FA15
P52/SCK0/SCL0 P51/RxD0 P50/TxD0 P97/:$,7/SDA0 $6/,26 P92/,543 P91/,544 P90//:5/,545/ $'75*
Rev. 2.0, 08/02, page
Name TFP-144 Mode PA7/CIN15/.,148/ PS2CD PA6/CIN14/.,147/ PS2CC PA5/CIN13/.,146/ PS2BD VCCB PA4/CIN12/.,145/ PS2BC PA3/CIN11/.,144/ PS2AD PA2/CIN10/.,143/ PS2AC PA1/CIN9/.,1< PA0/CIN8/.,1; Extended modes Mode Mode (EXPE PA7/A23/CIN15/ .,148/PS2CD PA6/A22/CIN14/ .,147/PS2CC PA5/A21/CIN13/ .,146/PS2BD VCCB PA4/A20/CIN12/ .,145/PS2BC PA3/A19/CIN11/ .,144/PS2AD PA2/A18/CIN10/ .,143/PS2AC PA1/A17/CIN9/.,1< PA0/A16/CIN8/.,1; Single-Chip Modes Mode Mode (EXPE PA7/CIN15/.,148/ PS2CD PA6/CIN14/.,147/ PS2CC PA5/CIN13/.,146/ PS2BD VCCB PA4/CIN12/.,145/ PS2BC PA3/CIN11/.,144/ PS2AD PA2/CIN10/.,143/ PS2AC PA1/CIN9/.,1< PA0/CIN8/.,1; Flash Memory Programmer Mode
Rev. 2.0, 08/02, page
Name TFP-144 Mode AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVCC AVref P60/FTCI/CIN0/ .,13/HFBACKI/ TMIX Extended modes Mode Mode (EXPE AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVCC AVref P60/FTCI/CIN0/ .,13/HFBACKI/ TMIX Single-Chip Modes Mode Mode (EXPE AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 AVCC AVref P60/FTCI/CIN0/ .,13/HFBACKI/ TMIX Flash Memory Programmer Mode
Rev. 2.0, 08/02, page
Name TFP-144 Mode P61/FTOA/CIN1/ .,14/VSYNCO Extended modes Mode Mode (EXPE P61/FTOA/CIN1/ .,14/VSYNCO Single-Chip Modes Mode Mode (EXPE P61/FTOA/CIN1/ .,14/VSYNCO P62/FTIA/CIN2/ .,15/VSYNCI/TMIY P63/FTIB/CIN3/ .,16/VFBACKI P64/FTIC/CIN4/ .,17/CLAMPO P66/FTOB/CIN6/ .,19/,549 P67/TMOX/CIN7/ .,1:/,54: P27/PW15/CBLANK P26/PW14 P25/PW13 P24/PW12 P23/PW11 P22/PW10 Flash Memory Programmer Mode
P62/FTIA/CIN2/ P62/FTIA/CIN2/ .,15/VSYNCI/TMIY .,15/VSYNCI/TMIY P63/FTIB/CIN3/ .,16/VFBACKI P64/FTIC/CIN4/ .,17/CLAMPO P66/FTOB/CIN6/ .,19/,549 P67/TMOX/CIN7/ .,1:/,54: P63/FTIB/CIN3/ .,16/VFBACKI P64/FTIC/CIN4/ .,17/CLAMPO P66/FTOB/CIN6/ .,19/,549 P67/TMOX/CIN7/ .,1:/,54: P27/A15/PW15/ CBLANK P26/A14/PW14 P25/A13/PW13 P24/A12/PW12 P23/A11/PW11 P22/A10/PW10
P65/FTID/CIN5/.,18 P65/FTID/CIN5/.,18 P65/FTID/CIN5/.,18 FA14 FA13 FA12 FA11 FA10
Rev. 2.0, 08/02, page
Name TFP-144 Mode PB7/D7/:8(: PB6/D6/:8(9 PB5/D5/:8(8 PB4/D4/:8(7 PB3/D3/:8(6 PB2/D2/:8(5 PB1/D1/:8(4 PB0/D0/:8(3 Extended modes Mode Mode (EXPE P21/A9/PW9 P20/A8/PW8 P17/A7/PW7 P16/A6/PW6 P15/A5/PW5 P14/A4/PW4 P13/A3/PW3 P12/A2/PW2 P11/A1/PW1 P10/A0/PW0 PB7/D7/:8(: PB6/D6/:8(9 PB5/D5/:8(8 PB4/D4/:8(7 PB3/D3/:8(6 PB2/D2/:8(5 PB1/D1/:8(4 PB0/D0/:8(3 Single-Chip Modes Mode Mode (EXPE P21/PW9 P20/PW8 P17/PW7 P16/PW6 P15/PW5 P14/PW4 P13/PW3 P12/PW2 P11/PW1 P10/PW0 PB7/:8(: PB6/:8(9 PB5/:8(8 PB4/:8(7 PB3/:8(6/&67 PB2/:8(5/&66 PB1/HIRQ4/:8(4/ LSCI PB0/HIRQ3/:8(3/ /60, P30/HDB0/LAD0 P31/HDB1/LAD1 P32/HDB2/LAD2 P33/HDB3/LAD3 P34/HDB4//)5$0( P35/HDB5//5(6(7 P36/HDB6/LCLK P37/HDB7/SERIRQ P80/HA0/30( Flash Memory Programmer Mode
Rev. 2.0, 08/02, page
Name TFP-144 Mode P84/,546/TxD1 P85/,547/RxD1 P86/,548/SCK1/ SCL1 P40/TMCI0/TxD2/ IrTxD P41/TMO0/RxD2/ IrRxD P42/TMRI0/SCK2/ SDA1 5(62 XTAL EXTAL Extended modes Mode Mode (EXPE P84/,546/TxD1 P85/,547/RxD1 P86/,548/SCK1/ SCL1 P40/TMCI0/TxD2/ IrTxD P41/TMO0/RxD2/ IrRxD P42/TMRI0/SCK2/ SDA1 5(62 XTAL EXTAL Single-Chip Modes Mode Mode (EXPE P81/&65/GA20 P82/HIFSD/ &/.581 P83//3&3' P84/,546/TxD1 P85/,547/RxD1 P86/,548/SCK1/ SCL1 P40/TMCI0/TxD2/ IrTxD P41/TMO0/RxD2/ IrRxD P42/TMRI0/SCK2/ SDA1 5(62 XTAL EXTAL Flash Memory Programmer Mode XTAL EXTAL
Note:* means VCCB drive means NMOS pushpull/open-drain drive.
Rev. 2.0, 08/02, page
1.3.3 Table
Functions Functions
Type Power
Symbol VCCB
FP-100B, TFP-100B TFP-144 Input Input Input
Name Function Power supply pin. Connect system power supply. Power supply pin. Connect VCC. power supply port input/output buffer. Ground pin. Connect system power supply Pins connection crystal resonators. EXTAL also input external clock. section Clock Pulse Generator, typical connection diagrams.
Input 111, Input Input
Clock
XTAL EXTAL
EXCL Operating mode control System control
Output Input Input Input Input
Supplies system clock external devices. Input 32.768 external subclock. Leave open. Leave open. These pins operating mode. These pins should changed while operating. Reset pin. When this becomes low, chip reset.
Input
5(62 67%<
Output Outputs reset signal external device. Input When this driven low, transition made hardware standby mode.
Rev. 2.0, 08/02, page
Type Address Symbol FP-100B, TFP-100B TFP-144 Name Function
Output Address output pins when 16-Mbyte space used.
Output Address output pins 110, Input/ output Input/ output Input Bidirectional data upper byte 16bit data. Bidirectional data lower byte 16bit data. Requests insertion wait state cycle when accessing external 3-state address space.
Data
control
:$,7
Output When this low, indicates that external address space being read. Output When this low, indicates that external address space being written upper half data valid. Output When this low, indicates that external address space being written lower half data valid. Output When this low, indicates that address output address valid. Input Input nonmaskable interrupt request. These pins request maskable interrupt.
$6/,26 Interrupt signals ,543 ,54:
Input 135, Input
16-bit freerunning timer (FRT)
FTCI FTOA FTOB FTIA
counter clock input pin.
Output output compare output pin. Output output compare output pin. Input input capture input pin.
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Type 16-bit freerunning timer (FRT) Symbol FTIB FTIC FTID FP-100B, TFP-100B TFP-144 Input Input Input Name Function input capture input pin. input capture input pin. input capture input pin.
8-bit timer TMO0 (TMR_0, TMO1 TMR_1, TMOX TMR_X) TMCI0 TMCI1 TMRI0 TMRI1 8-bit timer TMIX (TMR_X, TMIY TMR_Y) 8-bit timer (PWM) 14-bit timer (PWMX) Serial communication interface (SCI_0, SCI_1, SCI_2) PW15
Output waveform output pins output compare function. Input Input Input Input pins external clock input counters. counter reset input pins. counter event input counter reset input pins.
Output timer pulse output pins. 110,
PWX0 PWX1
Output pulse output pins.
TxD0 TxD1 TxD2 RxD0 RxD1 RxD2 SCK0 SCK1 SCK2
Output Transmit data output pins.
Input
Receive data input pins.
Input/ Clock input/output pins. Output output type NMOS push-pull. Output Input output pins data encoded IrDA use. Input
with IrDA (SCI_2)
IrTxD IrRxD
Rev. 2.0, 08/02, page
Type Symbol FP-100B, TFP-100B TFP-144 130, 118, Name Function
Keyboard PS2AC buffer PS2BC controller PS2CC PS2AD PS2BD PS2CD Host interface (XBS) HDB7 HDB0 &64, &65/ (&65, &66, GA20 HIRQ11 HIRQ1 HIRQ12 HIRQ3 HIRQ4 HIFSD
Input/ Keyboard buffer controller synchronization Output clock input/output pins. Input/ Keyboard buffer controller data input/output Output pins. Input/ Bidirectional 8-bit accessing XBS. Output Input Input pins selecting channels (&65 input selected with system control register. Input that enables reading from XBS. Input that enables writing XBS. Input that indicates whether access data access command access.
Input Input Input
Output gate control signal output pin. Output Output pins interrupt requests host.
Input
Control input used place input/output pins high-impedance/ cutoff state.
Host interface (LPC)
LAD3 LAD0 /)5$0(
Input/ command, address, data Output input/output pins. Input Input that indicates start cycle forced termination abnormal cycle. Input that indicates reset. clock input pin.
/5(6(7 LCLK
Input Input
Rev. 2.0, 08/02, page
Type Host interface (LPC) Symbol SERIRQ FP-100B, TFP-100B TFP-144 Name Function
Input/ Input/output serialized host Output interrupts (HIRQ1, SMI, HIRQ6, HIRQ9 HIRQ12).
LSCI, /60,, GA20 &/.581 /3&3' Keyboard .,13 buffer .,148 controller
119, 120, Input/ auxiliary output pins. Functionally, Output they general ports. Input/ gate control signal output pin. Output Output state monitoring input possible. Input/ Input/output that requests start Output LCLK operation when LCLK stopped. Input Input that controls module shutdown. Matrix keyboard input pins. .,13 .,148 used key-scan inputs, used key-scan outputs. This allows maximum 16-output 16-input, 256-key matrix configured. Wakeup event input pins. These pins allow same kind wakeup key-wakeup from various sources. Analog input pins. conversion input pins, since they also used digital input/output pins, accuracy will fall.
Input Input
:8(3 :8(: converter CIN0 CIN15
Input
Input Input
$'75* converter
input external trigger start conversion.
Output Analog output pins.
Rev. 2.0, 08/02, page
Type Symbol FP-100B, TFP-100B TFP-144 Input Name Function analog power supply converter converter. When converters used, this should connected system power supply AVref Input reference power supply converter converter. When converters used, this should connected system power supply AVSS Input ground converter converter. This should connected system power supply Timer connection synchronous signal input pins.
AVCC converter converter
Timer connection
VSYNCI HSYNCI CSYNCI VFBACKI HFBACKI VSYNCO HSYNCO CLAMPO CBLANK
Input
Output Timer connection synchronous signal output pins.
interface (IIC)
SCL0 SCL1 SDA0 SDA1
Input/ clock pins. output type Output NMOS open-drain output. Input/ data pins. output type NMOS Output open-drain output.
Rev. 2.0, 08/02, page
Type ports Symbol FP-100B, TFP-100B TFP-144 Name Function
Input/ Eight input/output pins. 110, Output Input/ Eight input/output pins. Output Input/ Eight input/output pins. Output Input/ Eight input/output pins. Output (The output type NMOS pushpull.) Input/ Three input/output pins. Output (The output type NMOS pushpull.) Input/ Eight input/output pins. Output Input Eight input pins.
Input/ Seven input/output pins. Output (The output type NMOS pushpull.) Input/ Eight input/output pins. Output (The output type NMOS pushpull.)
Input/ Eight input/output pins. Output Input/ Eight input/output pins. Output Input/ Eight input/output pins. Output Input/ Eight input/output pins. Output Input/ Eight input/output pins. Output
Rev. 2.0, 08/02, page
Type ports Symbol FP-100B, TFP-100B TFP-144 Input/ Output Input/ Output Name Function Eight input/output pins. Eight input/output pins. (The output type H8S/2160B H8S/2161B NMOS push-pull.)
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Rev. 2.0, 08/02, page
Section
H8S/2000 high-speed central processing unit with internal 32-bit architecture that upward-compatible with H8/300 H8/300H CPUs. H8S/2000 sixteen 16-bit general registers, address 16-Mbyte linear address space, ideal realtime control. This section describes H8S/2000 CPU. usable modes address spaces differ depending product. details each product, refer section Operating Modes.
Features
Upward-compatibility with H8/300 H8/300H CPUs execute H8/300 H8/300H object programs General-register architecture Sixteen 16-bit general registers also usable sixteen 8-bit registers eight 32-bit registers Sixty-five basic instructions 8/16/32-bit arithmetic logic instructions Multiply divide instructions Powerful bit-manipulation instructions Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) @(d:32,ERn)] Register indirect with post-increment pre-decrement [@ERn+ @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, @aa:32] Immediate [#xx:8, #xx:16, #xx:32] Program-counter relative [@(d:8,PC) @(d:16,PC)] Memory indirect [@@aa:8] 16-Mbyte address space Program: Mbytes Data: Mbytes High-speed operation frequently-used instructions executed states 8/16/32-bit register-register add/subtract: state 8-bit register-register multiply: states (MULXU.B), states (MULXS.B) 8-bit register-register divide: states (DIVXU.B) 16-bit register-register multiply: states (MULXU.W), states (MULXS.W) 16-bit register-register divide: states (DIVXU.W)
CPU210A_010020020700
Rev. 2.0, 08/02, page
operating modes Normal mode Advanced mode Power-down state Transition power-down state SLEEP instruction Selectable clock speed 2.1.1 Differences between H8S/2600 H8S/2000
differences between H8S/2600 H8S/2000 shown below. Register configuration register supported only H8S/2600 CPU. Basic instructions four instructions MAC, CLRMAC, LDMAC, STMAC supported only H8S/2600 CPU. number execution states MULXU MULXS instructions
Execution States Instruction MULXU Mnemonic MULXU.B MULXU.W MULXS MULXS.B MULXS.W H8S/2600 H8S/2000
addition, there differences address space, register functions, power-down modes, etc., depending model. 2.1.2 Differences from H8/300
comparison H8/300 CPU, H8S/2000 following enhancements. More general registers control registers Eight 16-bit extended registers 8-bit control register have been added. Expanded address space Normal mode supports same 64-kbyte address space H8/300 CPU. Advanced mode supports maximum 16-Mbyte address space. Enhanced addressing addressing modes have been enhanced make effective 16-Mbyte address space.
Rev. 2.0, 08/02, page
Enhanced instructions Addressing modes bit-manipulation instructions have been enhanced. Signed multiply divide instructions have been added. Two-bit shift two-bit rotate instructions have been added. Instructions saving restoring multiple registers have been added. test instruction been added. Higher speed Basic instructions executed twice fast. 2.1.3 Differences from H8/300H
comparison H8/300H CPU, H8S/2000 following enhancements. Additional control register 8-bit control register been added. Enhanced instructions Addressing modes bit-manipulation instructions have been enhanced. Two-bit shift two-bit rotate instructions have been added. Instructions saving restoring multiple registers have been added. test instruction been added. Higher speed Basic instructions executed twice fast.
Rev. 2.0, 08/02, page
Operating Modes
H8S/2000 operating modes: normal advanced. Normal mode supports maximum 64-kbyte address space. Advanced mode supports maximum 16-Mbyte address space. mode selected LSI's mode pins. 2.2.1 Normal Mode
exception vector table stack have same structure H8/300 normal mode. Address space Linear access maximum address space kbytes possible. Extended registers (En) extended registers used 16-bit registers, upper 16-bit segments 32-bit registers. When extended register used 16-bit register contain value, even when corresponding general register (Rn) used address register. general register referenced register indirect addressing mode with pre-decrement (@-Rn) postincrement (@Rn+) carry borrow occurs, value corresponding extended register (En) will affected.) Instruction instructions addressing modes used. Only lower bits effective addresses (EA) valid. Exception vector table memory indirect branch addresses normal mode, area starting H'0000 allocated exception vector table. branch address stored bits. exception vector table normal mode shown figure 2.1. details exception vector table, section Exception Handling. memory indirect addressing mode (@@aa:8) employed instructions uses 8-bit absolute address included instruction code specify memory operand that contains branch address. normal mode, operand 16-bit (word) operand, providing 16-bit branch address. Branch addresses stored area from H'0000 H'00FF. Note that this area also used exception vector table. Stack structure normal mode, when program counter (PC) pushed onto stack subroutine call normal mode, condition-code register (CCR) pushed onto stack exception handling, they stored shown figure 2.2. extended control register (EXR) pushed onto stack. details, section Exception Handling.
Rev. 2.0, 08/02, page
H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B
Reset exception vector (Reserved system use)
(Reserved system use) Exception vector table Exception vector Exception vector
Figure Exception Vector Table (Normal Mode)
bits)
CCR* bits)
Subroutine Branch Note: Ignored when returning.
Exception Handling
Figure Stack Structure Normal Mode 2.2.2 Advanced Mode
Address space Linear access maximum address space Mbytes possible. Extended registers (En) extended registers used 16-bit registers. They also used upper 16-bit segments 32-bit registers address registers. Instruction instructions addressing modes used.
Rev. 2.0, 08/02, page
Exception vector table memory indirect branch addresses advanced mode, area starting H'00000000 allocated exception vector table 32-bit units. each bits, upper bits ignored branch address stored lower bits (see figure 2.3). details exception vector table, section Exception Handling.
H'00000000 Reserved Reset exception vector H'00000003 H'00000004 Reserved (Reserved system use) H'00000007 H'00000008 Exception vector table
H'0000000B H'0000000C
(Reserved system use)
H'00000010
Reserved Exception vector
Figure Exception Vector Table (Advanced Mode) memory indirect addressing mode (@@aa:8) employed instructions uses 8-bit absolute address included instruction code specify memory operand that contains branch address. advanced mode, operand 32-bit longword operand, providing 32-bit branch address. upper bits these bits reserved area that regarded H'00. Branch addresses stored area from H'00000000 H'000000FF. Note that area this range also used exception vector table. Stack structure advanced mode, when program counter (PC) pushed onto stack subroutine call, condition-code register (CCR) pushed onto stack exception handling, they stored shown figure 2.4. extended control register (EXR) pushed onto stack. details, section Exception Handling.
Rev. 2.0, 08/02, page
Reserved bits)
bits)
Subroutine Branch
Exception Handling
Figure Stack Structure Advanced Mode
Address Space
Figure shows memory H8S/2000 CPU. H8S/2000 provides linear access maximum 64-kbyte address space normal mode, maximum 16-Mbyte (architecturally 4-Gbyte) address space advanced mode. usable modes address spaces differ depending product. details each product, refer section Operating Modes.
H'0000 kbytes H'FFFF Mbytes Program area H'00000000
H'00FFFFFF
Data area
available this
H'FFFFFFFF Normal Mode Advanced Mode
Figure Memory
Rev. 2.0, 08/02, page
Register Configuration
H8S/2000 internal registers shown figure 2.6. There types registers: general registers control registers. Control registers 24-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition code register (CCR).
General Registers (Rn) Extended Registers (En)
(SP)
Control Registers
EXR*
Legend
Stack pointer Program counter Extended control register Trace Interrupt mask bits Condition-code register Interrupt mask User interrupt mask Half-carry flag User Negative flag Zero flag Overflow flag Carry flag
Note: Does affect operation this LSI.
Figure Internal Registers
Rev. 2.0, 08/02, page
2.4.1
General Registers
H8S/2000 eight 32-bit general registers. These general registers functionally alike used both address registers data registers. When general register used data register, accessed 32-bit, 16-bit, 8-bit register. Figure illustrates usage general registers. When general registers used 32-bit registers address registers, they designated letters (ER0 ER7). When general registers used 16-bit registers, registers divided into 16-bit general registers designated letters R7). These registers functionally equivalent, providing maximum sixteen 16-bit registers. registers also referred extended registers. When general registers used 8-bit registers, registers divided into 8-bit general registers designated letters (R0H R7H) (R0L R7L). These registers functionally equivalent, providing maximum sixteen 8-bit registers. usage each register selected independently. General register function stack pointer (SP) addition general-register function, used implicitly exception handling subroutine calls. Figure shows stack.
Address registers 32-bit registers 16-bit registers 8-bit registers
registers (extended registers) registers (ER0 ER7) registers registers (R0L R7L) registers (R0H R7H)
Figure Usage General Registers
Rev. 2.0, 08/02, page
Free area (ER7)
Stack area
Figure Stack 2.4.2 Program Counter (PC)
This 24-bit counter indicates address next instruction will execute. length instructions bytes (one word), least significant ignored. (When instruction fetched read, least significant regarded 2.4.3 Extended Control Register (EXR)
does affect operation this LSI.
Name Initial Value Description Trace Does affect operation this LSI. Reserved These bits always read Interrupt Mask Bits affect operation this LSI.
2.4.4
Condition-Code Register (CCR)
This 8-bit register contains internal status information, including interrupt mask half-carry (H), negative (N), zero (Z), overflow (V), carry flags. Operations performed bits LDC, STC, ANDC, ORC, XORC instructions. flags used branching conditions conditional branch (Bcc) instructions.
Rev. 2.0, 08/02, page
Name
Initial Value
Description Interrupt Mask Masks interrupts other than when accepted regardless setting. start exception-handling sequence. details, refer section Interrupt Controller.
Undefined
User Interrupt Mask written read from software using LDC, STC, ANDC, ORC, XORC instructions.
Undefined
Half-Carry Flag When ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B NEG.B instruction executed, this flag there carry borrow cleared otherwise. When ADD.W, SUB.W, CMP.W, NEG.W instruction executed, flag there carry borrow cleared otherwise. When ADD.L, SUB.L, CMP.L, NEG.L instruction executed, flag there carry borrow cleared otherwise.
Undefined
User written read from software using LDC, STC, ANDC, ORC, XORC instructions.
Undefined
Negative Flag Stores value most significant data sign bit.
Undefined
Zero Flag indicate zero data, cleared indicate non-zero data.
Undefined
Overflow Flag when arithmetic overflow occurs, cleared otherwise.
Undefined
Carry Flag when carry occurs, cleared otherwise. Used instructions, indicate carry Subtract instructions, indicate borrow Shift rotate instructions, indicate carry
carry flag also used accumulator manipulation instructions.
Rev. 2.0, 08/02, page
2.4.5
Initial Register Values
program counter (PC) among internal registers initialized when reset exception handling loads start address from vector table. trace cleared interrupt mask bits other bits general registers initialized. Note that stack pointer (ER7) undefined. stack pointer should therefore initialized MOV.L instruction executed immediately after reset.
Data Formats
H8S/2000 process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), 32-bit (longword) data. Bit-manipulation instructions operate 1-bit data accessing byte operand data. decimal-adjust instructions treat byte data digits 4-bit data. 2.5.1 General Register Data Formats
Figure shows data formats general registers.
Data Type
1-bit data
Register Number
Data Image
Don't care
1-bit data Don't care
4-bit data Upper
Lower
Don't care
4-bit data Don't care Upper
Lower
Byte data
Don't care
Byte data
Don't care
Figure General Register Data Formats
Rev. 2.0, 08/02, page
Data Type Word data
Register Number
Data Image
Word data
Longword data
Legend
General register General register General register General register General register Least significant
Most significant
Figure General Register Data Formats
Rev. 2.0, 08/02, page
2.5.2
Memory Data Formats
Figure 2.10 shows data formats memory. H8S/2000 access word data longword data memory, word longword data must begin even address. attempt made access word longword data address, address error occurs least significant address regarded access starts preceding address. This also applies instruction fetches. When (ER7) used address register access stack, operand size should word size longword size.
Data Type Address
1-bit data Address
Data Image
Byte data
Address
Word data
Address Address
Longword data
Address Address Address Address
Figure 2.10 Memory Data Formats
Rev. 2.0, 08/02, page
Instruction
H8S/2000 types instructions. instructions classified function shown table 2.1. Table
Function Data transfer
Instruction Classification
Instructions POP* PUSH* LDM* STM*
Size B/W/L B/W/L B/W/L B/W/L B/W/L
Types
MOVFPE* MOVTPE* Arithmetic operations ADD, SUB, CMP,
ADDX, SUBX, DAA, INC, ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS*
Logic operations Shift manipulation Branch System control
AND, XOR, SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
Total:
BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR BCC* JMP, BSR, JSR, TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,
Block data transfer EEPMOV
Notes: Byte size; Word size; Longword size. POP.W PUSH.W identical MOV.W @SP+, MOV.W @SP. POP.L PUSH.L identical MOV.L @SP+, MOV.L ERn, @-SP. general name conditional branch instructions. Cannot used this LSI. When using instruction, registers ER0, ER1, ER4, ER5. used register that saved (STM)/restored (LDM) when using STM/LDM instruction, because stack pointer.
Rev. 2.0, 08/02, page
2.6.1
Table Instructions Classified Function
Tables 2.10 summarize instructions each functional category. notation used tables 2.10 defined below. Table
Symbol (EAd) (EAs) #IMM disp :8/:16/:24/:32
Operation Notation
Description General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register (negative) flag (zero) flag (overflow) flag (carry) flag Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical Logical Logical exclusive Move (logical complement) 16-, 24-, 32-bit length
Note:* General registers include 8-bit registers (R0H R7H, R7L), 16-bit registers E7), 32-bit registers (ER0 ER7).
Rev. 2.0, 08/02, page
Table
Instruction
Data Transfer Instructions
Size*
Function (EAs) (EAd) Moves data between general registers between general register memory, moves immediate data general register.
B/W/L
MOVFPE MOVTPE
Cannot used this LSI. Cannot used this LSI. @SP+ Pops general register from stack. POP.W identical MOV.W @SP+, POP.L identical MOV.L @SP+,
PUSH
@-SP Pushes general register onto stack. PUSH.W identical MOV.W @-SP. PUSH.L identical MOV.L ERn, @-SP.
LDM* STM*
@SP+ (register list) Pops more general registers from stack. (register list) @-SP Pushes more general registers onto stack.
Notes: Size refers operand size. Byte Word Longword used register that saved (STM)/restored (LDM) when using STM/LDM instruction, because stack pointer.
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Table
Instruction
Arithmetic Operations Instructions
Size* B/W/L Function #IMM Performs addition subtraction data general registers, immediate data data general register. (Subtraction immediate data data general register cannot performed bytes. SUBX instruction.) #IMM Performs addition subtraction with carry data general registers, immediate data data general register. B/W/L Adds subtracts value from data general register. (Only value added subtracted from byte operands.) Adds subtracts value from data 32-bit register. (decimal adjust) Decimal-adjusts addition subtraction result general register referring produce 4-bit data. Performs unsigned multiplication data general registers: either bits bits bits bits bits bits.
ADDX SUBX
ADDS SUBS MULXU
MULXS
Performs signed multiplication data general registers: either bits bits bits bits bits bits.
DIVXU
Performs unsigned division data general registers: either bits bits 8-bit quotient 8-bit remainder bits bits 16-bit quotient 16-bit remainder.
Note:* Size refers operand size. Byte Word Longword
Rev. 2.0, 08/02, page
Table
Instruction DIVXS
Arithmetic Operations Instructions
Size*
Function Performs signed division data general registers: either bits bits 8-bit quotient 8-bit remainder bits bits 16-bit quotient 16-bit remainder.
B/W/L
#IMM Compares data general register with data another general register with immediate data, sets bits according result.
B/W/L
Takes two's complement (arithmetic complement) data general register.
EXTU
(zero extension) Extends lower bits 16-bit register word size, lower bits 32-bit register longword size, padding with zeros left.
EXTS
(sign extension) Extends lower bits 16-bit register word size, lower bits 32-bit register longword size, extending sign bit.
TAS*
@ERd (<bit @ERd) Tests memory contents, sets most significant (bit
Notes: Size refers operand size. Byte Word Longword When using instruction, registers ER0, ER1, ER5.
Rev. 2.0, 08/02, page
Table
Instruction
Logic Operations Instructions
Size* B/W/L Function #IMM Performs logical operation general register another general register immediate data.
B/W/L
#IMM Performs logical operation general register another general register immediate data.
B/W/L
#IMM Performs logical exclusive operation general register another general register immediate data.
B/W/L
Takes one's complement (logical complement) data general register.
Note:* Size refers operand size. Byte Word Longword
Table
Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR
Shift Instructions
Size* B/W/L Function (shift) Performs arithmetic shift data general register. 1-bit shift possible. B/W/L (shift) Performs logical shift data general register. 1-bit shift possible. B/W/L B/W/L (rotate) Rotates data general register. 1-bit rotation possible. (rotate) Rotates data including carry flag general register. 1-bit rotation possible.
Note:* Size refers operand size. Byte Word Longword
Rev. 2.0, 08/02, page
Table
Instruction BSET
Manipulation Instructions
Size* Function (<bit-No.> <EAd>) Sets specified general register memory operand number specified 3-bit immediate data lower three bits general register.
BCLR
(<bit-No.> <EAd>) Clears specified general register memory operand number specified 3-bit immediate data lower three bits general register.
BNOT
(<bit-No.> <EAd>) (<bit-No.> <EAd>) Inverts specified general register memory operand. number specified 3-bit immediate data lower three bits general register.
BTST
(<bit-No.> <EAd>) Tests specified general register memory operand sets clears flag accordingly. number specified 3-bit immediate data lower three bits general register.
BAND
(<bit-No.> <EAd>) Logically ANDs carry flag with specified general register memory operand stores result carry flag.
BIAND
(<bit-No.> <EAd>) Logically ANDs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data.
(<bit-No.> <EAd>) Logically carry flag with specified general register memory operand stores result carry flag.
BIOR
<bit-No.> <EAd>) Logically carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data.
Note:* Size refers operand size. Byte
Rev. 2.0, 08/02, page
Table
Instruction BXOR
Manipulation Instructions
Size* Function (<bit-No.> <EAd>) Logically exclusive-ORs carry flag with specified general register memory operand stores result carry flag.
BIXOR
(<bit-No.> <EAd>) Logically exclusive-ORs carry flag with inverse specified general register memory operand stores result carry flag. number specified 3-bit immediate data.
(<bit-No.> <EAd>) Transfers specified general register memory operand carry flag.
BILD
(<bit-No.> <EAd>) Transfers inverse specified general register memory operand carry flag. number specified 3-bit immediate data.
(<bit-No.> <EAd>) Transfers carry flag value specified general register memory operand.
BIST
(<bit-No.>. <EAd>) Transfers inverse carry flag value specified general register memory operand. number specified 3-bit immediate data.
Note:* Size refers operand size. Byte
Rev. 2.0, 08/02, page
Table
Instruction
Branch Instructions
Size Function Branches specified address specified condition true. branching conditions listed below. Mnemonic (BT) (BF) (BHS) (BLO) Description Always (true) Never (false) High same Carry clear (high same) Carry (low) equal Equal Overflow clear Overflow Plus Minus Greater equal Less than Greater than Less equal NV=0 NV=1 Condition Always Never CZ=0 CZ=1
Branches unconditionally specified address. Branches subroutine specified address Branches subroutine specified address Returns from subroutine
Rev. 2.0, 08/02, page
Table
Instruction TRAPA SLEEP
System Control Instructions
Size* Function Starts trap-instruction exception handling. Returns from exception-handling routine. Causes transition power-down state. (EAs) CCR, (EAs) Moves memory operand contents immediate data EXR. Although 8-bit registers, word-size transfers performed between them memory. upper bits valid.
(EAd), (EAd) Transfers contents general register memory operand. Although 8-bit registers, word-size transfers performed between them memory. upper bits valid.
ANDC XORC
#IMM CCR, #IMM Logically ANDs contents with immediate data. #IMM CCR, #IMM Logically contents with immediate data. #IMM CCR, #IMM Logically exclusive-ORs contents with immediate data. Only increments program counter.
Note:* Size refers operand size. Byte Word
Rev. 2.0, 08/02, page
Table 2.10 Block Data Transfer Instructions
Instruction EEPMOV.B Size Function then Repeat @ER5 @ER6+ R4L-1 Until else next; then Repeat @ER5 @ER6+ R4-1 Until else next; Transfers data block. Starting from address ER5, transfers data number bytes address location ER6. Execution next instruction begins soon transfer completed.
EEPMOV.W
2.6.2
Basic Instruction Formats
H8S/2000 instructions consist 2-byte (1-word) units. instruction consists operation field (op), register field (r), effective address extension (EA), condition field (cc). Figure 2.11 shows examples instruction formats. Operation field Indicates function instruction, addressing mode, operation carried operand. operation field always includes first four bits instruction. Some instructions have operation fields. Register field Specifies general register. Address registers specified bits, data registers bits bits. Some instructions have register fields, some have register field. Effective address extension bits specifying immediate data, absolute address, displacement. Condition field Specifies branching condition instructions.
Rev. 2.0, 08/02, page
Operation field only NOP,
Operation field register fields ADD.B
Operation field, register fields, effective address extension (disp) MOV.B @(d:16, Rn),
Operation field, effective address extension, condition field (disp) d:16
Figure 2.11 Instruction Formats (Examples)
Addressing Modes Effective Address Calculation
H8S/2000 supports eight addressing modes listed table 2.11. Each instruction uses subset these addressing modes. Arithmetic logic operations instructions register direct immediate addressing modes. Data transfer instructions addressing modes except program-counter relative memory indirect. manipulation instructions register direct, register indirect, absolute addressing mode specify operand, register direct (BSET, BCLR, BNOT, BTST instructions) immediate (3-bit) addressing mode specify number operand. Table 2.11 Addressing Modes
Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8
Rev. 2.0, 08/02, page
2.7.1
Register Direct-Rn
register field instruction code specifies 16-, 32-bit general register which contains operand. specified 8-bit registers. specified 16-bit registers. specifie
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