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IA-32 Intel Architecture Software Developer's Manual
With Preliminary Willamette Architecture Information
Volume Instruction Reference
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CHAPTER ABOUT THIS MANUAL 1.1. OVERVIEW IA-32 INTEL ARCHITECTURE SOFTWARE DEVELOPER'S MANUAL, VOLUME INSTRUCTION REFERENCE 1.2. OVERVIEW IA-32 INTEL ARCHITECTURE SOFTWARE DEVELOPER'S MANUAL, VOLUME BASIC ARCHITECTURE 1.3. OVERVIEW IA-32 INTEL ARCHITECTURE SOFTWARE DEVELOPER'S MANUAL, VOLUME SYSTEM PROGRAMMING GUIDE 1.4. NOTATIONAL CONVENTIONS. 1.4.1. Byte Order 1.4.2. Reserved Bits Software Compatibility. 1.4.3. Instruction Operands 1.4.4. Hexadecimal Binary Numbers 1.4.5. Segmented Addressing 1.4.6. Exceptions. 1.5. RELATED LITERATURE CHAPTER INSTRUCTION FORMAT 2.1. GENERAL INSTRUCTION FORMAT 2.2. INSTRUCTION PREFIXES 2.3. OPCODE 2.4. MODR/M BYTES. 2.5. DISPLACEMENT IMMEDIATE BYTES 2.6. ADDRESSING-MODE ENCODING MODR/M BYTES
CHAPTER INSTRUCTION REFERENCE 3.1. INTERPRETING INSTRUCTION REFERENCE PAGES 3.1.1. Instruction Format. 3.1.1.1. Opcode Column 3.1.1.2. Instruction Column 3.1.1.3. Description Column. 3.1.1.4. Description. 3.1.2. Operation. 3.1.3. Intel C/C++ Compiler Intrinsics Equivalents 3.1.3.1. Intrinsics 3.1.3.2. Technology Intrinsics 3.1.3.3. Streaming SIMD Extensions Streaming SIMD Extensions Intrinsics. 3.1.4. Flags Affected 3-11 3.1.5. Flags Affected. 3-11 3.1.6. Protected Mode Exceptions 3-11 3.1.7. Real-Address Mode Exceptions 3-12 3.1.8. Virtual-8086 Mode Exceptions. 3-13 3.1.9. Floating-Point Exceptions. 3-13 3.1.10. SIMD Floating-Point Exceptions 3-13 3.2. INSTRUCTION REFERENCE 3-15 AAA-ASCII Adjust After Addition 3-16 AAD-ASCII Adjust Before Division 3-17 AAM-ASCII Adjust After Multiply 3-18 AAS-ASCII Adjust After Subtraction 3-19
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ADC-Add with Carry 3-20 ADD-Add 3-22 ADDPD-Packed Double-Precision Floating-Point 3-24 ADDPS-Packed Single-Precision Floating-Point 3-26 ADDSD-Scalar Double-Precision Floating-Point 3-28 ADDSS-Scalar Single-Precision Floating-Point 3-30 AND-Logical 3-32 ANDPD-Bitwise Logical Packed Double-Precision Floating-Point Values 3-34 ANDPS-Bitwise Logical Packed Single-Precision Floating-Point Values 3-36 ANDNPD-Bitwise Logical Packed Double-Precision Floating-Point Values 3-38 ANDNPS-Bit-wise Logical Single-FP. 3-40 ARPL-Adjust Field Segment Selector 3-42 BOUND-Check Array Index Against Bounds. 3-44 BSF-Bit Scan Forward. 3-46 BSR-Bit Scan Reverse 3-48 BSWAP-Byte Swap. 3-50 BT-Bit Test 3-51 BTC-Bit Test Complement 3-53 BTR-Bit Test Reset. 3-55 BTS-Bit Test 3-57 CALL-Call Procedure 3-59 CBW/CWDE-Convert Byte Word/Convert Word Doubleword 3-70 CDQ-Convert Double Quad 3-71 CLC-Clear Carry Flag 3-72 CLD-Clear Direction Flag 3-73 CLFLUSH-Cache Line Flush 3-74 CLI-Clear Interrupt Flag 3-77 CLTS-Clear Task-Switched Flag 3-79 CMC-Complement Carry Flag 3-80 CMOVcc-Conditional Move 3-81 CMP-Compare Operands 3-85 CMPPD-Compare Packed Double-Precision Floating-Point Values 3-88 CMPPS-Compare Packed Single-Precision Floating-Point Values 3-92 CMPS/CMPSB/CMPSW/CMPSD-Compare String Operands. 3-96 CMPSD-Compare Scalar Double-Precision Floating-Point Value 3-99 CMPSS-Compare Scalar Single-Precision Floating-Point Values 3-103 CMPXCHG-Compare Exchange 3-107 CMPXCHG8B-Compare Exchange Bytes 3-109 COMISD-Compare Scalar Ordered Double-Precision Floating-Point Values EFLAGS 3-111 COMISS-Compare Scalar Ordered Single-Precision Floating-Point Values EFLAGS. 3-114 CPUID-CPU Identification 3-117 CVTDQ2PD-Convert Packed Signed Doubleword Integers Packed Double-Precision Floating-Point Values 3-129 CVTDQ2PS-Convert Packed Signed Doubleword Integers Packed
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Single-Precision Floating-Point Values 3-131 CVTPD2DQ-Convert Packed Double-Precision Floating-Point Values Packed Doubleword Integers 3-133 CVTPD2PI-Convert Packed Double-Precision Floating-Point Packed Doubleword Integers. 3-135 CVTPD2PS-Covert Packed Double-Precision Floating-Point Values Packed Single-Precision Floating-Point Values 3-137 CVTPI2PD-Convert Packed Doubleword Integers Packed Double-Precision Floating-Point Values 3-139 CVTPI2PS-Convert Packed Doubleword Integers Packed Single-Precision Floating-Point Values 3-141 CVTPS2DQ-Convert Packed Single-Precision Floating-Point Values Packed Doubleword Integers 3-143 CVTPS2PD-Covert Packed Single-Precision Floating-Point Values Packed Double-Precision Floating-Point Values 3-145 CVTPS2PI-Convert Packed Single-Precision Floating-Point Values Packed Doubleword Integers 3-147 CVTSD2SI-Convert Scalar Double-Precision Floating-Point Value Doubleword Integer with Truncation 3-149 CVTSD2SS-Convert Scalar Double-Precision Floating-Point Value Scalar Single-Precision Floating-Point Value 3-151 CVTSI2SD-Convert Doubleword Integer Scalar Double-Precision Floating-Point Value 3-153 CVTSI2SS-Convert Doubleword Integer Scalar Single-Precision Floating-Point Value. 3-155 CVTSS2SD-Convert Scalar Single-Precision Floating-Point Value Scalar Double-Precision Floating-Point Value 3-157 CVTSS2SI-Convert Scalar Single-Precision Floating-Point Value Doubleword Integer 3-159 CVTTPD2PI-Convert Packed Double-Precision Floating-Point Values Packed Doubleword Integers with Truncation. 3-161 CVTTPD2DQ-Convert Packed Double-Precision Floating-Point Values Packed Doubleword Integers with Truncation. 3-163 CVTTPS2DQ-Convert Packed Single-Precision Floating-Point Values Packed Doubleword Integers with Truncation 3-165 CVTTPS2PI-Convert Packed Single-Precision Floating-Point Values Packed Doubleword Integers with Truncation. 3-167 CVTTSD2SI-Convert Packed Double-Precision Floating-Point Value Signed Doubleword Integer with Truncation 3-169 CVTTSS2SI-Convert Scalar Double-Precision Floating-Point Value Doubleword Integer with Truncation. 3-171 CWD/CDQ-Convert Word Doubleword/Convert Doubleword Quadword3-173 CWDE-Convert Word Doubleword. 3-174 DAA-Decimal Adjust after Addition. 3-175 DAS-Decimal Adjust after Subtraction 3-178 DEC-Decrement 3-179
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DIV-Unsigned Divide DIVPD-Packed Double-Precision Floating-Point Divide DIVPS-Packed Single-Precision Floating-Point Divide DIVSD-Scalar Double-Precision Floating-Point Divide. DIVSS-Scalar Single-Precision Floating-Point Divide EMMS-Empty State ENTER-Make Stack Frame Procedure Parameters F2XM1-Compute 2x-1 FABS-Absolute Value FADD/FADDP/FIADD-Add. FBLD-Load Binary Coded Decimal FBSTP-Store Integer FCHS-Change Sign FCLEX/FNCLEX-Clear Exceptions FCMOVcc-Floating-Point Conditional Move FCOM/FCOMP/FCOMPP-Compare Real FCOMI/FCOMIP/ FUCOMI/FUCOMIP-Compare Real EFLAGS. FCOS-Cosine FDECSTP-Decrement Stack-Top Pointer FDIV/FDIVP/FIDIV-Divide FDIVR/FDIVRP/FIDIVR-Reverse Divide FFREE-Free Floating-Point Register FICOM/FICOMP-Compare Integer FILD-Load Integer. FINCSTP-Increment Stack-Top Pointer FINIT/FNINIT-Initialize Floating-Point Unit FIST/FISTP-Store Integer FLD-Load Real Constant. FLDCW-Load Control Word FLDENV-Load Environment. FMUL/FMULP/FIMUL-Multiply. FNOP-No Operation FPATAN-Partial Arctangent FPREM-Partial Remainder FPREM1-Partial Remainder FPTAN-Partial Tangent. FRNDINT-Round Integer FRSTOR-Restore State FSAVE/FNSAVE-Store State FSCALE-Scale FSIN-Sine FSINCOS-Sine Cosine FSQRT-Square Root FST/FSTP-Store Real FSTCW/FNSTCW-Store Control Word FSTENV/FNSTENV-Store Environment
3-181 3-184 3-186 3-188 3-190 3-192 3-193 3-196 3-198 3-200 3-203 3-205 3-208 3-210 3-212 3-214 3-217 3-220 3-222 3-223 3-227 3-231 3-232 3-234 3-236 3-237 3-239 3-242 3-244 3-246 3-248 3-250 3-253 3-254 3-256 3-260 3-263 3-265 3-266 3-268 3-271 3-273 3-275 3-277 3-279 3-282 3-284
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FSTSW/FNSTSW-Store Status Word 3-286 FSUB/FSUBP/FISUB-Subtract 3-288 FSUBR/FSUBRP/FISUBR-Reverse Subtract 3-291 FTST-TEST 3-294 FUCOM/FUCOMP/FUCOMPP-Unordered Compare Real 3-296 FWAIT-Wait 3-299 FXAM-Examine. 3-300 FXCH-Exchange Register Contents. 3-302 FXRSTOR-Restore FPU, MMX, Streaming SIMD Extensions, Streaming SIMD Extensions State 3-304 FXSAVE-Save FPU, MMX, Streaming SIMD Extensions, Streaming SIMD Extensions State 3-307 FXTRACT-Extract Exponent Significand 3-312 FYL2X-Compute log2x 3-314 FYL2XP1-Compute log2(x 3-316 HLT-Halt 3-318 IDIV-Signed Divide 3-319 IMUL-Signed Multiply 3-322 IN-Input from Port 3-325 INC-Increment 3-327 INS/INSB/INSW/INSD-Input from Port String 3-329 n/INTO/INT 3-Call Interrupt Procedure. 3-332 INVD-Invalidate Internal Caches. 3-344 INVLPG-Invalidate Entry 3-346 IRET/IRETD-Interrupt Return 3-347 Jcc-Jump Condition 3-355 JMP-Jump. 3-359 LAHF-Load Status Flags into Register 3-367 LAR-Load Access Rights Byte 3-368 LDMXCSR-Load Streaming SIMD Extension Control/Status 3-371 LDS/LES/LFS/LGS/LSS-Load Pointer 3-375 LEA-Load Effective Address. 3-378 LEAVE-High Level Procedure Exit. 3-380 LES-Load Full Pointer 3-382 LFENCE-Load Fence. 3-383 LFS-Load Full Pointer 3-384 LGDT/LIDT-Load Global/Interrupt Descriptor Table Register 3-385 LGS-Load Full Pointer. 3-387 LLDT-Load Local Descriptor Table Register 3-388 LIDT-Load Interrupt Descriptor Table Register 3-390 LMSW-Load Machine Status Word. 3-391 LOCK-Assert LOCK# Signal Prefix 3-393 LODS/LODSB/LODSW/LODSD-Load String 3-395 LOOP/LOOPcc-Loop According Counter 3-398 LSL-Load Segment Limit 3-400 LSS-Load Full Pointer 3-403 LTR-Load Task Register 3-404
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MASKMOVDQU-Mask Move Double Quadword Unaligned. MASKMOVQ-Mask Move Quadword. MAXPD-Maximum Packed Double-Precision Floating-Point Values MAXPS-Maxiumum Packed Single-Precision Floating-Point Values MAXSD-Maximum Scalar Double-Precision Floating-Point Value MAXSS-Maximum Scalar Single-Precision Floating-Point Value MFENCE-Memory Fence MINPD-Packed Double-Precision Floating-Point Minimum MINPS-Minimum Packed Single-Precision Floating-Point Values MINSD-Minimum Scalar Double-Precision Floating-Point Value MINSS-Minimum Scalar Single-Precision Floating-Point Value. MOV-Move MOV-Move to/from Control Registers MOV-Move to/from Debug Registers. MOVAPD-Move Aligned Packed Double-Precision Floating-Point Values MOVAPS-Move Aligned Packed Single-Precision Floating-Point Values MOVD-Move Doubleword MOVDQA-Move Aligned Double Quadword MOVDQU-Move Unaligned Double Quadword MOVDQ2Q-Move Quadword. MOVHLPS- Move Packed Single-Precision Floating-Point Values High MOVHPD-Move High Packed Double-Precision Floating-Point Value MOVHPS-Move High Packed Single-Precision Floating-Point Values. MOVLHPS-Move Packed Single-Precision Floating-Point Values High MOVLPD-Move Packed Double-Precision Floating-Point Value MOVLPS-Move Packed Single-Precision Floating-Point Values MOVMSKPD-Extract Packed Double-Precision Floating-Point Sign Mask MOVMSKPS-Extract Packed Single-Precision Floating-Point Sign Mask MOVNTDQ-Move Double Quadword Non-Temporal. MOVNTI-Move Doubleword Non-Temporal MOVNTPD-Move Packed Double-Precision Floating-Point Values Non-Temporal MOVNTPS-Move Aligned Four Packed Single-FP Temporal MOVNTQ-Move Quadword Non-Temporal. MOVQ-Move Quadword. MOVQ2DQ-Move Quadword. MOVS/MOVSB/MOVSW/MOVSD-Move Data from String String. MOVSD-Move Scalar Double-Precision Floating-Point Value MOVSS-Move Scalar Single-Precision Floating-Point Values MOVSX-Move with Sign-Extension MOVUPD-Move Unaligned Packed Double-Precision Floating-Point Values MOVUPS-Move Unaligned Packed Single-Precision Floating-Point Values MOVZX-Move with Zero-Extend. MUL-Unsigned Multiply. MULPD-Packed Double-Precision Floating-Point Multiply MULPS-Packed Single-Precision Floating-Point Multiply MULSD-Scalar Double-Precision Floating-Point Multiply MULSS-Scalar Single-FP Multiply.
3-406 3-408 3-411 3-414 3-417 3-419 3-421 3-422 3-424 3-427 3-429 3-431 3-436 3-438 3-440 3-442 3-444 3-446 3-448 3-450 3-451 3-452 3-454 3-456 3-457 3-459 3-461 3-463 3-465 3-467 3-469 3-471 3-473 3-475 3-477 3-478 3-481 3-483 3-485 3-487 3-489 3-491 3-493 3-495 3-497 3-499 3-501
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NEG-Two's Complement Negation 3-503 NOP-No Operation. 3-505 NOT-One's Complement Negation 3-506 OR-Logical Inclusive 3-508 ORPD-Bitwise Logical Double-Precision Floating-Point Values 3-511 ORPS-Bitwise Logical Single-Precision Floating-Point Values. 3-513 OUT-Output Port 3-515 OUTS/OUTSB/OUTSW/OUTSD-Output String Port. 3-517 PACKSSWB/PACKSSDW-Pack with Signed Saturation. 3-521 PACKUSWB-Pack with Unsigned Saturation. 3-525 PADDB/PADDW/PADDD-Packed 3-528 PADDQ-Packed Quadword 3-532 PADDSB/PADDSW-Packed with Saturation 3-534 PADDUSB/PADDUSW-Packed Unsigned with Saturation 3-537 PAND-Logical 3-540 PANDN-Logical 3-542 PAUSE-Pause Preset Amount Time 3-544 PAVGB/PAVGW-Packed Average 3-545 PCMPEQB/PCMPEQW/PCMPEQD-Packed Compare Equal 3-548 PCMPGTB/PCMPGTW/PCMPGTD-Packed Compare Greater Than 3-552 PEXTRW-Extract Word. 3-556 PINSRW-Insert Word 3-558 PMADDWD-Packed Multiply 3-561 PMAXSW-Packed Signed Integer Word Maximum 3-565 PMAXUB-Packed Unsigned Integer Byte Maximum 3-568 PMINSW-Packed Signed Integer Word Minimum 3-571 PMINUB-Packed Unsigned Integer Byte Minimum 3-574 PMOVMSKB-Move Byte Mask General-Purpose Register 3-577 PMULHUW-Packed Multiply High Unsigned 3-579 PMULHW-Packed Multiply High Signed 3-582 PMULLW-Packed Multiply Signed 3-585 PMULUDQ-Multiply Doubleword Unsigned 3-588 POP-Pop Value from Stack 3-590 POPA/POPAD-Pop General-Purpose Registers 3-594 POPF/POPFD-Pop Stack into EFLAGS Register 3-596 POR-Bitwise Logical 3-599 PREFETCHh-Prefetch Data Into Caches. 3-601 PSADBW-Packed Absolute Differences. 3-603 PSHUFD-Packed Shuffle Doublewords 3-606 PSHUFHW-Packed Shuffle High Words. 3-609 PSHUFLW-Packed Shuffle Words 3-611 PSHUFW-Packed Shuffle Words 3-613 PSLLDQ-Packed Shift Left Logical Double Quadword 3-615 PSLLW/PSLLD/PSLLQ-Packed Shift Left Logical 3-616 PSRAW/PSRAD-Packed Shift Right Arithmetic 3-620 PSRLDQ-Packed Shift Right Logical Double Quadword 3-624 PSRLW/PSRLD/PSRLQ-Packed Shift Right Logical. 3-625
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PSUBB/PSUBW/PSUBD-Packed Subtract. PSUBQ-Packed Subtract Quadword PSUBSB/PSUBSW-Packed Subtract with Saturation. PSUBUSB/PSUBUSW-Packed Subtract Unsigned with Saturation High Packed Data Packed Data. PUSH-Push Word Doubleword Onto Stack PUSHA/PUSHAD-Push General-Purpose Registers PUSHF/PUSHFD-Push EFLAGS Register onto Stack PXOR-Logical Exclusive RCL/RCR/ROL/ROR-Rotate RCPPS-Packed Single-Precision Floating-Point Reciprocal RCPSS-Scalar Single-Precision Floating-Point Reciprocal RDMSR-Read from Model Specific Register RDPMC-Read Performance-Monitoring Counters RDTSC-Read Time-Stamp Counter REP/REPE/REPZ/REPNE /REPNZ-Repeat String Operation Prefix. RET-Return from Procedure ROL/ROR-Rotate RSM-Resume from System Management Mode RSQRTPS-Packed Single-Precision Floating-Point Square Root Reciprocal RSQRTSS-Scalar Single-Precision Floating-Point Square Root Reciprocal SAHF-Store into Flags SAL/SAR/SHL/SHR-Shift SBB-Integer Subtraction with Borrow SCAS/SCASB/SCASW/SCASD-Scan String SETcc-Set Byte Condition SFENCE-Store Fence SGDT/SIDT-Store Global/Interrupt Descriptor Table Register SHL/SHR-Shift Instructions SHLD-Double Precision Shift Left SHRD-Double Precision Shift Right SHUFPD-Shuffle Double-Precision Floating-Point Values SHUFPS-Shuffle Single-Precision Floating-Point Values SIDT-Store Interrupt Descriptor Table Register SLDT-Store Local Descriptor Table Register SMSW-Store Machine Status Word SQRTPD-Packed Double-Precision Floating-Point Square Root SQRTPS-Packed Single-Precision Floating-Point Square Root SQRTSD-Scalar Double-Precision Floating-Point Square Root. SQRTSS-Scalar Single-Precision Floating-Point Square Root. STC-Set Carry Flag STD-Set Direction Flag STI-Set Interrupt Flag STOS/STOSB/STOSW/STOSD-Store String
3-629 3-632 3-634 3-637 3-640 3-644 3-648 3-651 3-653 3-655 3-658 3-663 3-665 3-667 3-669 3-671 3-672 3-675 3-681 3-682 3-683 3-685 3-687 3-688 3-692 3-694 3-697 3-700 3-701 3-703 3-704 3-706 3-708 3-711 3-714 3-715 3-717 3-719 3-721 3-723 3-725 3-727 3-728 3-729 3-731
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STR-Store Task Register 3-734 SUB-Subtract 3-736 SUBPD-Packed Double-Precision Floating-Point Subtract. 3-738 SUBPS-Packed Single-Precision Floating-Point Subtract 3-740 SUBSD-Scalar Double-Precision Floating-Point Subtract 3-742 SUBSS-Scalar Single-FP Subtract 3-744 SYSENTER-Fast Transition System Call Entry Point 3-746 SYSEXIT-Fast Transition from System Call Entry Point 3-750 TEST-Logical Compare 3-753 UCOMISD-Unordered Compare Scalar Double-Precision Floating-Point Values EFLAGS 3-755 UCOMISS-Unordered Compare Scalar Single-Precision Floating-Point Values EFLAGS 3-758 UD2-Undefined Instruction 3-761 UNPCKHPD-Unpack High Packed Double-Precision Floating-Point Values 3-762 UNPCKHPS-Unpack High Packed Single-Precision Floating-Point Values 3-765 UNPCKLPD-Unpack Packed Double-Precision Floating-Point Values 3-768 UNPCKLPS-Unpack Packed Single-Precision Floating-Point Values 3-771 VERR, VERW-Verify Segment Reading Writing 3-774 WAIT/FWAIT-Wait. 3-776 WBINVD-Write Back Invalidate Cache 3-777 WRMSR-Write Model Specific Register. 3-779 XADD-Exchange Add. 3-781 XCHG-Exchange Register/Memory with Register 3-783 XLAT/XLATB-Table Look-up Translation 3-786 XOR-Logical Exclusive 3-788 XORPD-Bitwise Logical Double-Precision Floating-Point Values 3-791 XORPS-Bitwise Logical Single-Precision Floating-Point Values 3-793 APPENDIX OPCODE A.1. AVAIABLE LATER DATE APPENDIX INSTRUCTION FORMATS ENCODINGS B.1. AVAILABLE LATER DATE APPENDIX INTEL C/C++ COMPILER INTRINSICS FUNCTIONAL EQUIVALENTS C.1. SIMPLE INTRINSICS. C.2. COMPOSITE INTRINSICS C-22
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Figure 1-1. Figure 2-1. Figure 3-1. Figure 3-2. Figure 3-3. Figure 3-4. Figure 3-5. Figure 3-6. Figure 3-7. Figure 3-8. Figure 3-9. Figure 3-10. Figure 3-11. Figure 3-12. Figure 3-13. Figure 3-14. Figure 3-15. Figure 3-16. Figure 3-17. Figure 3-18. Figure 3-19. Figure 3-20. Figure 3-21.
Byte Order Intel Architecture Instruction Format Offset BIT[EAX,21] Memory Indexing 3-11 Version Feature Information Registers 3-119 Operation PACKSSDW Instruction 3-522 Operation PACKUSWB Instruction. 3-525 PMADDWD Execution Model 3-561 PMULHUW PMULHW Instruction Operation 3-579 PMULLU Instruction Operation. 3-585 PSADBW Instruction Operation. 3-603 PSHUFD Instruction Operation 3-606 PSLLW, PSLLD, PSLLQ Instruction Operation 3-616 PSRAW PSRAD Instruction Operation. 3-620 PSRLW, PSRLD, PSRLQ Instruction Operation 3-625 PUNPCKHBW Instruction Operation 3-640 PUNPCKLBW Instruction Operation. 3-644 SHUFPD Shuffle Operation 3-708 SHUFPS Shuffle Operation 3-711 UNPCKHPD Interleave Operation 3-762 UNPCKHPS Interleave Operation 3-765 UNPCKLPD Interleave Operation 3-768 UNPCKLPS Interleave Operation 3-771
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Table 2-1. Table 2-2. Table 2-3. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Table 3-10. Table 3-11. Table 3-12. Table 3-13. Table 3-14. Table C-1. Table C-2.
16-Bit Addressing Forms with ModR/M Byte 32-Bit Addressing Forms with ModR/M Byte 32-Bit Addressing Forms with Byte. Register Encodings Associated with +rb, +rw, Nomenclature Exception Mnemonics, Names, Vector Numbers. 3-12 Floating-Point Exception Mnemonics Names 3-13 SIMD Floating-Point Exception Mnemonics Names 3-14 Streaming SIMD Extensions Faults (Interrupts 3-15 Comparison Predicate CMPPD CMPPS Instructions. 3-88 Information Returned CPUID Instruction 3-117 Highest CPUID Source Operand IA-32 Processors Processor Families. 3-117 Processor Type Field 3-118 Encoding Cache Descriptors 3-123 Mapping Brand Index Processor Brand String 3-125 Processor Brand String Example. 3-126 Processor Brand String Example. 3-126 Layout FXSAVE FXRSTOR Memory Region 3-305 Simple Intrinsics .C-3 Composite Intrinsics .C-22
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About This Manual
CHAPTER ABOUT THIS MANUAL
This preliminary version IA-32 Intel Architecture Software Developer's Manual, Volume Instruction Reference, with Preliminary Willamette Architecture Information preview version IA-32 Intel Architecture Software Developer's Manual, Volume Instruction Reference Intel's next generation IA-32 processors. next generation IA-32 processors consist implementations Intel's Willamette architecture. processor, code named "Willamette," designed serve needs desktop products; second processor, code named "Foster," designed serve needs work station server products. this manual, term "Willamette processor" refers architectural information that applies both Willamette Foster processors. IA-32 Intel Architecture Software Developer's Manual, Volume Instruction Reference part three-volume that describes architecture programming environment Intel Architecture processors. other volumes this are:
IA-32 Intel Architecture Software Developer's Manual, Volume Basic Architecture. IA-32 Intel Architecture Software Developer's Manual, Volume System Programing.
IA-32 Intel Architecture Software Developer's Manual, Volume describes basic architecture programming environment Intel Architecture processor; IA-32 Intel Architecture Software Developer's Manual, Volume describes instructions processor opcode structure. These volumes aimed application programmers writing programs under existing operating systems executives. IA-32 Intel Architecture Software Developer's Manual, Volume describes operating-system support environment Intel Architecture processor, including memory management, protection, task management, interrupt exception handling, system management mode. also provides Intel Architecture processor compatibility information. This volume aimed operatingsystem BIOS designers programmers. (Volume currently being prepared publication.)
1.1.
OVERVIEW IA-32 INTEL ARCHITECTURE SOFTWARE DEVELOPER'S MANUAL, VOLUME INSTRUCTION REFERENCE
contents IA-32 Intel Architecture Software Developer's Manual, Volume follows: Chapter About This Manual. Gives overview three volumes IA-32 Intel Architecture Software Developer's Manual. also describes notational conventions these manuals lists related Intel manuals documentation interest programmers hardware designers.
Preliminary Version
ABOUT THIS MANUAL
Chapter Instruction Format. Describes machine-level instruction format used IA-32 instructions gives allowable encodings prefixes, operand-identifier byte (ModR/M byte), addressing-mode specifier byte (SIB byte), displacement immediate bytes. Chapter Instruction Reference. Describes each IA-32 instructions detail, including algorithmic description operations, effect flags, effect operand- address-size attributes, exceptions that generated. instructions arranged alphabetical order. general-purpose, FPU, MMXTM, Streaming SIMD Extensions, Streaming SIMD Extensions system instructions included this chapter. Appendix Opcode Map. Gives opcode IA-32 instruction set. ntel C/C++ Compiler Intrinsics Functional Equivalents Appendix Instruction Formats Encodings. Gives binary encoding each form each IA-32 instruction. Appendix Intel C/C++ Compiler Intrinsics Functional Equivalents. Lists Intel C/C++ compiler intrinsics their assembly code equivalents each IA-32 MMX, Streaming SIMD Extensions, Streaming SIMD Extensions instructions.
1.2.
OVERVIEW IA-32 INTEL ARCHITECTURE SOFTWARE DEVELOPER'S MANUAL, VOLUME BASIC ARCHITECTURE
contents this manual follows: Chapter About This Manual. Gives overview three volumes IA-32 Intel Architecture Software Developer's Manual. also describes notational conventions these manuals lists related Intel manuals documentation interest programmers hardware designers. Chapter Introduction IA-32 Architecture. Introduces IA-32 architecture families Intel processors that based this architecture. also gives overview common features found these processors brief history IA-32 architecture. Chapter Basic Execution Environment. Introduces models memory organization describes register used applications. Chapter Data Types. Describes data types addressing modes recognized processor; provides overview floating point numbers, IEEE Standard FloatingPoint Arithmetic, floating-point exceptions. Chapter Instruction Summary. Lists IA-32 architecture instructions, divided into technology groups (general-purpose, FPU, technology, Streaming SIMD Extensions, Streaming SIMD Extensions system instructions). Within these groups, instructions presented functionally related groups.
Preliminary Version
ABOUT THIS MANUAL
Chapter Procedure Calls, Interrupts, Exceptions. Describes procedure stack mechanisms provided making procedure calls servicing interrupts exceptions. Chapter Programming With General-Purpose System Instructions. Describes basic load store, program control, arithmetic, string instructions that operate basic data types general-purpose segment registers; describes system instructions that executed protected mode. Chapter Programming With Floating Point Unit. Describes floatingpoint unit (FPU), including floating-point registers data types; gives overview floating-point instruction set; describes processor's floating-point exception conditions. Chapter Programming with Intel Technology. Describes Intel technology, including registers data types, gives overview instruction set. Chapter Programming with Streaming SIMD Extensions. Describes Streaming SIMD Extensions, including registers single-precision floating-point data types; gives overview Streaming SIMD Extensions instruction set; gives guidelines writing code that accesses Streaming SIMD Extensions. Chapter Programming with Streaming SIMD Extensions Describes Streaming SIMD Extensions including registers double-precision floating-point double quadword integer data types; gives overview Streaming SIMD Extensions instruction set; gives guidelines writing code that accesses Streaming SIMD Extensions Chapter Input/Output. Describes processor's mechanism, including port addressing, instructions, protection mechanism. Chapter Processor Identification Feature Determination. Describes determine type features that available processor. Appendix EFLAGS Cross-Reference. Summarizes IA-32 instructions affect flags EFLAGS register. Appendix EFLAGS Condition Codes. Summarizes conditional jump, move, byte condition code instructions condition code flags (OF, EFLAGS register. Appendix Floating-Point Exceptions Summary. Summarizes exceptions that raised FPU, Streaming SIMD Extensions, Streaming SIMD Extensions floating-point instructions. Appendix Guidelines Writing Exception Handlers. Describes design write MS-DOS* compatible exception handling facilities exceptions, including both software hardware requirements assembly-language code examples. This appendix also describes general techniques writing robust exception handlers. Appendix Guidelines Writing Streaming SIMD Exception Handlers. Gives guidelines writing exception handlers handle exceptions generated Streaming SIMD Extensions Streaming SIMD Extensions
Preliminary Version
ABOUT THIS MANUAL
1.3.
OVERVIEW IA-32 INTEL ARCHITECTURE SOFTWARE DEVELOPER'S MANUAL, VOLUME SYSTEM PROGRAMMING GUIDE
next version IA-32 Intel Architecture Software Developer's Manual, Volume currently being prepared. planned contents this manual will follows: Chapter About This Manual. Gives overview three volumes IA-32 Software Developer's Manual. also describes notational conventions these manuals lists related Intel manuals documentation interest programmers hardware designers. Chapter System Architecture Overview. Describes modes operation IA-32 processor mechanisms provided IA-32 architecture support operating systems executives, including system-oriented registers data structures systemoriented instructions. steps necessary switching between real-address protected modes also identified. Chapter Protected-Mode Memory Management. Describes data structures, registers, instructions that support segmentation paging explains they used implement "flat" (unsegmented) memory model segmented memory model. Chapter Protection. Describes support page segment protection provided IA-32 architecture. This chapter also explains implementation privilege rules, stack switching, pointer validation, user supervisor modes. Chapter Interrupt Exception Handling. Describes basic interrupt mechanisms defined IA-32 architecture, shows interrupts exceptions relate protection, describes architecture handles each exception type. Reference information each IA32 exception given this chapter. Chapter Task Management. Describes mechanisms that IA-32 architecture provides support multitasking inter-task protection. Chapter Multiple Processor Management. Describes instructions flags that support multiple processors with shared memory, memory ordering, advanced programmable interrupt controller (APIC). Chapter Processor Management Initialization. Defines state IA-32 processor after reset initialization. This chapter also explains IA-32 processor real-address mode operation protected mode operation, switch between modes. Chapter Memory Cache Control. Describes general concept caching, caching mechanisms supported IA-32 architecture, cache control instructions. This chapter also describes memory type range registers (MTRRs) they used memory types physical memory. Chapter Technology System Programming. Describes those aspects Intel technology that must handled considered system programming level, including task switching, exception handling, compatibility with existing system environments.
Preliminary Version
ABOUT THIS MANUAL
Chapter System Management Mode (SMM). Describes IA-32 architecture's system management mode (SMM), which used implement power management functions. Chapter Machine Check Architecture. Describes machine check architecture. Chapter Code Optimization. Discusses general optimization techniques programming IA-32 processor. Chapter Debugging Performance Monitoring. Describes debugging registers other debug mechanism provided IA-32 architecture. This chapter also describes time-stamp counter performance monitoring counters. Chapter 8086 Emulation. Describes real-address virtual-8086 modes IA32 architecture. Chapter Mixing 16-Bit 32-Bit Code. Describes 16-bit 32-bit code modules within same program task. Chapter IA-32 Architecture Compatibility. Describes programming among IA32 processors, which include Intel 286, Intel386TM, Intel486TM, Pentium®, family, Willamette processors. differences among 32-bit IA-32 processors also described throughout three volumes IA-32 Software Developer's Manual, relevant particular features architecture. This chapter provides collection relevant compatibility information IA-32 processors also describes basic differences with respect 16-bit IA-32 processors (the Intel 8086 Intel processors). Appendix Performance-Monitoring Events. Lists events that counted with performance-monitoring counters codes used select these events. Appendix Model Specific Registers (MSRs). Lists MSRs available Pentium, family, Willamette family processors their functions.
1.4.
NOTATIONAL CONVENTIONS
This manual uses special notation data-structure formats, symbolic representation instructions, hexadecimal numbers. review this notation makes manual easier read.
1.4.1.
Byte Order
illustrations data structures memory, smaller addresses appear toward bottom figure; addresses increase toward top. positions numbered from right left. numerical value equal raised power position. Intel Architecture processors "little endian" machines; this means bytes word numbered starting from least significant byte. Figure illustrates these conventions.
Preliminary Version
ABOUT THIS MANUAL
Highest Address
Data Structure
offset
Byte
Byte
Byte
Byte
Lowest Address
Byte Offset
Figure 1-1. Byte Order
1.4.2.
Reserved Bits Software Compatibility
many register memory layout descriptions, certain bits marked reserved. When bits marked reserved, essential compatibility with future processors that software treat these bits having future, though unknown, effect. behavior reserved bits should regarded only undefined, unpredictable. Software should follow these guidelines dealing with reserved bits:
depend states reserved bits when testing values registers which contain such bits. Mask reserved bits before testing. depend states reserved bits when storing memory register. depend ability retain information written into reserved bits. When loading register, always load reserved bits with values indicated documentation, any, reload them with values previously read from same register.
NOTE
Avoid software dependence upon state reserved bits Intel Architecture registers. Depending upon values reserved register bits will make software dependent upon unspecified manner which processor handles these bits. Programs that depend upon reserved values risk incompatibility with future processors.
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1.4.3.
Instruction Operands
When instructions represented symbolically, subset Intel Architecture assembly language used. this subset, instruction following format:
label: mnemonic argument1, argument2, argument3
where:
label identifier which followed colon. mnemonic reserved name class instruction opcodes which have same function. operands argument1, argument2, argument3 optional. There from zero three operands, depending opcode. When present, they take form either literals identifiers data items. Operand identifiers either reserved names registers assumed assigned data items declared another part program (which shown example).
When operands present arithmetic logical instruction, right operand source left operand destination. example:
LOADREG: EAX, SUBTOTAL
this example, LOADREG label, mnemonic identifier opcode, destination operand, SUBTOTAL source operand. Some assembly languages source destination reverse order.
1.4.4.
Hexadecimal Binary Numbers
Base (hexadecimal) numbers represented string hexadecimal digits followed character (for example, F82EH). hexadecimal digit character from following set: Base (binary) numbers represented string sometimes followed character (for example, 1010B). designation only used situations where confusion type number might arise.
1.4.5.
Segmented Addressing
processor uses byte addressing. This means memory organized accessed sequence bytes. Whether more bytes being accessed, byte address used locate byte bytes memory. range memory that addressed called address space.
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ABOUT THIS MANUAL
processor also supports segmented addressing. This form addressing where program have many independent address spaces, called segments. example, program keep code (instructions) stack separate segments. Code addresses would always refer code space, stack addresses would always refer stack space. following notation used specify byte address within segment: Segment-register:Byte-address example, following segment address identifies byte address FF79H segment pointed register:
DS:FF79H
following segment address identifies instruction address code segment. register points code segment register contains address instruction.
CS:EIP
1.4.6.
Exceptions
exception event that typically occurs when instruction causes error. example, attempt divide zero generates exception. However, some exceptions, such breakpoints, occur under other conditions. Some types exceptions provide error codes. error code reports additional information about error. example notation used show exception error code shown below.
#PF(fault code)
This example refers page-fault exception under conditions where error code naming type fault reported. Under some conditions, exceptions which produce error codes able report accurate code. this case, error code zero, shown below general-protection exception.
#GP(0)
Chapter Interrupt Exception Handling, IA-32 Intel Architecture Software Developer's Manual, Volume list exception mnemonics their descriptions.
1.5.
RELATED LITERATURE
Literature related Intel processors listed on-line following Intel site:
Some documents listed this site viewed on-line; others ordered online. literature available listed Intel processor then following literature types: applications notes, data sheets, manuals, papers, specification updates. following literature interest:
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Data Sheet particular Intel IA-32 processor. Specification Update particular Intel IA-32 processor.
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ABOUT THIS MANUAL
following application notes: AP-485, Intel Processor Identification CPUID Instruction, Order Number 241618. AP-528, Optimizations Intel's 32-Bit Processors, Order Number 242816-001.
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Instruction Format
CHAPTER INSTRUCTION FORMAT
This chapter describes instruction format Intel Architecture processors.
2.1.
GENERAL INSTRUCTION FORMAT
Intel Architecture instruction encodings subsets general instruction format shown Figure 2-1. Instructions consist optional instruction prefixes order), primary opcode bytes, addressing-form specifier required) consisting ModR/M byte sometimes (Scale-Index-Base) byte, displacement required), immediate data field required).
Instruction Prefixes four prefixes 1-byte each (optional)
Opcode byte opcode
ModR/M byte required)
byte required)
Displacement Address displacement bytes none Index Base
Immediate Immediate data bytes none
Reg/ Opcode
Scale
Figure 2-1. Intel Architecture Instruction Format
2.2.
INSTRUCTION PREFIXES
instruction prefixes divided into four groups, each with allowable prefix codes:
Lock repeat prefixes. F0H-LOCK prefix. F2H-REPNE/REPNZ prefix (used only with string instructions). F2H-Streaming SIMD Extensions prefix. F3H-REP prefix (used only with string instructions). F3H-REPE/REPZ prefix (used only with string instructions). F3H-Streaming SIMD Extensions prefix. F3H-Streaming SIMD Extensions prefix.
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Segment override. 2EH-CS segment override prefix. 36H-SS segment override prefix. 3EH-DS segment override prefix. 26H-ES segment override prefix. 64H-FS segment override prefix. 65H-GS segment override prefix.
Operand-size override, Streaming SIMD Extensions prefix, Address-size override, Streaming SIMD Extensions prefix, Streaming SIMD Extensions prefix,
each instruction, prefix used from each these groups placed order. effect redundant prefixes (more than prefix from group) undefined vary from processor processor. nature Streaming SIMD Extensions Streaming SIMD Extensions technology allows existing instruction formats. Instructions ModR/M format preceded prefix byte. general, operations duplicated provide directions (i.e. separate load store variants).
2.3.
OPCODE
primary opcode either bytes. additional 3-bit opcode field sometimes encoded ModR/M byte. Smaller encoding fields defined within primary opcode. These fields define direction operation, size displacements, register encoding, condition codes, sign extension. encoding fields opcode varies, depending class operation.
2.4.
MODR/M BYTES
Most instructions that refer operand memory have addressing-form specifier byte (called ModR/M byte) following primary opcode. ModR/M byte contains three fields information:
field combines with field form possible values: eight registers addressing modes. reg/opcode field specifies either register number three more bits opcode information. purpose reg/opcode field specified primary opcode.
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field specify register operand combined with field encode addressing mode.
Certain encodings ModR/M byte require second addressing byte, byte, fully specify addressing form. base-plus-index scale-plus-index forms 32-bit addressing require byte. byte includes following fields:
scale field specifies scale factor. index field specifies register number index register. base field specifies register number base register.
Section 2.6., "Addressing-Mode Encoding ModR/M Bytes", encodings ModR/M bytes.
2.5.
DISPLACEMENT IMMEDIATE BYTES
Some addressing forms include displacement immediately following either ModR/M byte. displacement required, bytes. instruction specifies immediate operand, operand always follows displacement bytes. immediate operand bytes.
2.6.
ADDRESSING-MODE ENCODING MODR/M BYTES
values corresponding addressing forms ModR/M bytes shown Tables through 2-3. 16-bit addressing forms specified ModR/M byte Table 2-1, 32-bit addressing forms specified ModR/M byte Table 2-2. Table shows 32-bit addressing forms specified byte. Tables 2-2, first column (labeled "Effective Address") lists different effective addresses that assigned operand instruction using fields ModR/M byte. first effective addresses give different ways specifying memory location; last eight (specified field encoding 11B) give ways specifying general-purpose, MMXTM, registers. Each register encodings list four possible registers. example, first register-encoding (selected field encoding 000B) indicates general-purpose registers EAX, register MM0, register XMM0. Which these five registers used determined opcode byte operand-size attribute, which select either register bits) register bits). second third columns Tables gives binary encodings fields ModR/M byte, respectively, required obtain associated effective address listed first column. possible combinations fields listed. Across Tables 2-2, eight possible values 3-bit Reg/Opcode field listed, decimal (sixth from top) binary (seventh from top). seventh
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INSTRUCTION FORMAT
labeled "REG=", which represents these bits give location second operand, which must general-purpose, MMX, register. instruction does require second operand specified, then bits Reg/Opcode field used extension opcode, which represented sixth row, labeled "/digit (Opcode)". five rows above give byte, word, doubleword general-purpose registers, registers, registers that correspond register numbers, with same assignments field when field encoding 11B. with field register options, which five possible registers used determined opcode byte along with operand-size attribute. body Tables (under label "Value ModR/M Byte Hexadecimal)") contains array giving values ModR/M byte, hexadecimal. Bits specified column table which byte resides, specifies bits also bits
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Table 2-1. 16-Bit Addressing Forms with ModR/M Byte
r8(/r) r16(/r) r32(/r) mm(/r) xmm(/r) /digit (Opcode) XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7
Effective Address [BX+SI] [BX+DI] [BP+SI] [BP+DI] [SI] [DI] disp162 [BX] [BX+SI]+disp83 [BX+DI]+disp8 [BP+SI]+disp8 [BP+DI]+disp8 [SI]+disp8 [DI]+disp8 [BP]+disp8 [BX]+disp8 [BX+SI]+disp16 [BX+DI]+disp16 [BP+SI]+disp16 [BP+DI]+disp16 [SI]+disp16 [DI]+disp16 [BP]+disp16 [BX]+disp16 EAX/AX/AL/MM0/XMM0 ECX/CX/CL/MM1/XMM1 EDX/DX/DL/MM2/XMM2 EBX/BX/BL/MM3/XMM3 ESP/SP/AHMM4/XMM4 EBP/BP/CH/MM5/XMM5 ESI/SI/DH/MM6/XMM6 EDI/DI/BH/MM7/XMM7 NOTES:
Value ModR/M Byte Hexadecimal)
default segment register effective addresses containing index, other effective addresses. "disp16" nomenclature denotes 16-bit displacement following ModR/M byte, added index. "disp8" nomenclature denotes 8-bit displacement following ModR/M byte, sign-extended added index.
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Table 2-2. 32-Bit Addressing Forms with ModR/M Byte
r8(/r) r16(/r) r32(/r) mm(/r) /digit (Opcode) Effective Address [EAX] [ECX] [EDX] [EBX] [-][-]1 disp322 [ESI] [EDI] disp8[EAX]3 disp8[ECX] disp8[EDX] disp8[EBX]; disp8[-][-] disp8[EBP] disp8[ESI] disp8[EDI] disp32[EAX] disp32[ECX] disp32[EDX] disp32[EBX] disp32[-][-] disp32[EBP] disp32[ESI] disp32[EDI] EAX/AX/AL/MM0 ECX/CX/CL/MM1 EDX/DX/DL/MM2 EBX/BX/BL/MM3 ESP/SP/AH/MM4 EBP/BP/CH/MM5 ESI/SI/DH/MM6 EDI/DI/BH/MM7 NOTES: [-][-] nomenclature means follows ModR/M byte. disp32 nomenclature denotes 32-bit displacement following byte, added index. disp8 nomenclature denotes 8-bit displacement following byte, sign-extended added index.
Value ModR/M Byte Hexadecimal)
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INSTRUCTION FORMAT
Table organized similarly Tables 2-2, except that body gives possible values byte, hexadecimal. Which general-purpose registers will used base indicated across table, along with corresponding values base field (bits decimal binary. rows indicate which register used index (determined bits along with scaling factor (determined bits
Table 2-3. 32-Bit Addressing Forms with Byte
Base Base Scaled Index [EAX] [ECX] [EDX] [EBX] none [EBP] [ESI] [EDI] [EAX*2] [ECX*2] [EDX*2] [EBX*2] none [EBP*2] [ESI*2] [EDI*2] [EAX*4] [ECX*4] [EDX*4] [EBX*4] none [EBP*4] [ESI*4] [EDI*4] [EAX*8] [ECX*8] [EDX*8] [EBX*8] none [EBP*8] [ESI*8] [EDI*8] NOTE: nomenclature means disp32 with base [EBP] otherwise. This provides following addressing modes: disp32[index] (MOD=00). disp8[EBP][index](MOD=01). disp32[EBP][index](MOD=10). Index
Value Byte Hexadecimal)
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INSTRUCTION FORMAT
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INSTRUCTION FORMAT
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Instruction Reference
CHAPTER INSTRUCTION REFERENCE
This chapter describes complete Intel Architecture instruction set, including generalpurpose, FPU, MMXtechnology, Streaming SIMD Extensions, Streaming SIMD Extensions system instructions. instruction descriptions arranged alphabetical order. each instruction, forms given each operand combination, including opcode, operands required, description. Also given each instruction description instruction operands, operational description, description effect instructions flags EFLAGS register, summary exceptions that generated.
3.1.
INTERPRETING INSTRUCTION REFERENCE PAGES
This section describes information contained various sections instruction reference pages that make majority this chapter. also explains notational conventions abbreviations used these sections.
3.1.1.
Instruction Format
following example format used each Intel Architecture instruction description this chapter:
CMC-Complement Carry Flag
Opcode Instruction Description Complement carry flag
3.1.1.1.
OPCODE COLUMN
"Opcode" column gives complete object code produced each form instruction. When possible, codes given hexadecimal bytes, same order which they appear memory. Definitions entries other than hexadecimal bytes follows:
/digit-A digit between indicates that ModR/M byte instruction uses only (register memory) operand. field contains digit that provides extension instruction's opcode. /r-Indicates that ModR/M byte instruction contains both register operand operand.
INSTRUCTION REFERENCE
cp-A 1-byte (cb), 2-byte (cw), 4-byte (cd), 6-byte (cp) value following opcode that used specify code offset possibly value code segment register. id-A 1-byte (ib), 2-byte (iw), 4-byte (id) immediate operand instruction that follows opcode, ModR/M bytes scale-indexing bytes. opcode determines operand signed value. words doublewords given with low-order byte first. +rb, +rw, +rd-A register code, from through added hexadecimal byte given left plus sign form single opcode byte. register codes given Table 3-1. +i-A number used floating-point instructions when operands ST(i) from register stack. number (which range from added hexadecimal byte given left plus sign form single opcode byte.
Table 3-1. Register Encodings Associated with +rb, +rw, Nomenclature
3.1.1.2.
INSTRUCTION COLUMN
"Instruction" column gives syntax instruction statement would appear ASM386 program. following list symbols used represent operands instruction statements:
rel8-A relative address range from bytes before instruction bytes after instruction. rel16 rel32-A relative address within same code segment instruction assembled. rel16 symbol applies instructions with operand-size attribute bits; rel32 symbol applies instructions with operand-size attribute bits. ptr16:16 ptr16:32-A pointer, typically code segment different from that instruction. notation 16:16 indicates that value pointer parts. value left colon 16-bit selector value destined code segment register. value right corresponds offset within destination segment.
INSTRUCTION REFERENCE
ptr16:16 symbol used when instruction's operand-size attribute bits; ptr16:32 symbol used when operand-size attribute bits.
r8-One byte general-purpose registers r16-One word general-purpose registers r32-One doubleword general-purpose registers EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI. imm8-An immediate byte value. imm8 symbol signed number between -128 +127 inclusive. instructions which imm8 combined with word doubleword operand, immediate value sign-extended form word doubleword. upper byte word filled with topmost immediate value. imm16-An immediate word value used instructions whose operand-size attribute bits. This number between -32,768 +32,767 inclusive. imm32-An immediate doubleword value used instructions whose operandsize attribute bits. allows number between +2,147,483,647 -2,147,483,648 inclusive. r/m8-A byte operand that either contents byte general-purpose register (AL, DH), byte from memory. r/m16-A word general-purpose register memory operand used instructions whose operand-size attribute bits. word general-purpose registers are: contents memory found address provided effective address computation. r/m32-A doubleword general-purpose register memory operand used instructions whose operand-size attribute bits. doubleword general-purpose registers are: EAX, EBX, ECX, EDX, ESP, EBP, ESI, EDI. contents memory found address provided effective address computation. 32-bit operand memory. m8-A byte operand memory, usually expressed variable array name, pointed DS:(E)SI ES:(E)DI registers. This nomenclature used only with string instructions XLAT instruction. m16-A word operand memory, usually expressed variable array name, pointed DS:(E)SI ES:(E)DI registers. This nomenclature used only with string instructions. m32-A doubleword operand memory, usually expressed variable array name, pointed DS:(E)SI ES:(E)DI registers. This nomenclature used only with string instructions. m64-A memory quadword operand memory. This nomenclature used only with CMPXCHG8B instruction. m128-A memory double quadword operand memory. This nomenclature used only with Streaming SIMD Extensions.
INSTRUCTION REFERENCE
m16:16, m16:32-A memory operand containing pointer composed numbers. number left colon corresponds pointer's segment selector. number right corresponds offset. m16&32, m16&16, m32&32-A memory operand consisting data item pairs whose sizes indicated left right side ampersand. memory addressing modes allowed. m16&16 m32&32 operands used BOUND instruction provide operand containing upper lower bounds array indices. m16&32 operand used LIDT LGDT provide word with which load limit field, doubleword with which load base field corresponding GDTR IDTR registers. moffs8, moffs16, moffs32-A simple memory variable (memory offset) type byte, word, doubleword used some variants instruction. actual address given simple offset relative segment base. ModR/M byte used instruction. number shown with moffs indicates size, which determined address-size attribute instruction. Sreg-A segment register. segment register assignments ES=0, CS=1, SS=2, DS=3, FS=4, GS=5. m32real, m64real, m80real-A single-, double-, extended-real (respectively) floating-point operand memory. m16int, m32int, m64int-A word-, short-, long-integer (respectively) floating-point operand memory. ST(0)-The element register stack. ST(i)-The element from register stack. through mm-An register. 64-bit registers are: through MM7. mm/m32-The order bits register 32-bit memory operand. 64-bit registers are: through MM7. contents memory found address provided effective address computation. mm/m64-An register 64-bit memory operand. 64-bit registers are: through MM7. contents memory found address provided effective address computation. xmm-An register. 128-bit registers are: XMM0 through XMM7. xmm/m32-An register 32-bit memory operand. 128-bit registers XMM0 through XMM7. contents memory found address provided effective address computation. xmm/m64-An register 64-bit memory operand. 128-bit SIMD floatingpoint registers XMM0 through XMM7. contents memory found address provided effective address computation. xmm/m128-An register 128-bit memory operand. 128-bit registers XMM0 through XMM7. contents memory found address provided effective address computation.
INSTRUCTION REFERENCE
3.1.1.3.
DESCRIPTION COLUMN
"Description" column following "Instruction" column briefly explains various forms instruction. following "Description" "Operation" sections contain more details instruction's operation. 3.1.1.4. DESCRIPTION
"Description" section describes purpose instructions required operands. also discusses effect instruction flags.
3.1.2.
Operation
"Operation" section contains algorithmic description (written pseudo-code) instruction. pseudo-code uses notation similar Algol Pascal language. algorithms composed following elements:
Comments enclosed within symbol pairs "(*" "*)". Compound statements enclosed keywords, such THEN, ELSE, statement, statement, CASE ESAC case statement. register name implies contents register. register name enclosed brackets implies contents location whose address contained that register. example, ES:[DI] indicates contents location whose segment relative address register [SI] indicates contents address contained register relative SI's default segment (DS) overridden segment. Parentheses around general-purpose register name, such (E)SI, indicates that offset read from register current address-size attribute read from register address-size attribute Brackets also used memory operands, where they mean that contents memory location segment-relative offset. example, [SRC] indicates that contents source operand segment-relative offset. indicates that value assigned symbols relational operators used compare values, meaning equal, equal, greater equal, less equal, respectively. relational expression such TRUE value equal otherwise FALSE. expression COUNT" COUNT" indicates that destination operand should shifted left right, respectively, number bits indicated count operand.
following identifiers used algorithmic descriptions:
OperandSize AddressSize-The OperandSize identifier represents operand-size attribute instruction, which either bits. AddressSize identifier represents address-size attribute, which either bits. example,
INSTRUCTION REFERENCE
following pseudo-code indicates that operand-size attribute depends form CMPS instruction used.
instruction CMPSW THEN OperandSize ELSE instruction CMPSD THEN OperandSize
"Operand-Size Address-Size Attributes" Chapter IA-32 Intel Architecture Software Developer's Manual, Volume general guidelines these attributes determined.
StackAddrSize-Represents stack address-size attribute associated with instruction, which value bits (see "Address-Size Attribute Stack" Chapter IA-32 Intel Architecture Software Developer's Manual, Volume SRC-Represents source operand. DEST-Represents destination operand.
following functions used algorithmic descriptions: ZeroExtend(value)-Returns value zero-extended operand-size attribute instruction. example, operand-size attribute zero extending byte value converts byte from doubleword value 000000F6H. value passed ZeroExtend function operand-size attribute same size, ZeroExtend returns value unaltered. SignExtend(value)-Returns value sign-extended operand-size attribute instruction. example, operand-size attribute sign extending byte containing value converts byte from doubleword value FFFFFFF6H. value passed SignExtend function operand-size attribute same size, SignExtend returns value unaltered. signed 16-bit value signed 8-bit value. signed 16-bit value less than -128, represented saturated value (80H); greater than 127, represented saturated value (7FH). signed 32-bit value signed 16-bit value. signed 32-bit value less than -32768, represented saturated value -32768 (8000H); greater than 32767, represented saturated value 32767 (7FFFH). signed 16-bit value unsigned 8-bit value. signed 16-bit value less than zero, represented saturated value zero (00H); greater than 255, represented saturated value (FFH).
INSTRUCTION REFERENCE
SaturateToSignedByte-Represents result operation signed 8-bit value. result less than -128, represented saturated value -128 (80H); greater than 127, represented saturated value (7FH). SaturateToSignedWord-Represents result operation signed 16-bit value. result less than -32768, represented saturated value -32768 (8000H); greater than 32767, represented saturated value 32767 (7FFFH). result operation signed 8-bit value. result less than zero represented saturated value zero (00H); greater than 255, represented saturated value (FFH). result operation signed 16-bit value. result less than zero represented saturated value zero (00H); greater than 65535, represented saturated value 65535 (FFFFH). LowOrderWord(DEST SRC)-Multiplies word operand word operand stores least significant word doubleword result destination operand. HighOrderWord(DEST SRC)-Multiplies word operand word operand stores most significant word doubleword result destination operand. Push(value)-Pushes value onto stack. number bytes pushed determined operand-size attribute instruction. "Operation" section "PUSH-Push Word Doubleword Onto Stack" this chapter more information push operation. Pop() removes value from stack returns statement Pop(); assigns 32-bit value from stack. will return either word doubleword depending operand-size attribute. "Operation" section Chapter "POP-Pop Value from Stack" more information operation. PopRegisterStack-Marks ST(0) register empty increments register stack pointer (TOP) Switch-Tasks-Performs task switch. Bit(BitBase, BitOffset)-Returns value within string, which sequence bits memory register. Bits numbered from low-order high-order within registers within memory bytes. base operand register, offset range 0.31. This offset addresses within indicated register. example, function Bit[EAX, illustrated Figure 3-1.
INSTRUCTION REFERENCE
BitOffset
Figure 3-1. Offset BIT[EAX,21]
BitBase memory address, BitOffset range from GBits GBits. addressed numbered (Offset within byte address (BitBase (BitOffset 8)), where signed division with rounding towards negative infinity, returns positive number. This operation illustrated Figure 3-2.
3.1.3.
Intel C/C++ Compiler Intrinsics Equivalents
Intel C/C++ compiler intrinsics equivalents special C/C++ coding extensions that allow using syntax function calls variables instead hardware registers. Using these intrinsics frees programmers from having manage registers assembly programming. Further, compiler optimizes instruction scheduling that executables runs faster. following sections discuss intrinsics technology SIMD floatingpoint intrinsics. Each intrinsic equivalent listed with instruction description. There additional intrinsics that have instruction equivalent. strongly recommended that reader reference compiler documentation complete list supported intrinsics. Please refer Intel C/C++ Compiler User's Guide With Support Streaming SIMD Extensions
(Order Number 718195-2001). Appendix Compiler Intrinsics Functional Equivalents more information using intrinsics.
3.1.3.1.
INTRINSICS
benefit coding with technology intrinsics Streaming SIMD Extensions Streaming SIMD Extensions intrinsics that syntax function calls variables instead hardware registers. This frees from managing registers programming assembly. Further, compiler optimizes instruction scheduling that your executable runs faster. each computational data manipulation instruction instruction set, there corresponding intrinsic that implements directly. intrinsics allow specify underlying implementation (instruction selection) algorithm leave instruction scheduling register allocation compiler. 3.1.3.2. TECHNOLOGY INTRINSICS
technology intrinsics based _m64 data type represent specific contents technology register. specify values bytes, short integers, 32-bit
INSTRUCTION REFERENCE
values, 64-bit object. _m64 data type, however, basic ANSI data type, therefore must observe following usage restrictions:
_m64 data only left-hand side assignment, return value, parameter. cannot with other arithmetic expressions ("+", ">>", on). _m64 objects aggregates, such unions access byte elements
structures; address _m64 object taken.
_m64 data only with technology intrinsics described this guide Intel C/C++ Compiler User's Guide With Support Streaming SIMD
Extensions (Order Number 718195-2001). Refer Appendix Compiler Intrinsics Functional Equivalents more information using intrinsics.
3.1.3.3.
STREAMING SIMD EXTENSIONS STREAMING SIMD EXTENSIONS INTRINSICS
Streaming SIMD Extensions Streaming SIMD Extensions intrinsics make registers Pentium(r) Willamette Processors. There three data types supported these intrinsics: _m128, _m128d, _m128i. _m128 data type used represent contents Streaming SIMD Extensions registers used Streaming SIMD Extension intrinsics. This either four packed single-precision floating-point values scalar single-precision number. _m128d data type holds 64-bit floating point (double-precision) values. _m128i data type hold sixteen 8-bit, eight 16-bit, four 32-bit, 64-bit integer values.
compiler aligns _m128, _m128d, _m128 local global data 16-byte boundaries stack. align integer, float, double arrays, declspec statement described Intel C/C++ Compiler User's Guide With Support Streaming SIMD Extensions
(Order Number 718195-2001).
_m128 data types basic ANSI data types therefore some restrictions placed usage:
_m128, _m128d, _m128i only left-hand side assignment, return value, parameter. other arithmetic expressions such ">>". initialize _m128, _m128d, _m128i with literals; there express 128-bit constants. _m128, _m128d, _m128i objects aggregates, such unions (for example, access float elements) structures. address these objects taken. _m128, _m128d, _m128i data only with intrinsics described this user's guide. Refer Appendix Compiler Intrinsics Functional Equivalents more information
using intrinsics.
INSTRUCTION REFERENCE
compiler aligns _m128, _m128d, _m128i local data 16-byte boundaries stack. Global _m128 data also aligned 16-byte boundaries. align float arrays, alignment declspec described following section.) Because instruction treats SIMD floating-point registers same whether using packed scalar data, there _m32 data type represent scalar data might expect. scalar operations, should _m128 objects "scalar" forms intrinsics; compiler processor implement these operations with 32-bit memory references. suffixes used denote "packed single" "scalar single" precision operations. packed floats represented right-to-left order, with lowest word (right-most) being used scalar operations: explain memory storage reflects this, consider following example. operation
float a[4] 1.0, 2.0, 3.0, _m128 _mm_load_ps(a);
produces same result follows:
_m128 _mm_set_ps(4.0, 3.0, 2.0, 1.0);
other words,
4.0, 3.0, 2.0,
where "scalar" element 1.0. Some intrinsics "composites" because they require more than instruction implement them. should familiar with hardware features provided Streaming SIMD Extensions, Streaming SIMD Extensions technology when writing programs with intrinsics. Keep following three important issues mind:
Certain intrinsics, such _mm_loadr_ps _mm_cmpgt_ss, directly supported instruction set. While these intrinsics convenient programming aids, mindful their implementation cost. Data loaded stored _m128 objects must generally 16-byte-aligned. Some intrinsics require that their argument immediates, that constant integers (literals), nature instruction. result arithmetic operations acting (Not Number) arguments undefined. Therefore, floating-point operations using arguments will match expected behavior corresponding assembly instructions.
more detailed description each intrinsic additional information related usage, refer Intel C/C++ Compiler User's Guide With Support Streaming SIMD Extensions
(Order Number 718195-2001). Refer Appendix Compiler Intrinsics Functional Equivalents more information using intrinsics.
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INSTRUCTION REFERENCE
3.1.4.
Flags Affected
"Flags Affected" section lists flags EFLAGS register that affected instruction. When flag cleared, equal when set, equal arithmetic logical instructions usually assign values status flags uniform manner (see Appendix EFLAGS Cross-Reference, IA-32 Intel Architecture Software Developer's Manual, Volume Non-conventional assignments described "Operation" section. values flags listed undefined changed instruction indeterminate manner. Flags that listed unchanged instruction.
BitBase
BitBase
BitBase
BitOffset
BitBase
BitBase BitOffset
BitBase
Figure 3-2. Memory Indexing
3.1.5.
Flags Affected
floating-point instructions have "FPU Flags Affected" section that describes each instruction affect four condition code flags status word.
3.1.6.
Protected Mode Exceptions
"Protected Mode Exceptions" section lists exceptions that occur when instruction executed protected mode reasons exceptions. Each exception given mnemonic that consists pound sign followed letters optional error code parentheses. example, #GP(0) denotes general protection exception with error code Table associates each two-letter mnemonic with corresponding interrupt vector number exception name. Chapter Interrupt Exception Handling, IA-32 Intel Architecture Software Developer's Manual, Volume detailed description exceptions. Application programmers should consult documentation provided with their operating systems determine actions taken when exceptions occur.
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INSTRUCTION REFERENCE
3.1.7.
Real-Address Mode Exceptions
"Real-Address Mode Exceptions" section lists exceptions that occur when instruction executed real-address mode.
Table 3-2. Exception Mnemonics, Names, Vector Numbers
Vector Mnemonic Divide Error Debug Breakpoint Overflow BOUND Range Exceeded Invalid Opcode (Undefined Opcode) Device Available Math Coprocessor) Double Fault Invalid Segment Present Stack Segment Fault General Protection Page Fault Floating-Point Error (Math Fault) Alignment Check Machine Check SIMD Floating-Point Numeric Error Name Source IDIV instructions. code data reference. instruction. INTO instruction. BOUND instruction. instruction reserved opcode.1 Floating-point WAIT/FWAIT instruction. instruction that generate exception, NMI, INTR. Task switch access. Loading segment registers accessing system segments. Stack operations register loads. memory reference other protection checks. memory reference. Floating-point WAIT/FWAIT instruction. data reference memory.2 Model dependent.3 Streaming SIMD Extensions.4
NOTES: instruction introduced Pentium® processor. This exception introduced Intel486processor. This exception introduced Pentium® processor enhanced Pentium processor. This exception introduced Pentium® processor.
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INSTRUCTION REFERENCE
3.1.8.
Virtual-8086 Mode Exceptions
"Virtual-8086 Mode Exceptions" section lists exceptions that occur when instruction executed virtual-8086 mode.
3.1.9.
Floating-Point Exceptions
"Floating-Point Exceptions" section lists additional exceptions that occur when floating-point instruction executed mode. these exception conditions result floating-point error exception (#MF, vector number being generated. Table associates each one- two-letter mnemonic with corresponding exception name. "Floating-Point Exception Conditions" Chapter IA-32 Intel Architecture Software Developer's Manual, Volume detailed description these exceptions.
Table 3-3. Floating-Point Exception Mnemonics Names
Vector Mnemonic Name Floating-point invalid operation: Stack overflow underflow Invalid arithmetic operation Floating-point divide-by-zero Floating-point denormalized operation Floating-point numeric overflow Floating-point numeric underflow Floating-point inexact result (precision) Source stack overflow underflow Invalid arithmetic operation divide-by-zero Attempting operate denormal number numeric overflow numeric underflow Inexact result (precision)
3.1.10. SIMD Floating-Point Exceptions
"SIMD Floating-Point Exceptions" section lists additional exceptions that occur when Streaming SIMD Extensions Streaming SIMD Extension floating-point instruction executed. these exception conditions result SIMD floating-point error exception (#XF, vector number being generated. Table associates each one-or two-letter mnemonic with corresponding exception name. detailed description these exceptions, refer "Streaming SIMD Extensions Streaming SIMD Extension Exceptions", Chatper IA-32 Intel Architecture Software Developer's Manual, Volume
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INSTRUCTION REFERENCE
Table 3-4. SIMD Floating-Point Exception Mnemonics Names
Vector
Mnemonic
Name Invalid opcode Invalid opcode
Source Memory access Refer Note Table Refer Note Table Memory access Refer Note Memory access Refer Note Refer Note Refer Note Refer Note Refer Note Refer Note Refer Note
Device available Stack exception General protection Page fault Alignment check Invalid operation Divide-by-zero Denormalized operand Numeric overflow Numeric underflow Inexact result
Note 1:These system exceptions. Table lists causes Interrupt Interrupt with Streaming SIMD Extensions. Note 2:Executing Streaming SIMD Extension with misaligned 128-bit memory reference generates general protection exception; 128-bit reference within stack segment, which aligned 16byte boundary will also generate fault, stack exception (SS). However, MOVUPS instruction, which performs unaligned 128-bit load store, will generate exception data that aligned 16-byte boundary. Note 3:This type alignment check done operands which less than 128-bits size: 32-bit scalar single 16-bit/32-bit/64-bit integer MMXtechnology; exception MOVUPS instruction, which performs 128-bit unaligned load store, also covered this alignment check. There three conditions that must true enable interrupt generation. Note 4:Invalid, Divide-by-zero Denormal exceptions pre-computation exceptions, i.e., they detected before arithmetic operation occurs. Note 5:Underflow, Overflow Precision exceptions post-computation exceptions.
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INSTRUCTION REFERENCE
Table 3-5. Streaming SIMD Extensions Faults (Interrupts
CR0.EM CR0.TS CR4.OSFXSR CPUID.XMM Exception Interrupt Interrupt Interrupt Interrupt
3.2.
INSTRUCTION REFERENCE
remainder this chapter provides detailed descriptions each Intel Architecture instructions.
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INSTRUCTION REFERENCE
AAA-ASCII Adjust After Addition
Opcode Instruction Description ASCII adjust after addition
Description Adjusts unpacked values create unpacked result. register implied source destination operand this instruction. instruction only useful when follows instruction that adds (binary addition) unpacked values stores byte result register. instruction then adjusts contents register contain correct 1-digit unpacked result. addition produces decimal carry, register incremented flags set. there decimal carry, flags cleared register unchanged. either case, bits through register cleared Operation
((AL 0FH) THEN ELSE 0FH;
Flags Affected flags adjustment results decimal carry; otherwise they cleared flags undefined. Exceptions (All Operating Modes) None.
3-16
INSTRUCTION REFERENCE
AAD-ASCII Adjust Before Division
Opcode Instruction mnemonic) Description ASCII adjust before division Adjust before division number base imm8
Description Adjusts unpacked digits (the least-significant digit register mostsignificant digit register) that division operation performed result will yield correct unpacked value. instruction only useful when precedes instruction that divides (binary division) adjusted value register unpacked value. instruction sets value register AH)), then clears register 00H. value register then equal binary equivalent original unpacked two-digit (base number registers generalized version this instruction allows adjustment unpacked digits number base (see "Operation" section below), setting imm8 byte selected number base (for example, octal, decimal, base numbers). mnemonic interpreted assemblers mean adjust ASCII (base values. adjust values another number base, instruction must hand coded machine code imm8). Operation
tempAL tempAH (tempAL (tempAH imm8)) FFH; imm8 mnemonic
immediate value (imm8) taken from second byte instruction. Flags Affected flags according result; flags undefined. Exceptions (All Operating Modes) None.
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INSTRUCTION REFERENCE
AAM-ASCII Adjust After Multiply
Opcode Instruction mnemonic) Description ASCII adjust after multiply Adjust after multiply number base imm8
Description Adjusts result multiplication unpacked values create pair unpacked (base values. register implied source destination operand this instruction. instruction only useful when follows instruction that multiplies (binary multiplication) unpacked values stores word result register. instruction then adjusts contents register contain correct 2-digit unpacked (base result. generalized version this instruction allows adjustment contents create unpacked digits number base (see "Operation" section below). Here, imm8 byte selected number base (for example, octal, decimal, base numbers). mnemonic interpreted assemblers mean adjust ASCII (base values. adjust values another number base, instruction must hand coded machine code imm8). Operation
tempAL tempAL imm8; imm8 mnemonic tempAL imm8;
immediate value (imm8) taken from second byte instruction. Flags Affected flags according result. flags undefined. Exceptions (All Operating Modes) None with default immediate value 0AH. however, immediate value used, will cause (divide error) exception.
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INSTRUCTION REFERENCE
AAS-ASCII Adjust After Subtraction
Opcode Instruction Description ASCII adjust after subtraction
Description Adjusts result subtraction unpacked values create unpacked result. register implied source destination operand this instruction. instruction only useful when follows instruction that subtracts (binary subtraction) unpacked value from another stores byte result register. instruction then adjusts contents register contain correct 1-digit unpacked result. subtraction produced decimal carry, register decremented flags set. decimal carry occurred, flags cleared, register unchanged. either case, register left with nibble Operation
((AL 0FH) THEN ELSE 0FH;
Flags Affected flags there decimal borrow; otherwise, they cleared flags undefined. Exceptions (All Operating Modes) None.
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INSTRUCTION REFERENCE
ADC-Add with Carry
Opcode Instruction AL,imm8 AX,imm16 EAX,imm32 r/m8,imm8 r/m16,imm16 r/m32,imm32 r/m16,imm8 r/m32,imm8 r/m8,r8 r/m16,r16 r/m32,r32 r8,r/m8 r16,r/m16 r32,r/m32 Description with carry imm8 with carry imm16 with carry imm32 with carry imm8 r/m8 with carry imm16 r/m16 with imm32 r/m32 with sign-extended imm8 r/m16 with sign-extended imm8 into r/m32 with carry byte register r/m8 with carry r/m16 with r/m32 with carry r/m8 byte register with carry r/m16 with r/m32
Description Adds destination operand (first operand), source operand (second operand), carry (CF) flag stores result destination operand. destination operand register memory location; source operand immediate, register, memory location. (However, memory operands cannot used instruction.) state flag represents carry from previous addition. When immediate value used operand, sign-extended length destination operand format. instruction does distinguish between signed unsigned operands. Instead, processor evaluates result both data types sets flags indicate carry signed unsigned result, respectively. flag indicates sign signed result. instruction usually executed part multibyte multiword addition which instruction followed instruction. Operation
DEST DEST
Flags Affected flags according result.
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INSTRUCTION REFERENCE
ADC-Add with Carry (Continued)
Protected Mode Exceptions #GP(0) destination located non-writable segment. memory operand effective address outside segment limit. register used access memory contains null segment selector. #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made while current privilege level
Real-Address Mode Exceptions memory operand effective address outside segment limit. memory operand effective address outside segment limit.
Virtual-8086 Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made.
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INSTRUCTION REFERENCE
ADD-Add
Opcode Instruction AL,imm8 AX,imm16 EAX,imm32 r/m8,imm8 r/m16,imm16 r/m32,imm32 r/m16,imm8 r/m32,imm8 r/m8,r8 r/m16,r16 r/m32,r32 r8,r/m8 r16,r/m16 r32,r/m32 Description imm8 imm16 imm32 imm8 r/m8 imm16 r/m16 imm32 r/m32 sign-extended imm8 r/m16 sign-extended imm8 r/m32 r/m8 r/m16 r/m32 r/m8 r/m16 r/m32
Description Adds first operand (destination operand) second operand (source operand) stores result destination operand. destination operand register memory location; source operand immediate, register, memory location. (However, memory operands cannot used instruction.) When immediate value used operand, sign-extended length destination operand format. instruction does distinguish between signed unsigned operands. Instead, processor evaluates result both data types sets flags indicate carry signed unsigned result, respectively. flag indicates sign signed result. Operation
DEST DEST SRC;
Flags Affected flags according result. Protected Mode Exceptions #GP(0) destination located non-writable segment. memory operand effective address outside segment limit. register used access memory contains null segment selector.
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INSTRUCTION REFERENCE
ADD-Add (Continued)
#SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made while current privilege level
Real-Address Mode Exceptions memory operand effective address outside segment limit. memory operand effective address outside segment limit.
Virtual-8086 Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made.
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INSTRUCTION REFERENCE
ADDPD-Packed Double-Precision Floating-Point
Opcode Instruction ADDPD xmm1, xmm2/m128 Description packed double-precision floating-point values from xmm2/m128 xmm1.
Description Performs SIMD packed double-precision floating-point values from source operand (second operand) destination operand (first operand), stores packed double-precision floating-point results destination operand. source operand register 128-bit memory location. destination operand register. Figure 11-3 IA-32 Intel Architecture Software Developer's Manual, Volume illustration SIMD double-precision floating-point operation. Operation
DEST[63-0] DEST[63-0] SRC[63-0]; DEST[127-64] DEST[127-64] SRC[127-64];
Intel C/C++ Compiler Intrinsic Equivalent
ADDPD _m128d _mm_add_pd (m128d m128d
SIMD Floating-Point Exceptions Overflow, Underflow, Invalid, Precision, Denormal. Protected Mode Exceptions #GP(0) illegal memory operand effective address segments memory operand aligned 16-byte boundary, regardless segment #SS(0) #PF(fault-code) illegal address segment; page fault; set. unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR
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INSTRUCTION REFERENCE
ADDPD-Packed Double-Precision Floating-Point (Continued)
CPUID feature flag SSE2 Real-Address Mode Exceptions #GP(0) Interrupt memory operand aligned 16-byte boundary, regardless segment part operand lies outside effective address space from 0FFFFH unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR CPUID feature flag SSE2 Virtual-8086 Mode Exceptions Same exceptions Real Address Mode #PF(fault-code) page fault;
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INSTRUCTION REFERENCE
ADDPS-Packed Single-Precision Floating-Point
Opcode Instruction ADDPS xmm1, xmm2/m128 Description packed single-precision floating-point values from xmm2/m128 xmm1.
Description Performs SIMD four packed single-precision floating-point values from source operand (second operand) destination operand (first operand), stores packed single-precision floating-point results destination operand. source operand register 128-bit memory location. destination operand register. Figure 10-5 IA-32 Intel Architecture Software Developer's Manual, Volume illustration SIMD single-precision floating-point operation. Operation
DEST[31-0] DEST[31-0] SRC[31-0]; DEST[63-32] DEST[63-32] SRC[63-32]; DEST[95-64] DEST[95-64] SRC[95-64]; DEST[127-96] DEST[127-96] SRC[127-96];
Intel C/C++ Compiler Intrinsic Equivalent
ADDPS _m128 _mm_add_ps(_m128 _m128
SIMD Floating-Point Exceptions Overflow, Underflow, Invalid, Precision, Denormal. Protected Mode Exceptions #GP(0) illegal memory operand effective address segments memory operand aligned 16-byte boundary, regardless segment #SS(0) #PF(fault-code) illegal address segment; page fault; set. unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT
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INSTRUCTION REFERENCE
ADDPS-Packed Single-Precision Floating-Point (Continued)
set. OSFXSR CPUID feature flag Real-Address Mode Exceptions #GP(0) Interrupt memory operand aligned 16-byte boundary, regardless segment part operand lies outside effective address space from 0FFFFH unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR CPUID feature flag Virtual-8086 Mode Exceptions Same exceptions Real Address Mode #PF(fault-code) page fault;
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INSTRUCTION REFERENCE
ADDSD-Scalar Double-Precision Floating-Point
Opcode Instruction ADDSD xmm1, xmm2/m64 Description double-precision floating-point value from xmm2/m64 xmm1.
Description Adds double-precision floating-point values from source operand (second operand) destination operand (first operand), stores double-precision floating-point result destination operand. source operand register 64-bit memory location. destination operand register. high quadword destination operand remains unchanged. Figure 11-4 IA-32 Intel Architecture Software Developer's Manual, Volume illustration scalar double-precision floating-point operation. Operation
DEST[63-0] DEST[63-0] SRC[63-0]; DEST[127-64] remains unchanged
Intel C/C++ Compiler Intrinsic Equivalent
ADDSD _m128d _mm_add_sd (m128d m128d
SIMD Floating-Point Exceptions Overflow, Underflow, Invalid, Precision, Denormal. Protected Mode Exceptions #GP(0) #SS(0) #PF(fault-code) illegal memory operand effective address segments. illegal address segment. page fault. set. unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR CPUID feature flag SSE2 unaligned memory reference current privilege level
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INSTRUCTION REFERENCE
ADDSD-Scalar Double-Precision Floating-Point (Continued)
Real-Address Mode Exceptions Interrupt part operand lies outside effective address space from 0FFFFH. unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR CPUID feature flag SSE2 Virtual-8086 Mode Exceptions Same exceptions Real Address Mode #PF(fault-code) page fault; unaligned memory reference current privilege level
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INSTRUCTION REFERENCE
ADDSS-Scalar Single-Precision Floating-Point
Opcode Instruction ADDSS xmm1, xmm2/m32 Description single-precision floating-point value from xmm2/m32 xmm1.
Description Adds single-precision floating-point values from source operand (second operand) destination operand (first operand), stores single-precision floating-point result destination operand. source operand register 32-bit memory location. destination operand register. three high-order doublewords destination operand remain unchanged. Figure 10-6 IA-32 Intel Architecture Software Developer's Manual, Volume illustration scalar single-precision floating-point operation. Operation
DEST[31-0] DEST[31-0] SRC[31-0]; DEST[127-32] remain unchanged
Intel C/C++ Compiler Intrinsic Equivalent
ADDSS _m128 _mm_add_ss(_m128 _m128
SIMD Floating-Point Exceptions Overflow, Underflow, Invalid, Precision, Denormal. Protected Mode Exceptions #GP(0) #SS(0) #PF(fault-code) illegal memory operand effective address segments. illegal address segment. page fault. set. unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR CPUID feature flag
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INSTRUCTION REFERENCE
ADDSS-Scalar Single-Precision Floating-Point (Continued)
unaligned memory reference current privilege level
Real-Address Mode Exceptions Interrupt part operand lies outside effective address space from 0FFFFH. unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR CPUID feature flag Virtual-8086 Mode Exceptions Same exceptions Real Address Mode #PF(fault-code) page fault; unaligned memory reference current privilege level
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INSTRUCTION REFERENCE
AND-Logical
Opcode Instruction AL,imm8 AX,imm16 EAX,imm32 r/m8,imm8 r/m16,imm16 r/m32,imm32 r/m16,imm8 r/m32,imm8 r/m8,r8 r/m16,r16 r/m32,r32 r8,r/m8 r16,r/m16 r32,r/m32 Description imm8 imm16 imm32 r/m8 imm8 r/m16 imm16 r/m32 imm32 r/m16 imm8 (sign-extended) r/m32 imm8 (sign-extended) r/m8 r/m16 r/m32 r/m8 r/m16 r/m32
Description Performs bitwise operation destination (first) source (second) operands stores result destination operand location. source operand immediate, register, memory location; destination operand register memory location. (However, memory operands cannot used instruction.) Each result both corresponding bits first second operands otherwise, Operation
DEST DEST SRC;
Flags Affected flags cleared; flags according result. state flag undefined. Protected Mode Exceptions #GP(0) destination operand points nonwritable segment. memory operand effective address outside segment limit. register contains null segment selector. #SS(0) #PF(fault-code) memory operand effective address outside segment limit. page fault occurs.
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INSTRUCTION REFERENCE
AND-Logical (Continued)
#AC(0) alignment checking enabled unaligned memory reference made while current privilege level
Real-Address Mode Exceptions memory operand effective address outside segment limit. memory operand effective address outside segment limit.
Virtual-8086 Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made.
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INSTRUCTION REFERENCE
ANDPD-Bitwise Logical Packed Double-Precision Floating-Point Values
Opcode Instruction ANDPD xmm1, xmm2/m128 Description Bitwise logical xmm2/m128 xmm1.
Description Performs bitwise logical packed double-precision floating-point values source operand (second operand) destination operand (first operand), stores result destination operand. source operand register 128-bit memory location. destination operand register. Operation
DEST[127-0] DEST[127-0] BitwiseAND SRC[127-0];
Intel C/C++ Compiler Intrinsic Equivalent
ANDPD _m128d _mm_and_pd(_m128d _m128d
SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) illegal memory operand effective address segments memory operand aligned 16-byte boundary, regardless segment #SS(0) #PF(fault-code) illegal address segment; page fault; set. unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR CPUID feature flag SSE2
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INSTRUCTION REFERENCE
ANDPD-Bitwise Logical Packed Double-Precision Floating-Point Values (Continued)
Real-Address Mode Exceptions #GP(0) Interrupt memory operand aligned 16-byte boundary, regardless segment part operand lies outside effective address space from 0FFFFH unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR CPUID feature flag SSE2 Virtual-8086 Mode Exceptions Same exceptions Real Address Mode #PF(fault-code) page fault;
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INSTRUCTION REFERENCE
ANDPS-Bitwise Logical Packed Single-Precision Floating-Point Values
Opcode Instruction ANDPS xmm1, xmm2/m128 Description Bitwise logical xmm2/m128 xmm1.
Description Performs bitwise logical four packed single-precision floating-point values source operand (second operand) destination operand (first operand), stores result destination operand. source operand register 128-bit memory location. destination operand register. Operation
DEST[127-0] DEST[127-0] BitwiseAND SRC[127-0];
Intel C/C++ Compiler Intrinsic Equivalent
ANDPS _m128 _mm_and_ps(_m128 _m128
SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) illegal memory operand effective address segments memory operand aligned 16-byte boundary, regardless segment #SS(0) #PF(fault-code) illegal address segment; page fault; set. unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR CPUID feature flag
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INSTRUCTION REFERENCE
ANDPS-Bitwise Logical Packed Single-Precision Floating-Point Values (Continued)
Real-Address Mode Exceptions #GP(0) Interrupt memory operand aligned 16-byte boundary, regardless segment part operand lies outside effective address space from 0FFFFH unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR CPUID feature flag Virtual-8086 Mode Exceptions Same exceptions Real Address Mode #PF(fault-code) page fault;
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INSTRUCTION REFERENCE
ANDNPD-Bitwise Logical Packed Double-Precision Floating-Point Values
Opcode Instruction ADDPD xmm1, xmm2/m128 Description Bitwise logical xmm2/m128 xmm1.
Description Inverts bits packed double-precision floating-point values destination operand (first operand), performs bitwise logical packed double-precision floating-point values source operand (second operand) temporary inverted result, stores result destination operand. source operand register 128-bit memory location. destination operand register. Operation
DEST[127-0] (NOT(DEST[127-0])) BitwiseAND (SRC[127-0]);
Intel C/C++ Compiler Intrinsic Equivalent
ANDNPD _m128d _mm_andnot_pd(_m128d _m128d
SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) illegal memory operand effective address segments memory operand aligned 16-byte boundary, regardless segment #SS(0) #PF(fault-code) illegal address segment; page fault; set. unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR
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INSTRUCTION REFERENCE
ANDNPD-Bitwise Logical Packed Double-Precision Floating-Point Values (Continued)
CPUID feature flag SSE2 Real-Address Mode Exceptions #GP(0) Interrupt memory operand aligned 16-byte boundary, regardless segment part operand lies outside effective address space from 0FFFFH unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR CPUID feature flag SSE2 Virtual-8086 Mode Exceptions Same exceptions Real Address Mode #PF(fault-code) page fault;
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INSTRUCTION REFERENCE
ANDNPS-Bit-wise Logical Single-FP
Opcode Instruction ANDNPS xmm1, xmm2/m128 Description Bitwise logical xmm2/m128 xmm1.
Description Inverts bits four packed single-precision floating-point values destination operand (first operand), performs bitwise logical four packed single-precision floating-point values source operand (second operand) temporary inverted result, stores result destination operand. source operand register 128-bit memory location. destination operand register. Operation
DEST[127-0] (NOT(DEST[127-0])) BitwiseAND (SRC[127-0]);
Intel C/C++ Compiler Intrinsic Equivalent
ANDNPS _m128 _mm_andnot_ps(_m128 _m128
SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) illegal memory operand effective address segments memory operand aligned 16-byte boundary, regardless segment #SS(0) #PF(fault-code) illegal address segment; page fault; set. unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR CPUID feature flag
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INSTRUCTION REFERENCE
ANDNPS-Bitwise Logical Packed Single-Precision Floating-Point Values (Continued)
Real-Address Mode Exceptions #GP(0) Interrupt memory operand aligned 16-byte boundary, regardless segment part operand lies outside effective address space from 0FFFFH unmasked SIMD floating-point exception OSXMMEXCPT unmasked SIMD floating-point exception OSXMMEXCPT set. OSFXSR CPUID feature flag Virtual-8086 Mode Exceptions Same exceptions Real Address Mode #PF(fault-code) page fault;
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INSTRUCTION REFERENCE
ARPL-Adjust Field Segment Selector
Opcode Instruction ARPL r/m16,r16 Description Adjust r/m16 less than
Description Compares fields segment selectors. first operand (the destination operand) contains segment selector second operand (source operand) contains other. (The field located bits each operand.) field destination operand less than field source operand, flag field destination operand increased match that source operand. Otherwise, flag cleared change made destination operand. (The destination operand word register memory location; source operand must word register.) ARPL instruction provided operating-system procedures (however, also used applications). generally used adjust segment selector that been passed operating system application program match privilege level application program. Here segment selector passed operating system placed destination operand segment selector application program's code segment placed source operand. (The field source operand represents privilege level application program.) Execution ARPL instruction then insures that segment selector received operating system lower (does have higher privilege) than privilege level application program. (The segment selector application program's code segment read from stack following procedure call.) "Checking Caller Access Privileges" Chapter IA-32 Intel Architecture Software Developer's Manual, Volume more information about this instruction. Operation
DEST[RPL) SRC[RPL) THEN DEST[RPL) SRC[RPL); ELSE
Flags Affected flag field destination operand less than that source operand; otherwise, cleared
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INSTRUCTION REFERENCE
ARPL-Adjust Field Segment Selector (Continued)
Protected Mode Exceptions #GP(0) destination located nonwritable segment. memory operand effective address outside segment limit. register used access memory contains null segment selector. #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made while current privilege level
Real-Address Mode Exceptions ARPL instruction recognized real-address mode.
Virtual-8086 Mode Exceptions ARPL instruction recognized virtual-8086 mode.
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INSTRUCTION REFERENCE
BOUND-Check Array Index Against Bounds
Opcode Instruction BOUND r16, m16&16 BOUND r32, m32&32 Description Check (array index) within bounds specified m16&16 Check (array index) within bounds specified m16&16
Description Determines first operand (array index) within bounds array specified second operand (bounds operand). array index signed integer located register. bounds operand memory location that contains pair signed doubleword-integers (when operand-size attribute pair signed word-integers (when operand-size attribute 16). first doubleword word) lower bound array second doubleword word) upper bound array. array index must greater than equal lower bound less than equal upper bound plus operand size bytes. index within bounds, BOUND range exceeded exception (#BR) signaled. (When this exception generated, saved return instruction pointer points BOUND instruction.) bounds limit data structure (two words doublewords containing lower upper limits array) usually placed just before array itself, making limits addressable constant offset from beginning array. Because address array already will present register, this practice avoids extra cycles obtain effective address array bounds. Operation
(ArrayIndex LowerBound ArrayIndex (UppderBound OperandSize/8])) Below lower bound above upper bound THEN #BR;
Flags Affected None. Protected Mode Exceptions #GP(0) bounds test fails. second operand memory location. memory operand effective address outside segment limit. register contains null segment selector.
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INSTRUCTION REFERENCE
BOUND-Check Array Index Against Bounds (Continued)
#SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made while current privilege level
Real-Address Mode Exceptions bounds test fails. second operand memory location. memory operand effective address outside segment limit. memory operand effective address outside segment limit.
Virtual-8086 Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #AC(0) bounds test fails. second operand memory location. memory operand effective address outside segment limit. memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made.
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INSTRUCTION REFERENCE
BSF-Bit Scan Forward
Opcode Instruction r16,r/m16 r32,r/m32 Description scan forward r/m16 scan forward r/m32
Description Searches source operand (second operand) least significant bit). least significant found, index stored destination operand (first operand). source operand register memory location; destination operand register. index unsigned offset from source operand. contents source operand contents destination operand undefined. Operation
THEN DEST undefined; ELSE temp WHILE Bit(SRC, temp) temp temp DEST temp;
Flags Affected flag source operand otherwise, flag cleared. flags undefined. Protected Mode Exceptions #GP(0) memory operand effective address outside segment limit. register contains null segment selector. #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made while current privilege level
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INSTRUCTION REFERENCE
BSF-Bit Scan Forward (Continued)
Real-Address Mode Exceptions memory operand effective address outside segment limit. memory operand effective address outside segment limit.
Virtual-8086 Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made.
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INSTRUCTION REFERENCE
BSR-Bit Scan Reverse
Opcode Instruction r16,r/m16 r32,r/m32 Description scan reverse r/m16 scan reverse r/m32
Description Searches source operand (second operand) most significant bit). most significant found, index stored destination operand (first operand). source operand register memory location; destination operand register. index unsigned offset from source operand. contents source operand contents destination operand undefined. Operation
THEN DEST undefined; ELSE temp OperandSize WHILE Bit(SRC, temp) temp temp DEST temp;
Flags Affected flag source operand otherwise, flag cleared. flags undefined. Protected Mode Exceptions #GP(0) memory operand effective address outside segment limit. register contains null segment selector. #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made while current privilege level
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INSTRUCTION REFERENCE
BSR-Bit Scan Reverse (Continued)
Real-Address Mode Exceptions memory operand effective address outside segment limit. memory operand effective address outside segment limit.
Virtual-8086 Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made.
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INSTRUCTION REFERENCE
BSWAP-Byte Swap
Opcode C8+rd Instruction BSWAP Description Reverses byte order 32-bit register.
Description Reverses byte order 32-bit (destination) register: bits through swapped with bits through bits through swapped with bits through This instruction provided converting little-endian values big-endian format vice versa. swap bytes word value (16-bit register), XCHG instruction. When BSWAP instruction references 16-bit register, result undefined. Intel Architecture Compatibility BSWAP instruction supported Intel Architecture processors earlier than Intel486 processor family. compatibility with this instruction, include functionally equivalent code execution Intel processors earlier than Intel486 processor family. Operation
TEMP DEST DEST[7.0] TEMP(31.24] DEST[15.8] TEMP(23.16] DEST[23.16] TEMP(15.8] DEST[31.24] TEMP(7.0]
Flags Affected None. Exceptions (All Operating Modes) None.
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INSTRUCTION REFERENCE
BT-Bit Test
Opcode Instruction r/m16,r16 r/m32,r32 r/m16,imm8 r/m32,imm8 Description Store selected flag Store selected flag Store selected flag Store selected flag
Description Selects string (specified with first operand, called base) bitposition designated offset operand (second operand) stores value flag. base operand register memory location; offset operand register immediate value. base operand specifies register, instruction takes modulo (depending register size) offset operand, allowing position selected 32-bit register, respectively (see Figure 3-1). base operand specifies memory location, represents address byte memory that contains base (bit specified byte) string (see Figure 3-2). offset operand then selects position within range -231 register offset immediate offset. Some assemblers support immediate offsets larger than using immediate offset field combination with displacement field memory operand. this case, loworder bits 16-bit operands, 32-bit operands) immediate offset stored immediate offset field, high-order bits shifted combined with byte displacement addressing mode assembler. processor will ignore high order bits they zero. When accessing memory, processor access bytes starting from memory address 32-bit operand size, using following relationship:
Effective Address (BitOffset 32))
access bytes starting from memory address 16-bit operand, using this relationship:
Effective Address (BitOffset 16))
even when only single byte needs accessed reach given bit. When using this addressing mechanism, software should avoid referencing areas memory close address space holes. particular, should avoid references memory-mapped registers. Instead, software should instructions load from store these addresses, register form these instructions manipulate data. Operation
Bit(BitBase, BitOffset)
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INSTRUCTION REFERENCE
BT-Bit Test (Continued)
Flags Affected flag contains value selected bit. flags undefined. Protected Mode Exceptions #GP(0) memory operand effective address outside segment limit. register contains null segment selector. #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made while current privilege level
Real-Address Mode Exceptions memory operand effective address outside segment limit. memory operand effective address outside segment limit.
Virtual-8086 Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made.
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INSTRUCTION REFERENCE
BTC-Bit Test Complement
Opcode Instruction r/m16,r16 r/m32,r32 r/m16,imm8 r/m32,imm8 Description Store selected flag complement Store selected flag complement Store selected flag complement Store selected flag complement
Description Selects string (specified with first operand, called base) bitposition designated offset operand (second operand), stores value flag, complements selected string. base operand register memory location; offset operand register immediate value. base operand specifies register, instruction takes modulo (depending register size) offset operand, allowing position selected 32-bit register, respectively (see Figure 3-1). base operand specifies memory location, represents address byte memory that contains base (bit specified byte) string (see Figure 3-2). offset operand then selects position within range -231 register offset immediate offset. Some assemblers support immediate offsets larger than using immediate offset field combination with displacement field memory operand. "BT-Bit Test" this chapter more information this addressing mechanism. Operation
Bit(BitBase, BitOffset) Bit(BitBase, BitOffset) Bit(BitBase, BitOffset);
Flags Affected flag contains value selected before complemented. flags undefined. Protected Mode Exceptions #GP(0) destination operand points nonwritable segment. memory operand effective address outside segment limit. register contains null segment selector. #SS(0) #PF(fault-code) memory operand effective address outside segment limit. page fault occurs.
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INSTRUCTION REFERENCE
BTC-Bit Test Complement (Continued)
#AC(0) alignment checking enabled unaligned memory reference made while current privilege level
Real-Address Mode Exceptions memory operand effective address outside segment limit. memory operand effective address outside segment limit.
Virtual-8086 Mode Exceptions #GP(0) #SS(0) #PF(fault-code) #AC(0) memory operand effective address outside segment limit. memory operand effective address outside segment limit. page fault occurs. alignment checking enabled unaligned memory reference made.
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INSTRUCTION REFERENCE
BTR-Bit Te
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