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SN74LS00DRE4 Texas Instruments Quad 2-input positive-NAND gates 14-SOIC 0 to 70
SN74LS00NSR Texas Instruments Quad 2-input positive-NAND gates 14-SO 0 to 70
SN74LS00PSR Texas Instruments Quad 2-input positive-NAND gates 8-SO 0 to 70
SN74LS00NSRG4 Texas Instruments Quad 2-input positive-NAND gates 14-SO 0 to 70
SN74LS00NE4 Texas Instruments Quad 2-input positive-NAND gates 14-PDIP 0 to 70
SN74LS00PSRE4 Texas Instruments LS SERIES, QUAD 2-INPUT NAND GATE, PDSO8, GREEN, PLASTIC, SOP-8

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data sheets of 74ls00

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: the closed loop control system. Any one of four operating modes (two for position control and two for velocity control) can be used with DC Brush motors. Please refer to the technical data sheets for the HCTL-1100 for detailed information on the different modes of operation. For more information , -1100 general purpose motion control IC can be used for closed loop position and velocity control of DC Brush , MOTOR CONTROLLER HCTL-1100 ENCODER Figure 1. Closed Loop Position and Velocity Control of DC Hewlett-Packard
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M-024 74LS00 74l500 UF 407 Diode 74ls00 circuit diagram Encoder interface with HCTL-1100 M109 B1 M-015 M-016 M-021 M-003 M-101
Abstract: the closed loop control system. Any one of four operating modes (two for position control and two for velocity control) can be used with DC Brush motors. Please refer to the technical data sheets for the HCTL-1100 for detailed information on the different modes of operation. For more information , -1100 general purpose motion control IC can be used for closed loop position and velocity control of DC Brush , integrated half and full bridges and, from various vendors with special features. A list of some of the Avago Technologies
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of ic 74ls00 datasheet of ic 74ls00 motorola byw 21 bridge rectifier diode u1d ON 74LS00 integrated circuit LOGIC OF 74L500 M-109 DAC08 REF-01 5964-9816E 5965-3476E
Abstract: time, resulting in a loss of data or worse. Figure 1 shows a simple circuit that ensures a clean , addition of a single flip-flop t o delay WE going active until data is valid. Figure 2 illustrates an , iRAM THE 2187 PROVIDES 8K BYTES OF EXTERNAL DATA MEMORY VERY SIMPLE INTERFACE NO ADDRESS LATCHES , FOUR 2186 iRAMs PROVIDE 32K BYTES OF LOCAL STORAGE CLEAN a GENERATED BY ONE TTL PACKAGE (74LS00) ONE TTL PACKAGE (74LS00) DELAYS UNTIL DATA IS VALID THE iRAMs ARE IN UNIVERAL SITE SOCKETS WlTH Intel
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8085 microprocessor opcode sheet intel 8085 opcode 8085 opcode sheet free 8085 microprocessor opcode OPCODE SHEET FOR 8051 MICROCONTROLLER intel 8085 opcode sheet 2186S AP-132 AR-235 IE-3011128211OK
Abstract: consequential or incidental damages. "Typical" parameters which may be provided in TigerJet data sheets and/or , with random logic. The delay of 3 NAND gates generates a short pulse to synchronize the divided DCLK by the D-type F.F. Both devices will have the same rising edge of FSC and DCLK signals which will meet the timing requirement for both GCI and Long-Frame interface. The delay of NAND need to be long enough to generate the PRESET signal to the D-FF. It is recommend to use slower 74LS00. This document TigerJet Network
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MSM7602 TIGER560C TigerJet Network tigerjet 74LS00 clock frequency
Abstract: of Product could cause loss of human life, bodily injury or damage to property, including data loss , specifications, the data sheets and application notes for Product and the precautions and conditions set forth , LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND LOSS OF DATA, AND (2 , maintaining the CMOS low power dissipation. The internal circuit is composed of 3 stages including buffer , and function compatible with 74LS00 Pin Assignment Weight DIP14-P-300-2.54 SOP14-P Toshiba
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TC74HC00AP/AF TC74HC00AP TC74HC00AF TC74HC00A
Abstract: of Product could cause loss of human life, bodily injury or damage to property, including data loss , specifications, the data sheets and application notes for Product and the precautions and conditions set forth , LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND LOSS OF DATA, AND (2 , maintaining the CMOS low power dissipation. The internal circuit is composed of 3 stages including buffer , function compatible with 74LS00 Weight DIP14-P-300-2.54 SOP14-P-300-1.27A Pin Assignment : 0.96 g Toshiba
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Abstract: could cause loss of human life, bodily injury or damage to property, including data loss or corruption , OPPORTUNITIES, BUSINESS INTERRUPTION AND LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED , circuit is composed of 3 stages including buffer output, which provide high noise immunity and stable , propagation delays: tpLH - tpHL Pin and function compatible with 74LS00 Weight SOL14-P-150-1.27 : 0.12 , : Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even Toshiba
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TC74HCT00AFN TC74HCT00A
Abstract: of Product could cause loss of human life, bodily injury or damage to property, including data loss , , this document, the specifications, the data sheets and application notes for Product and the , output voltage levels. The internal circuit is composed of 3 stages including buffer output, which , : tpLH tpHL - · Pin and function compatible with 74LS00 TC74HCT00AFN Pin Assignment , temperature Tstg -65~150 °C DC output voltage Note 1: Exceeding any of the absolute maximum Toshiba
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TC74HCT00AP TC74HCT00AF IC TTL 74LS00 CI 74LS00 74LS00 CMOS IC 74LS00 TC74HCT00AP/AF/AFN
Abstract: limitation, this document, the specifications, the data sheets and application notes for Product and the , PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL , . The internal circuit is composed of 3 stages including buffer output, which provide high noise , : tpLH - tpHL Pin and function compatible with 74LS00 Weight DIP14-P-300-2.54 SOP14-P , ~150 Unit V V V mA mA mA mA mW °C Note 1: Exceeding any of the absolute maximum ratings, even Toshiba
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max1918 TC74HCT00AP/AF
Abstract: of Product could cause loss of human life, bodily injury or damage to property, including data loss , specifications, the data sheets and application notes for Product and the precautions and conditions set forth in , PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL , power dissipation. The internal circuit is composed of 3 stages including buffer output, which provide , operating voltage range: VCC (opr) = 2 to 6 V Pin and function compatible with 74LS00 Weight SOL14-P Toshiba
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TC74HC00AFN
Abstract: could cause loss of human life, bodily injury or damage to property, including data loss or corruption , specifications, the data sheets and application notes for Product and the precautions and conditions set forth in , LSTTL while maintaining the CMOS low power dissipation. The internal circuit is composed of 3 stages , range: VCC (opr) = 2 to 6 V · Pin and function compatible with 74LS00 TC74HC00AFN Pin , )/180 (SOP) mW Storage temperature Tstg -65 to 150 °C Note 1: Exceeding any of the Toshiba
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NAND 74LS00 pin diagram of ic 74ls00 TC74HC00AP/AF/AFN
Abstract: could cause loss of human life, bodily injury or damage to property, including data loss or corruption , OPPORTUNITIES, BUSINESS INTERRUPTION AND LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED , maintaining the CMOS low power dissipation. The internal circuit is composed of 3 stages including buffer , : VCC (opr) = 2 to 6 V Pin and function compatible with 74LS00 Weight DIP14-P-300-2.54 SOP14-P , ) (Note 2)/180 (SOP) -65 to 150 Unit V V V mA mA mA mA mW °C Note 1: Exceeding any of the absolute Toshiba
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logic symbol 74LS00
Abstract: could cause loss of human life, bodily injury or damage to property, including data loss or corruption , OPPORTUNITIES, BUSINESS INTERRUPTION AND LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED , . The internal circuit is composed of 3 stages including buffer output, which provide high noise , compatible with 74LS00 Weight DIP14-P-300-2.54 SOP14-P-300-1.27A : 0.96 g (typ.) : 0.18 g (typ , Storage temperature Tstg â'65~150 °C DC output voltage Note 1: Exceeding any of the Toshiba
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Abstract: sheets of a schematic: Use the Page Up and Page Down keys or use the GoTo, Previous Page, or Next Page , machine readable form without the prior written consent of Innoveda, Inc. The software programs described , 's company without the prior written consent of Innoveda, Inc. The copyright notice appearing above is included to provide statutory protection in the event of unauthorized or unintentional public disclosure. All trademarks and registered trademarks are the property of their respective owners. Contents Innoveda
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CI 74LS148
Abstract: intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only , detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data , to access any of the registers. A0 and A1 steer the input 8-bit data byte to the low- or high-byte , parallel. The contents are then applied to the input of the D/A converter. When WR goes low, data is , which data can be clocked into the input shift register is 10MHz. The timing of the control signals is Burr-Brown
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pin diagram of 74ls00 uv 709 DAC707 DAC708 DAC709 16-BIT DAC707JP/KP DAC708/709
Abstract: of information in TI data books or data sheets is permissible only if reproduction is without , detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data , to access any of the registers. A0 and A1 steer the input 8-bit data byte to the low- or high-byte , parallel. The contents are then applied to the input of the D/A converter. When WR goes low, data is , which data can be clocked into the input shift register is 10MHz. The timing of the control signals is Burr-Brown
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74HTC specification of 74ls00
Abstract: other intellectual property of TI. Reproduction of information in TI data books or data sheets is , detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data , . Refer to Connection Diagram for connection of external op amp to DAC708. D13 Data bit 13 15 ACOM Analog common D12 Data bit 12 16 SJ (DAC709) IOUT (DAC708) Summing junction of , Diagram for connection of external op amp to DAC708. D11 Data bit 11 17 BPO Bipolar offset Burr-Brown
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TTL 74ls00 analog devices ic 74LS00 lead side brazed hermetic op amp 709 DAC708BH DAC707KH
Abstract: other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is , detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data , . Refer to Connection Diagram for connection of external op amp to DAC708. D13 Data bit 13 15 ACOM Analog common D12 Data bit 12 16 SJ (DAC709) IOUT (DAC708) Summing junction of , Diagram for connection of external op amp to DAC708. D11 Data bit 11 17 BPO Bipolar offset Burr-Brown
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709b 7407 connection diagram
Abstract: ) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown , DAC708. Refer to Connection Diagram for connection of external op amp to DAC708. D11 Data bit 11 , Input Over Temperature ns, min ns, max TDW Data valid to end of WR 80 TCW CS valid to end of WR 80 TAW A0, A1, A2 valid to end of WR 80 TWP Write pulse width 80 TDH Data hold after end of , -bit data byte to the low- or high-byte input latch respectively. A2 gates the contents of the two input Burr-Brown
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Abstract: detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data , . Refer to Connection Diagram for connection of external op amp to DAC708. D13 Data bit 13 15 ACOM Analog common D12 Data bit 12 16 SJ (DAC709) IOUT (DAC708) Summing junction of , Diagram for connection of external op amp to DAC708. D11 Data bit 11 17 BPO Bipolar offset , Write pulse width 80 TDH Data hold after end of WR 0 The signals CHIP SELECT (CS), WRITE (WR Burr-Brown
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