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SN74LS90-W Texas Instruments Decade Counter 0-WAFERSALE ri Buy
CD54ACT163H Texas Instruments IC AC SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, UUC16, Counter ri Buy
SN54S163W-00 Texas Instruments IC S SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDFP16, Counter ri Buy

counter MOD 2N

Catalog Datasheet Results Type PDF Document Tags
Abstract: Number of Counter Stages n Count 2n 0 0 13 8192 0 1 10 1024 1 0 8 256 1 1 16 65536 1-800-AVG-SEMI 1-800-AVG-SEMI , binary counter, an integrated oscillator for use with external capacitor and two resistors. a automatic , tho power-on reset is enabled and initializes the counter. With the power already on. an external , with a frequency determined by external RC network. The 16-stage counter devides the oscillator frequency to the extent determined by inputs A and B. With Auto Reset pin set to a *0" the counter circuit ... OCR Scan
datasheet

3 pages,
474.68 Kb

DV4541B 16-Stage Binary Counter datasheet abstract
datasheet frame
Abstract: fR counter block Control block - ON/OFF · PS-ON SW DATASTB CLK - Input register block PD block PD «y - fv counter block MOD - Lock block -LOCK PLL Synthesizer Block Diagram fR counter block: The fR consists of an 11-bit counter and a half divider. Reference frequency fR , radio applications. Features Incorporates an 11 -bit counter for standard frequency, a 10-bit main counter for the comparative frequency and a 7-bit swallow counter. · Low power dissipation in intermittent ... OCR Scan
datasheet

9 pages,
410.84 Kb

HD61945 HD61945MP HD61945MP abstract
datasheet frame
Abstract: to mresidue format use the following: Ar = A 2n mod M The efficiency of the modular multiplier , multiply algorithm. S = Ar Br 2n mod M To remove this extra factor of 2n it is simply a matter of , because multiplication by a non m-residue value will reintroduce the 2-n factor: S = 1 S 2n mod M , process beginning with converting X to m-residue format: ai , bi , mi {0,1} Xr = X 2n mod M , e mod m M = C f mod m Key generation for RSA starts with the selection of two prime numbers which ... Original
datasheet

8 pages,
1550.88 Kb

CF-032305-1 APPLICATIONS OF mod 8 COUNTER altera cyclone 3 slice 7x clock multiplier VPN 3220 AR 8316 ARSA datasheet abstract
datasheet frame
Abstract: PROGRAMMABLE TIMER The MC14541B MC14541B programmable timer consistsof a 16-stage bihary counter, an , reset is enabled and initializes the counter, within the specified Vqd range. With the power already on , will oscillate with a frequency determined by the externaj RC network. The 16-stage counter divides the oscillator frequency (fosc> with the nth stage frequency being fosc/2n. Available Outputs 28, 21 213 or 216 , of Automatic Reset Operation _ . _ Operates as 2n Frequency Divider or Single Transition Timer Q/C ... OCR Scan
datasheet

5 pages,
184.65 Kb

MC14XXXBD MC14XXXBCP MC14XXXBCL MC14541B mc14541 datasheet abstract
datasheet frame
Abstract: base counter On-chip clock generator Programmable wait function Standby function (STOP/HALT) The , TIMER TIME BASE COUNTER PORT with COMPARATOR PORT X1 CG X2 TOUT/P15 Note Not , Memory field (000 to 111) mod Mode field (00 to 10) s Sign extension specification bit (0 , Register DW (16 bits) SP Stack pointer (16 bits) PC Program counter (16 bits) PSW Program , Table 2-8 Number of Clocks. Table 2-7. Number of Clocks for Each Memory Addressing mod 00 mem ... Original
datasheet

76 pages,
476.52 Kb

UPD70320GJ-8 uPD70320-8 uPD70320 PD70320 uPD70320L-8 uPD70108 nec V25 microcontroller IEM-1220 datasheet abstract
datasheet frame
Abstract: Counter Length Acknowledge cycle 4 16 bits Programmable: 1. Nonacknowledge cycle 2. Single acknowledge , buffer length Byte count register End-of-frame interrupt counter DMA status register DMA interrupt enable , Clock, Timer constant register (TCONR) Timer upcounter (TCNT) Counter reset o +N BC* i - +8 \é < -\- N , HD64570 HD64570 (SCA) User's Manual 1 .6 3 MSC1 Registers (1) Addrast CPU Mod- 0 t 1 Register Nam* Mode , 4BH 52H 53H 54H CPU Mod- 2 « 3 2FH 2EM 31H 30H 37H 36H 34H 2DH 23H 22H 25H 24H 27H 29H 28 H 2BH ... OCR Scan
datasheet

40 pages,
883.49 Kb

HD64570F16 bpl lpr 250K3 hitachi c1h HD64570 D64570 HD64570 abstract
datasheet frame
Abstract: clock by 2n where n = 0, 1, .7. Any o f the binary sub-multiples of the counter input clock can be , connector P4. The counter accumulates 2n+l counts (n = 0, 2, .11) at which time the selected output , controllable: Unipolar/Bipolar input range Sleep Mode All Cal Modes · On-board Decimation Counter · Multiple , ) ORDERING INFORMATION: CDB5501 CDB5501 or CDB5503 CDB5503 osc CLKIN « .A Decimation Counter ' 7 CS5501 CS5501 , value of the reference to be accurately trimmed. D ecim ation Counter T he C D B 5501/C 5501/C D B 5503 ... OCR Scan
datasheet

13 pages,
510.02 Kb

CDB5501/CDB5503 CDB5501/CDB5503 abstract
datasheet frame
Abstract: QAM DEMOD/MOD ICs INCORPORATES ALL RF FILTERS INCLUDING Tx ANTI ALIASING DIGITAL LINEAR RF TRANSMITTER , disabling of the respective N counter divider and debiasing of its respective fiN inputs (to a high , reaches a TRI-STATE condition. The R counter and Oscillator functionality does not become disabled until , internal use only Counter Reset4 Notes: 1. Parenthesis data indicates programmable reference divider , selected HIGH (while the #19 and #20 mode bits are set for Fastlock). 4. The Counter Reset mode bits R19 ... OCR Scan
datasheet

6 pages,
200.51 Kb

ISG3300EU ISG3300EU abstract
datasheet frame
Abstract: linearity performance. INTERFACES DIRECTLY WITH QAM DEMOD/MOD ICs INCORPORATES ALL RF FILTERS INCLUDING , powerdown modes result in the disabling of the respective N counter divider and debiasing of its respective , when the charge pump reaches a TRI-STATE condition. The R counter and Oscillator functionality does not , internal use only Counter Reset4 Notes: 1. Parenthesis data indicates programmable reference divider , (while the #19 and #20 mode bits are set for Fastlock). 4. The Counter Reset mode bits R19 and R20 when ... OCR Scan
datasheet

6 pages,
192.92 Kb

ISG3300DS datasheet abstract
datasheet frame
Abstract: linearity performance. · INTERFACES DIRECTLY WITH QAM DEMOD/MOD ICs · BUILT IN RF TRANSMITTER: 50 dB AGC , powerdown modes result in the disabling of the respective N counter divider and debiasing of its respective , when the charge pump reaches a TRI-STATE condition. The R counter and Oscillator functionality does not , internal use only Counter Reset4 Notes: 1. Parenthesis data indicates programmable reference divider , (while the #19 and #20 mode bits are set for Fastlock). 4. The Counter Reset mode bits R19 and R20 when ... OCR Scan
datasheet

6 pages,
196.17 Kb

ISG2000 ISG2000 abstract
datasheet frame

Datasheet Content (non pdf)

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, we must counter the possibility of a double rounding error because what we calculate is actually , A º 0 (mod 2 N-1 ) , B Î [2 N-1 ,2 N ) Ç Z and (A/B) rnd Î [2 N-1 ,2 N ) Ç Z . Let | > 2 e_a-e_b-2N , if s a < s b , and w a/b = | a/b - f | > 2 e_a-e_b-2N+1 ulp in F N = 1 ulp in F 2N , and in Theorem 5 (a), 1/2 N+1 = 1/2 N+1 ulp in F N = 1 ulp in F 2N + 1 , the above can be expressed in the following corollaries of these
www.datasheetarchive.com/files/intel/technologies/itj/q21998/articles/art_3e-v1.htm
([4] explains this). Second, we must counter the possibility of a double rounding error because , where A Î Z Ç F N , A º 0 (mod 2 N-1 ) , B Î [2 N-1 ,2 N ) Ç Z and (A/B) rnd Î [2 = | a/b - f | > 2 e_a-e_b-2N , if s a < s b , and w a/b = | a/b - f N = 1 ulp in F 2N , and in Theorem 5 (a), 1/2 N+1 = 1/2 N+1 ulp in F N = 1 ulp in F 2N + 1 , the above can be expressed in the following corollaries of these two
www.datasheetarchive.com/files/intel/techno~1/itj/q21998/articles/art_3e-v2-vx2.htm
Intel 04/05/1999 26.31 Kb HTM art_3e-v2-vx2.htm
([4] explains this). Second, we must counter the possibility of a double rounding error because , where A Î Z Ç F N , A º 0 (mod 2 N-1 ) , B Î [2 N-1 ,2 N ) Ç Z and (A/B) rnd Î [2 = | a/b - f | > 2 e_a-e_b-2N , if s a < s b , and w a/b = | a/b - f N = 1 ulp in F 2N , and in Theorem 5 (a), 1/2 N+1 = 1/2 N+1 ulp in F N = 1 ulp in F 2N + 1 , the above can be expressed in the following corollaries of these two
www.datasheetarchive.com/files/intel/techno~1/itj/q21998/articles/art_3e-v2.htm
Intel 02/02/1999 26.31 Kb HTM art_3e-v2.htm
([4] explains this). Second, we must counter the possibility of a double rounding error because , where A Î Z Ç F N , A º 0 (mod 2 N-1 ) , B Î [2 N-1 ,2 N ) Ç Z and (A/B) rnd Î [2 = | a/b - f | > 2 e_a-e_b-2N , if s a < s b , and w a/b = | a/b - f N = 1 ulp in F 2N , and in Theorem 5 (a), 1/2 N+1 = 1/2 N+1 ulp in F N = 1 ulp in F 2N + 1 , the above can be expressed in the following corollaries of these two
www.datasheetarchive.com/files/intel/techno~1/itj/q21998/articles/art_3e.htm
Intel 31/10/1998 26.31 Kb HTM art_3e.htm
([4] explains this). Second, we must counter the possibility of a double rounding error because , where A Î Z Ç F N , A º 0 (mod 2 N-1 ) , B Î [2 N-1 ,2 N ) Ç Z and (A/B) rnd Î [2 = | a/b - f | > 2 e_a-e_b-2N , if s a < s b , and w a/b = | a/b - f N = 1 ulp in F 2N , and in Theorem 5 (a), 1/2 N+1 = 1/2 N+1 ulp in F N = 1 ulp in F 2N + 1 , the above can be expressed in the following corollaries of these two
www.datasheetarchive.com/files/intel/techno~1/itj/q21998/articles/art_3e-v1.htm
Intel 02/02/1999 26.31 Kb HTM art_3e-v1.htm
No abstract text available
www.datasheetarchive.com/download/6716472-207788ZD/lbk.tar.gz
Xilinx 30/08/2001 371.21 Kb GZ lbk.tar.gz
No abstract text available
www.datasheetarchive.com/download/89106023-207735ZD/lblox.zip (lblox.pdf)
Xilinx 28/03/2001 483.48 Kb ZIP lblox.zip
No abstract text available
www.datasheetarchive.com/download/71516031-207734ZD/lblox.tar.gz
Xilinx 28/03/2001 482.47 Kb GZ lblox.tar.gz
No abstract text available
www.datasheetarchive.com/download/64498353-207789ZD/lbk.zip (lbk.pdf)
Xilinx 29/08/2001 372.01 Kb ZIP lbk.zip
TRIACs directly n 8-bit Timer/Counter with 7-bit programmable prescaler n 8-bit Auto-reload Timer These compact low-cost devices feature a Timer comprising an 8-bit counter and a 7-bit program- mable Program Counter register (PC register). 1.3.2.1 Program Memory Protection The Program Memory in OTP or used to stack subroutine and interrupt return addresses, as well as the current program counter A/D DATA REGISTER 0D0h A/D CONTROL REGISTER 0D1h TIMER PRESCALER REGISTER 0D2h TIMER COUNTER
www.datasheetarchive.com/files/stmicroelectronics/stonline/books/ascii/docs/6220-v4.htm
STMicroelectronics 11/01/2000 179.15 Kb HTM 6220-v4.htm