NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Number of Counter Stages n Count 2n 0 0 13 8192 0 1 10 1024 1 0 8 256 1 1 16 65536 1-800-AVG-SEMI 1-800-AVG-SEMI , binary counter, an integrated oscillator for use with external capacitor and two resistors. a automatic , tho power-on reset is enabled and initializes the counter. With the power already on. an external , with a frequency determined by external RC network. The 16-stage counter devides the oscillator frequency to the extent determined by inputs A and B. With Auto Reset pin set to a *0" the counter circuit ... | OCR Scan |
3 pages, |
DV4541B 16-Stage Binary Counter datasheet abstract |
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| Abstract: to mresidue format use the following: Ar = A 2n mod M The efficiency of the modular multiplier , multiply algorithm. S = Ar Br 2n mod M To remove this extra factor of 2n it is simply a matter of , because multiplication by a non m-residue value will reintroduce the 2-n factor: S = 1 S 2n mod M , process beginning with converting X to m-residue format: ai , bi , mi {0,1} Xr = X 2n mod M , e mod m M = C f mod m Key generation for RSA starts with the selection of two prime numbers which ... | Original |
8 pages, |
APPLICATIONS OF mod 8 COUNTER 7x clock multiplier VPN 3220 AR 8316 ARSA datasheet abstract |
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| Abstract: PROGRAMMABLE TIMER The MC14541B MC14541B programmable timer consistsof a 16-stage bihary counter, an , reset is enabled and initializes the counter, within the specified Vqd range. With the power already on , will oscillate with a frequency determined by the externaj RC network. The 16-stage counter divides the oscillator frequency (fosc> with the nth stage frequency being fosc/2n. Available Outputs 28, 21 213 or 216 , of Automatic Reset Operation _ . _ Operates as 2n Frequency Divider or Single Transition Timer Q/C ... | OCR Scan |
5 pages, |
MC14XXXBD MC14XXXBCP MC14XXXBCL MC14541B mc14541 MC14541B abstract |
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| Abstract: base counter On-chip clock generator Programmable wait function Standby function (STOP/HALT) The , TIMER TIME BASE COUNTER PORT with COMPARATOR PORT X1 CG X2 TOUT/P15 Note Not , Memory field (000 to 111) mod Mode field (00 to 10) s Sign extension specification bit (0 , Register DW (16 bits) SP Stack pointer (16 bits) PC Program counter (16 bits) PSW Program , Table 2-8 Number of Clocks. Table 2-7. Number of Clocks for Each Memory Addressing mod 00 mem ... | Original |
76 pages, |
uPD70320-8 PD70320 uPD70320L-8 uPD70108 nec V25 microcontroller IEM-1220 datasheet abstract |
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| Abstract: Address pointer (linear) : 20 bits · Terminal counter : 16 bits · · · · · 16-bit timer : 2 channels Time base counter (20 bits) : 1 channel On-chip clock generator Programmable wait function , /word TC (terminal counter) setting value Number of times of DMA transfer Byte/word Byte Byte/word (Number of times of DMA transfer) 1 Generation timing of terminal counter TC = 0 , TIMER TIME BASE COUNTER PORT with COMPARATOR PORT X1 CG X2 VDD TOUT/P15 REFRQ ... | Original |
82 pages, |
uPD70330 UPD70325L10 uPD70325L-8 uPD70325L-10 uPD70325GJ-8-5BG PD70320 PD70325 tool temp 162 stm cl-11 uPD70108 nec V25 microcontroller uPD70325GJ-10-5BG datasheet abstract |
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| Abstract: registers. The 16 x 1 or 32 x 1 RAM behaves like an edge-triggered register. An address counter supplies , is acceptable, and a linear feedback shift register counter is the most efficient. In the examples below the conventional LFSR counter algorithm has been modified to guarantee no lock-up, even in the all-ones state. the feedback for those states, the 4-bit LFSR counter counts modulo 16, and has no , For a 5-bit counter, Table 2 shows the connections required for dividing by any number up to 32. ... | Original |
6 pages, |
4 bit right left shift register ics 8 shift register by using D flip-flop mod 16 counter X-NOR four inputs XAPP 138 1.1 XAPP 138 data XC3000 XC4000E XC4000EX XC4000XL XC4010E 127-bit datasheet abstract |
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| Abstract: L-o- -CH Mod Modulator FSK PSK BIPH Manchester Clk Data R7 R6 R5 R4 R3 R2 R1 RO , ^ m < < < < Counter Figure 2. Block diagram IDIC stands for IDentification Integrated Circuit and , add 2 V VpPcoU=l-5V 100 Q O- Coil 1 X ~ 2 V Coil 2 O-1=1-^V-2V 100 Q > Mod Figure 6. , , 4 pF dynamic Coill (Pin 8) nnn Data H F + 2.2 nF UUU Coil2 (Pin 1) fres = -]= = 125 kHz 2n ... | OCR Scan |
5 pages, |
Temic IDIC rf transmitter ic diagram and of s08 ic package Temic IDIC chip telefunken radio chip rf transmitter circuit diagram datasheet abstract |
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| Abstract: Phase comparator The phase comparator has a phase detection range of -2n to +2n, and is designed to , VCO. • Counters The divide ratios of the comparator-side counter and reference-side counter can be , Type Vcc Icc Operating frequency Prescaler divide ratio (M) Comparator counter divide ratio (N) Swallow counter divide ratio (A) Reference counter divide ratio (R) PLL1 2.7 V 1.5 mA 0.5 GHz 8/9, 16/17 5 to , MOD + UpCONV (IF = 233 MHz) 27.0 mA PHS 0.9,1.9 GHz Doubler + MOD UpCONV IF = 413 MHz 28.0 mA ... | OCR Scan |
14 pages, |
SSOP-20 SSOP-16 MB15G000 LQFP64 LQFP-64 LQFP-48 FPT-16P-M05 C4805 BCC-16 MB15G000 abstract |
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| Abstract: , CLK, DATA, EN port from MCU should be pulled low. 2. When power goes up first, R counter data should be entered earlier than N1 and N2 counter data. 3. When power goes up first, control data should be entered earlier than N1 and N2 counter data. 1us CK DATA LSB MSB N1 (R1) 0.2us , OSCI 2'nd MIX or OPEN 1.3GHZ DUAL PLL S1T8825B S1T8825B PROGRAMMABLE REFERENCE COUNTER This block , R8 R9 R10 R11 R12 GC2 "1" Division Ratio of the R counter, R GC1 "1" Group Code ... | Original |
16 pages, |
S1T8825B01-R0B0 S1T8825B KB8825 16TSSOP 16-TSSOP S1T8825B abstract |
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| Abstract: be pulled low. 2. When power goes up first, R counter data should be entered earlier than N1 and N2 counter data. 3. When power goes up first, control data should be entered earlier than N1 and N2 counter , PROGRAMMABLE REFERENCE COUNTER This block generates the reference frequency for the PLL. The reference , R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 Division Ratio of the R counter, R , ) S1T8825 S1T8825 1.1GHZ DUAL PLL CHANNEL 1, CHANNEL 2 PROGRAMMABLE N COUNTER These programmable dividers are ... | Original |
16 pages, |
S1T8825X01-R0B0 KB8825 16TSSOP S1T8825 1GHz vco Frequency Generator 1GHz crystal generator 1GHz 1GHz PLL Generator S1T8825 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| Configuration MAX Count Limit Binary Binary Counter 2 n -1 Johnson Johnson Counter 2n LFSR Linear Feedback Shift Register 2 n -1 One Hot Generates a ONE_HOT sequence. n Note: n is the width of attribute values are any number between 2 and 2 n -1 inclusive. Johnson: The only allowed Count Limit attribute values are 2n or 2n-1 LFSR: The Count Limit attribute can be any number between 2 and 2 n guaranteed to return to legal count sequences after as many as 2 n (Binary) or 2n (Johnson) clock pulses www.datasheetarchive.com/files/xilinx/docs/wcd00045/wcd0458a.htm |
Xilinx | 16/02/1999 | 20.69 Kb | HTM | wcd0458a.htm |
| (a) a/b can be expressed as a/b = A/B - 2 E , where A Î Z Ç F N , A º 0 (mod 2 N-1 ) , B Î [2 N-1 ,2 N ) Ç Z and (A/B) rnd Î [2 N-1 ,2 N ) Ç Z . Let A = 2 k - A 1 , such that A 1 Î [2 N-1 , 2 N ) Ç Z . If A 1 B, then k = N-1. (b) a/b Î F N if and only if A/B Î [2 N-1 ,2 N ) Ç Z. (c) a/b is a integer + 1/2 in [2 N-1 ,2 N ). (d) If a/b Ï F N , then a/b Ï F N+1 (this is to www.datasheetarchive.com/files/intel/techno~1/itj/q21998/articles/art_3e.htm |
Intel | 31/10/1998 | 26.31 Kb | HTM | art_3e.htm |
| (a) a/b can be expressed as a/b = A/B - 2 E , where A Î Z Ç F N , A º 0 (mod 2 N-1 ) , B Î [2 N-1 ,2 N ) Ç Z and (A/B) rnd Î [2 N-1 ,2 N ) Ç Z . Let A = 2 k - A 1 , such that A 1 Î [2 N-1 , 2 N ) Ç Z . If A 1 B, then k = N-1. (b) a/b Î F N if and only if A/B Î [2 N-1 ,2 N ) Ç Z. (c) a/b is a integer + 1/2 in [2 N-1 ,2 N ). (d) If a/b Ï F N , then a/b Ï F N+1 (this is to www.datasheetarchive.com/files/intel/techno~1/itj/q21998/articles/art_3e-v1.htm |
Intel | 02/02/1999 | 26.31 Kb | HTM | art_3e-v1.htm |
| /b can be expressed as a/b = A/B - 2 E , where A Î Z Ç F N , A º 0 (mod 2 N-1 ) , B Î [2 N-1 ,2 N ) Ç Z and (A/B) rnd Î [2 N-1 ,2 N ) Ç Z . Let A = 2 k - A 1 , such that A 1 Î [2 N-1 , 2 N ) Ç Z . If A 1 B, then k = N-1. (b) a/b Î F N if and only if A/B Î [2 N-1 ,2 N ) Ç Z. (c) a/b is a midpoint between two consecutive floating-point numbers in F N if and only if A/B is an integer + 1/2 in [2 N-1 ,2 N www.datasheetarchive.com/files/intel/technologies/itj/q21998/articles/art_3e-v1.htm |
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| =@VON Need To Mirror/Rotate Pin Display Properties True s^@refdes %s+,%s-,%Vcontrol,0, mod^@refdes \n.model mod^@refdes vswitch (ron=@ron) vswitch GAIN Implementation BiasValue Power Dbreak Name IMPL PLSYN E^@REFDES %OUT 0 VALUE {LIMIT(V(%IN),@LO,@HI)} VREF SDWN DELAY E^@REFDES %OUT 0 VALUE { @EXP1 ?EXP2| \n+ @EXP2 COUNTER MODE E^@REFDES %OUT 0 VALUE {V(%IN2,%IN1)} VPULSE COMPENSATOR BiasValue Current VTHRESH G^@REFDES %out+ %out- VALUE { @EXP1 ?EXP2| \n+ @EXP2| ?EXP3| \n+ @EXP3| ?EXP4| \n+ @EXP4| } E^@REFDES %OUT+ %OUT www.datasheetarchive.com/download/47485530-919933ZC/slvm191.zip (TPS62061.DSN) |
Texas Instruments | 06/08/2011 | 161.37 Kb | ZIP | slvm191.zip |
| =@VON Need To Mirror/Rotate Pin Display Properties True s^@refdes %s+,%s-,%Vcontrol,0, mod^@refdes \n.model mod^@refdes vswitch (ron=@ron) vswitch GAIN Implementation BiasValue Power Dbreak Name IMPL PLSYN E^@REFDES %OUT 0 VALUE {LIMIT(V(%IN),@LO,@HI)} VREF SDWN DELAY E^@REFDES %OUT 0 VALUE { @EXP1 ?EXP2| \n+ @EXP2 COUNTER MODE E^@REFDES %OUT 0 VALUE {V(%IN2,%IN1)} VPULSE COMPENSATOR BiasValue Current VTHRESH G^@REFDES %out+ %out- VALUE { @EXP1 ?EXP2| \n+ @EXP2| ?EXP3| \n+ @EXP3| ?EXP4| \n+ @EXP4| } E^@REFDES %OUT+ %OUT www.datasheetarchive.com/download/23701436-918350ZC/slim236.zip (TPS62067.DSN) |
Texas Instruments | 06/08/2011 | 160.74 Kb | ZIP | slim236.zip |
| >, PCI_BUS/AD_REG TARGET/$1N13 : BIT TARGET/$2N110 : BIT TARGET/$2N48 : BIT TARGET/$2N58 : BIT TARGET/$3N69 : BIT TARGET/121 TARGET/121 TARGET/121 TARGET/121 : BIT TARGET/274 TARGET/274 TARGET/274 TARGET/274 : BIT TARGET X-BLOX for Design mod_fpga.xtg Page 26 TARGET/COUNTER/298 X-BLOX for Design mod_fpga.xtg Page 14 Data Type alias of: LOCAL_BUS/AD_REG, PCI_BUS/$2I139/X 2I139/X AD_REG13 REG13 REG13 REG13 : BIT X-BLOX for Design mod www.datasheetarchive.com/download/34359902-960688ZC/rev1e.zip (ALIAS.BLX) |
Xilinx | 05/09/1996 | 307.31 Kb | ZIP | rev1e.zip |
| >, PCI_BUS/AD_REG TARGET/$1N13 : BIT TARGET/$2N110 : BIT TARGET/$2N48 : BIT TARGET/$2N58 : BIT TARGET/$3N69 : BIT TARGET/121 TARGET/121 TARGET/121 TARGET/121 : BIT TARGET/274 TARGET/274 TARGET/274 TARGET/274 : BIT TARGET X-BLOX for Design mod_fpga.xtg Page 26 TARGET/COUNTER/298 X-BLOX for Design mod_fpga.xtg Page 14 Data Type alias of: LOCAL_BUS/AD_REG, PCI_BUS/$2I139/X 2I139/X AD_REG13 REG13 REG13 REG13 : BIT X-BLOX for Design mod www.datasheetarchive.com/download/158555-989438ZC/wcd03cd3.zip (ALIAS.BLX) |
Xilinx | 12/02/1999 | 307.31 Kb | ZIP | wcd03cd3.zip |
| >, PCI_BUS/AD_REG TARGET/$1N13 : BIT TARGET/$2N110 : BIT TARGET/$2N48 : BIT TARGET/$2N58 : BIT TARGET/$3N69 : BIT TARGET/121 TARGET/121 TARGET/121 TARGET/121 : BIT TARGET/274 TARGET/274 TARGET/274 TARGET/274 : BIT TARGET X-BLOX for Design mod_fpga.xtg Page 26 TARGET/COUNTER/298 X-BLOX for Design mod_fpga.xtg Page 14 Data Type alias of: LOCAL_BUS/AD_REG, PCI_BUS/$2I139/X 2I139/X AD_REG13 REG13 REG13 REG13 : BIT X-BLOX for Design mod www.datasheetarchive.com/download/91711962-987801ZC/wcd03266.zip (ALIAS.BLX) |
Xilinx | 13/07/1998 | 307.31 Kb | ZIP | wcd03266.zip |
| >, PCI_BUS/AD_REG TARGET/$1N13 : BIT TARGET/$2N110 : BIT TARGET/$2N48 : BIT TARGET/$2N58 : BIT TARGET/$3N69 : BIT TARGET/121 TARGET/121 TARGET/121 TARGET/121 : BIT TARGET/274 TARGET/274 TARGET/274 TARGET/274 : BIT TARGET X-BLOX for Design mod_fpga.xtg Page 26 TARGET/COUNTER/298 X-BLOX for Design mod_fpga.xtg Page 14 Data Type alias of: LOCAL_BUS/AD_REG, PCI_BUS/$2I139/X 2I139/X AD_REG13 REG13 REG13 REG13 : BIT X-BLOX for Design mod www.datasheetarchive.com/download/31153822-996207ZC/rev1e.zip (ALIAS.BLX) |
Xilinx | 09/04/1997 | 307.31 Kb | ZIP | rev1e.zip |