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convolutional interleaver

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convolutional interleaver

Abstract: Convolutional Convolutional Interleaver Megafunction Solution Brief 16 Target Applications: Digital Signal , www.ktechtelecom.com March 1997, ver. 1 s s s s Implements a convolutional interleaver function Accepts a , cable modems General Description The convolutional interleaver megafunction implements a , megafunction requires an external dual-port RAM. A convolutional interleaver megafunction that uses external , shows a functional block diagram of the convolutional interleaver megafunction. Figure 1
Altera
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block convolutional interleaving

Abstract: convolutional interleaver Convolutional Interleaver Megafunction Solution Brief 16 Target Applications: Digital Signal , www.ktechtelecom.com March 1997, ver. 1 s s s s Implements a convolutional interleaver function Accepts a , cable modems General Description The convolutional interleaver megafunction implements a , megafunction requires an external dual-port RAM. A convolutional interleaver megafunction that uses external , shows a functional block diagram of the convolutional interleaver megafunction. Figure 1
Altera
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vhdl code for interleaver

Abstract: vhdl code for block interleaver . 8 Convolutional Interleaver/Deinterleaver , Convolutional Interleaver DVB IEEE 802.14 .23 , PlugIn 1 Convolutional Interleaver/Deinterleaver Block Interleaver/Deinterleaver Convolutional Interleaver/Deinterleaver Block Interleaver/Deinterleaver GSM Turbo Code Block Interleaver/Deinterleaver Convolutional Interleaver/Deinterleaver 1 1. A
Altera
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32-Bit Parallel-IN Serial-OUT Shift Register

Abstract: 32-Bit sipo Shift Register convolutional interleaver technique is used in telecommunication applications such as SDH and PDH radio systems , transmission channels from noise. On the transmit side, the convolutional interleaver parallelizes serial , Interleavers with Virtex Devices Convolutional Interleaver The heart of a convolutional interleaver is a , : Convolutional Interleaver and De-interleaveer Schematic System Synchronization In a radio system, a , ), XC4062XL (delay elements by Core Gen), and XCV200 (SRL16s) devices. Table 2: Convolutional Interleaver
Xilinx
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XAPP222 SRL16 32-Bit Parallel-IN Serial-OUT Shift Register 32-Bit sipo Shift Register vhdl code for interleaver vhdl code for block interleaver vhdl code for sipo vhdl code for asynchronous piso DS022 DS003 DS001 XAPP210

Block Interleaver

Abstract: . 10 Convolutional Interleaver/de-interleaver , correction. The Lattice Interleaver/de-interleaver IP core supports rectangular block type and convolutional , from the branch outputs. Latticeâ'™s Convolutional Interleaver/de-interleaver IP Cores are compliant , Convolutional Interleaver Coreï'  Requirements Minimal Device Needed Rectangular De-interleaver , /de-interleaver IP Configuration Convolutional Interleaver Coreï'  Requirements FPGA Families Supported
Lattice Semiconductor
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Block Interleaver IPUG61 LFXP2-30E-7F484C LFSC3GA25E-7F900C

Interleaver-De-interleaver

Abstract: interleaver Block Diagrams Figure 1. Convolutional Interleaver/De-interleaver Block Diagram rst_b d_out clk first_dout d_in first_din valid_din valid_dout Convolutional Interleaver/ De-interleaver , correction. The Lattice Interleaver/De-interleaver IP Core supports rectangular block type and convolutional , from the branch outputs. Lattice's Convolutional Interleaver/De-interleaver IP Cores are compliant with , Interleaver/De-interleaver IP cores. Table 1. Convolutional Interleaver/De-interleaver Signal Description
Lattice Semiconductor
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LFX125B-04F256C Interleaver-De-interleaver interleaver design for block interleaver deinterleaver convolutional interleaver LFX125B04F256C Convolutional

ETS-300-421

Abstract: Convolutional supports 8PSK at a code rate of 5/6 and 16QAM at a code rate of 3/4. · Convolutional interleaver , interleaver and symbol encoders for QPSK, 8PSK and 16QAM using convolutional encoding and PTCM. The chip , The SMC-960A consists of a (204,188) Reed-Solomon encoder, a 17x11 convolutional interleaver , total bytes/block. Convolutional Interleaver The convolutional interleaver re-arranges data among , bytes from the interleaver into QPSK, 8PSK or 16QAM symbols, applying convolutional or PTCM coding at
SiCOM
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ETS-300-421 Reed-Solomon Decoder for DVB application smc96 television internal parts block diagram 6 PTCM 8PSK SMC960A 014-A0011

vhdl code for interleaver

Abstract: vhdl code for block interleaver .8 Convolutional Interleaver/Deinterleaver , .22 Convolutional Interleaver Example: DVB IEEE Std. 802.14 Transmitter & Receiver.23 Glossary , a convolutional or a block interleaver/deinterleaver. Convolutional interleaver/deinterleaver , . Data Stream Comparison A A1 B B1 C Convolutional Interleaver A1 Block Interleaver C1 A1 B1 C1 B1 C1 2 Figure 2 illustrates convolutional interleaving and
Altera
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RE35 umts turbo encoder vhdl code download REED SOLOMON interleaver time interleaver by vhdl

vhdl code for interleaver

Abstract: vhdl code for block interleaver RAM; for convolutional interleaving, the interleaver/deinterleaver function utilizes embedded array , index. The symbol interleaver/deinterleaver supports two algorithms: convolutional and block , shows the structure of the convolutional interleaver/deinterleaver. Figure 1. Convolutional Interleaver , branches Convolutional Specifies the number of branches used by the interleaver Direction Block or convolutional Specifies whether you wish to create an interleaver or a deinterleaver Memory
Altera
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ahdl code for deinterleaver block convolutional interleaving PLSM Convolutional Encoder

interleaver

Abstract: "Single-Port RAM" convolutional Specifies a block or convolutional interleaver/deinterleaver. Number of columns Block , Convolutional interleaver using FLEX 10KE EABs Block interleaver using single-port RAM FLEX 10KE , Interleaver/Deinterleaver MegaCore Function Solution Brief 42 June 1999, ver. 1 Target , convolutional interleaving algorithms Parameterized symbol width, depth, and block length Compatible with , codewords. The Altera interleaver/deinterleaver MegaCoreTM function uses internal or external single-port
Altera
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design for convolutional interleaver deinterleaver

convolutional interleaver

Abstract: ipad =8) Convolutional Interleaver: Forney I=12, M=17 Inner Coder: Convolutional Rate 1/2, K=7 Punctured to 2/3 , Randomizer and the input to the Convolutional Interleaver in the processing chain. It is a Reed-Solomon , Convolutional Interleaver The Convolutional Interleaver block sits between the output of the Outer Coder and , Coder The Inner Coder block sits between the output of the Convolutional Interleaver and the input to , Baseband Shaping block · 204/188 Reed-Solomon Outer Coder · Selectable convolutional code rates
Memec Design
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ipad block interleaver in modelsim randomizer solomon Block Interleaver time EN-300-421 digital FIR Filter verilog HDL code

turbo encoder model simulink

Abstract: vhdl code for interleaver .27 Altera Corporation vii Contents Convolutional Interleaver Example: DVB IEEE Std , .31 Convolutional Interleaver/Deinterleaver , Used EABs Used fMAX (MHz) Convolutional interleaver using FLEX 10KE EABs Depth = 12 , the type of algorithm (convolutional or block) and the direction (interleaver or deinterleaver) and , generate configuration files. Convolutional Interleaver Example: DVB IEEE Std. 802.14 Transmitter &
Altera
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turbo encoder model simulink umts simulink matlab umts simulink turbo encoder circuit, VHDL code timing interleaver turbo codes matlab simulation program

vhdl code for interleaver

Abstract: vhdl code for block interleaver www.xilinx.com 1 Interleaver/De-Interleaver v5.1 Forney Convolutional Operation Figure 1 shows the operation of a Forney Convolutional interleaver. The core operates as a series of delay line shift , : Forney Convolutional Interleaver In Figure 1, the branches increase in length by a uniform amount, L , -2) branch_length_vector(B-1) Figure 3: Forney Convolutional Interleaver/De-interleaver with Branch Lengths Set By File , symbols must be grouped into blocks. Unlike the convolutional interleaver, where symbols can be
Xilinx
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spartan d-i6 forney XC5VSX95T DS250 CDMA2000

vhdl code for interleaver

Abstract: transistors BC 543 Interleaver Symbol Mapper ROM or LUT Convolutional Encoder Q FIR Compiler N LPF Altera , a block interleaver/de-interleaver. Convolutional interleaver/de-interleaver functions process data , A A1 B B1 C Convolutional Interleaver A1 Block Interleaver C1 A1 B1 , . Convolutional Structure De-Interleaver Interleaver (I-1)J J 2J 2J din dout dout din J , branch 1. Altera Corporation 9 Specifications Convolutional Interleaver/De-Interleaver
Altera
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transistors BC 543 FIR Filter verilog code error correction code in vhdl vhdl for 8 point fft digital clock verilog code

verilog hdl code for encoder

Abstract: X9013 : Reed-Solomon RS (204,188,T=6) Convolutional Interleaver: Forney I=12, M=17 Inner Coder: Convolutional , are: Mux Adaptation & Energy Dispersal, Outer Coder, Convolutional Interleaver, Inner Coder, and , operation. Inner Coder The Inner Coder block sits between the output of the Convolutional Interleaver , Convolutional Inter-leaver in the processing chain. It is a Reed-Solomon encoder, RS(204, 188), that takes the , operation spans 8 symbols. Convolutional Interleaver The Convolutional Interleaver block sits between
Xilinx
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verilog hdl code for encoder X9013 prbs generator using vhdl verilog code for pseudo random sequence generator in digital FIR Filter verilog code polyphase 171OCT V50-4

vhdl code for 16 prbs generator

Abstract: verilog code for pseudo random sequence generator in : Reed-Solomon RS (204,188,T=6) Convolutional Interleaver: Forney I=12, M=17 Inner Coder , Dispersal, Outer Coder, Convolutional Interleaver, Inner Coder, and Baseband Shaping. Figure 1 and Table 1 , the Convolutional Inter-leaver in the processing chain. It is a Reed-Solomon encoder, RS(204, 188 , a separate core from Memec Design Services, part number XF-RSENC-DVB. Convolutional Interleaver The Convolutional Interleaver block sits between the output of the Outer Coder and the input to the
Xilinx
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vhdl code for 16 prbs generator qpsk modulation VHDL CODE 0x47 vhdl code for pseudo random sequence generator Puncturing vhdl low pass fir Filter VHDL code

power 22E

Abstract: 311E-03 convolutional interleaver. The error generator introduces channel errors at the selected rate. The codeword is , Encoder LED 5 Hold Delay 1s error_position C h a n n e l Convolutional Interleaver Hold Delay 1s swerror Error Generation LED 6 decfail Convolutional De-interleaver , LCD. The interleaver and RS megafunction's parameters are preset to match the DVB standards: I I , 204 symbols per codeword ­ 16 check symbols Interleaver with: ­ Symbol delay of 17 ­ Symbol depth
Altera
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power 22E 311E-03 epc2tc32 373E-09 20K400E

DVB-T Schematic set top box

Abstract: VIRTEX7-XC7VX485T . Forney Convolutional Operation Figure 1 shows the operation of a Forney Convolutional Interleaver. The , 1: Forney Convolutional Interleaver In Figure 1, the branches increase in length by a uniform , -3) branch_length_vector(B-2) branch_length_vector(B-1) Figure 3: Forney Convolutional Interleaver/De-interleaver with , . Unlike the Convolutional Interleaver, where symbols can be continuously input, the Rectangular Block , be an interleaver or de-interleaver. For the Forney Convolutional type, the branch lengths are
Xilinx
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DVB-T Schematic set top box VIRTEX7-XC7VX485T Radix-10 vhdl code for bit interleaver vhdl code for interleaver test bench code vhdl code for dvb-t DS861 TM-7000

synchronizer megafunction

Abstract: 5 bit multiplier using adders Speedbridge Megafunction SB 16 Convolutional Interleaver Megafunction SB 17 Early/Late Gate , Slave Interface Megafunction SB 41 FIR Compiler MegaCore Function SB 42 Interleaver , MegaCore Function User Guide Reed-Solomon MegaCore Function User Guide Symbol Interleaver/De-Interleaver
Altera
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synchronizer megafunction 5 bit multiplier using adders function generator catalog CAN BUS megafunction generator function iir filter applications 1394-C

ALTERA MAX 5000 programming

Abstract: Altera Classic EPLDs Megafunction Convolutional Interleaver Megafunction Early/Late Gate Synchronizer Megafunction Binary Pattern , Filter Megafunction Convolutional Interleaver Megafunction Early/Late Gate Synchronizer Megafunction , Megafunction Convolutional Interleaver Megafunction Early/Late Gate Synchronizer Megafunction Binary Pattern
Altera
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ALTERA MAX 5000 programming Altera Classic EPLDs Altera Programming Hardware advantages of multipliers Reed-Solomon CODEC Reed-Solomon altera EPF10K50V EPF10K130V 000-G EPF10K100 7000S
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