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Part Manufacturer Description Datasheet BUY
SN74LS320J Texas Instruments 20MHz, OTHER CLOCK GENERATOR, CDIP16 visit Texas Instruments
SN74LS321J Texas Instruments 20MHz, OTHER CLOCK GENERATOR, CDIP16 visit Texas Instruments
EL4585CS-T13 Intersil Corporation 36MHz, VIDEO CLOCK GENERATOR, PDSO16, SO-16 visit Intersil
HD1-4702/883 Intersil Corporation 2.4576MHz, OTHER CLOCK GENERATOR, CDIP16, CERDIP-16 visit Intersil
EL4584CS Intersil Corporation 36MHz, VIDEO CLOCK GENERATOR, PDSO16, SO-16 visit Intersil
EL4585CS Intersil Corporation 36MHz, VIDEO CLOCK GENERATOR, PDSO16, SO-16 visit Intersil

clock generator for 486 dx2

Catalog Datasheet MFG & Type PDF Document Tags

MIX486DX66

Abstract: INTEL 486 dx2 Integrated DMA address generator logic Address Generator (DAG) gate array for 32-bit, (DAG compatible) for 32 , TIONS DRAM MEMORY Baseboard MIX 486/SX33 MIX 486/DX33 MIX 486/DX66 Clock Rates CPU 82C258 ADMA 87C51 , intel MIX BASEBOARDS MIX 486/DX66, 486/DX33, AND 486/SX33 BASEBOARDS The Intel Modular Interface extension (MIX) 486/DX66, 486/DX33, and 486/SX33 baseboards represent the leading edge in customizable mezzanine I/O solutions. These technically advanced baseboards are designed for cost-effective CPU
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MIX486DX66 INTEL 486 dx2 DX-66 486 DX33 8259 intel microcontroller architecture INTEL I486 DX2 486/DX66 486/DX33 486/SX33 486TM 128KB 486/020A

7416245

Abstract: Cyrix 486 dx2 bus is used. Table 4 Speed Selections for Clock Generator Frequency MHz JP35 JP36 , low-power suspend mode. Sheet 4 - XD Bus, Clock Generator, Option Jumpers Sheet 4 contains the keyboard controller, BIOS ROM, and clock generator chip. Clock Generator Limitation The clock generator chip , . JP30 - selects the clock input frequency for the CPU, 1X or 2X. If a 2X CPU is used on this board, the , clock generator output frequency. Refer to the print on the demo board, the chart on the schematics or
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82C465MVA 7416245 Cyrix 486 dx2 IBM Blue Lightning 82C602 intel 486 dx4 JP59 465V5 465V3 465MV XJP6-21
Abstract: M â  SL-Enhanced Com patible System and Power M anagem ent â'" Stop clock control for reduced , , flexible clock control, and enhanced SMM. Table 1 shows avail­ able processors in the Enhanced Am 486 m , VOLDEjT VÅ", Clock Interface 32-Bit Data Bus Clock Generator 32-BH Data Bus CLK , .56 Thermal Resistance (°C/W) 9jc and 0JA for the Am 486 CPU in 168-Pin PGA Package . 67 M , asynchronous, but must meet setup and hold times t ^ and t2 i for recognition during a specific clock During -
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486DX2 208-P 004A37T

intel 80386 SL

Abstract: 80386 instruction set phase lock loop or DDL for minimum clock start-up time Ideal for battery-powered, portable , PRODUCT BRIEF ® Intel 186/386/486 Processors In today's communications environment , providing the tools and support needed to speed design time for products ranging from handheld devices to , performance i486TM DX4 (write-back) i486TM DX2 (write-through) low power 80L186/188 EC 80L186/188 EB 80L186/188 EA i386TM EX i386TM SX ULP i486TM 1486TM DX4(write-back) ULP i486TM GXSF 1486TM DX2
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intel 80386 SL 80386 instruction set 80386 intel microprocessor intel 80386dx 80486DX4 80486DX4-100 386TM 80C186/188 0702/CMD/CM/A

78f0849

Abstract: 78F0839 SCL0: Serial Clock Input/Output CRxD: Receive Data for CAN SDA0: Serial Data Input , Port SGO: Sound Generator Output EVSS: Ground for Port SGOA: Sound Generator Amplitude PWM Output EXCLK: External Clock Input (Main SGOF: Sound Generator Frequency Output , , : Stepper Motor Outputs Clock) SM21-SM24, External Potential Input for SM31-SM34, Low-voltage , User's Manual 8 78K0/Dx2 78K0 78K0/DE2: PD78F0836(A) PD78F0836(A2) PD78F0837(A
NEC
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PD78F0840 PD78F0841 PD78F0844 78F0836 78F0839 78F0841 78f0849 78F0847 78K0/D 78K0/DF2 PD78F0838 PD78F0839

82c495

Abstract: 82C495XLC /3, CLKI/4, CLKI/5 or CLKI/6. Single Phase Clock Input for the 82C495XLC internal state machine. The 82C495XLC uses single phase clock input only. CPU Reset for the 386 or 486 microprocessor. 14.3 MHz , master devices Low cost, low power, CMOS Technology Supports 386DX, 486 DX/DX2/SX CPUs as well as , Copy-Back Direct-Mapped Cache: 32/64/128/256KB for 386, and 64/128/256/512KB for 486 Up to 10% performance , for low to mid range 386/486-based AT systems. The OPTi 82C495XLC is designed for 486 systems running
OPTi
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82C495XLC/82C206 82c495 opti 386dx INTEL P24T cyrix 486 opti chipset 386 486dx isa bios opti
Abstract: System and Power Management â'" Stop clock control for reduced power consumption â , MHz DX2 40 MHz 168-pin PGA 168-pin PGA The Enhanced CPU clock control feature permits , asynchronous, but must meet setup and hold times t^ and fe, for recognition during a specific clock. During , , and two for 16-bit devices. The bus sizing pins are sampled every clock. The microprocessor sam­ ples the pins every clock before RDY to determine the appropriate bus size for the requesting device -
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80486 microprocessor description

Abstract: 80486DX2-S and Power Management - Stop clock control for reduced power consumption - Industry-standard 2 , Interface 32-Bit Data Bus Clock Generator 32-Bit Data Bus CLK CLKMUL STPCLK 32-Bit Linear , meet setup and hold times t20 and t21 for recognition during a specific clock. During normal operation , the next clock. The data bus remains active and data can be transferred for previously issued read or , two for 16-bit devices. The bus sizing pins are sampled every clock. The microprocessor samples the
Advanced Micro Devices
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80486 microprocessor description 80486DX2-S 80486 instruction set 80486 microprocessor pin out diagram microprocessor 80486 internal architecture 80486 DX4 WB

FRC 40 PIN Male connector

Abstract: FRC 34 PIN Male connector TECHNICAL USER'S MANUAL FOR: Workstation 1 (MSWS1-486) O:\TEXT\HANDB-V6\MSWS1.DOC , with power-fail detection AT-96 Clock: IEEE-996 standard bus, by Siemens for Eurosize PC's 24mA , address lines valid on the bus for one system clock period before driving /MEMR active. These signals are , , it must have the address lines valid on the bus for one system clock period before driving /MEMW , Signal Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Clock signal for the PS/2 mouse Data signal for
DIGITAL-LOGIC
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CH-4542 FRC 40 PIN Male connector FRC 34 PIN Male connector FRC 64 PIN Male connector 26 pin male FRC connector ST-9096A 80386dx memory interfacing MSWS1-486 RS232 AT386

umc8663

Abstract: Cyrix 486 dx2 AMD AM486DX, DX2, DX4 Cyrix Cx486 DX, DX2, DX2V, DX4, MISC 237-pin ZIF socket System Clock: 25 , Clock The MPXS486 system board supports all 486 serial microprocessors up to DX4 (P24C) running at , always set with pins 1 & 2 shorted), JP42, JP43, and 52-57; and the system clock generator (JP22 and , 3x system clock Open Intel/AMD DX4 = 3x system clock System Clock Generator Clock Setting , - 3 Clears CMOS data. PCI-BUS Clock (JP21) The maximum clock speed for PC1 devices is 33 MHz
Mylex
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umc8663 SIS-496-497 486SX-33 sis 496-497 INTEL DX2 computer schematic intel 486 dx2 clock circuit SIS-496-497/A/B-2AIBC32C 771947-D02 SST-28EEO 26EEO

mitsubishi melcard

Abstract: melcard AM2 pinout : Reflection on iSAbus signal BOSC disturbs keyboard clock (= BOSC/2). This sometimes generates unwanted key inputs. M: Keyboard Clock derived from VMEbus SYSCLK oscillator. RC-Termination at the clock driver. 07.05.93 2.2 Is PLDs modified for automatic test vector generation. m: New part: PLD 4861. H: New parts , auto detected. E: Default Setup support added (utility DOS-SETUP). E: Improved floppy disk handling for , locked by Setup. This is very usefull for diagnostic software (i.e. MSD.EXE) which activates the watchdog
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mitsubishi melcard melcard AM2 pinout 80486DX2 microprocessor 82c482 P4842 80486 ADDRESSING MODES EXAMPLES D-86159 N-50SB2

intel 8042 microcontroller, ibm pc

Abstract: Cyrix 486 dx2 SMM operation and clock switching for the popular 486 derivatives. Two event timers, programmable I/O , . It provides all of the system logic for implementing a high performance, Energy Star compliant 486 PC , :9 SD8:15 1 F244 Clock buffer 1 F00 Miscellaneous Add for Cache: 2 F244 Cache address 1 , used as a time base for the power management timers. 2x system clock (when CLKIN is 2x). In full speed , the 4041, and any other logic requiring a 2x clock. The lx system clock for everything except the CPU
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intel 8042 microcontroller, ibm pc S042E SCHEMATIC ATI graphics card F84041 F84045 A2023 CS4041

f244 motorola

Abstract: F84041 for SMM operation and clock switching for the popular 486 derivatives. Two event timers , Used For A SA & LA XD0:7 SD0:7 & MA2:9 SD8:15 Clock buffer Miscellaneous Cache , of their respective holders. Disclaimer This document is provided for the general information of , . CHIPS makes no warranty for the use of its products and bears no responsibility for any errors which , , DWE, and MA for up to 36 DRAM chips - Hidden refresh with staggered RAS - SMM memory support -
Chips and Technologies
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f244 motorola CS4021 4MB flash bios chip 8 pin weitek 146818 rtc CS4031

82C895

Abstract: 82C802 for fully compatible, high performance PC/AT platforms. This chipset will support 486SX/DX/DX2/DX4 and , merchantability or fitness for any particular purpose. Further, OPTi Inc. reserves the right to revise the design , .12 3.1.11 Clock Signals , .15 4.2 System Clock Generation , Rate
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82C895 82C802 D2586 82C601 opti 82C802

82C802GA

Abstract: Cyrix M6 occurs. This active low signal is used to generate IGNNE# for the 486 CPU. Ignore numeric coprocessor , Cacheable or non-cacheable status for the 486 CPU's internal cache: KEN# is asserted if the current cycle , frequency for the 82C802G. The 82C802G supports 25, 33, 40 and 50MHz oper­ ation. This clock should be in , double-word address sequencing expected by the 486 CPU. The DRAM burst counter is used for cache read-miss , degrading system performance. For 486 systems, the sec­ ondary cache operates independently and in
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82C802GA Cyrix M6 opti 82c602 82C801 80486SX 486DX 128MB 256KB IRQ12

82C802G

Abstract: opti 82C802 occurs. This active low signal is used to generate IGNNE# for the 486 CPU. IGNNE# 95 O Ignore numeric , Description KEN# 107 0 Cacheable or non-cacheable status for the 486 CPU's internal cache: KEN# is asserted if , CPU DRAM cycles for parity checking and generation, during CPU AT byte 2 write cycle in 486 mode and , operating frequency for the 82C802G. The 82C802G supports 25, 33, 40 and 50MHz operation. This clock should , sequencing expected by the 486 CPU. The DRAM burst counter is used for cache read-miss cycles and dirty
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OPTi chipset 486 opti 486 chipset 82c80 d2687 SD834 82C601/602-B

Cyrix 486

Abstract: 486DLC Intel 486 CPUs, a double frequency clock is recommended for 20, 25, and 33MHz operation, while 40 or , Supports Intel® 486 SX/DX/DX2, 487SX, and Intel 386DX/Cyrix® 486DLC/IBM 486DLC microprocessors , . Numeric Processor Error Indication: Used to generate IGERR# for the Intel 486 CPU. Also, it generates , : Cacheable or non-cacheable status for the internal cache of Intel 486 and IBM/Cyrix 486DLC. This signal is , equal to twice the rated CPU clock if the 2X-clock scheme is chosen. This signal is used for secondary
OPTi
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82C499 dram 64kx1 t418 isa bus master 386 82c499b1 t435 crystal

AT/82C601

Abstract: 82c822 described and espe­ cially disclaims any implied warranties of merchantability or fitness for any , . 12 3.1.11 Clock Signals , . 15 4.2 System Clock Generation , 4.18 Auto Clock Detection , 4.19.6.2.3 Mode 2 - Rate Generator
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AT/82C601 82c822 82C898

W641GG2KB

Abstract: gddr3 schematic write access for the GDDR3 GRAPHICS SDRAM effectively consists of a 4n data transfer every two clock , cycle Single ended interface for data, address and command Differential clock inputs CLK, CLK# Commands , DLL aligns DQ and RDQS transitions with CLK clock edges for Reads Burst length (BL): 4 or 8 Sequential , . 13 5.1 State Diagram for One Activated Bank . 13 5.1.1 State diagram for one bank
Winbond Electronics
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W641GG2KB gddr3 schematic WBGA-136 W641GG2 A01-001

6822 n9

Abstract: 700TC to transfer two data words per clock cycle at the I/O pins. A single read or write access for the , center-aligned with data for WRITEs. The GDDR3 GRAPHICS SDRAM operates from a differential clock (CLK and CLK , access Double-data rate architecture: two data transfers per clock cycle Single ended interface for data , . 13 5.1 State Diagram for One Activated Bank . 13 5.1.1 State diagram for one bank
Winbond Electronics
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W641GG2JB 6822 n9 700TC CY 6152 cmd transistor marking cy SEN 1327 A01-002
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