NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Type | Ordering |
| CLK-215S | Synergy Microwave | Mixers Double Balanced (LO +7 dBm) |
6 pages, |
Original |  |
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| CLK-215S | Synergy Microwave | DOUBLE -BALANCED STARVED L.O. MIXER |
6 pages, |
Original | |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: 30 1 TOLERANCE: HS1 NC 30 NC 29 U/D 28 R/L 27 NC 26 TX3+ 25 TX324 TX324 GND8 23 CLK+ 22 CLK21 GND7 20 TX2+ 19 TX218 TX218 NC 17 TX1+ 16 TX115 TX115 GND6 14 TX0+ 13 TX012 TX012 GND5 11 NC 10 NC 9 GND4 8 GND3 7 GND2 6 GND1 5 5VLCD4 4 5VLCD3 3 5VLCD2 2 5VLCD1 1 FI-X30H FI-X30H JAE +10mm -10mm TX0+ TX1+ R/L TX2+ TX3+ GND7 CLK+ GND5 GND3 GND1 5VLCD2 5VLCD1 CN2 TX02 1 TX14 3 U/D 6 5 TX28 7 TX310 TX310 9 GND8 12 11 CLK14 CLK14 13 GND6 16 15 18 ... | Original |
1 pages, |
TX14 TX115 FI-X30H digital view DF13-40DS-125C CLK21 lvds 26 pin for jae 30 pin JAE LVDS 30 PIN TX324 TX218 TX012 TX310 CLK14 DF13-40DS-1 TX324 abstract |
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| Abstract: INTEGRATED CIRCUITS AN070 AN070 Verilog implementation of a Manchester Encoder/Decoder in Philips CPLDs 1997 May 14 Philips Semiconductors Philips Semiconductors Application note Verilog implementation of a Manchester Encoder/Decoder in Philips CPLDs AN070 AN070 In this application note, Manchester code is defined, and the advantages relative to NonÂReturn to Zero code are given. Target applications of Manchester code are discussed. A verilog implementation of the Manchester En ... | Original |
37 pages, |
AN070 AN070 abstract |
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| Abstract: INTEGRATED CIRCUITS AN070 AN070 Verilog implementation of a Manchester Encoder/Decoder in Philips CPLDs 1997 May 14 Philips Semiconductors Philips Semiconductors Application note Verilog implementation of a Manchester Encoder/Decoder in Philips CPLDs AN070 AN070 In this application note, Manchester code is defined, and the advantages relative to NonÂReturn to Zero code are given. Target applications of Manchester code are discussed. A verilog implementation of the Manchester En ... | Original |
38 pages, |
AN070 verilog code for uart communication philips application manchester verilog line code manchester manchester code manchester encoder manchester code verilog philips application manchester manchester verilog decoder AN070 abstract |
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| Abstract: t2 RAS inactive from CLK21 10 19 25 ns t3 Column address valid from CLK21 8 15 20 ns t4 Column address invalid from CLK21 9 18 24 ns t5 CAS active from CLK21 8 14 19 ns t6 CAS inactive from CLK21 10 , from CLK2 4 8 15 20 ns tio WË inactive from CLK21 9 16 21 ns til ROMCS active from CLK2 J 8 15 20 ns tl2 ROMCS inactive from CLK21 9 16 21 ns tl3 RAS active from ATMR1 6 10 17 ns tl4 RAS inactive from ... | OCR Scan |
26 pages, |
UM82C231 clk21 82c232 82C206 80286 82c206 Unicorn Microelectronics 82C231 UM82C231 abstract |
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| Abstract: CLK1 CLK2 VSS VDD2 CLK3 CLK4 VSS VDD3 CLK5 CLK6 SDATA CLK20 CLK20 CLK21 VDD10 VDD10 VDD CIN1 ... | Original |
1 pages, |
CB683 CB683 abstract |
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| Abstract: 130 Low level twL 130 Set up time D before CLK2Ì tsu 70 Hold time D after CLK21 th 50 , after CLK2-1 th - 50 Clock margin time 1 (from CLK11 CLK11 to CLK2Ì) tei 20 ns Clock margin time 2 ... | OCR Scan |
10 pages, |
SC80 KSOO83 KS0104 KS0103 CLK11 KS0083 7 segment digital clock circuit 74148 pin configuration 80-CHANNEL KS0083 abstract |
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| Abstract: Produces 7.159 MHz clock CLK21 19 Output CLOCK2 output #1 CLK22 CLK22 20 Output CLOCK2 output #2 DGND 21 - , Il CI.K22 CLK42 CLK42 C 10 1-9 Il CLK21 CLK41 CLK41 C 11 18 â-¡ REFCIK2 AG\"D C 12 17 â-¡ AVDD OE L 13 16 â-¡ , SCLK20 SCLK20 (Pin 26) (Pin 27) (Pin 28) CLK22-5 CLK22-5 CLK21 (Pins 20.23-25) (Pin 19) 0 o n 66.63 33.32 0 0 1 50.11 ... | OCR Scan |
13 pages, |
AV9129 AV9128 AV9128-24 AV9127 775 MOTHERBOARD CIRCUIT diagram AV9128/9 AV9128/9 abstract |
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| Abstract: Output REFERENCE CLOCK output #2. Produces 7.159 MHz clock CLK21 19 Output CLOCK2 output #1 CLK22 CLK22 20 , Diagram for AV9129-06 AV9129-06 â-¡ SCLK20 SCLK20 â-¡ SCLK21 SCLK21 â-¡ SCLK22 SCLK22 â-¡ CLK25 CLK25 â-¡ CLK24 CLK24 â-¡ CLK23 CLK23 ^ VDD â-¡ DGN'D H CL.K22 â-¡ CLK21 â-¡ , (Pin 26) (Pin 27) (Pin 28) CLK22-5 CLK22-5 CLK21 (Pins 20.23-25) (Pin 19) 0 0 n 66.63 33.32 0 0 1 50.11 25.06 0 ... | OCR Scan |
13 pages, |
laptop motherboard resistors laptop motherboard circuit diagram AV9129 AV9128 775 MOTHERBOARD CIRCUIT diagram AV9128/9 AV9127 AV9128/9 abstract |
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| Abstract: CLK1T 90% CLKU 0.8/2 V RDY 50% CLK1 r 50% CLKIT 50% CLK 11 50% CLK21 50% CLK1T 10% CLK2T 10% , »RDYh 50% CLKIT 0.8/2 V D0-D15 D0-D15 50% CLKV 0.8 V ADS: 2 V SPCT 50% CLK21 0.8/2 V D0-D1 5 0.8 V ADST ... | OCR Scan |
12 pages, |
TIC 2260 AD12 coprocesor C1HS TI32082W-2 D2877 TI32082W-2 abstract |
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| Abstract: CLK1 CLK2 VSS VDD2 CLK3 CLK4 VSS VDD3 CLK5 CLK6 SDATA CLK20 CLK20 CLK21 VDD10 VDD10 VDD CIN1 , ) CLK23 CLK23 (Active = 1, Forced low = 0) CLK24 CLK24 (Active = 1, Forced low = 0) CLK21 (Active = 1, Forced low = ... | Original |
7 pages, |
CB683AAB CB683 CB683 abstract |
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| Abstract: 5 4 3 2 1 +5V C1 0.1uF D R1 ~2K D +5V R2 C2 0.1uF 10 +5V C3 22uF CN1 AUTOF St ERROR D0 INIT D1 SELin D2 GND D3 GND D4 GND D5 GND D6 GND D7 GND ACK GND BUSY GND PAPER GND SEL 1 2 3 4 5 6 7 8 9 10 11 12 13 C5 0.1uF R4 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 R3 82 1 U1 1 2 3 4 5 6 7 8 Y1 50 Ohms Parallel Port EXTFBK XTAL1 XTAL2 DATCLK VSS VSS LOAD LD/N2 D ... | Original |
1 pages, |
ics1562-201 datasheet abstract |
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| Abstract: 1998 4 - 2- 1998 4 IM P50 E30 : IM P50E30 P50E30 IM P , , 16 , : EPAC ASIC A/ D 1. EPAC ( Elect ricall y Pro g rammable Analo g , 2 3. Circuit ) F P GA ( Field Pro g rammable Gate Array ) , , ASIC ( App licatio n Sp ecific Custo m IC) IC IM P50E30 P50E30 , IM P EPAC , IM P50E30 P50E30 : :16 / 8 ,24 s ; ; ; ; C ; ; ; 2. IM P50 ... | Original |
3 pages, |
datasheet abstract |
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| Abstract: CY7C330 CY7C330: Saturday, January 4, 1992 Revision: October 19, 1995 CY7C330 CY7C330 D D feed back multiplexer output enable (OE) multiplexer Global, synchronous, product termcontrolled, state register set and re setinputs to product term are clocked by input clock D plexer 256 product terms32 per pair of macrocells, variable distribution D registered, threestate I/O pins input register clock select multi Common (pin 14-controlled) or product term-controlled output e ... | Original |
1 pages, |
CY7C330 CY7C330 abstract |
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| Abstract: ISL3687 ISL3687 ® Data Sheet July 2003 5GHz RF/IF Converter with Integrated Synthesizer The ISL3687 ISL3687 is a highly integrated, SiGe, Half Duplex RF/IF Converter with integrated PLL Synthesizer and VCO IC device. It is part of the Intersil PRISM® V, 5GHz radio chipset. The ISL3687 ISL3687 directly interfaces with Intersil's ISL3787 ISL3787 1.2GHz IF Converter with AGC and Synthesizer to allow operation with a single SAW filter for both Transmit and Receive functions. The addition of the Intersil's ISL ... | Original |
1 pages, |
ISL3877 ISL3787 ISL3687IR-TK ISL3687IR ISL3687 FN8002 ISL3687 abstract |
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| Abstract: ISL3687 ISL3687 ® Data Sheet September 2002 5GHz RF/IF Converter with Integrated Synthesizer The ISL3687 ISL3687 is a highly integrated, SiGe, Half Duplex RF/IF Converter with integrated PLL Synthesizer and VCO IC device. It is part of the Intersil PRISM® V, 5GHz radio chipset. The ISL3687 ISL3687 directly interfaces with Intersil's ISL3787 ISL3787 1.2GHz IF Converter with AGC and Synthesizer to allow operation with a single SAW filter for both Transmit and Receive functions. The addition of the Intersil' ... | Original |
1 pages, |
ISL3877 ISL3787 ISL3687IR-TK ISL3687IR ISL3687 802.11a "vco ic" FN8002 ISL3687 abstract |
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| Abstract: fax id: 6019 1CY 7C33 0 CY7C330 CY7C330 CMOS Programmable Synchronous State Machine · 66-MHz operation - 3-ns input set-up and 12-ns clock to output Features · Twelve I/O macrocells each having: - registered, three-state I/O pins - 15-ns input register clock to state register clock · Low power - 130 mA ICC · 28-pin, 300-mil DIP, LCC · Erasable and reprogrammable - input register clock select multiplexer - feed back multiplexer - output enable (OE) multiplexer · All tw ... | Original |
1 pages, |
CY7C330 CY7C330 abstract |
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| DIGITAL-LOGIC AG HITACHI TM26D51 TM26D51 TM26D51 TM26D51 1 Hitachi TM26D51 TM26D51 TM26D51 TM26D51 Model TM26D51 TM26D51 TM26D51 TM26D51 Filename LC_26D51 26D51 26D51 26D51.XXX Manufacturer Toshiba Bios code EB Resolution 640x480 Bios/Table version V1.0/V1.0 Number of Colors 512 Used Controller 535 Technology TFT-Color Date of adaption 2.95 Interface Digital Size 10,4" Notes LCD signal LCD connector pin Controller signal 16bit Controller signal 24bit CLK 21 CLK CLK HS 19 LP LP VS 17 FLM FLM VDD 23,24 EVDD EVDD VEE 26,27 EVEE* EVEE* GND 1,16,18,20,22,25 GND GND Red 2 2 P15 P23 Red 1 3 P14 P22 www.datasheetarchive.com/download/16108483-80313ZC/tft.zip (lc_26d51.pdf) |
Digital Logic | 15/11/2006 | 1313.8 Kb | ZIP | tft.zip |
| ; ################################################################################ # CLKGRP_RX_CLK21 is defined as a 6x12 ARRAY using pad 1 in Bank 5 ################################################################################ NET "clk_rx21_I" TNM_NET = "rx_clk21"; TIMESPEC "TS_rx_clk21" = PERIOD "rx_clk21" 8 ns HIGH 50%; TIMEGRP "rx_clk21" AREA_GROUP = "CLKGRP_RX_CLK21"; AREA_GROUP "CLKGRP_RX_CLK21" RANGE = SLICE_X10Y0 X10Y0 X10Y0 X10Y0 : SLICE_X21Y21 X21Y21 X21Y21 X21Y21; NET clk_rx21_I LOC = AP31; NET data www.datasheetarchive.com/download/69656127-995996ZC/xapp609.zip (top24.ucf) |
Xilinx | 11/11/2004 | 2577.83 Kb | ZIP | xapp609.zip |
| ; ################################################################################ # CLKGRP_RX_CLK21 is defined as a 6x12 ARRAY using pad 1 in Bank 5 ################################################################################ NET "clk_rx21_I" TNM_NET = "rx_clk21"; TIMESPEC "TS_rx_clk21" = PERIOD "rx_clk21" 8 ns HIGH 50%; TIMEGRP "rx_clk21" AREA_GROUP = "CLKGRP_RX_CLK21"; AREA_GROUP "CLKGRP_RX_CLK21" RANGE = SLICE_X10Y0 X10Y0 X10Y0 X10Y0 : SLICE_X21Y21 X21Y21 X21Y21 X21Y21; NET clk_rx21_I LOC = AP31; NET data www.datasheetarchive.com/download/69656127-995996ZC/xapp609.zip (top24.ucf) |
Xilinx | 11/11/2004 | 2577.83 Kb | ZIP | xapp609.zip |
| TR") showText ) BoundaryEvent ( source("S_CLK",21) cycleBar("bar") showVert labelText("TH") show www.datasheetarchive.com/download/56684786-173679ZC/i960.zip (FIGURE29.TD) |
Intel | 16/03/1997 | 1212.21 Kb | ZIP | i960.zip |
| TR") showText ) BoundaryEvent ( source("S_CLK",21) cycleBar("bar") showVert labelText("TH") show www.datasheetarchive.com/download/56684786-173679ZC/i960.zip (FIGURE29.TDK) |
Intel | 16/03/1997 | 1212.21 Kb | ZIP | i960.zip |
| TR") showText ) BoundaryEvent ( source("S_CLK",21) cycleBar("bar") showVert labelText("TH") show www.datasheetarchive.com/download/12463218-260307ZC/i960.zip (FIGURE29.TD) |
Intel | 17/03/1997 | 1212.21 Kb | ZIP | i960.zip |
| TR") showText ) BoundaryEvent ( source("S_CLK",21) cycleBar("bar") showVert labelText("TH") show www.datasheetarchive.com/download/12463218-260307ZC/i960.zip (FIGURE29.TDK) |
Intel | 17/03/1997 | 1212.21 Kb | ZIP | i960.zip |
| VIN_EN 12 NC 13 VIN_SNS14 SNS14 SNS14 SNS14 VPWR 15 VDD33 VDD33 VDD33 VDD33_OUT 16 VDD33 VDD33 VDD33 VDD33_IN 17 VDD25 VDD25 VDD25 VDD25 18 WP19 PWRGD 20 SHARE_CLK21 WDI www.datasheetarchive.com/download/57707030-364831ZC/1508a.zip (DC1508A_SCHEMATIC.pdf) |
Linear | 25/01/2010 | 1436.79 Kb | ZIP | 1508a.zip |
| VIN_EN 12 NC 13 VIN_SNS14 SNS14 SNS14 SNS14 VPWR 15 VDD33 VDD33 VDD33 VDD33_OUT 16 VDD33 VDD33 VDD33 VDD33_IN 17 VDD25 VDD25 VDD25 VDD25 18 WP19 PWRGD 20 SHARE_CLK21 WDI www.datasheetarchive.com/download/57707030-364831ZC/1508a.zip (DC1508A-sch.pdf) |
Linear | 25/01/2010 | 1436.79 Kb | ZIP | 1508a.zip |
| Bar("bar") showVert labelText("1") showText ) BoundaryEvent ( source("S_CLK",21) cycleBar("bar") showVert label www.datasheetarchive.com/download/56684786-173679ZC/i960.zip (FIGURE13.TD) |
Intel | 16/03/1997 | 1212.21 Kb | ZIP | i960.zip |