NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Datasheet 64-PIN 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Recommended Application: CK505 , Resistor IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator 9LPR501 9LPR501 1118N-05/19/11 1118N-05/19/11 1 ICS9LPR501 ICS9LPR501 64-PIN 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information , PWR OUT 14 DOTC_96/SRCC0 96/SRCC0 OUT 15 16 GND VDD PWR PWR IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator 1118N-05/19/11 1118N-05/19/11 2 ICS9LPR501 ICS9LPR501 64-PIN 64-PIN CK505 W/FULLY ... | Original |
21 pages, |
9LPR501SGLFT 9LPR501 9LPR501SGLF 64-PIN CK505 64-PIN abstract |
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| Abstract: Datasheet ICS9LPR501 ICS9LPR501 64-PIN 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Recommended Application: Key Specifications: CK505 compliant clock with fully integrated voltage regulator, PCIe , 64-pin CK505 w/Fully Integrated Voltage Regulator 1118M-11/24/09 1118M-11/24/09 1 ICS9LPR501 ICS9LPR501 64-PIN 64-PIN CK505 W , , 3.3V nominal. IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator 1118M-11/24/09 1118M-11/24/09 2 ICS9LPR501 ICS9LPR501 64-PIN 64-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR Datasheet Advance Information Pin ... | Original |
21 pages, |
VDD96 intel ck505 clock specification idt ck505 ICS9LPR501 clock ck505 9LPR501 ck505 reference 25MHz ck505 64-PIN CK505 64-PIN abstract |
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| Abstract: 27Mhz on SE1 and SE2 None 25Mhz on SE1 and SE2 N/A N/A N/A N/A N/A N/A IDTTM 56-pin CK505 for , DATASHEET 56-pin CK505 for Embedded Intel Systems Recommended Application: 56-pin CK505 , CPU_STOP#/SRCC5_LRS 56-TSSOP 56-TSSOP IDT TM 56-pin CK505 for Embedded Intel Systems 1614B-01/21/10 1614B-01/21/10 1 ICS9EPRS525 ICS9EPRS525 56-pin CK505 for Embedded Systems Pin Description PIN # PIN NAME 1 , CRC# controls SRC0 pair (default), 1= CRC# controls SRC2 pair IDTTM 56-pin CK505 for Embedded Intel ... | Original |
20 pages, |
DOT96 ck505 reference 25MHz 9EPRS525 CK505 VDD48 GND48 VDD96IO CK505 abstract |
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| Abstract: FEATURES OUTPUTS: KEY SPECIFICATIONS: · · · · · · · Compliant with Intel CK505 Gen II , 25MHz support. 2 - 0.7V differential CPU CLK pair 10 - 0.7V differential SRC CLK pair 1 - CPU_ITP , ] CPU Output Buffer Stop Logic PLL3 SSC CPU_ITP/SRC8 SRC1/25MHz/24.576MHz PCI/SATA SRC CLK , /DOT96C /DOT96C VSS_IO VDD_PLL3 SRCT1/25MHz SRCC1/25MHz1/24.576MHz VSS_PLL3 VDD_PLL3_IO SATAT/SRCT2 SATAC , control register, default is SRC0. GND 3.3V SRC or 25MHz, mode selected by pin 48, Sel_SRC1_25_24.576 ... | Original |
21 pages, |
CK505 IDTCV193 IDTCV193 abstract |
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| Abstract: Compliant with Intel CK505 Gen II spec One high precision PLL for CPU, SSC and N programming One high , ) PLL1 (2) PLL2 (CV183-1 CV183-1)(3) PLL4 (CV183-2 CV183-2)(1) Pin17 = 25MHz, PLL2 Pin18 = 1394A, PLL4 (1 , control 27MHz, 3.3V, Byte4 bit0 control the SSC enable, Byte1 bit5 control the down/center 25MHz 3.3V, SSC off Byte4 bit0 lose control Pin17 = 25MHz, PLL2 Pin18 = 1394A, PLL3 Both no SSC Reserved , PLL4 25MHz from PLL2 1394 from PLL3, SATA/PCI from PLL4 Reserved Reserved IO_VOUT [2:0] TABLE ... | Original |
22 pages, |
K1018 IDTCV183-2 IDTCV183-1 ck505 reference 25MHz IDTCV183-2A CV183-2APAG8 CV183-1APAG CV183-1 CV183 CK505 CV183-2APAG IDTCV183-1A IDTCV183-1 abstract |
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| Abstract: Intel CK505 Gen II spec One high precision PLL for CPU, SSC and N programming One high precision PLL , ) CFB table (default SRC) PLL4(1) PLL2(3) PLL4(1) Pin17 = 25MHz, PLL2 Pin18 = 1394A , control the SSC enable, Byte1 bit5 control the down/center 25MHz 3.3V, SSC off Byte4 bit0 lose control Pin17 = 25MHz, PLL2 Pin18 = 1394A, PLL3 Both no SSC Reserved Reserved SATA/PCI from PLL3 or PLL4 , 1110 1111 From PLL3 , SATA/PCI from PLL4 From PLL3 , SATA/PCI from PLL4 25MHz from PLL2 1394 ... | Original |
22 pages, |
IDTCV183-2A IDTCV183-2A abstract |
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| Abstract: PROGRAMMABLE FLEXPC CLOCK IDTCV183-2B IDTCV183-2B FEATURES: · · · · · · · Compliant with Intel CK505 Gen II spec , ) CFB table (default SRC) CFB table (default SRC) Pin17 = 25MHz, PLL2 Pin18 = 1394A, PLL3 (3) PLL4 (1 , lose control 27MHz, 3.3V, Byte4 bit0 control the SSC enable, Byte1 bit5 control the down/center 25MHz 3.3V, SSC off Byte4 bit0 lose control Pin17 = 25MHz, PLL2 Pin18 = 1394A, PLL3 Both no SSC Reserved , from PLL4 From PLL3 , SATA/PCI from PLL4 From PLL3 , SATA/PCI from PLL4 25MHz from PLL2 1394 from PLL3 ... | Original |
22 pages, |
CK505 72 pin CV183-2BPAG8 IDTCV183-2B IDTCV183-2B abstract |
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| Abstract: clock device, incorporating Intel CK505 requirements for the Intel advance P4 processor. The CPU output buffer is designed to support up to 400MHz reference clock for the CPU. This chip has three PLLs inside for CPU, SRC/PCI and 48MHz/DOT96 IO clocks. · Compliant with Intel CK505 · Power management , 3.3V only 1394B 1394B on SE1 and SE2 1011 27MHz, 3.3V only 27MHz on SE1 and SE2 1100 25MHz 3.3V only 25MHz on SE1 and SE2 1101 Reserved Reserved 1110 Reserved Reserved ... | Original |
21 pages, |
DOT96 ck505 reference 25MHz CK505 72 pin CK505 IDTCV174C IDTCV174C abstract |
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| Abstract: ICS9LPRS535 ICS9LPRS535 Integrated Circuit Systems, Inc. Datasheet 48-pin CK505 for Intel Systems Recommended Application: 48-pin Low Cost CK505 w/fully integrated VREG and series resistors on differential , differential push-pull pair · 1 - 25MHz SE1 output for Wake-on-Lan applications · 3 - PCI, 33MHz · 1 - , Power supply, nominal 3.3V 14 SE1 OUT CK505 Singled Ended Output 1. 3.3V. 15 GND 16 , CK_PWRGD/PD# 41 FSLB/TEST_MODE 42 GNDREF Notifies CK505 to sample latched inputs, or iAMT ... | Original |
17 pages, |
VDD96 ICS9LPRS535 DOT96 CK505 9lprs ICS9LPRS535 abstract |
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| Abstract: ICS9LPRS545 ICS9LPRS545 Integrated Circuit Systems, Inc. Datasheet 48-pin CK505 for Intel Systems Recommended Application: 48-pin Low Cost CK505 w/fully integrated VREG and series resistors on differential , differential push-pull pair · 1 - 25MHz SE1 output for Wake-on-Lan applications · 3 - PCI, 33MHz · 1 - , 3.3V 14 SE1 OUT CK505 Singled Ended Output 1. 3.3V. 15 GND 16 SRCT2_LPR/SATAT_LPR , 41 FSLB/TEST_MODE 42 GNDREF Notifies CK505 to sample latched inputs, or iAMT entry/exit ... | Original |
17 pages, |
VDD96 DOT96 CK505 ICS9LPRS545 9LPRS545BGLFT ICS9LPRS545 abstract |
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