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SN7476J Texas Instruments IC TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, FF/Latch visit Texas Instruments
SN7476J-00 Texas Instruments IC TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, FF/Latch visit Texas Instruments
SN7476N-00 Texas Instruments TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 visit Texas Instruments
SN7476N-10 Texas Instruments TTL/H/L SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 visit Texas Instruments
ADCS7476AIMFX/NOPB Texas Instruments 1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 & LLP 6-SOT-23 -40 to 125 visit Texas Instruments Buy
ADCS7476AIMF/NOPB Texas Instruments 1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 & LLP 6-SOT-23 -40 to 125 visit Texas Instruments Buy

circuit diagram with IC 7476

Catalog Datasheet MFG & Type PDF Document Tags

IC 7476

Abstract: 7476 truth table FAIRCHILD TTL/SSI . 9N76/5476, 7476 DUAL JK MASTER/SLAVE FLIP-FLOP WITH SEPARATE PRESETS, CLEARS AND CLOCKS DESCRIPTION - The TTL/SSI 9N76/5476, 7476 is a Dual JK Master/Slave flip-flop with separate , slave. LOGIC AND CONNECTION DIAGRAM DIP (TOP VIEW) K, Q, 0, GND l , NOTES: tn = Bit time before clock pulse. tn+-j = Bit time after clock pulse. SCHEMATIC DIAGRAM (EACH FLIP-FLOP) Component values shown are typical. CLOCK WAVEFORM LOGIC DIAGRAM (EACH FLIP-FLOP) CLOCK O 5-118
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IC 7476 7476 truth table circuit diagram with IC 7476 7476 IC J-K Flip-Flop 7476 7476 logic diagram 9N76XM/5476XM 9N76XC/7476XC 9N76/7476

IC 7476

Abstract: INTERNAL DIAGRAM OF IC 7476 /5/EU. This device contains: FCC ID: PVH071902 IC: 5325A-0719X This device complies with Part , OUT Short circuit or overload at one of the outputs IN FS 7476_en_02 Failsafe, analog and , 13 ILB BT ADIO 2/2/16/16 Internal Basic Circuit Diagram UL FS ID plus Antenna ID , with electrical isolation Optocoupler Input filter Output driver 7476_en_02 PHOENIX CONTACT , ILB BT ADIO 2/2/16/16 Bluetooth I/O Module With 16 Digital Inputs and 16 Digital Outputs and 2
Phoenix Contact
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INTERNAL DIAGRAM OF IC 7476 IC 7476 function applications IC 7476 7476 Connection diagram assignment on bluetooth of IC 7476 in file

logic ic 7476 pin diagram

Abstract: , Three-State, Non-Inverting D ecem 1992 ber Pinouts Features 20 PIN C ER AM IC DUAL-IN-LINE M , output enable input (OE) puts the I/O port in the high-impedance state when high. 20 PIN C ER AM IC , Diagram Truth Table ONE OF 8 TRANSCEIVERS CO NTRO L INPUTS - o A DATA 9 OPERATION Ã"à , , all I/O term inals should be term inated with 10k£2 to 1 M£2 resistors. CAU TIO N : These devices are sensitive to electrostatic discharge. U sers should follow proper I.C. Handling Procedures. C
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logic ic 7476 pin diagram HCS245MS IL-STD-1835 CDIP2-T20 MIL-STD-1835 CDFP4-F20 HCS245M

circuit diagram with IC 7476

Abstract: 74LS76A 7476 . . . N PACKAG E SN 74LS76A . . . D O R N PACKAGE (TO P VIEW ) ic l k C ^ 1 6 D ik 15 13 11 description The '7 6 contains tw o independent J-K flip-flops with individual J-K , clock, preset, and clear , at a tim e, and tha duration of tha short circuit should not exceed ona sacond. N O TE 2; With all , SN5476, SN54LS76A, SN7476, SN74LS76A DUAL J K FLIP FLOPS WITH PRESET AND CLEAR DECEMBER 1 9 8 3 , parameters. Te x a s In s t r u m e n t s SN5476, SN7476 DUAL J K FLIP FLOPS WITH PRESET AND CLEAR
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logic diagram of ic 7476 IC 7476 JK 54LS76A

74LS259N

Abstract: 74LS259M DM74LS259 8-Bit Addressable March 1998 F /M R C H II_ D tm S E M IC O N D U C T O R , llo w the data input with all unaddressed latches rem aining in th e ir previous states. In th e m em , -B it parallel-out storage register perform s serial-to-parallel conversion with storage A synchronous , 22 mA Latches Connection Diagram D ual-ln-Line Package V cc | 16 Function Table Inputs , F a irch ild S e m ic o n d u c to r C o rp o ra tio n D S006418 w w w .fa irch ild se m i.co
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74LS259N 74LS259M 54LS259J 74LS259W 54LS259W 54LS259/BEAJC

logic ic 7476 pin diagram

Abstract: and pin diagram of IC 7476 DM7476 Dual Master-Slave J -K Flip-Flops with Clear, Preset, and Complementary Outputs March 1998 F A I R C H I L D S E M I C O N D U C T O R TM DM7476 Dual Master-Slave J-K Flip-Flops with , specifications. Connection Diagram D ual-ln-Line Package K1 16 Q1 15 Q1 14 GND 13 K2 12 Q2 11 Q2 10 J2 9 , /or clear inputs return to their inactive (high) level. © 1 9 9 8 F a irch ild S e m ic o n d u c , Max 5.5 Min 4.75 2 0.8 - 0 .4 16 15 DM 7476 Norn 5 Max 5.25 V V V mA mA MHz Units oi -5 5 125
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and pin diagram of IC 7476 7476n logic ic 7476 flip-flop pin diagram pin diagram for IC 7476 Features of IC 7476 5476J
Abstract: R TM 74F189 64-Bit Random Access Memory with 3-STATE Outputs General Description The F189 is a , Access Memory with 3-STATE Outputs Ordering Code: Order Number 74F189SC 74F189SJ 74F189PC Package , Diagram RAM 1 6 X 4 *o - *i a2 0' 0 A- A 15 -G 1 . ^ 3 - 3 CS- ^ 1 EN , Data High Im pedance WE L H X Write Read Inhibit Block Diagram D0 D1 D 2 D 3 WE · CS w w , State (with Vc c = 0V) Standard O utput 3-STATE O utput C urrent Applied to O utput in LO W State (Max -
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S-013 DS009493

logic ic 7476 pin diagram

Abstract: (D suffix). 9 12 10 11 Functional Diagram Truth Table ONE OF 8 TRANSCEIVERS , prevent excess currents in the High-Z (Isolation) modes, all I/O terminals should be terminated with 10 , . Users should follow proper I.C. Handling Procedures. Copyright © Harris Corporation 1992 j pjjQ , .1W For Ta = +100°C to +125°C Derate Linearly at 13mW/°C CAUTION: As with all semiconductors , '0". 7-476 ' Specifications HCS245MS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER
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logic ic 7476 pin diagram

Abstract: HCS245MS Package (D suffix). GND Functional Diagram Truth Table ONE OF 8 TRANSCEIVERS CONTROL , the High-Z (Isolation) modes, all I/O terminals should be terminated with 10k to 1M resistors , should follow proper I.C. Handling Procedures. Copyright © Harris Corporation 1992 7-475 File , 1W For TA = +100oC to +125oC Derate Linearly at 13mW/oC CAUTION: As with all semiconductors , as a logic "0". 7-476 Specifications HCS245MS TABLE 2. AC ELECTRICAL PERFORMANCE
Harris Semiconductor
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4 bit synchronous ic 7476

Abstract: logic ic 7476 pin diagram determined by the SCLK. REV. PrH FUNCTIONAL BLOCK DIAGRAM S CL K CO NT RO L LO G IC S DA TA CS , . 2 Mark/Space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of , the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1 , 1MSPS with 3V Supplies 15mW typ at 1MSPS with 5V Supplies Wide Input Bandwidth: 70dB SNR at 200kHz , 10-/12-B IT S UC CE S SIV E AP P RO X IM A TIO N AD C T /H RY A IN AL IM IC L N RE CH A
Analog Devices
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4 bit synchronous ic 7476 AD7476 AD7476ART AD7476BRT AD7477 AD7477ART AD7476/AD7477 MC68HC16 68HC16
Abstract: EMICQNDUCTGR t m 74F189 64-Bit Random Access Memory with 3-STATE Outputs General Description The F189 is a , ringing Access Memory with 3-STATE Outputs Ordering Code: Order Number 74F189SC 74F189SJ 74F189PC , plem ent o f Stored Data High Im pedance Block Diagram D0 D1 D2 D3 A 0 -A1 - , State (with Standard O utput V qq 1) 3 - s t a t e o u tp u t C urrent Applied to O utput in LOW , nnnnnnnn 0.2914-0.2992 7.4-7.6 R 7] 0.3940 10.00- h 1 2 3 4 5 6 7 8 ÉÉUÜÜÜÜ: u 0.0926-0.1043 -
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S-001

74hc595n

Abstract: 74HC595M MM74HC595 8-Bit Shift Registers with Output Latches FAIRCHILD SEMICONDUCTOR T M S eptem ber 1983 , Revised February 1999 r MM74HC595 8-Bit Shift Registers with Output Latches , -Lead Sm all O utline Integrated C ircuit (SO IC), JED E C M S-013, 0 .300" W ide 16-Lead Small O utline , "X " to th e o rd e rin g code. Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP , Semiconductor Corporation D S005342.prf www.fairchildsenii.com MM74HC595 Logic Diagram (positive
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74hc595n 74HC595M MM74HC595N 74hc595w M74HC595N MS-001
Abstract: R C H II_ D E M IC O N D U C T O R t 74F779 8-Bit Bidirectional Binary Counter with , e m i.c o m 74F779 8-Bit Bidirectional Binary Counter with 3-STATE Outputs February 1998 F /M , fully synchronous 8-stage up/down counter with m ultiplexed 3-STATE I/O ports for bus-oriented a , current 80 m A typ G uaranteed 4000V m inim um ESD protection Available in S O IC (300 mil only , le in 13" reel. U se suffix = SCX. Connection Diagram Logic Symbol Pin A ssignm ent for D -
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74F779PC 74F779SC DS009593

INTERNAL DIAGRAM OF IC 7476

Abstract: D4029BC coun ter to any state asynchronously with the clock. The counter is advanced one count at the , escription 16-Lead Sm all O utline Integrated C ircuit (SO IC), JED EC M S-013, 0 .300" W ide body 16-Lead Sm , a p p e n d in g th e suffix le tte r "X " to th e orde rin g code. Connection Diagram Pin A ssig nm ents for DIP, SO IC and SOP JA M INPUTS V DD CLOCK 15 UP/DOWN B IN A R Y / DECADE PRESET EN , Semiconductor Corporation DS005960.prf www.fairchildsenii.com CD4029BC Logic Diagram CARRY w w
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D4029BC 4029bc cd4029bcn 7476 up down counter LD 7476 PS 7476 counter 4029BC

circuit diagram with IC 7476

Abstract: 600/DG34-1021-36-1012-F ADVANCE I^ IC R D N 32K, 64K X MT2LSYT3272B2, MT4LSYT6472B2 72 SYNCHRONOUS SRAM MODULE SYNCHRONOUS SRAM MODULE FEATURES · 80 position dual-read-out dual in-line memory module (DIMM) with 160 , 30pF output drive capability at rated access time 32K, 64K x 72 SRAM +3.3V SUPPLY WITH CLOCKED , a trademark of IBM Corporation. blllSMT GGlGbH? TTS ADVANCE M IC R O N I SEMICONDUCTOR , wide as controlled by the byte write enables. Burst operation can be initiated with either address
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600/DG34-1021-36-1012-F 160-L MT2LSYT3272B2G-10 MT4LSYT6472B2G-10 256KB 512KB A3-A18

74LS259N

Abstract: and pin diagram of IC 7476 DM74LS259 8-Bit Addressable Latches M arch 1998 F/MRCHII_D S E M IC O N D U C T O R tm , the data input with all unaddressed latches rem aining in th e ir previous states. In th e m em ory m , , the addressed output w ill fo llo w the level o f the D input with all oth e r outputs low. In th e , parallel-out storage register perform s serial-to-parallel conversion with storage A synchronous parallel , lCc 22 mA Connection Diagram D ual-ln -Lin e Package V cc | 16 CLEAR 15 E 14 D 13 Q7 12 Q6 11 Q5
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pin diagram decoder 7476

IC AND GATE 7408 specification sheet

Abstract: 74LS96 |d create an ED IF file with V iew log ic softw are, the fo llow ing a pplicatio ns are required: LI , Step 2: Design an equivalent circuit with the M AX+PLUS G raphic Editor. ALTR AO5 o jB .I N o o , expanded m e m ory with version 3.2 or higher o f L o tu s / In te l/M ic ro s o ft (L1M) E xpanded M em o , 0 0 Allow s M A X 5000 E P L D designs to be created with workstation C A E tools and transferred to , rin g d ev ice- or b o a rd -lev el sim ulatio n with po pular C A E tools. P LS-ED IF runs on IBM
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IC AND GATE 7408 specification sheet 74LS96 74LS183 SN 74168 7486 XOR GATE IC 74LS192
Abstract: . Trigger O peration The block diagram of the CD4538BC is shown in Figure 1, with circuit operation , M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150â' Narrow Body CD4538BCWM M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300â' Wide Body , th e orde rin g code. Connection Diagram Truth Table Pin A ssig nm ents for DIP and SOIC Tà , dual, precision monostable multivibra­ tor with independent trigger and reset controls. The device -
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CD4528BC CD4538BCM CD4538BCN

pin diagram for IC 7476

Abstract: logic ic 7476 pin diagram `B' Series CMOS Devices" 12 INHIBIT D2 8 9 Q4 Functional Diagram Applications · 3 State Hex Inverter for Interfacing ICs with Data Buses · COS/MOS to TTL Hex Buffer 3 STATE 4 , with 3 state outputs. A logic "1" on the OUTPUT DISABLE input produces a high impedance state in all , to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or , NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with
Intersil
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CD4502BMS ic 7476 pin diagram or ic 7473 CMOS ttl 7478 IOH15 TTL 7479 ISO9000

IC 7474 pinout

Abstract: Specifications for Description of â'˜Bâ'™ Series CMOS D evicesâ' Functional Diagram Applications â'¢ 3 State Hex Inverter for Interfacing ICs with Data Buses â'¢ COS/M O S to TTL Hex Buffer â  Q1 Description â Q2 CD4502BMS consists of six inverter/buffers with 3 state outputs. A logic â' 1â' on , N : These devices are sensitive to electrostatic discharge. U sers should follow proper I.C , . 0ja 0jC Ceram ic DIP and FRIT P a cka g e 80°C /W 20°C/W Flatpack P a c k a g e
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IC 7474 pinout CD4502BM
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