NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: 10UTOPIA 1. POSIC2G System Application Diagram POSIC2G Logic Block Diagram SONETTX_PAROUT TXCLKI , LVTTL 32 Y Address/Data Bus. ChipSel I LVTTL 1 Y The chip select signal for ... | Original |
43 pages, |
CYS25G0101DX CY7C9537B OC-48/STM-16 CY7C9537B abstract |
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| Abstract: System Application Diagram POSIC2G Logic Block Diagram SONETTX_PAROUT TXCLKI TXCLKOUT TXD[31:0 , [31:0] I/O LVTTL 32 Y Address/Data Bus. ChipSel I LVTTL 1 Y The chip , Addr = 0xb) to deactivate the chip from the reset condition. TEST[2:0] I LVTTL 3 Y ... | Original |
43 pages, |
CYS25G0101DX CY7C9537B OC-48/STM-16 CY7C9537B abstract |
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| Abstract: O /E CPU Figure 1. POSIC2GVC System Application Diagram POSIC2GVC Logic Block Diagram RXD , a new address. CE1 O LVTTL 1 N Synchronous Chip Enable 1, active LOW. Sampled on the , Synchronous Chip Enable 2, active LOW. Sampled on the rising edge of CLK. Used to select/deselect second bank of the NoBL memory. CE3 O LVTTL 1 N Synchronous Chip Enable 3, active LOW. Sampled ... | Original |
46 pages, |
OIF-SPI3-01 CYS25G0101DX CY7C9536B OC-48/STM-16 CY7C9536B abstract |
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| Abstract: O /E CPU Figure 1. POSIC2GVC System Application Diagram POSIC2GVC Logic Block Diagram RXD , a new address. CE1 O LVTTL 1 N Synchronous Chip Enable 1, active LOW. Sampled on the , Synchronous Chip Enable 2, active LOW. Sampled on the rising edge of CLK. Used to select/deselect second bank of the NoBL memory. CE3 O LVTTL 1 N Synchronous Chip Enable 3, active LOW. Sampled ... | Original |
46 pages, |
CYS25G0101DX CY7C9536B-BLC CY7C9536B nobl sram 1994 OC-48/STM-16 CY7C9536B abstract |
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| Abstract: n s c e iv e r O /E CPU Figure 1. POSIC2GVC System Application Diagram POSIC2GVC Logic , driven LOW in order to load a new address. CE1 O LVTTL 1 N Synchronous Chip Enable 1 , CE2 O LVTTL 1 N Synchronous Chip Enable 2, active LOW. Sampled on the rising edge of CLK. , Chip Enable 3, active LOW. Sampled on the rising edge of CLK. Used to select/deselect third bank ... | Original |
46 pages, |
CYS25G0101DX CY7C9536B cfk logic chip CY7C9536B-BLC OC-48/STM-16 CY7C9536B abstract |
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| Abstract: a n s c e iv e r O /E CPU Figure 1. POSIC2GVC System Application Diagram POSIC2GVC Logic , driven LOW in order to load a new address. CE1 O LVTTL 1 N Synchronous Chip Enable 1 , CE2 O LVTTL 1 N Synchronous Chip Enable 2, active LOW. Sampled on the rising edge of CLK. , Chip Enable 3, active LOW. Sampled on the rising edge of CLK. Used to select/deselect third bank of ... | Original |
46 pages, |
CYS25G0101DX CY7C9536B-BLC CY7C9536B OC-48/STM-16 CY7C9536B abstract |
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| Abstract: (Programmable Logic Array) for Data Conversion at 0-Port (MB88501/A MB88501/A) • 8-bit Programmable Timer/Counter with , Respective Manufacturer MIS MB88500 MB88500 SERIES FUJITSU nanus Fig. 2: MB88501/A MB88501/A LOGIC SYMBOL EX Clock - , Control port Fig. 4: MB88505 MB88505 AND MB88507 MB88507 LOGIC STKBOL 5V EX X RESET START IRQ TÇ _ SC/TO SI SO 1 , : An 8-bit parallel latched output only port with the on-chip mask programmable PLA (Programmable Logic , iZ 1/1 AC ... | OCR Scan |
48 pages, |
ICX 061 mb88500 MB88505 MB88507 MBM27C32A MB88505A th314 IRK. Series application irf 4095 Z007 MB88501A MB88501 MB88500 MB8850 MB88500 abstract |
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| Abstract: Application Diagram POSIC2GVC-R Logic Block Diagram RXD[31:0] RXCLK RXFRAME_PULSE RXCLKs SONETRX_PARIN , by the change. The POH serial access port of POSIC2GVC-R can be interfaced to external control logic ... | Original |
46 pages, |
CYS25G0101DX cypress 1994 sram zero CY7C9538 concatenated and OC-3 and STM-1 OC-48/STM-16 CY7C9538 abstract |
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| Abstract: System Application Diagram POSIC2GVC-R Logic Block Diagram RXD[31:0] RXCLK RXFRAME_PULSE RXCLKs , by the change. The POH serial access port of POSIC2GVC-R can be interfaced to external control logic ... | Original |
46 pages, |
CYS25G0101DX CY7C9538 SDH 209 OC-48/STM-16 CY7C9538 abstract |
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| Abstract: FUJITSU HIGH-SPEED CMOS SINGLE CHIP 4-BIT MICROCOMPUTER HIGH-SPEED CMOS SINGLE-CHIP 4-BIT , (Programmable Logic Array) for Data Conversion at 0-Port (MB88501H MB88501H, MB88503H MB88503H) • 8-bit Programmable Timer , Clock - Device control Control port - Fig. 2: MB88501H MB88501H ÄND MB88503H MB88503H LOGIC SYMBOL 5V EX X RESET , Fig. 4: MB88505H MB88505H LOGIC SYMBOL SV EX X RESET START IRQ TÇ _ SC/TO SI SO 1 Vcc MB88505H MB88505H VSS T , : An 8-bit parallel latched output only port witb the on-chip mask programmable PLA (Programmable Logic ... | OCR Scan |
38 pages, |
MBM27C32A DCA 305 ICX 061 mb88500 MB88500H MB88501H MB88503H MB88505H MB88508H IR 503H crt bpl circuit diagram a87l MB88500 MB88400/500 MB88500H abstract |
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| Directly Bus-Structured Pinout True Logic Outputs Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), Standard Plastic (N) and Ceramic (J) 300-mil DIPs, and used to place the eight outputs in eithera normal logic state (high or low) or a high-impedance state : JM38510/38201B2A JM38510/38201B2A JM38510/38201B2A JM38510/38201B2A, JM38510/38201BRA JM38510/38201BRA JM38510/38201BRA JM38510/38201BRA, SN54ALS573CJ SN54ALS573CJ SN54ALS573CJ SN54ALS573CJ, SNJ54ALS573CFK, SNJ54ALS573CJ SNJ54ALS573CJ SNJ54ALS573CJ SNJ54ALS573CJ, SNJ54ALS573CW SNJ54ALS573CW SNJ54ALS573CW SNJ54ALS573CW, SNJ54 SNJ54 SNJ54 SNJ54 www.datasheetarchive.com/files/texas-instruments/sc/psheets/abstract/datasht/sdas048d.htm |
Texas Instruments | 01/06/1998 | 6.97 Kb | HTM | sdas048d.htm |
| Needs Constraining? Internal clock speed for one or more clocks I/O speed Logic using multi-cycle clocks Pin to Pin timing Pin Locations & Logic Locations OUT1 X Y Z OUT2 2 Levels of Logic Clk & CE Speed I/O Speed Pin 2 Pin Speed I/O Speed Pin Locations Pin Locations Logic Locations 1 Level of Logic Q D Q D CLK Types of constraints supported Timing Constraints Specify delay along logic paths Allows both "quick and dirty" and "highly detailed" timing control www.datasheetarchive.com/download/52089125-967446ZC/rp025be.ppt |
Xilinx | 22/02/2000 | 515.5 Kb | PPT | rp025be.ppt |
| Needs Constraining? Internal clock speed for one or more clocks I/O speed Logic using multi-cycle clocks Pin to Pin timing Pin Locations & Logic Locations OUT1 X Y Z OUT2 2 Levels of Logic Clk & CE Speed I/O Speed Pin 2 Pin Speed I/O Speed Pin Locations Pin Locations Logic Locations 1 Level of Logic Q D Q D CLK Types of constraints supported Timing Constraints Specify delay along logic paths Allows both "quick and dirty" and "highly detailed" timing control www.datasheetarchive.com/download/95460563-988318ZC/wcd036b3.zip (timingcsts1.5.ppt) |
Xilinx | 12/02/1999 | 144.35 Kb | ZIP | wcd036b3.zip |
| Needs Constraining? Internal clock speed for one or more clocks I/O speed Logic using multi-cycle clocks Pin to Pin timing Pin Locations & Logic Locations OUT1 X Y Z OUT2 2 Levels of Logic Clk & CE Speed I/O Speed Pin 2 Pin Speed I/O Speed Pin Locations Pin Locations Logic Locations 1 Level of Logic Q D Q D CLK Types of constraints supported Timing Constraints Specify delay along logic paths Allows both "quick and dirty" and "highly detailed" timing control www.datasheetarchive.com/download/98664486-977921ZC/rp09979.ppt |
Xilinx | 23/02/2000 | 500 Kb | PPT | rp09979.ppt |
| Needs Constraining? Internal clock speed for one or more clocks I/O speed Logic using multi-cycle clocks Pin to Pin timing Pin Locations & Logic Locations OUT1 X Y Z OUT2 2 Levels of Logic Clk & CE Speed I/O Speed Pin 2 Pin Speed I/O Speed Pin Locations Pin Locations Logic Locations 1 Level of Logic Q D Q D CLK Types of constraints supported Timing Constraints Specify delay along logic paths Allows both "quick and dirty" and "highly detailed" timing control www.datasheetarchive.com/download/21932626-988091ZC/wcd0344a.ppt |
Xilinx | 13/01/1999 | 500 Kb | PPT | wcd0344a.ppt |