bq2084-V143 SLUS732 bq29312 38-PIN bq2084DBT-V143 36-PIN bq2084RTT-V143 - Datasheet Archive

 

bq2084-V143 DBT www.ti.com SLUS732 ­ SEPTEMBER 2006 SBS v1.1-COMPLIANT GAS GAUGE FOR USE WITH THE bq29312 FEATURES ·

 

RTT bq2084-V143 bq2084-V143 DBT www.ti.com SLUS732 SLUS732 ­ SEPTEMBER 2006 SBS v1.1-COMPLIANT GAS GAUGE FOR USE WITH THE bq29312 bq29312 FEATURES · · · · · · · · · · · Provides Accurate Measurement of Available Charge in Li-Ion and Li-Polymer Batteries Supports the Smart Battery Specification (SBS) V1.1 Integrated Time Base Removes Need for External Crystal with Optional Crystal input Works With the TI bq29312 bq29312 Analog Front-End (AFE) Protection IC to Provide Complete Pack Electronics for 7.2-V, 10.8-V or 14.4-V Battery Packs With Few External Components Based on a Powerful Low-Power RISC CPU Core With High-Performance Peripherals Integrated Flash Memory Eliminates the Need for External Configuration EEPROM Uses 16-Bit Delta Sigma Converter for Accurate Voltage and Temperature Measurements Measures Charge Flow Using a High Resolution 16-Bit Integrating Converter ­ Better Than 0.65-nVh of Resolution ­ Self-Calibrating ­ Offset Error Less Than 1-µV Programmable Cell Modeling for Maximum Battery Fuel Gauge Accuracy Drives 3-, 4-, or 5-Segment LED Display for Remaining Capacity Indication Available in a 38-Pin TSSOP (DBT) Package APPLICATIONS · · · Notebook PCs Medical and Test Equipment Portable Instrumentation DESCRIPTION The bq2084-V143 bq2084-V143 SBS-compliant gas gauge IC for battery pack or in-system installation maintains an accurate record of available charge in Li-ion or Li-polymer batteries. The bq2084-V143 bq2084-V143 monitors capacity and other critical parameters of the battery pack and reports the information to the system host controller over a serial communication bus. It is designed to work with the bq29312 bq29312 AFE protection IC to maximize functionality and safety and minimize component count and cost in smart battery circuits. Using information from the bq2084-V143 bq2084-V143, the host controller can manage remaining battery power to extend the system run time as much as possible. The bq2084-V143 bq2084-V143 uses an integrating converter with continuous sampling for the measurement of battery charge and discharge currents. Optimized for coulomb counting in portable applications, the self-calibrating integrating converter has a resolution better than 0.65-nVh and an offset measurement error of less than 1-µV (typical). For voltage and temperature reporting, the bq2084-V143 bq2084-V143 uses a 16-bit A-to-D converter. With the bq29312 bq29312, the onboard ADC also monitors the pack and individual cell voltages in a battery pack and allows the bq2084-V143 bq2084-V143 to generate the control signals necessary to implement the cell balancing and the required safety protection for Li-ion and Li-polymer battery chemistries. The bq2084-V143 bq2084-V143 supports the Smart Battery Data (SBData) commands and charge-control functions. It communicates data using the System Management Bus (SMBus) 2-wire protocol. The data available include the battery's remaining capacity, temperature, voltage, current, and remaining run-time predictions. The bq2084-V143 bq2084-V143 provides LED drivers and a pushbutton input to depict remaining battery capacity from full to empty in 20%, 25%, or 33% increments with a 3-, 4-, or 5-segment display. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated bq2084-V143 bq2084-V143 www.ti.com SLUS732 SLUS732 ­ SEPTEMBER 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The bq2084-V143 bq2084-V143 contains 1k bytes of internal data flash memory, which store configuration information. The information includes nominal capacity and voltage, self-discharge rate, rate compensation factors, and other programmable cell-modeling factors used to accurately adjust remaining capacity for use-conditions based on time, rate, and temperature. The bq2084-V143 bq2084-V143 also automatically calibrates or learns the true battery capacity in the course of a discharge cycle from programmable near full to near empty levels. The bq29312 bq29312 analog front-end (AFE) protection IC is used to maximize functionality and safety and minimize component count and cost in smart battery circuits. The bq29312 bq29312 AFE protection IC provides power to the bq2084-V143 bq2084-V143 from a 2-, 3-, or 4-series Li-ion cell stack, eliminating the need for an external regulator circuit. ORDERING INFORMATION PACKAGE (1) TA 38-PIN 38-PIN TSSOP ­20°C to 85°C (1) (2) (3) (DBT) (2) bq2084DBT-V143 bq2084DBT-V143 36-PIN 36-PIN QFN (RTT) (3) bq2084RTT-V143 bq2084RTT-V143 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. The bq2084DBT-V141 bq2084DBT-V141 is available in tape and reel. Add an R suffix to the device type (e.g., bq2084DBTR-V141 bq2084DBTR-V141) to order tape and reel version. The bq2084RTT-V140 bq2084RTT-V140 is available in tape and reel only. Add an T suffix to the device type (e.g., bq2084RTTT-V140 bq2084RTTT-V140) to order mini tape and reel version. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) UNIT Supply voltage range, VDD relative to VSS (2) ­0.3 V to 4.1 V Open-drain I/O pins, V(IOD) relative to VSS (2) ­0.3 V to 6 V Input voltage range to all other pins, VI relative to VSs (2) ­0.3 V to VDD + 0.3 V TA Operating free-air temperature range ­20°C to 85°C Tstg Storage temperature range ­65°C to 150°C (1) (2) 2 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. VSS refers to the common node of V(SSA), V(SSD), and V(SSP). Submit Documentation Feedback bq2084-V143 bq2084-V143 www.ti.com SLUS732 SLUS732 ­ SEPTEMBER 2006 ELECTRICAL CHARACTERISTICS VDD = 3 V to 3.6 V, TA = ­20°C to 85°C unless otherwise noted PARAMETER VDD TEST CONDITIONS MIN TYP MAX 3 3.3 3.6 Supply voltage VDDA and VDDD IDD Operating mode current No flash programming or LEDs active I(SLP) Low-power storage mode current Sleep mode VOL Output voltage low SMBC, SMBD, SDATA, SCLK, SAFE, PU IOL = 0.5 mA 0.4 LED1-LED5 IOL = 10 mA UNIT 0.4 380 µA 8 µA ­0.3 0.8 ­0.3 Input voltage high SMBC, SMBD, SDATA, SCLK, EVENT, PU, PRES, PFIN 2 6 2 V 0.8 DISP VIH Input voltage low SMBC, SMBD, SDATA, SCLK, EVENT, PU, PRES, PFIN DISP VIL V VDD + 0.3 V(AI1) Input voltage range VIN, TS V(AI2) Input voltage range SR1, SR2 VSS ­ 0.3 Z(AI1) Input impedance SR1, SR2 ­0.25 V to 0.25 V Z(AI2) Input impedance VIN, TS 1.0 VSS ­ 0.25 0.25 0 V­1 V V V V V 2.5 M 8 M POWER-ON RESET Negative-going voltage input 2.1 2.3 2.5 V Vhys Power-on reset hysteresis 50 125 200 mV POWER ON RESET BEHAVIOR vs FREE-AIR TEMPERATURE 2.50 140 2.45 135 2.40 130 VIT- 2.35 125 2.30 120 2.25 115 Vhys 2.20 110 2.15 105 2.10 -20 -10 V hys - Hysterisis Voltage - mV V IT - Negative Going Input Threshold Voltage - V VIT+ 100 0 10 20 30 40 50 60 70 80 TA - Free-Air Temperature - °C INTEGRATING ADC CHARACTERISTICS VDD = 3 V to 3.6 V, TA = ­20°C to 85°C unless otherwise noted PARAMETER V(SR) Input voltage range, V(SR2) and V(SR1) V(SROS) Input offset INL Integral nonlinearity error TEST CONDITIONS VSR = V(SR2)­ V(SR1) MIN TYP ­0.25 MAX 0.25 1 FAST = 0, ­0.1 V to 0.8 x Vref Submit Documentation Feedback 0.004% UNIT V mV 0.018% 3 bq2084-V143 bq2084-V143 www.ti.com SLUS732 SLUS732 ­ SEPTEMBER 2006 PLL SWITCHING CHARACTERISTICS VDD = 3 V to 3.6 V, TA = ­20°C to 85°C unless otherwise noted PARAMETER t(SP) (1) Start-up time TEST CONDITIONS MIN TYP MAX ±0.5% frequency error (1) 2 5 UNIT ms The frequency error is measured from the trimmed frequency of the internal system clock, which is 128 x oscillator frequency, nominally 4.194 MHz. OSCILLATOR VDD = 3 V to 3.6 V, TA = ­20°C to 85°C (unless otherwise noted) (TYP: VDD = 3.3 V, TA = 25°C) PARAMETER f(eio) Frequency error from 32.768 kHz f(dio) TEST CONDITIONS ROSC = 100k Frequency drift (1) f(sio) f(sxo) (1) (2) XCK1 = 12 pF XTAL ROSC = 100k, TA = 0°C to 50°C MIN TYP MAX ­2% 0.5% 2% ­0.25% UNIT 0.25% ­1% 1% ROSC = 100k µs XCK1 = 12 pF XTAL Start-up time (2) 200 250 ms The frequency drift is measured from the trimmed frequency at VDD = 3.3 V, TA = 25°C. The start-up time is defined as the time it takes for the oscillator output frequency to be ±1% DATA FLASH MEMORY CHARACTERISTICS VDD = 3 V to 3.6 V, TA = ­20°C to 85°C unless otherwise noted PARAMETER TEST CONDITIONS MIN Data retention See (1) Flash programming write-cycles See (1) Word programming time See (1) I(DDPROG) Flash-write supply current See (1) MAX 20k t(WORDPROG) TYP 10 tDR (1) UNIT Years Cycles 2 ms 8 12 mA TYP MAX UNIT 10 100 nA Specified by design. Not production tested. REGISTER BACKUP PARAMETER I(RBI) RBI data-retention input current V(RBI) RBI data-retention voltage TEST CONDITIONS (1) MIN VRBI > 2 V, VDD < VIT (1) 1.3 V Specified by design. Not production tested. SMBus TIMING SPECIFICATIONS VDD = 3 V to 3.6 V, TA = -20°C to 85°C unless otherwise noted PARAMETER TEST CONDITIONS f(SMB) SMBus operating frequency Slave mode, SMBC 50% duty cycle f(MAS) SMBus master clock frequency Bus free time between start and stop T(HD:STA) Hold time after (repeated) start t(SU:STA) Repeated start setup time t(SU:STO) Stop setup time t(HD:DAT) Data hold time tSU:DAT) UNIT 100 kHz Error signal/detect t(LOW) kHz µs 4 µs 4.7 µs 4 µs Receive mode 0 Transmit mode 300 Clock low period (1) 51.2 4.7 Data setup time t(TIMEOUT) 4 TYP MAX 10 Master mode, no clock low slave extend t(BUF) MIN ns 250 See (1) 25 4.7 The bq2084-V143 bq2084-V143 times out when any clock low exceeds t(TIMEOUT). Submit Documentation Feedback ns 35 ms µs bq2084-V143 bq2084-V143 www.ti.com SLUS732 SLUS732 ­ SEPTEMBER 2006 SMBus TIMING SPECIFICATIONS (continued) VDD = 3 V to 3.6 V, TA = -20°C to 85°C unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX 4 UNIT t(HIGH) Clock high period See (2) 50 µs tLOW:SEXT) Cumulative clock low slave extend time See (3) 25 ms tLOW:MEXT Cumulative clock low master extend time See (4) 10 ms tf Clock/data fall time (VILMAX ­ 0.15 V) to (VIHMIN + 0.15 V) 300 ns tr Clock/data rise time 0.9 VDD to (VILMAX­ 0.15 V) 1000 ns (2) (3) (4) t(HIGH) Max. is minimum bus idle time. SMBC = 1 for t > 50 ms causes reset of any transaction involving bq2084-V143 bq2084-V143 that is in progress. t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop. t(LOW:MEXT) is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop. SMBus TIMING DIAGRAMS Submit Documentation Feedback 5 bq2084-V143 bq2084-V143 www.ti.com SLUS732 SLUS732 ­ SEPTEMBER 2006 SYSTEM DIAGRAM Discharge / Charge / Pre-Charge FET s Fuse Pack + Pre-Charge Control Fail-Safe Protection Power Management LDO, TOUT and Power Mode Control Pres Temperature Measurement Cell Imbalance Threshold AND SBS. Current()> Balance IMAX for a period of Cell Imbalance time then the CIM bit in PF Status is set. Table 6. Cell Balancing and Cell Imbalance Programming NAME DF ADDRESS DESCRIPTION Cell Balance Threshold 0xe8-0xe9 Sets the maximum voltage in mV that each cell must achieve to initiate cell balancing. Programming Cell Balance Threshold to 65,535 disables cell balancing. Cell Balance Min 0xec Sets in mV the cell differential that must exist to initiate cell balancing Cell Balance Window 0xea-0xeb Sets in mV the amount that the cell balance threshold increases during cell balancing Cell Balance Interval 0xed Sets the cell balancing time interval in seconds. Cell Imbalance Threshold 0xee-0xef Sets the severe imbalance fault limit for cell imbalance detection Balance IMAX 0xf2-0xf3 Sets the charge current required to allow a cell imbalance to be detected Cell Imbalance Time 0x134 Sets the time period during which a cell imbalance must be selected for the bq2084 to enter PF mode. Submit Documentation Feedback 19 bq2084-V143 bq2084-V143 www.ti.com SLUS732 SLUS732 ­ SEPTEMBER 2006 DISPLAY PORT General The display port drives a 3-, 4-, or 5-LED bar-graph display. The display is activated by a logic signal on the DISP input. The bq2084-V143 bq2084-V143 can display RM in either a relative or absolute mode with each LED representing a percentage of the full-battery reference. In relative mode, the bq2084-V143 bq2084-V143 uses FCC as the full-battery reference; in absolute mode, it uses Design Capacity (DC). The DMODE bit in Pack Configuration DF 0x28 programs the bq2084-V143 bq2084-V143 for the absolute or relative display mode. The LED bits program the 3-, 4-, or 5-LED option. Activation The display may be activated at any time by a high-to-low transition on the DISP input. This is usually accomplished with a pullup resistor and a pushbutton switch. Detection of the transition activates the display and starts a 4-s display timer. Reactivation of the display requires that the DISP input return to a logic-high state and then transition low again. The second high-to-low transition can be detected only after the display timer expires. If unused, the DISP input must be pulled up to VCC. If the EDV0 bit is set, the bq2084-V143 bq2084-V143 disables the LED display. Display Modes In relative mode, each LED output represents 20%, 25%, or 33% of the RelativeStateOfCharge() value. In absolute mode, each LED output represents 20%, 25% or 33% of the AbsoluteStateOfCharge() value. Table 7 shows the display options for 5 LEDs, for 4 LEDs, Table 8 and Table 9 for 3 LEDs. In either mode, the bq2084-V143 bq2084-V143 blinks the LED display if RemainingCapacity() is less than Remaining CapacityAlarm(). The display is disabled if EDV0 = 1. Table 7. Display Mode for Five LEDs CONDITION RELATIVE OR ABSOLUTE FIVE-LED DISPLAY OPTION StateOfCharge() LED1 LED2 LED3 LED4 LED5 EDV0 = 1 OFF OFF OFF OFF OFF charge detection current (DF 0x113/4) GG Charge OC (set by DF 0x12a to 0x12c) CHG off, ZVCHG off, DSG on Same AFE SCC GG Discharge OC (set by DF 0x12d to 0x12f) CHG on, ZVCHG off, DSG off Same AFE SCD NR=0 FAILURE FET STATUS EXIT CONDITIONS AFE OLV All FETs off RRES=high AFE SCC All FETs off PRES=high AFE SCD All FETs off PRES=high GG Charge OC (set by DF 0x12a to 0x12c) All FETs off PRES=high GG Discharge OC (set by DF 0x12d to 0x12f) All FETs off PRES=high 22 Submit Documentation Feedback bq2084-V143 bq2084-V143 www.ti.com SLUS732 SLUS732 ­ SEPTEMBER 2006 The AFE protection features can also recover automatically after AFE Recovery Time (DF 0x160) if the AFE Recovery Time is set to a nonzero value. When the protection feature is recovered in this manner, it does not re-trigger for AFE Hold Off Time (DF 0x161). AFE Integrity Check The bq2084-V143 bq2084-V143 checks the programming of the AFE registers at a period determined by AFE Check Time DF 0xfb. The units of the check period are seconds unless the bq2084-V143 bq2084-V143 is in sleep mode, in which case the period is AFE Check Time x Sleep Current Multiplier (DF 0xfd). If the data is not correct, the bq2084-V143 bq2084-V143 increments an internal counter until it reaches the AFE Fail Limit (DF 0xe4). Setting AFE Check Time to 0 disables this function. When the internal AFE Fail counter reaches AFE Fail Limit, then the AFE bit in PF Status is set. AFE Watchdog Fault and Clear The bq29312 bq29312 has a feature where the 32-kHz output (CLKOUT, pin 35) of the bq2084-V143 bq2084-V143 is used to drive its internal clock. If this clock fails, a fault is declared in the AFE. See the bq29312 bq29312 data sheet for further details. The fault is cleared automatically on return of the 32-kHz input via the bq2084-V143 bq2084-V143 CLKOUT pin. Permanent Failure Mode (SAFE Output) The SAFE output of the bq2084-V143 bq2084-V143 provides an additional level of safety control. The active low safety output can blow a fuse or control another switch on the basis of temperature, pack-voltage cell-voltage, CHG FET Failure, severe cell imbalance, or an integrity check of the AFE and Data Flash configuration registers. The bq2084-V143 bq2084-V143 can also activate the SAFE output and set the PF Flag based on the PFIN input. If this pin is low for PFIN Time seconds ±1 s, then the PFIN bit in PF Status is set. The SAFE output can be driven low in any of the following conditions, and the bq2084-V143 bq2084-V143 sets the PF Flag register (DF 0x11e) to 0x66 (011001100). The activation of the SAFE output and the setting of the PF Flag can be enabled or disabled for different safety option per the PF Config (DF 0x11f) register settings. The SAFE output and PF Flag register can only be cleared using a series of ManufacturerAccess() commands. Table 12. SAFE Activation Conditions (1) CONDITION ACTIONS Voltage() > Safety Over Voltage (DF 0x6b and 0x6c), SOV and PF set Temperature() > Safety Over Temperature in Charge (DF 0x75 and 0x76) SOTC and PF set Temperature() > Safety Over Temperature in Discharge (DF 0x77 and 0x78) SOTD and PF set When Miscellaneous Configuration (0x2a) bit 13 AC is set, and the number of AFE failures has reached the AFE Fail Limit (DF 0xe4) AFE and PF set When VCELL(MAX) - VCELL(MIN) > Cell Imbalance Threshold (DF 0xee, 0xef) during charging CIM and PF set If charge FET is off, and charge current greater than FET Fail charge current stored in DF 0x125-0x126 for the time determined by FET Fail time in DF 0x129, or if discharge FET is off and discharge current greater than FET Fail discharge current stored in DF 0x127-0x128 for the time determined by FET Fail time in DF 0x129. The PFIN input has detected a low state for PFIN Time in consecutive seconds, as determined by DF 0x120 (1) FETF and PF set PFIN, PF set SAFE output activated and PF Flag set only if enabled by PF Config (DF 0x0x11f) Permanent Failure Status (PF Status) PF Status DF 0x11d contains the flags for the cause of the permanent failure mode. b7 b6 b5 b4 b3 b2 b1 b0 PFF PFIN FETF CIM AFE SOTD SOTC SOV Submit Documentation Feedback 23 bq2084-V143 bq2084-V143 www.ti.com SLUS732 SLUS732 ­ SEPTEMBER 2006 SOV The SOV bit indicates a safety overvoltage occurred which if enabled by PF Config would cause the SAFE output to activate. 0 SOV fault not detected (default) 1 SOV fault detected SOTC The SOTC bit indicates a safety overtemperature in charge occurred which if enabled by PF Config would cause the SAFE output to activate. 0 SOTC fault not detected (default) 1 SOTC fault detected SOTD The SOTD bit indicates a safety overtemperature in discharge occurred which if enabled by PF Config would cause the SAFE output to activate. 0 SOTD fault not detected (default) 1 SOTD fault detected AFE The AFE bit indicates an AFE integrity fault state occurred which if enabled by PF Config would cause the SAFE output to activate. 0 AFE is operating correctly (default) 1 AFE Integrity check fail limit reached CIM The CIM bit indicates that a severe cell imbalance occurred during charging, which if enabled by PF Config, would cause the SAFE output to activate. 0 All cells are within the Cell Imbalance Threshold (default) 1 There is a severe cell imbalance FETF The FETF bit indicates a FET or FET driver failure occurred, which if enabled by PF Config would cause the SAFE output to activate. 0 The FETs are operating normally (default) 1 The FETs or FET drivers have a fault PFIN The PFIN bit is used to indicate that the output of the 2nd level protector has activated. 0 The PFIN input is high (default) 1 The PFIN input drive and held low by 2nd level protector output FPP The FPP bit is used to indicate that current has been detected when the fuse has been set to be blown. 0 1 24 Current not detected with fuse blown Current detected with fuse blown Submit Documentation Feedback bq2084-V143 bq2084-V143 www.ti.com SLUS732 SLUS732 ­ SEPTEMBER 2006 Permanent Failure Configuration (PF Config) PF Config DF 0x11f contains the enable/disable configuration that determines if the SAFE output is activated and the PF Flag set for each possible failure mode. b7 b6 b5 b4 b3 b2 b1 b0 - XPFIN XFETF XCIM XAFE XSOTD XSOTC XSOV XSOV The XSOV bit enables or disables the activation of SAFE and the setting of the PF Flag when PF Status SOV is set. 0 Activation disabled (default) 1 Activation enabled XSOTC The XSOTC bit enables or disables the activation of SAFE and the setting of the PF Flag when PF Status SOTC is set. 0 Activation disabled (default) 1 Activation enabled XSOTD The XSOTD bit enables or disables the activation of SAFE and the setting of the PF Flag when PF Status SOTD is set. 0 Activation disabled (default) 1 Activation enabled XAFE The XAFE bit enables or disables the activation of SAFE and the setting of the PF Flag when PF Status AFE is set. Bit 13 of Miscellaneous Config DF 0x2a also needs to be set for activation. 0 Activation disabled (default) 1 Activation enabled XCIM The XCIM bit enables or disables the activation of SAFE and the setting of the PF Flag when PF Status CIM is set. 0 Activation disabled (default) 1 Activation enabled XFETF The XFETF bit enables or disables the activation of SAFE and the setting of the PF Flag when PF Status FETF is set. 0 Activation disabled (default) 1 Activation enabled XPFIN The XPFIN bit enables or disables the activation of SAFE and the setting of the PF Flag when PF Status PFIN is set. 0 Activation disabled (default) 1 Activation enabled Submit Documentation Feedback 25 bq2084-V143 bq2084-V143 www.ti.com SLUS732 SLUS732 ­ SEPTEMBER 2006 Permanent Failure Flag (PF Flag) PF Flag DF 0x11e contains the flag indicating if the /SAFE output has been activated. STATE b7 b6 b5 b4 b3 b2 b1 b0 Clear 0 0 0 0 0 0 0 0 Set 0 1 1 0 0 1 1 0 PF FLAG The PF Flag indicates that the SAFE output of the bq2084-V143 bq2084-V143 has been activated. 0x00 SAFE output high (default) 0x66 SAFE output activated An example circuit using the SAFE output to blow a fuse is shown in Figure 2. Figure 2. Example SAFE Circuit Implementation Low-Power Modes The bq2084-V143 bq2084-V143 enters sleep mode when the charge and discharge current is less than the threshold programmed in Sleep Current Threshold DF 0xfc, the SMBus lines are low for at least 2s, and bit 12 of Misc. Configuration DF 0x2a is set to zero. Additionally, PRES must be pulled high if the NR bit in Misc Config is set to 0. The bq2084-V143 bq2084-V143 wakes up periodically to monitor voltage and temperature and to apply self-discharge adjustment. The sleep period is set in Sleep Timer DF 0xfe. The bq2084-V143 bq2084-V143 wakes up at a period set by Sleep Current Multiplier DF 0xfd multiplied by Sleep Time to measure current. The bq2084-V143 bq2084-V143 comes out of sleep when either of the SMBus lines go high or when the current is measured and it is greater than the Sleep Current Threshold. The sleep current threshold, SLP (mA), is stored in Sleep Current Thresh DF 0xfc as: Sleep Current Thresh = SLP(mA)/0.5 The wake-up period for current measurement, WAT(s), is set using the following formula: Sleep Current Multiplier x Sleep Time = WAT(s) During sleep mode, both charge and discharge FETs are turned off if the NR bit in Misc Config is cleared. If the bq2084-V143 bq2084-V143 is in Non-Removable mode where NR=1, then the discharge FET retains its state on entry to sleep. Shutdown Mode The bq2084-V143 bq2084-V143 goes into shutdown, in which all FETs are turned off and the pack electronics are powered down (including the bq2084-V143 bq2084-V143), when SBS.Voltage() falls below Shutdown Voltage DF 0x7c-0x7d and Voltage at the Pack pin is less than VPACK threshold (DF 0x131, 0x132) both for 2 consecutive samples (1 to 2 s). 26 Submit Documentation Feedback bq2084-V143 bq2084-V143 www.ti.com SLUS732 SLUS732 ­ SEPTEMBER 2006 Vpack is programmed in units of 0.935 mV/count and has tolerance of ±6%. For example, to set 12 V as Vpack Threshold, the program value should be 12000/0.935 = 12834. When the DSG FET is turned on, the pack voltage is close to the battery voltage even with no charger attached. Therefore, to enter shutdown, the Vpack threshold should be set higher than the shutdown threshold plus the tolerance. The bq2084-V143 bq2084-V143 can also be instructed to enter Shutdown mode via the ManufacturerAccess() command. When the command is sent to the bq2084-V143 bq2084-V143, the bq29312 bq29312 is instructed to enter shutdown mode by the bq2084-V143 bq2084-V143. This forces the chipset into its lowest power mode. The bq2084-V143 bq2084-V143 does not issue a shutdown command to the AFE unless the pack voltage is less than the Vpack Threshold. Program the Vpack threshold higher than the SBS.Voltage() when ship command is issued. Exit from this mode is only achieved by application of a charger. After exiting shutdown mode, the bq2084-V143 bq2084-V143 does not enter the shutdown mode again until the Shutdown Timer (DF 0x133, units are seconds) has expired even if the correct conditions are present. After the Shutdown Timer has expired, the SMBus command or voltage and current conditions enables the bq2084-V143 bq2084-V143 to enter shutdown mode. Submit Documentation Feedback 27 bq2084-V143 bq2084-V143 www.ti.com SLUS732 SLUS732 ­ SEPTEMBER 2006 Normal Operation SBS.VCELLx( ) Measured SBS.PackVoltage( ) Measured SBS.Voltage( ) calculated SBS.Voltage( )