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block convolutional interleaving

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vhdl code for interleaver

Abstract: vhdl code for block interleaver samples per second (MSPS) Supports convolutional interleaving algorithm Supports block interleaving , configurations based on user-defined parameters. For block interleaving, the MegaWizard Plug-In uses single-port RAM; for convolutional interleaving, the interleaver/deinterleaver function utilizes embedded array , index. The symbol interleaver/deinterleaver supports two algorithms: convolutional and block , ., digital video broadcasting). Compared to block interleavers/deinterleavers, convolutional interleavers
Altera
Original

convolutional interleaver

Abstract: Convolutional convolutional interleaving design that is optimized for PCS and cable modem applications. In FLEX 10K devices , convolutional interleaving applications, such as PCS and cable modems. The FLEX 10K EABs support a maximum , shows a functional block diagram of the convolutional interleaver megafunction. Figure 1. Convolutional Interleaver Megafunction Functional Block Diagram Convolutional Interleaver Megafunction , Convolutional Interleaver Megafunction Solution Brief 16 Target Applications: Digital Signal
Altera
Original

block convolutional interleaving

Abstract: convolutional interleaver convolutional interleaving design that is optimized for PCS and cable modem applications. In FLEX 10K devices , convolutional interleaving applications, such as PCS and cable modems. The FLEX 10K EABs support a maximum , shows a functional block diagram of the convolutional interleaver megafunction. Figure 1. Convolutional Interleaver Megafunction Functional Block Diagram Convolutional Interleaver Megafunction , Convolutional Interleaver Megafunction Solution Brief 16 Target Applications: Digital Signal
Altera
Original

interleaver

Abstract: "Single-Port RAM" convolutional interleaving algorithms Parameterized symbol width, depth, and block length Compatible with , convolutional Specifies a block or convolutional interleaver/deinterleaver. Number of columns Block , Specifies the unit delay for each branch of the function. Direction Block or convolutional , convolutional Specifies internal or external memory. Convolutional interleaving uses synchronous dual-port RAM; block interleaving uses synchronous single-port RAM. For internal memory, the MegaWizard
Altera
Original

vhdl code for interleaver

Abstract: vhdl code for block interleaver megasamples per second (MSPS) Supports convolutional interleaving algorithm Supports block interleaving , . Convolutional interleaving uses synchronous dual-port RAM. Block interleaving uses synchronous single-port RAM , a convolutional or a block interleaver/deinterleaver. Convolutional interleaver/deinterleaver , . Data Stream Comparison A A1 B B1 C Convolutional Interleaver A1 Block Interleaver C1 A1 B1 C1 B1 C1 2 Figure 2 illustrates convolutional interleaving and
Altera
Original

vhdl code for interleaver

Abstract: transistors BC 543 you enter. For block interleaving, the MegaWizard Plug-In uses single-port RAM; for convolutional , convolutional interleaving algorithm Supports block interleaving algorithm Parameterized symbol width and , a block interleaver/de-interleaver. Convolutional interleaver/de-interleaver functions process data , functions or Turbo Code encoders/decoders. Compared to block interleavers/de-interleavers, convolutional , A A1 B B1 C Convolutional Interleaver A1 Block Interleaver C1 A1 B1
Altera
Original

turbo encoder model simulink

Abstract: vhdl code for interleaver megasamples per second (MSPS) Supports convolutional interleaving algorithm Supports block interleaving , /Deinterleaver wizard interface to implement interleaving/deinterleaving functions, including block and convolutional interleaving. New in Version 1.3.0 Supports OpenCore® and OpenCore Plus hardware , the type of algorithm (convolutional or block) and the direction (interleaver or deinterleaver) and , shows a block diagram of a system using the convolutional interleaver/deinterleaver with a Reed-Solomon
Altera
Original

Interleaver-De-interleaver

Abstract: interleaver IEEE 802.16 Convolutional and Rectangular Block Type Architectures Available Fully Synchronous , Block Diagrams Figure 1. Convolutional Interleaver/De-interleaver Block Diagram rst_b d_out clk , correction. The Lattice Interleaver/De-interleaver IP Core supports rectangular block type and convolutional , obtained by reading the columns of the matrix. Convolutional interleaving feeds the input data to a number , for Input and Output Interfaces Rectangular Block Type Features Features High Performance and
Lattice Semiconductor
Original

vhdl code for interleaver

Abstract: vhdl code for block interleaver / Convolutional Interleaving Block Interleaving Discrete Streaming (RS)APEXFLEX DSP EEC , PlugIn 1 Convolutional Interleaver/Deinterleaver Block Interleaver/Deinterleaver Convolutional Interleaver/Deinterleaver Block Interleaver/Deinterleaver GSM Turbo Code Block Interleaver/Deinterleaver Convolutional Interleaver/Deinterleaver 1 1. A A1 8 B B1 C C1 Convolutional Interleaver Block Interleaver A1 A1 B1
Altera
Original

vhdl code for interleaver

Abstract: vhdl code for block interleaver -5, SpartanTM-3, and Spartan-3E FPGA families · Forney Convolutional and Rectangular Block type , generated with this core: Forney Convolutional and Rectangular Block. Although they both perform the general , 2 3 Output Data = {4, 8, 0, 5, 9, 1, 6, 10, 2, 7, 11, 3} Figure 4: Block Interleaving , Data = {6, 10, 2, 5, 9, 1, 7, 11, 3, 4, 8, 0} Figure 5: Block Interleaving Example with Row and , size. Representative symbols for the Forney Convolutional type and Rectangular Block type are shown in
Xilinx
Original

Block Interleaver

Abstract: correction. The Lattice Interleaver/de-interleaver IP core supports rectangular block type and convolutional , obtained by reading the columns of the matrix. Convolutional interleaving feeds the input data to a number , described in this chapter. Figure 2-1 shows a convolutional interleaver/de-interleaver block diagram. Figure , . Convolutional Interleaver/De-interleaver Block Diagram rstn dout clk obstart din ibstart inpvalid , . 10 Block Diagrams
Lattice Semiconductor
Original

Implementation of convolutional encoder

Abstract: DN504 FEC of FEC: linear block codes (BCH, Reed-Solomon, etc) and convolutional codes. An (n,k) linear block encoder takes k-bit block of message data and appends n-k redundant bits algebraically related to the k message bits, producing a n-bit code block. There are 2k valid code words, which is far less than the 2n possible code words, and a good linear block code is one in which the minimum distance dmin, the minimum , dimensionless ratio r = k/n is called the code rate. A convolutional encoder is fundamentally a finite state
Texas Instruments
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differential encoding in qam

Abstract: fpga based Numerically Controlled Oscillator words, and the interleaving is fixed at I = 12 x J = 17. Figure 4 shows the block diagram of an Annex A , . Figure 8 shows the convolutional encoder block diagram. 5 Versatile Digital QAM Modulator , indicates an error in transmission. Reed-Solomon corrects for block errors, which are typically caused by , modulation (TCM). See the "Trellis Coded Modulation" section for more information. Interleaving Data interleaving spreads data over a variable period of time in order to combat adjacent burst errors that the
Altera
Original

SiCOM

Abstract: SM370 . Selectable Error Correction Coding (PTCM, Convolutional Interleaving, Reed-Solomon) and Rotational , rates up to 60 MHz, applies Energy Dispersal and ReedSolomon Error Correction Coding, Convolutional Interleaving, Symbol Generation, Pulse Shaping, Transmitter Linearization, Interpolation, Modulation, Digital , Block Diagram depicts the SM7060 functional modules. Data input to the SM7060 is first processed by the , , the data passes through an (N,N-16) R/S Encoder which adds 16 parity bytes to every N-Byte block of
SiCOM
Original
SM37030 SiCOM SM370 QPSK Modulator block diagram N-16 EN-300-421 16QAM

rsc Encoder

Abstract: convolutional encoder interleaving module. Interleaving begins once a full block of data is received and stored into the dual port RAM. All , C.S0002-A - CCSDS 101.0-B-5 Up to 60 MHz Clock Speed Variable Input Block Sizes User Defined Number , secured simulation model - Behavioral testbench Block Diagram Figure 1. Turbo Encoder Block Diagram , recursive systematic convolutional (RSC) encoders. Each RSC encoder contains the same structure but operates , the second encoder operates on an "interleaved" version of data. Interleaving is the method in which
Lattice Semiconductor
Original
LFX500B-04F516C LFEC20E-5F672C rsc Encoder convolutional encoder interleaving Turbo Encoder interleaver convolutional ccsds

MC92053

Abstract: atm recommendation availability convolutional deinterleaving of the downstream payload blocks for the full range of interleaving depths (M = , external memory for convolutional interleaving of the downstream data. If the interleaving depth is very , interleaving depth is small (M 2) Performs Reed-Solomon encoding of the upstream frames and decoding of the , Figure 1. MC92052 Block Diagram This document contains information on a new product. Specifications and , When in the "out-of-frame" condition, the frame alignment block searches the serial data (which is LSB
Motorola
Original
MC92053 atm recommendation availability DSA0038472 MC68360 MC92052CG randomizer solomon MC92052/D

DVB-T Schematic set top box

Abstract: VIRTEX7-XC7VX485T KintexTM-7, Virtex ®-7, Spartan®-6, Virtex-6 Forney Convolutional and Rectangular Block type architectures , /de-interleavers can be generated with this core: Forney Convolutional and Rectangular Block. Although they both , . Unlike the Convolutional Interleaver, where symbols can be continuously input, the Rectangular Block , = {4, 8, 0, 5, 9, 1, 6, 10, 2, 7, 11, 3} Figure 4: Block Interleaving Example with Row , , 2, 5, 9, 1, 7, 11, 3, 4, 8, 0} Figure 5: Block Interleaving Example with Row and Column
Xilinx
Original
DVB-T Schematic set top box VIRTEX7-XC7VX485T Radix-10 forney interleaver by vhdl vhdl code for bit interleaver DS861 TM-7000 CDMA2000

1/3 Convolutional encoder

Abstract: rsc Encoder receives all the data in a block, the interleaving process begins. The interleaver module is required to , implemented in the interleaver module. Interleaving begins once a full block of data is received and stored , C.S0002-A - CCSDS 101.0-B-5 Up to 60 MHz Clock Speed Variable Input Block Sizes User Defined Number , secured simulation model - Behavioral testbench Block Diagram Figure 1. Turbo Encoder Block Diagram , when asserted. block_size Input 11-15 Block size up to 215 bits can be set depending on the
Lattice Semiconductor
Original
1/3 Convolutional encoder pin diagram encoder circuit diagram of encoder turbo encoder circuit encoder source code ip1018 OR4E02-2BA352

Convolutional Encoder

Abstract: CS3530 first convolutional encoder, and the second supplying the interleaved data block to the second , systematic storage, when read back, supplies the natural-order input data block to the first convolutional encoder, and the interleaver storage supplies the interleaved data block to the second convolutional , W-CDMA. Since 3G turbo coding forces a block structure on the convolutional code, a series of three , FEATURES Supports full range of W-CDMA and CDMA2000 data block lengths and coding rates
Amphion Semiconductor
Original
CS3530 Convolutional Encoder Block Interleaver time DS3530

IS54B

Abstract: 486DX state 0 to force the encoder to also return to the zero state. A block diagram of the convolutional encoder is show in Figure 3. 3 Figure 3. IS-54 Convolutional Encoding Block Diagram , Processing Block Diagram PCM Input Speech Samples Transmitter Interleave Bit Storage VSELP Encoder Class 2 Bits DQPSK Modulate Interleave Class 1 Bits Generate CRC Convolutional , Sync Class 2 Bits Convolutional Decode CRC Check 1 ­ CRC Pass 2 ­ CRC Fail 2 1
Texas Instruments
Original
SPRA135 IS54B 486DX TMS320 Viterbi Trellis Decoder texas VSELP motorola rAised cosine TMS320C5 IS-54B
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