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LM339DBLE Texas Instruments Quad Differential Comparator 14-SSOP 0 to 70
CD74FCT574M96 Texas Instruments BiCMOS FCT Interface Logic Octal Non-Inverting D-Type Flip-Flops with 3-State Outputs 20-SOIC 0 to 70
LINUXDVSDK-OMAP Texas Instruments Linux Digital Video Software Development Kits
SN74F158AN Texas Instruments Quadruple 2-Line To 1-Line Data Selectors/Multiplexers 16-PDIP 0 to 70
TMS320C541PZ2-40 Texas Instruments Digital Signal Processor 100-LQFP
PMP5334 Texas Instruments Boost (5V@2A) for Laser

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bc pro 450 CIRCUIT diagram

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: FELSIC HV (BC - BD) FELSIC 105 (BC - BD) FELSIC 105 LP - - - 470 000 450 1 500 - , thickness of about 40 Å 2. Schéma équivalent: 2. Diagram of the equivalent circuit: Rp RL CA , (2) FELSIC IND (BC - BD) 93.6, 94.6 FELSIC TFRS (CO 45) FELSIC UPS FELSIC 85 BC - FELSIC 039 FELSIC 85 BC - FELSIC 039 FELSIC 037 (CO 37) FELSIC 039 (CO 39) FELSIC 125 FRS FELSIC 85 480 V - 500 V FELSIC 105 77 x 220 FELSIC CAPAX - FELSIC 85 (BC - BD) FELSIC 105 TFRS (BC) (CO 45) FELSIC -
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capax 7-35 Felsic capacitors 125 FRS CO 47 Felsic capacitors FELSIC 018 CO 18 capacitor sic-safco felsic co 18 sic-safco capacitor FELSIC 037 CO 37
Abstract: c â¡ c c MOD/DTMF MC/BC RTS ENP DGND â¡ TxD PRD Xtal IN Xtal OUT DCD RxD ZCO , Diagram . ATxl V+ DGND V- AGND M88TS7514-03 2/21 r r z SGS-THOMSON Ã" 7# 62 , write operations to control registers (if MOD/DMTF = 0 and MC/BC = 0). MC/BC 2 3 Digital , circuit sends an analog signal to the ATO output. The signaL depends on the operating mode selected , and MC/BC = 0, the RTS pin acts as a clock for serial data loading into the input register. ENP -
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TS7514 DIP24 PLCC28 M88TS7514-13 M88TS7514-14 M88TS7514-15
Abstract: of many AGC systems, interdigitation, or crosscoupling, of critical portions of the circuit reduces , pro cessing, multiplexing, instrumentation amplifiers operating from the nanopower range to high , Plastic DIP 16 Lead Ceramic DIP Pinout CA3280 (PDIP, CDIP) TOP VIEW Functional Diagram Id , ai , * Output Short Circuit Duration , Sec.). +300°C ` Short circuit may be applied to ground or to either -
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ICAN-6668 CA3280E ICAN-6077 CA-3280E CA3280AE CA3280E equivalent CA3280A ICAN6818
Abstract: 450 800 800 450 800 - - - - - - - - - - Test conditions > m II U J U > BC BC BC BC BC BC , BC 208 Gr. C for BC 209 for BC 209 Gr. B for BC 209 G r. C 450 220 - 450 800 220 450 - 800 800 450 - 800 * Pulsed: pulse duration = 300 p.s, duty factor = 1% 68 BG 207 BC 208 BC 209 , -1 mA VCE = -12 V = 1 0 0 MHz = -1 mA VCE= -12 V = 450 kHz MHz PF 7.5 dB lc = -1 mA Vc e = - , = -1 mA VCE = -12 V = 450 kHz VCE = -12 V f = 200 MHz -320 -380 -430 mV -320 -380 -430 mV 20 50 -
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APC UPS CIRCUIT DIAGRAM rs 1500 APC UPS es 500 CIRCUIT DIAGRAM APC UPS 650 CIRCUIT DIAGRAM schematic diagram APC back ups XS 1000 TAA550 APC UPS CIRCUIT DIAGRAM AF106
Abstract: ] Terminal Equivalent Circuits Pin No. 1 Equivalent circuit 10 k 2 pF 2 pF 19 2 1 450 2 pF , 0.60±0.10 19 13 (0.44) 0.50 0.20±0.06 QFN024-P-0405A (Lead-free package) Block Diagram , disc na15 n ww wi co on nce anc g fo .se ng ntin tin14 ty e ty ur mi UR ue ued pe pe Pro co L a d t ty , ce c fo .se ng ntin tin ty e ty ur mi UR ue ued pe pe Pro co L a d t ty du n.p bo yp pe ct life an ut , value of signal source (output impedance 50 ) described in the " Application Circuit Example". di p Panasonic
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gmx matsua AN6227FHN
Abstract: Communications Block Diagram VCC (14) FIN1 FIN2 FIN3 FIN4 FIN (13 (13) LD (10) VMON (5) Loop Filter VCSO (8 , , 12) OD (6) Figure 1. Functional block diagram Page 1 of 10 Vectron International · 267 , LVPECL LVCMOS 3.46 100 VCC-1.4 450 VCC-2.4 250 tR tF SYM n n n n n n n J J TOP 45 VCC , 0 to 70 or -40 to 85 VCC-1.0 950 VCC-2.5 450 55 V mV p-p V mV p-p ns ns % dBc/Hz dBc/Hz dBc , Ordering Information. Parameters are tested with production test circuit below (Fig 2). Parameters are Vectron International
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ky 202 FX-400 FX-424 1-88-VECTRON-1 FX-400-XXX-SNNNN D-74924
Abstract: . 42 Symbol VAP BC 20 uA 360 42 1 k 60 k 30 k Equivalent circuit Description · Vertical contour , wi co on ce c fo .se ng ntin tin ty e ty ur mi UR ue ued pe pe Pro co L a d t ty du n.p bo yp pe ct , AN2101FH I Block Diagram CGAM R-Y in CGAM Y-B in CSW R-Y out CSW Y-B out Sync. mix. in Base clip out 1HGC out 2 HAP BC in 60 59 58 57 56 55 54 53 52 51 50 49 48 , CP2 LLSUP DA7 DL Base clip DL Base clip DL 41 40 HAP BC 39 Y out 38 Fade B/W 37 Edge test Pblic Panasonic
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dcp-20 n27m QFP080-P-1212 QFP080-P-1212A
Abstract: Technical catalogue System pro M compact® and other modular devices for low voltage installation System pro M compact® and other modular devices for low voltage installation In , STOTZ-KONTAKT GmbH http://www.abb.com 00 COP PRO M.indd 1 15-11-2006 14:47:55 SUMMARY , marks and approvals 01 PRO M.indd 1 11 14 24-11-2006 16:44:33 "New entries" . NE Three new ranges of special RCDs to complete System pro M compact range's offer: F200 400 Hz F200 B ABB Automation
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2CSC400002D0205 PR221DS sace tmax ABB RD2 earth leakage relay mccb 60947-2 max zs ABB Sace Tmax S941N C2 DDA200
Abstract: gm adjustable over 6 decades Excellent gm linearity Connection Diagram Dual-In-Line and Small , ) Output Short Circuit Duration Buffer Output Current (Note 3) 36 VqC or ± 1 8V 44 VDC or ± 22V 570 mW ± 5V , 20 mA See AN-450 " Surface Mounting Methods and Their Effect on Product Reliability" for other , = 5 fiA * iAbc - 500 p.A R l = 00.5 fiA Iabc 500 ju,a U bc = 500 /¿A, Both Channels A V o s /A V + A , , Input = ±4 V Iab c = 0 (Refer to Test Circuit) Differential Input Current Leakage Current nA nA -
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LM13600 RC 13600 13kil LM13600 NS DI00E LM136 LM13600N LM13600AN TL/H/7980-36
Abstract: Overview The AN2125FHS is a super single-chip IC, working as an image signal processing circuit for CCD , circuit for external synchronization · On-chip comparator for electronic iris Ma int en an , fo .se ng ntin tin ty e ty ur mi UR ue ued pe pe Pro co L a d t ty du n.p bo yp pe ct life an ut e d , 82 CSW R-YOUT Y GAMMA IN 85 HAP BC IN 88 VAP BC IN 89 0H GAMIN 76 GND 74 AGC OUT LLSUP IN 93 FADE , I Block Diagram 1HGC OUT2 Clamp CP2 CBLK LL SUP Base Clip Fade Cont. 75 Drive 6dB Amp. SYCP BUF Panasonic
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REGULATOR IC an7805 3 pins trimmer capacitor
Abstract: : SCLK Serial data: SIN Package Miscellaneous : SH-DIP-64, QFP-64 : Power-on reset circuit integrated , for display control by an external circuit, for example, for halftone display control. 53 54 55 56 , /monochrome display is controlled by an external circuit. (The following correspondence is used for , DIAGRAM MB90091A 8 MB90091A ABSO LUTE M AXIMUM RATINGS , SCLK Values Min. 1000 450 450 - Max. - - - 200 200 - - - - 200 200 Unit ns ns ns ns -
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1250HD DS04-28823-2E 1250HDTV 1125HDTV F9704
Abstract: : SCLK Serial data: SIN Package Miscellaneous SH-DIP-64, QFP-64 Power-on reset circuit integrated 2 , external circuit, for example, for halftone display control. 53 54 55 56 46 47 48 49 FSEL SCLK SIN , /monochrome display is controlled by an external circuit. (The following correspondence is used for , 002760=1 TTb MB90091A BLOCK DIAGRAM M B90091A 374T75L D27Ö10 71fl MB90091A , . 1000 450 450 - Max. - - - Unit ns ns ns ns ns ns ns ns ns ns ns tWCL tCR Shift clock -
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1125HD FIQT DIP-64P-M01 FPT-64P-M06 777-GND 374T7S MB90091AP MB90091APF
Abstract: Connection Diagram Dual-ln-Line and Small Outline Packages AMP BIAS INPUT DIODE BIAS INPUT INPUT BU FFER , ) Output Shorl Circuit Duration Buffer Output Current (Note 3) 36 V qc Or ± 18V 44 VDc or ± 22V 570 mW ± 5V , AN-450 " Surface Mounting Methods and Their Effect on Product Reliability" for other methods of , (Refer to Test Circuit) 5 1-632 \\ V dB dB nA nA < < 20 150 150 20 150 150 , Compensated (Note 5), Except I^ bc = 0 jiA (Note 5) 10 Conditions Min 10 LM 13600 Typ 26 2 50 0 .2 -
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schematic of lm 13600 1647T m13600 LM13600M
Abstract: standard June 1988 717 ET2716/ M2716 BLOCK DIAGRAM « V P P»5 V 4 V C C* 5 V 4 - V S SG N , Min. - - - 0 0 0 M ax. 450 450 120 100 - 100 Unit TAVQV TELQV TGLQV TGHQZ TAXQX TEHQZ , removed after or at the sam e tim e as V p p Typical conditions are for operation at: T A » 2 5 BC , V C , Reference Level Inputs, Outputs 0.8V and 2V AC TESTING INPUT/OUTPUT WAVEFORM AC TESTING LOAD CIRCUIT , higher) must not be maintained lon ger than tpwiMAX)on the program pin during pro gramming. M/ET2716's -
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M2716F1 M2716-1F1 ET2716Q-1 M2716-F1 M27161F ET2716 M/ET2716-1 AO--A10 CL45V STAN08Y ET2716Q
Abstract: Diagram Features IC W O R KS BiCMOS process O SCJN 0r NC Operating voltage 2.7V to 5.5V , Block Diagram - Prescaler 32/33 or 64/65 ( 10 ) Binary 7-Bit Swallow Counter 4 VP , Application Diagram Example - WB1225 2.5GHz PLL -IN . C2 ii H h a R2 R C3 > ill , Max Unit mA 180 2.5 ma Input Sensitivity F in 45.0 MHz MHz 2 4 -1 5 , accordingly: W hen VCO characteristics are like (1), FC should be set HIGH or OPEN CIRCUIT: VCO Output -
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WB1225ZX-TR B1225
Abstract: very accurate system clock timing. ,!.'`~~~i., *,~,~.>.,., An eighth latched input, D7, is pro , ~~e @BC's, at the expense of only a single added line tq,~~dwa bus for each additional PDC, without , 3380 1275 300 1390 3630 1475 450 Mtaa 1540 3880 1675 700 700 I ps T & 6 , to the ln~t 225 450 325 650 125 trom the cross point of the input to the c- signal , from 31.75 gates to 32 gates. A tured below. Use of this diagram will simplify~~~~:~l%nation of how Motorola
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OOE195 D70f EL95 Y14W MC10E195/D MCIOE195 MK145BP
Abstract: characteristic of m any AG C system s. Interdigitation, or crosscoupling, of critical portions of the circuit , Proceedings, December 1969 Functional Diagram Pinout CA3280 (PDIP, CERDIP) TOP VIEW 16] +IN , A1 15 , Circuit Duration (Note 3 ) .Indefinite Linearizing Diode Bias Current , indicated in the operational sections o f this specification is not implied. NOTES: 2. Short circuit may , PARAMETER TYP MAX MIN TYP MAX UNITS 350 450 550 350 450 550 HA I d -
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CD4013 equivalent AN6818 A3280 CA3280AF3
Abstract: The TS7514 is an FSK modem which can be pro grammed tor asynchronous halt-duplex voice-band , M C/BC Q RTS Q ENP Q DG ND ^ TXD Q PRD Q X T A L IN XTAL O UT DCD Q RXD Q zco ^ 1 2 3 4 5 6 7 8 , Selection. Also controls write operations to control registers (if MO D/D MTF = 0 and MC/BC = 0). Digital , of dialing or control registers programming. Request to Send. When RTS = 0, the circuit sends an , sianal sent to ATO is suDDressed after its first zero crossina. When MOD/DMTF = 0 and MC/BC = 0, the RTS -
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3.579MHz crystal FZJ 141 SGS BC 141 579MH TS7514CP TS7514CFN
Abstract: Diagram Features IC W ORKS BiCMOS process 0r O SCJN NC Operating voltage 2.7V to 5.5V , Option Note: Operating temperature range: -40°C to +85°C. Figure 2 WB1225 PLL Block Diagram , Figure 3 Application Diagram Example - WB1225 2.5GHz PLL i-| . C2 R2 'IH H / V W ; C3 , ), FC should be set HIGH or OPEN CIRCUIT: VCO Output Frequency When VCO characteristics are like (2), FC should be set LOW. When FC is set HIGH or OPEN CIRCUIT, Fout pin is set to the reference -
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WB1225UX-TR
Abstract: ID - P B0, » |~ P B , 1 ~ PBos I/O PORTS Bc 00 0 ro cn o\ > C /3 u Ü - PB, E I~ p b o 3 Ü , Block diagram of the M5M82C255ASP is shown in the following page. The M5M82C255ASP consists of block 0 , 82C 255A SP CMOS P R O G R A M M A B LE P E R IP H E R A L IN TERFACE BLOCK DIAGRAM CH IP , « M 5M 82C 255A SP CMOS PRO G R A M M A B LE P E R IP H E R A L IN TER FACE FUNCTIONAL DESCRIPTION , MITSUBISHI ELECTRIC M ITSUBISHI L S Is M 5M 82C 255A SP CMOS PRO G R A M M A B LE P E R IP H E R A L -
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M5M82C255 m5l8085ap m5m82c55AP-2 5m82c255 M5M82C55AP2 M5M82C55AP M5M82C55AP-2 255ASP
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