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LT1103CY Linear Technology IC SWITCHING CONTROLLER, Switching Regulator or Controller visit Linear Technology - Now Part of Analog Devices
LT1945IMS Linear Technology IC 0.4 A DUAL SWITCHING CONTROLLER, PDSO8, PLASTIC, MSOP-10, Switching Regulator or Controller visit Linear Technology - Now Part of Analog Devices
LTC3830DWF Linear Technology IC SWITCHING CONTROLLER, 250 kHz SWITCHING FREQ-MAX, UUC, DIE, Switching Regulator or Controller visit Linear Technology - Now Part of Analog Devices
LTC3830DICE Linear Technology IC SWITCHING CONTROLLER, 250 kHz SWITCHING FREQ-MAX, UUC, DIE, Switching Regulator or Controller visit Linear Technology - Now Part of Analog Devices
LT3524S Linear Technology IC SWITCHING CONTROLLER, PDSO, Switching Regulator or Controller visit Linear Technology - Now Part of Analog Devices
LT1103IY Linear Technology IC 2 A SWITCHING CONTROLLER, PSFM7, TO-220, 7 PIN, Switching Regulator or Controller visit Linear Technology - Now Part of Analog Devices

axi compliant ddr3 controller

Catalog Datasheet MFG & Type PDF Document Tags

rk3188

Abstract: RK3188-T 10/100MEthernet Controller Â" IEEE802.3u compliant Ethernet Media Access Controller(MAC) Â" Support , memory interface(DDR3/LPDDR2/LVDDR3) capable of sustaining demanding memory bandwidths, also provides a , DDR3-800, LPDDR2-800, LVDDR3-800 z Totally 3-channels SD/MMC interface to support MMC4.41, SD3 , Cache controller + L2 Dataram, and including PD_A9_0, PD_A9_1, PD_A9_2, PD_A9_3, PD_DGB One isolated , memory Â" DDR3-800, 16/32bits data widths, 2 ranks, totally 2GB(max) address space, maximum address
Rockchip
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rk3188 RK3188-T ARGB888 emmc boot sequence RK3188T RK3188 264/MVC/VP8 DDR3-800 BT656 BT601

zynq axi ethernet software example

Abstract: AMBA AXI dma controller designer user guide interface modules. The dynamic memory controller supports DDR3, DDR3L, DDR2, and LPDDR2 memories. The static , set of dedicated I/Os. Speed of up to 1333 Mb/s for DDR3 is supported. The DDR memory controller is , memory. The DDR controller features four AXI slave ports for this purpose: · · · One 64-bit port is , SGMII interfaces Two USB 2.0 OTG peripherals, each supporting up to 12 Endpoints · USB 2.0 compliant device IP core · Supports on-the-go, high-speed, full-speed, and low-speed modes · Intel EHCI compliant
Xilinx
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zynq axi ethernet software example AMBA AXI dma controller designer user guide XC7Z020 ZYNQ-7000 Xilinx Z-7020 DDR3L lpddr2 DS190 TM-7000
Abstract: memory controller â'¢ Timer and Interrupts â'¢ 16-bit or 32-bit interfaces to DDR3, DDR2, or , and static memory interface modules. The dynamic memory controller supports DDR3, DDR2, and LPDDR2 , access to a common memory. The DDR controller features four AXI slave ports for this purpose: â , host controller registers and data structures Two full CAN 2.0B compliant CAN bus interface , -bit) serial NOR flash 8-Channel DMA Controller â'¢ Memory-to-memory, memory-to-peripheral Xilinx
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DS188 Z-7010 Z-7020 Z-7030

CLG225

Abstract: UG585 ) Byte-parity support Multiprotocol dynamic memory controller â'¢ 16-bit or 32-bit interfaces to DDR3 , modules. The dynamic memory controller supports DDR3, DDR3L, DDR2, and LPDDR2 memories. The static memory , own set of dedicated I/Os. Speed of up to 1333 Mb/s for DDR3 is supported. The DDR memory controller , to a common memory. The DDR controller features four AXI slave ports for this purpose: â'¢ One 64 , high speed and full speed modes Intel EHCI compliant USB host controller registers and data
Xilinx
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CLG225 UG585 zynq7000

XA7Z020

Abstract: CLG225 controller and static memory interface modules. The dynamic memory controller supports DDR3, DDR2, and LPDDR2 , set of dedicated I/Os. Speed of up to 1066 Mb/s for DDR3 is supported. The DDR memory controller is , memory. The DDR controller features four AXI slave ports for this purpose: · · · One 64-bit port is , PHY interface Intel EHCI compliant USB host controller registers and data structures CAN 2.0 , External Memory Interfaces · · · · Multiprotocol dynamic memory controller 16-bit or 32-bit interfaces to
Xilinx
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XA7Z020 XA7Z020-1CLG484I HSTL RGMII XA7Z010 CLG484 ARm cortexA9 GPIO
Abstract: '¢ Multiprotocol dynamic memory controller â'¢ 16-bit or 32-bit interfaces to DDR3, DDR3L, DDR2, or LPDDR2 , to have shared access to a common memory. The DDR controller features four AXI slave ports for this , EHCI compliant USB host controller registers and data structures Two full CAN 2.0B compliant CAN bus , controller and the third goes to the dual-ported on-chip memory (OCM). Each high-performance AXI port has , '¢ USB 2.0 compliant device IP core â'¢ Supports on-the-go, high-speed, full-speed, and low-speed Xilinx
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DS196

ZYNQ-7000

Abstract: xc7z020 dynamic memory controller and static memory interface modules. The dynamic memory controller supports DDR3 , logic to have shared access to a common memory. The DDR controller features four AXI slave ports for , PHY interface Intel EHCI compliant USB host controller registers and data structures CAN 2.0 , SGMII interfaces Two USB 2.0 OTG peripherals, each supporting up to 12 Endpoints · USB 2.0 compliant device IP core · Supports on-the-go, high-speed, full-speed, and low-speed modes · Intel EHCI compliant
Xilinx
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FFG676 xc7z030 Z-7045 axi interface ddr3 memory controller UG480 axi compliant ddr3 controller LPDDR2 1Gb Memory

Z-7020

Abstract: ) Byte-parity support Multiprotocol dynamic memory controller â'¢ 16-bit or 32-bit interfaces to DDR3 , modules. The dynamic memory controller supports DDR3, DDR3L, DDR2, and LPDDR2 memories. The static memory , own set of dedicated I/Os. Speed of up to 1333 Mb/s for DDR3 is supported. The DDR memory controller , to a common memory. The DDR controller features four AXI slave ports for this purpose: â'¢ One 64 , high speed and full speed modes Intel EHCI compliant USB host controller registers and data
Xilinx
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Abstract: ) Byte-parity support Multiprotocol dynamic memory controller â'¢ 16-bit or 32-bit interfaces to DDR3 , modules. The dynamic memory controller supports DDR3, DDR3L, DDR2, and LPDDR2 memories. The static memory , own set of dedicated I/Os. Speed of up to 1333 Mb/s for DDR3 is supported. The DDR memory controller , to a common memory. The DDR controller features four AXI slave ports for this purpose: â'¢ One 64 , high speed and full speed modes Intel EHCI compliant USB host controller registers and data Xilinx
Original
Abstract: '¢ Multiprotocol dynamic memory controller â'¢ 16-bit or 32-bit interfaces to DDR3, DDR3L, DDR2, or LPDDR2 , to have shared access to a common memory. The DDR controller features four AXI slave ports for this , EHCI compliant USB host controller registers and data structures Two full CAN 2.0B compliant CAN bus , '¢ USB 2.0 compliant device IP core â'¢ Supports on-the-go, high-speed, full-speed, and low-speed modes â'¢ Intel EHCI compliant USB host â'¢ 8-bit ULPI external PHY interface â'¢ 32 KB Level Xilinx
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FBG676

Abstract: Bring-up: Enables hands-on operation with the base TRD, which features PCIe, DDR3 memory, AXI stream interconnect, and AXI virtual FIFO controller IP coresâ'"all supported through a custom evaluation graphical , Target - Figure 14 64 bits at 800 Mb/s XADC DDR3 IO UCD90120A AXI MIG Power and , controller from NorthWest Logic and DDR3 64-bit SODIMM memory operating at 800 Mb/s. Artix-7 FPGA Base TRD , IP AXI4 Stream Interconnect PG038, LogiCORE IP AXI VFIFO Controller UG952, AC701 Evaluation Board
Xilinx
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FBG676 UG967 2002/96/EC

axi interface ddr3 memory controller

Abstract: M2S050-1FG484I controller is compliant with the Motorola SPI, Texas Instruments synchronous serial, and National , . Users would then instantiate a soft AHB or AXI SDRAM memory controller in the FPGA fabric and connect I , ), memory protection unit (MPU), 8 Kbyte instruction cache, and additional peripherals, including controller , )/DDR3 memory controllers provide high speed memory interfaces. SmartFusion2 Family Reliability · · , in MSS PCI Express (PCIe) Endpoint Controller x1, x2, x4 Lane PCI Express Core Up to 2 Kbytes Maximum
Microsemi
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M2S050-1FG484I M2s010-fgg484 M2S050-FG484 M2S050T-1FG484I M2S120T-1FC1152I M2S005-VF400 51700115PB-5/2
Abstract: ) can be obtained by instantiating a soft AHB or AXI SDRAM memory controller in the FPGA fabric and , are initiated though this block. SPI The serial peripheral interface controller is compliant with , /deserialization (SERDES) communication, while double data rate 2 (DDR2)/DDR3 memory controllers provide high , '" Supports LPDDR/DDR2/DDR3 â'" Maximum 333 MHz Clock Rate â'" SECDED Enable/Disable Feature â , Fabric or an SGMII Interface to a soft Ethernet MAC â'" PCI Express (PCIe) Endpoint Controller Microsemi
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51700121PB-5/12

M2GL150T-1FCG1152I

Abstract: peripheral interface controller is compliant with the Motorola SPI, Texas Instruments synchronous serial , /deserialization (SERDES) communication, while double data rate 2 (DDR2)/DDR3 memory controllers provide high , ) HPMS DDR (MDDR) and Fabric DDR (FDDR) Controllers â'" Supports LPDDR/DDR2/DDR3 Up to 240 , SGMII Interface to the Ethernet MAC in HPMS â'" PCI Express (PCIe) Endpoint Controller x1, x2 , a Soft SDRAM Memory Controller High Performance Memory Subsystem â'¢ 64 KB Embedded SRAM
Microsemi
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M2GL150T-1FCG1152I 51700121PB-1/6
Abstract: internal coefficient memory â'¢ Preadder/subtractor for improved efficiency Memory controller DDR3 , support up to two hard memory controllers for DDR3, DDR2, and LPDDR2 SDRAM devices. Each controller , . For the Cyclone V SoC FPGA devices, an additional hard memory controller in the HPS supports DDR3 , (EMAC), USB 2.0 On-The-GO (OTG) controller, quad serial peripheral interface (QSPI) flash controller, NAND flash controller, Secure Digital/MultiMediaCard (SD/MMC) controller, UART, controller area Altera
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CV-51001

QSFP28 I2C

Abstract: controller with support for DDR4, DDR3, DDR2, LPDDR2 â'¢ 40-bit (32-bit + 8-bit ECC) with select packages , 10.3125 Gbps transceiver data rate (chip to chip) Memory devices supported 28.05 Gbps DDR3 SDRAM @ 667 MHz/1333 Mbps DDR4 SDRAM @ 1333 MHz/2666 Mbps DDR3 SDRAM @ 1067 MHz/2133 Mbps Hybrid Memory , /2666 Mbps DDR4 external memory interface 1067 MHz/2133 Mbps DDR3 external memory interface 1.2 V to , Gen1/Gen2/Gen3 complete protocol stack, x1/x2/x4/x8 end point and root port â'¢ DDR4/DDR3/DDR3L/DDR3U
Altera
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QSFP28 I2C AIB-01023

M2S150

Abstract: MS2025 ULPI Interface â'¢ CAN Controller, 2.0B Compliant, Conforms ISO11898-1, 32 Transmit and 32 , peripheral interface controller is compliant with the Motorola SPI, Texas Instruments synchronous serial , . Users would then instantiate a soft AHB or AXI SDRAM memory controller in the FPGA fabric and connect I , instruction cache, and additional peripherals, including controller area network (CAN), Gigabit Ethernet, and , /deserialization (SERDES) communication, while double data rate 2 (DDR2)/DDR3 memory controllers provide high
Microsemi
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M2S150 MS2025 51700115PB-12/10

axi compliant ddr3 controller

Abstract: M85000 >> DDR3 Memory Controller with ECC Single block of low cost memory supports all external memory needs , for FFT, DCT, and filter processing operations. A single DDR3 memory controller, configurable for , supported through 64-bit AXI, 64-bit AHB, and APB buses, with multiple dedicated DMA engines, allowing all , -2, HMAC · Indus trial temp range · M ulti-layer 64bit AR M AXI bus · Two independently c , time slots total - H.100/H.110 compliant F or more produc t information, pleas e vis it www.minds
Mindspeed Technologies
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M85000 arm cortex a9 comcerto cortex a9 CORTEX-A9 85000G

T3150

Abstract: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 DDR3 Memory , Transcede 3xxx DDR3 SDRAM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . .92 DDR3 SDRAM Device Interface Timing . . . . . . . . . . . . . . . . . . , Access Controller (GMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 8.1 , 20.6.2.1 MAP Master Controller (MC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mindspeed Technologies
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T3150
Abstract: internal coefficient memory â'¢ Preadder/subtractor for improved efficiency Memory controller DDR3, DDR2 , (OTG) controller, quad serial peripheral interface (QSPI) flash controller, NAND flash controller, Secure Digital/MultiMediaCard (SD/MMC) controller, UART, controller area network (CAN), serial , peripheralsâ'"general-purpose timers, watchdog timers, direct memory access (DMA) controller, FPGA configuration manager, and , transactions to slaves in the HPS, and vice versa â'¢ FPGA-to-HPS SDRAM controller subsystemâ'"provides a Altera
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