NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Samples | Ordering |
| AD8283WBCPZ | Analog Devices | Radar Receive Path AFE: 6-Channel LNA/PGA/AAF with ADC Package: 72 ld LFCSP (10x10mm, 8.5mm exposed pad); No of Pins: 72; Temperature Range: AUTOMOTIVE; Container: 168/Tray | 
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| AD8283WBCPZ-RL | Analog Devices | Radar Receive Path AFE: 6-Channel LNA/PGA/AAF with ADC Package: 72 ld LFCSP (10x10mm, 8.5mm exposed pad); No of Pins: 72; Temperature Range: AUTOMOTIVE; Container: 2000/Reel |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: 5000V Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks , HIGH-DENSITY IN-SYSTEM PROGRAMMABLE LOGIC 3.3V Power Supply User Selectable 3.3V/2.5V I/O 18000 PLD Gates , Reprogrammable Non-Volatile Programmable Speed/Power Logic Path Optimization · IN-SYSTEM PROGRAMMABLE , , programmable AND-array with 160 logic product terms and 5 extra control product terms. The GLB has 68 inputs , term. The 160 product terms are grouped in 32 sets of five and sent into a Product Term Sharing Array ... | Original |
2 pages, |
32X32 application of programmable array logic datasheet abstract |
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| Abstract: Programmable array logic Personal computer Printed circuit board Peripheral component interconnect Plastic , Complex programmable logic device Central processing unit Ceramic quad flat pack Cyclic redundancy code , test Embedded array block Electronic application utility Electronic design automation EDIF Input , Format Electrically erasable programmable read-only memory Erasable programmable logic device Erasable , Field-programmable gate array File transfer protocol Generic array logic Graphic Design File (.gdf) Gunning ... | Original |
4 pages, |
UV A led .pof "Low Voltage Differential Signaling" J-Lead, QFP ceramic Erasable Programmable Logic Device BGA and QFP Package vhdl code for asynchronous fifo "Content Addressable Memory" TRANSISTOR ARRAY system design using pll vhdl code peripheral component interconnect mtbf dual transceiver datasheet abstract |
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| Abstract: Production is often started using the same programmable logic in which the application was designed. This , versus Full ASIC Gate Array Implementation Converting a device from programmable logic to a HardWire , programmable logic. Working Xilinx FPGA Design Generic Gate Array · Convert netlist to G/A format · , attributes of the HardWire Arrays are virtually identical to the programmable logic devices. Xilinx uses the , lower cost for that unit, while maintaining the ease-of-use of off-the-shelf programmable logic in the ... | Original |
4 pages, |
XC95144 equivalent XC2000 XC3000 XC3000L XC4000 XC4000E XC4300 XC4305 XC4313 XC4400 XC4403 XC4408 xc4413 XC5000 XC5406 datasheet abstract |
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| Abstract: in internal or external logic. The fixed delay, regardless of programmable interconnect array , without increasing the number of product terms in each macrocell. Logic Array Blocks There are 12 logic array blocks in the CY7C341 CY7C341. Each LAB consists of a macrocell array containing 16 macrocells, an , bidirectional I/O pins 0.8-micron double-metal CMOS EPROM technology Programmable interconnect array 384 , CY7C341 CY7C341 is an Erasable Programmable Logic Device (EPLD) in which CMOS EPROM cells are used to configure ... | Original |
2 pages, |
CY7C341B CY7C341 7400 series logic ICs CY7C341B abstract |
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| Abstract: Programmable Logic Device (CPLD) providing insystem reprogrammability (ISR) and full Joint Test Action Group , product term matrix. Each logic block in the Ultra39000 architecture is connected through a Programmable , LOGIC LOGIC BLOCK I/O BLOCK BLOCK BLOCK BLOCK BLOCK I/O Programmable , UltraLogict 384Macrocell CPLD Features D D D D D D D D D D 384 macrocells in 24 logic blocks , Programmable speed/power options 192 I/O pins 4 dedicated inputs/clocks No hidden delays High speed f t ... | Original |
1 pages, |
7C39384 7C39384 abstract |
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| Abstract: Ultra39320 is a highdensity, high performance Complex Programmable Logic Device (CPLD) providing insystem , product term array and a fast, intelligent product term matrix. Each logic block in the Ultra39000 , application being im plemented. Logic Block Diagram I/O I/O I/O I/O LOGIC LOGIC LOGIC LOGIC LOGIC BLOCK I/O I/O BLOCK BLOCK BLOCK BLOCK I/O Programmable , UltraLogict 320Macrocell CPLD Features D D D D D D D D D D 320 macrocells in 20 logic blocks ... | Original |
1 pages, |
ieee1149.1 cypress application of programmable array logic 7C39320 7C39320 abstract |
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| Abstract: Signetics PLHS173 PLHS173 Field Programmable Logic Array (22 x 42 x 10) Application Specific Products • , Application Specific Products • Series 24 Objective Specification Field Programmable Logic Array (22x42x10 , achieved in devices of this complexity. The PLHS173 PLHS173 is a two-level logic element consisting of 42 AND , of EX-OR gates for implementing AND/OR or AND/NOR logic functions. The PLHS173 PLHS173 is field-programmable , DIAGRAM Signetics Programmable Logic Objective Specification FEATURES • Field Programmable (Ni-Cr links ... | OCR Scan |
2 pages, |
signetics 24 SIGNETICS or gates PLHS173 PLS173 application of programmable array logic "OR Gates" and gates logic gates pin configuration pin configuration of logic gates PLHS173 abstract |
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| Abstract: CMOS Programmable Electrically Erasable Logic Device Advanced Product Information â- > GOULD , inputs, 10 I/O pins -Dual programmable logic arrays: AND (36 inputs X 42 product terms) OR (20 sum terms , array -Security from unauthorized copying -Signature word for user specified ID • Application , the PEEL18CP210 PEEL18CP210 include replacement of random SSI/MSI logic circuitry and a wide range of , and development tools from Gould. PEEL18CP210/PEEL153 PEEL18CP210/PEEL153 Logic Array Diagram TTTTTTTTTTTTTYTTYTT ... | OCR Scan |
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application of programmable array logic PEEL18CP210 ICT Peel Gould Electronics 82S153 PLS153 PEEL153 PEEL programming 18CP210 18CP210 abstract |
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| Abstract: performance Complex Programmable Logic Device (CPLD) providing insystem reprogrammability (ISR) and full , logic blocks. Each log ic block contains 16 macrocells along with a product term array and a fast , parameters that are not dependent on the device resources uti lized or the type of application being im , /O Programmable LOGIC LOGIC LOGIC LOGIC BLOCK I/O BLOCK BLOCK BLOCK , macrocells in 16 logic blocks InSystem Reprogrammable (ISRt) Fully PCI compliant Full JTAG compatibility ... | Original |
1 pages, |
7C39256 7C39256 abstract |
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| Abstract: AND array and a fixed OR array make possible a wide variety of logic functions. Device functionality , save product terms. The programmable AND array contains a total of thirty-two product terms. Product , current Areas of Application High-performance communication equipment Glue logic joining ECL gate arrays , INFORMATION Features/Benefits • 20 logic Inputs; 12 external, 8 feedback • (I outputs • Programmable , SKINNYDIP® package • Programmable using standard TTL programmers Description The PAL10H20P8 PAL10H20P8 is a 10KH ... | OCR Scan |
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PAL10H20P8 application of programmable array logic 303AE EPP-80 Monolithic Memories palasm PAL10H20P8 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| Clear Logic, Inc. Clear Logic is a fabless manufacturer of Laser-configured Application Specific Integrated Circuit (LASIC Programmable Gate Array (FPGA) products into lower cost and lower power LASIC implementations. Clear Logic trademark of Altera Corporation. Clear Logic and LASIC are trademarks of Clear Logic, Inc. If you solution. The company has developed a new ASIC chip architecture that radically simplifies the task of www.datasheetarchive.com/files/scantec/clogic/clogic-cd/noframes.htm |
Scantec | 15/06/1998 | 3.86 Kb | HTM | noframes.htm |
| Clear Logic Company Profile Legal Notice This website contains information and materials related to products and services of Clear Logic, Incorporated ("Clear Logic"). These " without any express or implied warranty of any kind. In no event shall Clear Logic or its suppliers be site, even if Clear Logic has been advised of the possibility of such damages. Because some of the information, text, graphics, links or other items contained within this website. Clear Logic www.datasheetarchive.com/files/scantec/clogic/clogic-cd/legal.htm |
Scantec | 02/04/1998 | 2.54 Kb | HTM | legal.htm |
| Xilinx. CPLD: Complex Programmable Logic Device Embedded Array: A hybrid of gate array and Xilinx Answer #2736 : Glossary of terms - programmable logic(CPLD, FPGA), ASIC etc !!! -> of Page Banner -> Answers Database Glossary of terms - programmable logic(CPLD, FPGA : Glossary of terms ASIC: Application Specific Integrated Circuit Channeled array: A set of . CLB: Complex Logic Block-the array of multi-input and multi-output logic cells to be programmed www.datasheetarchive.com/files/xilinx/docs/rp00012/rp012aa.htm |
Xilinx | 29/02/2000 | 6.74 Kb | HTM | rp012aa.htm |
| of terms - programmable logic(CPLD, FPGA), ASIC etc. Problem Description: Keywords: programmable logic, CPLD, FPGA, ASIC, LUT, gate array, standard cell, sea of gates Urgency: Standard Book from Xilinx. CPLD: Complex Programmable Logic Device Embedded Array: A hybrid of gate Xilinx Answer #2736 : Glossary of terms - programmable logic(CPLD, FPGA), ASIC etc Database Glossary of terms - programmable logic(CPLD, FPGA), ASIC etc www.datasheetarchive.com/files/xilinx/docs/wcd00009/wcd0092a-v1.htm |
Xilinx | 16/02/1999 | 6.08 Kb | HTM | wcd0092a-v1.htm |
| of terms - programmable logic(CPLD, FPGA), ASIC etc. Problem Description: Keywords: programmable logic, CPLD, FPGA, ASIC, LUT, gate array, standard cell, sea of gates Urgency: Standard Book from Xilinx. CPLD: Complex Programmable Logic Device Embedded Array: A hybrid of gate Xilinx Answer #2736 : Glossary of terms - programmable logic(CPLD, FPGA), ASIC etc Database Glossary of terms - programmable logic(CPLD, FPGA), ASIC etc www.datasheetarchive.com/files/xilinx/docs/wcd00008/wcd008dc.htm |
Xilinx | 17/07/1998 | 5.99 Kb | HTM | wcd008dc.htm |
| -NRE CONVERSION OF ALTERA FPGAS Oct 13, 1997 STARTUP TO OFFER QUICK, NO-NRE FPGA-TO-ASIC CONVERSION Sep 15, 1997 CLEAR LOGIC APPOINTS RICHARD OTSUKA VICE PRESIDENT OF SALES Sep 1, 1997 BEEKLEY, KNOWLTON KICK Clear Logic Press Releases Press Releases Click on a press release CONVERSIONS OF ALTERA FLEX 8000 FPGAS Feb 23, 1998 NEW TECH SOLUTIONS OFFERS NO-NRE ASIC CONVERSIONS OF LOGIC Jan 19, 1998 CLEAR LOGIC CONVERTS ALTERA FLEX® 8000 DESIGNS TO LASIC™ DEVICES IN A WEEK, WITH www.datasheetarchive.com/files/scantec/clogic/clogic-cd/index(1).html |
Scantec | 02/04/1998 | 3.44 Kb | HTML | index(1).html |
| Gate Arrays/Embedded Arrays - Application Notes EPROM Field Programmable Gate Array Flash Memory/DataFlash FPGA Configuration Memory FPSLIC Gate Arrays/ Embedded Arrays Parallel EEPROM Power Metering Programmable Updated: January 30, 2000 Gate Arrays/Embedded Arrays - Application Notes ASIC Design Translation (6 pages, updated 9/97) "This Application Note describes the types of data required www.datasheetarchive.com/files/atmel/atmel/prod81-v5.htm |
Atmel | 30/01/2000 | 21.1 Kb | HTM | prod81-v5.htm |
| quick overview PROGRAMMABLE ARRAYS Welcome to the world of FPGAs. Field programmable logic and in particular, field programmable arrays, have become the solution of choice for logic portions of the design to prove implementation feasibility. Many programmable logic solutions are not push schedule. If the hardware design is realized in programmable logic, the hardware can be manipulated as . Programmable logic not only vastly improves the time necessary to implement a static design, but significant www.datasheetarchive.com/files/motorola/design-n/fpga/quickove.htm |
Motorola | 25/11/1996 | 4.47 Kb | HTM | quickove.htm |
| Gate Arrays/Embedded Arrays - Application Notes Complex ASIC Cores Dream Sound Synthesis EPROM Field Programmable Gate Array Parallel EEPROM Power Metering Programmable Logic Device Secure Memories Secure Updated: May 15, 2001 Gate Arrays/Embedded Arrays - Application Notes ASIC Design of any particular CAD tool or silicon process. They are applicable to Gate Arrays, Cell-Based ASICs www.datasheetarchive.com/files/atmel/atmel/prod81.htm.bak |
Atmel | 16/05/2001 | 21.73 Kb | BAK | prod81.htm.bak |
| Gate Arrays/Embedded Arrays - Application Notes Complex ASIC Cores Dream Sound Synthesis EPROM Field Programmable Gate Array Parallel EEPROM Power Metering Programmable Logic Device Secure Memories Secure Updated: May 15, 2001 Gate Arrays/Embedded Arrays - Application Notes ASIC Design of any particular CAD tool or silicon process. They are applicable to Gate Arrays, Cell-Based ASICs www.datasheetarchive.com/files/atmel/atmel/prod81-v3.htm |
Atmel | 20/05/2001 | 21.75 Kb | HTM | prod81-v3.htm |