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and logic gate pdf

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Abstract: differential amplifier input and logic gate output. The input amplifier is referenced to zero volts and employs , and TTL circuits. APPLICATIONS Zero-Crossing Detector High Stability One-Shot Bi-Directional , CIRCUIT SCHEMATIC TIMING R, •o-W- 3? NOTE Pins 5, 6, 8, and 10 are tied to pin 14 through isolation , Sine wave inputs up to approximately 500 kHz are limited, amplified and used lo trigger the timing , integrated and then filtered to attenuate the remaining high frequency carrier components- EggnnfiGE 719 ... OCR Scan
datasheet

3 pages,
75.94 Kb

lt 719 8T363 frequency doubler 500 va sine wave ups circuit high voltage doubler circuit zero crossing detector isolation diodes AC Zero detector "Frequency To Voltage" in916 frequency to voltage converter B885 8T363 abstract
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Abstract: 8T363 8T363 N DESCRIPTION Th e 8T 363 D ual Zero C ro ssin g Detector is an interface circuit incorporating a differential amplifier input and logic gate output. Th e input amplifier is referenced to zero volts and em ploys tem perature com pensation to ensure stable thresholds. The output structure of the 8T 3 6 3 is compatible with D T L and T T L circuits. PIN CONFIGURATION APPLICATIONS Z e ro -C ro ssin g Detector High Stability O n e -Sh o t Bi-Directional O n e -Sh o t Frequency Doubler ... OCR Scan
datasheet

3 pages,
139.86 Kb

AND LOGIC GATE "frequency to Voltage Converter" 8T363 8T363 abstract
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Abstract: bus applications. The ON Semiconductor VCX family mates perfectly to the LCX family for gate and , plans for VCX call for additional gate and octal functions, as well as wider, 18 bit devices. V , logic gate delays of less than 5 ns. The ultra­small geometry (.35 micron CMOS technology) applied to , a major step towards increasing gate speeds and output drive. These new devices are over­voltage tolerant at both input and output so that they can interface with nearly any logic family operating below ... Original
datasheet

4 pages,
50.57 Kb

VHC244 and logic gate HB205 LVX4245 LVXC3245 VCX16244 AC244 motorola ac244 motorola hb205 transmission line theory LCX16244 Difference VHC LVC AND8021/D AND8021/D abstract
datasheet frame
Abstract: small capacitive loads and logic gate inputs at extremely high speeds. But the slew rate will slow , outputs to the base of the MRF-501 MRF-501 form the AND gate, while the other two 14 Schottkys provide for fast turn-off. A logic AND gate could instead be used, but would add considerably more delay than , as a fast AND gate. The reference level is set to 1V, an arbitrary threshold. Only when both , specifications. The LT1720 LT1720 is offered in SO-8, with just three pins per comparator plus power and ground. For a ... Original
datasheet

6 pages,
273.24 Kb

1N5711 LM3045 LT1227 LT1394 LT1636 MRF501 LT1720 CA3039 300mv pulse stretcher circuit diagram and logic gate LT1720 abstract
datasheet frame
Abstract: sent to the LED Driver via a AND logic gate. The LED driver supplies the transmit diode with a typical , , output stage (electrical output driver) · Built in transmitter and receiver gate for half duplex mode , half duplex mode. LED and photodiode are driven by the multifunction IC E100.34C2 from ELMOS. The transmitting and receiving functional units with ELMOS-IC E100.34C2 may be split into the following blocks: Features · Optical transmitter and receiver for maximum datarate 10 Mbaud (half duplex burst mode) · ... Original
datasheet

11 pages,
236.01 Kb

qfbr ELMOS datasheet abstract
datasheet frame
Abstract: the LED Driver via a AND logic gate. The LED driver supplies the transmit diode with a typical , in transmitter and receiver gate for half duplex mode (mutual blocking of transmitter and receiver , photodiode for bidirectional optical transmission in half duplex mode. LED and photodiode are driven by the multifunction IC E100.34C2 from ELMOS. · Optical transmitter and receiver for maximum datarate 10 Mbaud (half duplex burst mode) The transmitting and receiving functional units with ELMOS-IC E100.34C2 may ... Original
datasheet

11 pages,
238.65 Kb

ELMOS DOTR and logic gate PHOTODIODE ALARM CIRCUIT ELMOS E100 cdi wiring diagram datasheet abstract
datasheet frame
Abstract: the LED Driver via a AND logic gate. The LED driver supplies the transmit diode with a typical , in transmitter and receiver gate for half duplex mode (mutual blocking of transmitter and receiver , photodiode for bidirectional optical transmission in half duplex mode. LED and photodiode are driven by the multifunction IC E100.34C2 from ELMOS. · Optical transmitter and receiver for maximum datarate 10 Mbaud (half duplex burst mode) The transmitting and receiving functional units with ELMOS-IC E100.34C2 may ... Original
datasheet

11 pages,
233.41 Kb

wiring diagram electric VDO Clock PREAMP AS-Interface Avago ELMOS E100 cdi wiring diagram cdi circuit Wiring Diagram logo BFt 65 ELMOS datasheet abstract
datasheet frame
Abstract: is inverted and sent to the LED Driver via a AND logic gate. The LED driver supplies the transmit , , output stage (electrical output driver) Built in transmitter and receiver gate for half duplex mode , Application of new chip technologies leads to increasing optical efficiency and growing and higher levels of optical performance. We therefore recommend that the current versions of the IEC 825-1 and EN 60825-1 standards are taken into account right from the outset, i.e. at the equipment development stage, and that ... Original
datasheet

13 pages,
191.87 Kb

bft3 IC100 8V11V cdi wiring diagram 34C-1 BFT003 and logic gate elmos ELMOS E100 PHOTODIODE ALARM CIRCUIT 34C1 datasheet abstract
datasheet frame
Abstract: time. IDSEL (ADx) @ 33 MHz 6 ns margin for clock skew, timeof-flight, and logic gate propagation 12 ns margin for clock skew, timeof-flight, and logic gate propagation 7 ns* for 33 MHz PCI , by the logic having twice as many delay elements as required between the latch and the output pin. , bypasses both the peripheral logic PLL and the CPU logic PLL With the CPU's PLL bypassed, there is no , logic's sys_logic_clk and the CPU's internal clock. The CPU bus clock is skewed with respect to the ... Original
datasheet

40 pages,
100.04 Kb

MPC8240 MPC824 MPC8240CE/D MPC8240CE/D abstract
datasheet frame
Abstract: IDSEL (ADx) @ 66 MHz 6 ns Margin for Clock Skew, Timeof-Flight, and Logic Gate Propagation 3 ns , ns Margin for Clock Skew, Timeof-Flight, and Logic Gate Propagation 7 ns* for 33 MHz PCI , 0x00000200 in order to negate the MCP signal. This logic anomaly and work around results in the system , This is caused by the logic having twice as many delay elements as required between the latch and the , external logic which detects the assertion of an address-only broadcast and gates off the PCI grants to ... Original
datasheet

40 pages,
141.34 Kb

MPC7450 doorbell project datasheet abstract
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D : Triacs logic level BT134 BT134 BT134 BT134 series E : Triacs sensitive gate BT134W BT134W BT134W BT134W series : Triacs BT134W BT134W BT134W BT134W series D : Triacs logic level BT134W BT134W BT134W BT134W series E : Triacs sensitive gate BT136 BT136 BT136 BT136 series : Triacs BT136 BT136 BT136 BT136 series D : Triacs logic level BT136 BT136 BT136 BT136 series E : Triacs sensitive gate BT136B BT136B BT136B BT136B series : Triacs BT136B BT136B BT136B BT136B series D : Triacs logic level BT136B BT136B BT136B BT136B series E : Triacs sensitive gate : Triacs logic level BT136X BT136X BT136X BT136X series E : Triacs sensitive gate BT137 BT137 BT137 BT137 series : Triacs BT137 BT137 BT137 BT137
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Figure 4.35 Type 3 AND Gate: Symbol and Logic Diagram
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Figure 4.34 Type 2 AND Gate: Symbol and Logic Diagram
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Figure 4.33 Type 1 AND Gate: Symbol and Logic Diagram
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Xilinx 04/06/1999 0.86 Kb HTM wcd02770.htm
Figure 4.35 Type 3 AND Gate: Symbol and Logic Diagram
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Figure 4.34 Type 2 AND Gate: Symbol and Logic Diagram
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Figure 4.33 Type 1 AND Gate: Symbol and Logic Diagram
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) 74V1T07 74V1T07 74V1T07 74V1T07 BUFFER (OPEN DRAIN) 74V1G08 74V1G08 74V1G08 74V1G08 2-Input AND Gate 74V1T08 74V1T08 74V1T08 74V1T08 2-Input AND Gate 74V1G14 74V1G14 74V1G14 74V1G14 HEX SCHMITT INVERTER LOGIC FAMILY LOGIC FAMILY Click here to get a complete list of ST's LOGIC FAMILY. VHC/VHCT SINGLE GATE Devices Description
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) 74V1T07 74V1T07 74V1T07 74V1T07 BUFFER (OPEN DRAIN) 74V1G08 74V1G08 74V1G08 74V1G08 2-Input AND Gate 74V1T08 74V1T08 74V1T08 74V1T08 2-Input AND Gate 74V1G14 74V1G14 74V1G14 74V1G14 HEX SCHMITT INVERTER LOGIC FAMILY LOGIC FAMILY Click here to get a complete list of ST's LOGIC FAMILY. VHC/VHCT SINGLE GATE Devices Description
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STMicroelectronics 14/06/1999 5.23 Kb HTM vhc-v2.htm
) 74V1T07 74V1T07 74V1T07 74V1T07 BUFFER (OPEN DRAIN) 74V1G08 74V1G08 74V1G08 74V1G08 2-Input AND Gate 74V1T08 74V1T08 74V1T08 74V1T08 2-Input AND Gate 74V1G14 74V1G14 74V1G14 74V1G14 HEX SCHMITT INVERTER LOGIC FAMILY LOGIC FAMILY Click here to get a complete list of ST's LOGIC FAMILY. VHC/VHCT SINGLE GATE Devices Description
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