NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: differential amplifier input and logic gate output. The input amplifier is referenced to zero volts and employs , and TTL circuits. APPLICATIONS Zero-Crossing Detector High Stability One-Shot Bi-Directional , CIRCUIT SCHEMATIC TIMING R, •o-W- 3? NOTE Pins 5, 6, 8, and 10 are tied to pin 14 through isolation , Sine wave inputs up to approximately 500 kHz are limited, amplified and used lo trigger the timing , integrated and then filtered to attenuate the remaining high frequency carrier components- EggnnfiGE 719 ... | OCR Scan |
3 pages, |
lt 719 frequency doubler isolation diodes 500 va sine wave ups circuit AC Zero detector zero crossing detector "Frequency To Voltage" B885 in916 frequency to voltage converter and logic gate "frequency to Voltage Converter" 8T363 8T363 8T363 abstract |
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| Abstract: bus applications. The ON Semiconductor VCX family mates perfectly to the LCX family for gate and , plans for VCX call for additional gate and octal functions, as well as wider, 18 bit devices. V , logic gate delays of less than 5 ns. The ultrasmall geometry (.35 micron CMOS technology) applied to , a major step towards increasing gate speeds and output drive. These new devices are overvoltage tolerant at both input and output so that they can interface with nearly any logic family operating below ... | Original |
4 pages, |
VHC244 VCX16244 LVXC3245 LVX4245 LCX16244 HB205 and logic gate AC244 motorola hb205 AND8021/D AND8021/D abstract |
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| Abstract: small capacitive loads and logic gate inputs at extremely high speeds. But the slew rate will slow , outputs to the base of the MRF-501 MRF-501 form the AND gate, while the other two 14 Schottkys provide for fast turn-off. A logic AND gate could instead be used, but would add considerably more delay than , as a fast AND gate. The reference level is set to 1V, an arbitrary threshold. Only when both , specifications. The LT1720 LT1720 is offered in SO-8, with just three pins per comparator plus power and ground. For a ... | Original |
6 pages, |
1N5711 CA3039 LM3045 LT1227 LT1394 LT1636 MRF501 LT1720 and logic gate pulse stretcher circuit diagram LT1720 abstract |
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| Abstract: the LED Driver via a AND logic gate. The LED driver supplies the transmit diode with a typical , in transmitter and receiver gate for half duplex mode (mutual blocking of transmitter and receiver , photodiode for bidirectional optical transmission in half duplex mode. LED and photodiode are driven by the multifunction IC E100.34C2 from ELMOS. · Optical transmitter and receiver for maximum datarate 10 Mbaud (half duplex burst mode) The transmitting and receiving functional units with ELMOS-IC E100.34C2 may ... | Original |
11 pages, |
ELMOS and logic gate PHOTODIODE ALARM CIRCUIT ELMOS E100 cdi wiring diagram datasheet abstract |
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| Abstract: the LED Driver via a AND logic gate. The LED driver supplies the transmit diode with a typical , in transmitter and receiver gate for half duplex mode (mutual blocking of transmitter and receiver , photodiode for bidirectional optical transmission in half duplex mode. LED and photodiode are driven by the multifunction IC E100.34C2 from ELMOS. · Optical transmitter and receiver for maximum datarate 10 Mbaud (half duplex burst mode) The transmitting and receiving functional units with ELMOS-IC E100.34C2 may ... | Original |
11 pages, |
wiring diagram electric VDO Clock PREAMP ELMOS E100 AS-Interface Avago cdi wiring diagram cdi circuit Wiring Diagram logo BFt 65 ELMOS datasheet abstract |
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| Abstract: is inverted and sent to the LED Driver via a AND logic gate. The LED driver supplies the transmit , , output stage (electrical output driver) Built in transmitter and receiver gate for half duplex mode , Application of new chip technologies leads to increasing optical efficiency and growing and higher levels of optical performance. We therefore recommend that the current versions of the IEC 825-1 and EN 60825-1 standards are taken into account right from the outset, i.e. at the equipment development stage, and that ... | Original |
13 pages, |
IC100 cdi wiring diagram 8V11V 34C1 ELMOS E100 BFT003 PHOTODIODE ALARM CIRCUIT elmos datasheet abstract |
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| Abstract: time. IDSEL (ADx) @ 33 MHz 6 ns margin for clock skew, timeof-flight, and logic gate propagation 12 ns margin for clock skew, timeof-flight, and logic gate propagation 7 ns* for 33 MHz PCI , by the logic having twice as many delay elements as required between the latch and the output pin. , bypasses both the peripheral logic PLL and the CPU logic PLL With the CPU's PLL bypassed, there is no , logic's sys_logic_clk and the CPU's internal clock. The CPU bus clock is skewed with respect to the ... | Original |
40 pages, |
MPC8240 MPC8240CE/D MPC8240CE/D abstract |
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| Abstract: IDSEL (ADx) @ 66 MHz 6 ns Margin for Clock Skew, Timeof-Flight, and Logic Gate Propagation 3 ns , ns Margin for Clock Skew, Timeof-Flight, and Logic Gate Propagation 7 ns* for 33 MHz PCI , 0x00000200 in order to negate the MCP signal. This logic anomaly and work around results in the system , This is caused by the logic having twice as many delay elements as required between the latch and the , external logic which detects the assertion of an address-only broadcast and gates off the PCI grants to ... | Original |
40 pages, |
MPC7450 doorbell project datasheet abstract |
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| Abstract: 66 MHz 6 ns Margin for Clock Skew, Timeof-Flight, and Logic Gate Propagation 3 ns for 66 MHz , Clock Skew, Timeof-Flight, and Logic Gate Propagation 7 ns* for 33 MHz PCI IDSEL_QUALIFIED , This logic anomaly and work around results in the system software having control over when the MCP , of a logic error, all the memory interface signals will be in a high-impedance state, and thus , negate the MCP signal. This logic anomaly and work around results in the system software having control ... | Original |
36 pages, |
MPC7450 MPC107 motorola bubble memory controller MPC107CE/D MPC107CE/D abstract |
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| Abstract: PCI_SYNC_IN 6 ns for 66 MHz PCI 6 ns margin for clock skew, timeof-flight, and logic gate propagation , margin for clock skew, timeof-flight, and logic gate propagation 7 ns* for 33 MHz PCI , 0x00000200 in order to negate the MCP signal. This logic anomaly and work around results in the system , When SDMA0 is cleared to logic 0 during reset, this circuit behavior is intermittent and erratic. , negate the MCP signal. This logic anomaly and work around results in the system software having control ... | Original |
36 pages, |
MPC7450 MPC107 MPC107CE/D MPC107CE/D abstract |
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| Replaces L6221A L6221A L6221A L6221A and L6221CD L6221CD L6221CD L6221CD Packages 16-Pin DIP (PDF) 20-Lead SOIC (PDF) Description Combining AND logic gates and switching inductive leads. They feature a minimum breakdown and sustaining voltage of 50 V. The logic inputs are compatible with TTL and 5 V CMOS logic systems. Typical applications include Output Voltage to 50 V TTL and 5 V CMOS Compatible Inputs www.datasheetarchive.com/files/allegro/sf/2540/index.htm |
Allegro | 17/10/2001 | 9.8 Kb | HTM | index.htm |
| -level logic and power loads to 100 W, the UDx2543B and UDx2543EB quad power drivers combine AND logic gates and high-current bipolar outputs. Each of the four independent outputs can sink up to 700 mA in the ON state. The outputs have a minimum breakdown voltage (load dump) of 60 V and a sustaining voltage of 35 V. The inputs are compatible with most TTL, DTL, LSTTL, and 5 V CMOS and PMOS logic systems Power and Display Drivers , Power Sink Drivers Purchase From www.datasheetarchive.com/files/allegro/sf/2543/index.htm |
Allegro | 17/10/2001 | 10.17 Kb | HTM | index.htm |
| logic gates and high-current bipolar outputs with complete output protection. Each of the four outputs a sustaining voltage of 40 V. The inputs are compatible with TTL and 5 V CMOS logic systems , High-Voltage Peripheral Power and Display Drivers , Power Sink Drivers Independent Over-Current Protection for Each Driver Thermal Protection for Device and Flyback Diodes TTL and 5 V CMOS Compatible Inputs Pin www.datasheetarchive.com/files/allegro/sf/2559/index.htm |
Allegro | 17/10/2001 | 10.46 Kb | HTM | index.htm |
| ) 28-lead batwing powertab PLCC (PDF) Description UDQ2549B UDQ2549B UDQ2549B UDQ2549B and UDK/UDN/UDQ2549EB UDK/UDN/UDQ2549EB UDK/UDN/UDQ2549EB UDK/UDN/UDQ2549EB quad power drivers combine AND logic gates and high-current bipolar outputs with complete output Power and Display Drivers , Power Sink Drivers Purchase From Independent Over-Current Protection for Each Driver Thermal Protection for Device and Flyback Diodes TTL and 5 V CMOS Compatible Inputs Pin www.datasheetarchive.com/files/allegro/sf/2549/index.htm |
Allegro | 17/10/2001 | 10.34 Kb | HTM | index.htm |
| , peripherals, and logic gates. Return to DSPS Home Page applications such as digital cellular phones, pagers, personal digital assistants (PDAs), and wireless modems as Global System for Mobile Communications (GSM), IS-54/136 IS-54/136 IS-54/136 IS-54/136, PDC, CDPD, and IS-95 IS-95 IS-95 IS-95 standards. It is . Some of the core's key features include a Viterbi Accelerator, four internal buses and dual address generators, a 40-bit adder with two 40-bit accumulators, and single-cycle normalization with exponential www.datasheetarchive.com/files/texas-instruments/data/sc/docs/dsps/details/40/leadf.htm |
Texas Instruments | 08/02/1999 | 7.19 Kb | HTM | leadf.htm |
| for external resistor strings, multiplexers, and logic gates, the MAX4539 MAX4539 MAX4539 MAX4539 provides an accurate , calibration input, and latch input. In turn, these inputs drive an internal, 16-output logic decoder Calibration-Multiplexers Ease System Calibration IC switches and multiplexers , incorporating fault-protected inputs, clamping the output voltage, and reducing the switch resistances -point calibration of gain and offset in precision data-acquisition systems. Called calibration www.datasheetarchive.com/files/maxim/0003/appno075.htm |
Maxim | 04/04/2001 | 11.8 Kb | HTM | appno075.htm |
| , peripherals, and logic gates. The 'C541 is currently available, at the suggested resale price of U.S. $23 applications such as digital cellular phones, pagers, personal digital assistants (PDAs), and wireless modems as Global System for Mobile Communications (GSM), IS-54/136 IS-54/136 IS-54/136 IS-54/136, PDC, CDPD, and IS-95 IS-95 IS-95 IS-95 standards. It is . Some of the core's key features include a Viterbi Accelerator, four internal buses and dual address generators, a 40-bit adder with two 40-bit accumulators, and single-cycle normalization with exponential www.datasheetarchive.com/files/texas-instruments/sc/docs/dsps/details/40/leadf-v1.htm |
Texas Instruments | 13/12/1996 | 6.69 Kb | HTM | leadf-v1.htm |
| , peripherals, and logic gates. The 'C541 is currently available, at the suggested resale price of U.S. $23 applications such as digital cellular phones, pagers, personal digital assistants (PDAs), and wireless modems as Global System for Mobile Communications (GSM), IS-54/136 IS-54/136 IS-54/136 IS-54/136, PDC, CDPD, and IS-95 IS-95 IS-95 IS-95 standards. It is . Some of the core's key features include a Viterbi Accelerator, four internal buses and dual address generators, a 40-bit adder with two 40-bit accumulators, and single-cycle normalization with exponential www.datasheetarchive.com/files/texas-instruments/sc/docs/dsps/details/40/leadf.htm |
Texas Instruments | 05/11/1997 | 7.14 Kb | HTM | leadf.htm |
| DSP core with microcontroller cores, additional memory, peripherals and logic gates. Full ) from TI lower power consumption and reduce chip count and system cost for wireless communications such as data/fax capabilities, text messages, encryption, speech recognition, echo cancellation and noise suppression. The TMS320C541 TMS320C541 TMS320C541 TMS320C541 and TMS320C542 TMS320C542 TMS320C542 TMS320C542 combine high performance, hard-wired functions means more carriers can begin building a more cost-effective digital infrastructure and pass the www.datasheetarchive.com/files/texas-instruments/data/sc/docs/integrat/95may/lead1.htm |
Texas Instruments | 08/02/1999 | 7.98 Kb | HTM | lead1.htm |
| DSP core with microcontroller cores, additional memory, peripherals and logic gates. Full ) from TI lower power consumption and reduce chip count and system cost for wireless communications such as data/fax capabilities, text messages, encryption, speech recognition, echo cancellation and noise suppression. The TMS320C541 TMS320C541 TMS320C541 TMS320C541 and TMS320C542 TMS320C542 TMS320C542 TMS320C542 combine high performance, hard-wired functions means more carriers can begin building a more cost-effective digital infrastructure and pass the www.datasheetarchive.com/files/texas-instruments/sc/docs/integrat/95may/lead1.htm |
Texas Instruments | 22/06/1995 | 7.64 Kb | HTM | lead1.htm |