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TTL-LOGIC-DATABOOK Texas Instruments TTL-LOGIC-DATABOOK visit Texas Instruments
HIP6004E/ISL6525EV1 Intersil Corporation Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor; visit Intersil
5962-87677012A Intersil Corporation SAMPLE AND HOLD AMPLIFIER, CQCC20, CERAMIC, QCC-20 visit Intersil
HA5351IB Intersil Corporation SAMPLE AND HOLD AMPLIFIER, 0.09us ACQUISITION TIME, PDSO8 visit Intersil
HA9P5320-5 Intersil Corporation SAMPLE AND HOLD AMPLIFIER, 1us ACQUISITION TIME, PDSO16 visit Intersil
HA1-2425-5 Intersil Corporation SAMPLE AND HOLD AMPLIFIER, 3.2us ACQUISITION TIME, CDIP14 visit Intersil

and logic gate pdf

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CMOS TTL Logic Family Specifications

Abstract: HCT08 · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT08 Quad 2-input AND gate Product , -input AND gate DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family , datasheet with package and family information, also download the following PDF files. The "Logic Package , 2Input AND Gate Quad 2Input AND Gate Quad 2Input AND Gate 15 5 Volts 14 + 5 Volts 14 + 5 Volts 14 + 5 , specification Quad 2-input AND gate FEATURES · Output capability: standard · ICC category: SSI GENERAL
Philips Semiconductors
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CMOS TTL Logic Family Specifications HCT08 74hc family catalog 74HC08P 74HC-HCT-HCMOS Logic Package Information selector guide 74HC 74HCT FAMILY T08PW9351 TSSOP14 74HC08DBT 74HC08 74HCT08 74HC/HCT/HCMOS

logic package information philips ic06

Abstract: logic family specification philips ic06 with package and family information, also download the following PDF files. The "Logic Package , · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT4002 Dual 4-input NOR gate Product , delay nA, nB, nC, nD to nY input capacitance power dissipation capacitance per gate notes 1 and 2 , .5 Logic diagram 74HC4002 (one gate). Fig.6 Logic diagram 74HCT4002 (one gate). December 1990 4 , HCT_PACKAGE_OUTLINES PDF File Description HC/T Family Specifications, The IC06 74HC/HCT/HCMOS Logic Family
Philips Semiconductors
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logic package information philips ic06 logic family specification philips ic06 74HC-HCT-HCMOS Logic Package Outlines philips ic06 cmos 4000B 74HCT4002DB9351 SSOP14 74HCT4002N DIP14

selector guide 74HC 74HCT FAMILY

Abstract: philips ic06 cmos package and family information, also download the following PDF files. The "Logic Package Information , · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT20 Dual 4-input NAND gate Product , Fig.4 Functional diagram. Fig.5 HC logic diagram (one gate). FUNCTION TABLE INPUTS nA L X X X H Notes 1. H = HIGH voltage level L = LOW voltage level X = don't care Fig.6 HCT logic diagram (one gate). , Dual 4-Input 15 NAND Gate Dual 4-Input 15 NAND Gate 5 Volts 14 + 5 Volts 14 + 5 Volts 14 + 5 Volts 14 +
Philips Semiconductors
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smd marking 2D 74hc20n JEDEC Standard No. 7A IC06 74HC Package Information philips IC06 74HCT20D

74HC-HCT-HCMOS Logic Family Specifications

Abstract: 74HC Logic Family Specifications device datasheet with package and family information, also download the following PDF files. The "Logic , · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT27 Triple 3-input NOR gate Product , input capacitance power dissipation capacitance per gate notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 , level L = LOW voltage level X = don't care Fig.4 Functional diagram. Fig.5 Logic diagram (one gate). nB , ) propagation delays and the output transition times. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package
Philips Semiconductors
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74HC-HCT-HCMOS Logic Family Specifications 74HC Logic Family Specifications smd marking code 1b smd marking 1C 6 PIN 3Y SMD 74HCT27P 74HC27N

The IC04 LOCMOS HE4000B Logic

Abstract: Family Specifications HEF, HEC North America Fig.1 Functional diagram. Fig.3 Logic diagram (one gate). FAMILY DATA, IDD LIMITS , package and family information, also download the following PDF files . Document Description 1 Download HEF_FAMILY_SPECIFICATIONS HEF Family Specifications, The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC PDF 2 , ) Gate 15 CMOS Low top Products, packages, availability and ordering North American type , , The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC(date Download 01-May-95) PDF File top
Philips Semiconductors
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HEF4001BP The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC of HEF4001BP he4000b family HE4000B Family specifications HEF4001B HEF4001BD HEF4001BT HEF4001BTD1

74HC03D

Abstract: selector guide 74HC 74HCT FAMILY · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT03 Quad 2-input NAND gate Product , and RL = ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay input capacitance power dissipation capacitance per gate notes 1, 2 and 3 CONDITIONS HC CL = , .4 Functional diagram. Fig.5 Logic diagram (one gate). December 1990 3 Philips Semiconductors , following PDF files. The "Logic Package Information" document is required to determine in which package(s
Philips Semiconductors
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74HC03D 74HCT03PW9351
Abstract: is used to power internal logic and to operate a gate bias generator. 1 of 4 111999 DS1640 , gate (see Figure 1). A set of four internal latches is controlled by the latch input. The logic levels passed to the FET gates are controlled by the gate inputs and latch pin status. When the latch pin is logic 0, the gate input levels are inverted and passed directly to the control gates, enabling the , -pin SOIC surface mount package Positive logic signal turns each FET on and ground or low level signal turns Dallas Semiconductor
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DS1640/DS1640C 56-G5005-002A P16-2 56-G4009-001B DS1640S DS1640SN
Abstract: Min. VB + 0.3 VHO High side floating output voltage HO VCC Low side and logic fixed supply voltage -0.3 25 VLO Low side output voltage LO -0.3 VCC + 0.3 VIN Logic , voltage COM Logic ground and low side driver return HIN Logic input for high side gate driver , for both channels 3.3 V, 5 V, and 15 V input logic input compatible Cross-conduction prevention logic Matched propagation delay for both channels Lower di/dt gate driver for better noise immunity International Rectifier
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PD60277 IRS2304 A/130 IRS2304P IRS2304SP IRS2304STRP
Abstract: voltage COM Logic ground and low-side driver return HIN Logic input for high-side gate driver , for both channels 3.3 V, 5 V, and 15 V input logic input compatible Cross-conduction prevention logic Matched propagation delay for both channels Lower di/dt gate driver for better noise immunity , . Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic , Notes and DesignTips for proper circuit board layout. www.irf.com PDF created with pdfFactory International Rectifier
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IR2304

Abstract: mosfet te 2304 Min. VB + 0.3 VHO High- side floating output voltage HO VCC Low- side and logic fixed supply voltage -0.3 25 VLO Low- side output voltage LO -0.3 VCC + 0.3 VIN Logic , Logic ground and low-side driver return HIN Logic input for high-side gate driver output LIN Logic input for low-side gate driver output VB High-side floating supply HO High-side driver , 3.3 V, 5 V, and 15 V input logic input compatible Cross-conduction prevention logic Matched
International Rectifier
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IR2304 mosfet te 2304 IRS2304PbF IRS2304STRPBF IRFBC20 IRFBC30

IRS2304

Abstract: ir2304s Min. VB + 0.3 VHO High- side floating output voltage HO VCC Low- side and logic fixed supply voltage -0.3 25 VLO Low- side output voltage LO -0.3 VCC + 0.3 VIN Logic , Logic ground and low-side driver return HIN Logic input for high-side gate driver output LIN Logic input for low-side gate driver output VB High-side floating supply HO High-side driver , 3.3 V, 5 V, and 15 V input logic input compatible Cross-conduction prevention logic Matched
International Rectifier
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MS-012AA ir2304s aX 010 IRFPB50 IRFBC40 IRFPE50

MAX6629MTT

Abstract: code d12 6-pin sot-23 +3.3V and TA = +25°C.) (Notes 2 and 3) PARAMETER LOGIC INPUTS (CS, SCK) Logic Input Low Voltage Logic , current permits powering them from the output of a logic gate. This specification is given to ensure that , from a gate output. Note 4: Timing characteristics are guaranteed by design and are not production , is greater than 3.0V and the logic output is not noisy. Setting the logic output low provides a , MAX6631 MAX6632 GND SO SCK CS Figure 1. Powering the Sensor from a Logic Gate is not noisy, as
Maxim Integrated Products
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MAX6629MTT code d12 6-pin sot-23 MAX6629 MAX6631/MAX6632 MAX6629/ MAX6630 MAX6629/MAX6630 MAX6632MTT

74HC154N

Abstract: hct154 package and family information, also download the following PDF files. The "Logic Package Information , address inputs and provide 16 mutually exclusive active LOW outputs. The 2-input enable gate can be used , and provide 16 mutually exclusive active LOW outputs. The 2-input enable gate can be used to strobe , 74HC/HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic Package Information · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT154 4-to-16 line decoder
Philips Semiconductors
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74HC154N hct154 sot355 DIP24
Abstract: logic supply range from 3.3 V to 20 V Logic and power ground +/- 5 V offset CMOS Schmitt-triggered , -0.3 VCC + 0.3 VDD Logic supply voltage -0.3 VSS + 25 VSS Logic supply offset voltage VCC - 25 VCC + 0.3 Logic input voltage (HIN, LIN & SD) VSS - 0.3 VDD + 0.3 â , offset voltage VIN TA VSS + 3 VSS + 20 -5 (Note 2) 5 Logic input voltage (HIN, LIN & , applicable to all three logic input leads: HIN, LIN, and SD. The VO and IO parameters are referenced to COM International Rectifier
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PD60251 IRS2112 IRS2112-2 IRS2112-1 IRS2112S IRS2112P

96E-9

Abstract: IRS2112 application circuit diagram 3.3 V to 20 V Logic and power ground +/- 5 V offset CMOS Schmitt-triggered inputs with pull-down , voltage -0.3 VCC + 0.3 VDD Logic supply voltage -0.3 VSS + 25 VSS Logic supply offset voltage VCC - 25 VCC + 0.3 Logic input voltage (HIN, LIN & SD) VSS - 0.3 VDD + 0.3 , VCC VDD Logic supply voltage VSS Logic supply offset voltage VIN TA VSS + 3 VSS + 20 -5 (Note 2) 5 Logic input voltage (HIN, LIN & SD) VSS VDD Ambient temperature
International Rectifier
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96E-9 IRS2112 application circuit diagram lta 301 IRF820 IRS2112PBF IRS2112-1P IRS2112-2P IRS2112SP IRS2112STRP SOIC-16

IRF820

Abstract: IRFBC20 3.3 V to 20 V Logic and power ground +/- 5 V offset CMOS Schmitt-triggered inputs with pull-down , voltage -0.3 VCC + 0.3 VDD Logic supply voltage -0.3 VSS + 25 VSS Logic supply offset voltage VCC - 25 VCC + 0.3 Logic input voltage (HIN, LIN & SD) VSS - 0.3 VDD + 0.3 , VCC VDD Logic supply voltage VSS Logic supply offset voltage VIN TA VSS + 3 VSS + 20 -5 (Note 2) 5 Logic input voltage (HIN, LIN & SD) VSS VDD Ambient temperature
International Rectifier
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MS-001AC MS-013AA

IRS2112 application circuit diagram

Abstract: lta 301 logic supply range from 3.3 V to 20 V Logic and power ground +/- 5 V offset CMOS Schmitt-triggered , Logic supply voltage -0.3 VSS + 25 VSS Logic supply offset voltage VCC - 25 VCC + 0.3 Logic input voltage (HIN, LIN & SD) VSS - 0.3 VDD + 0.3 - 50 Units VIN dVs/dt PD , Logic supply voltage VSS Logic supply offset voltage VIN TA VSS + 3 VSS + 20 -5 (Note , , and IIN parameters are referenced to VSS and are applicable to all three logic input leads: HIN, LIN
International Rectifier
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HCPL-060L

Abstract: HCPL-063L PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 5). 6 VO2 VF2 + 4 5 SHIELD 6 - 105 6104-117 , together, and pins 3 and 4 shorted together. For dual channel products only. 6 - 112 6104-117(PDF , circuit for common mode transient immunity and typical waveforms. 6 - 114 6104-117(PDF) Page 114 , 220 74LS04 OR ANY TOTEM-POLE OUTPUT LOGIC GATE 350 2 7 3 6 VO 5 GND , with any totem-poleoutput TTL/LSTTL/HCMOS logic gate. The buffer PNP transistor allows the circuit to
Agilent Technologies
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HCPL-260L HCPL-060L HCPL-063L HCPL-263L E55361 ppc capacitor HCPL-260L/ 060L/263L/063L HCPL-260L/060L/263L/063L HCPL-260L/060L HCPL-263L/063L
Abstract: .+14V GATE_ to GND .-0.3V to (VIN_ + 6.2V) ON_, PGOOD_, TIM to GND.-0.3V to the higher of (VIN1 + 0.3V) and (VIN2 + 0.3V) SENSE_, MON_, LIM_ to GND .-0.3V , VGATEX (V) 15 VINX = 1V VINY = 2.7V VGATEX = VINX + 6.2V VINX = 5V VINX = 13.2V 6 GATE DISCHARGE , COMP. GATE2 CHARGE PUMP DEVICE CONTROL LOGIC CURRENT CONTROL AND STARTUP LOGIC CURRENT CONTROL AND , period feature allows systems to be customized for MOSFET gate capacitance and board capacitance (CBOARD Maxim Integrated Products
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MAX5955/MAX5956 MAX5955 MAX5956 21-0055F E16-1 MAX5956AEEE

PHILIPS 74HC132N

Abstract: 74HCT132D device datasheet with package and family information, also download the following PDF files. The "Logic , , jitter-free output signals. The gate switches at different points for positive and negative-going signals. The , dissipation capacitance per gate notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 11 3.5 24 17 3.5 20 HCT ns , Fig.5 Fig.4 Functional diagram. Logic diagram (one Schmitt trigger). APPLICATIONS · Wave and pulse , /HCMOS Logic Family Specifications PDF
Philips Semiconductors
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PHILIPS 74HC132N 74HCT132D 74HCT132PW 74HC132N 74HC132D 74HC/HCT132 HTML04232003/74HC132N
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