NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Model Name: FHS-A7015S61 FHS-A7015S61 DELTA ELECTRONICS, INC. Pictures Application: · AMD Athlon X2 2XX ( Regor CPU / 65W ) · AMD Sempron 140 ( Sargas CPU / 45W ) (SocketAM2/SocketAM2+/Socket AM3) Thermal , : FHS-A7015B62 FHS-A7015B62 DELTA ELECTRONICS, INC. Pictures Application: · AMD Phenom X4 9XX/8XX ( Deneb CPU,95W ) · AMD Phenom X3 7XX ( Heka CPU,95W ) · AMD Phenom X2 5XX ( Callisto CPU,80W ) (SocketAM2 , 0.30 0.29 3000 3500 4000 4500 5000 5500 6000 29.00 6500 Fan Speed ( rpm ... | Original |
3 pages, |
A6063-T5 amd x2 athlon 4000 deneb TC5121 FHS-A7015S61 AMD Phenom 2 datasheet AMD Phenom AMD Athlon X2 FHS-A7015B62 AMD sempron 3000 molex 2759T AMD phenom x4 amd am3 pin socket AM3 FHS-A7015S61 abstract |
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| Abstract: Search H8DGU-LN4F+ A+ Products Motherboards [ H8DGU -LN4F+ ] Key Features 1. Dual AMD OpteronTM 6000 series processors (G34) 16/12/8-Core ready; HT3.0 Link support 2. AMD SR5690 SR5690 / SP5100 SP5100 Chipset , Dimensions Processor/Chipset Dual 1944-pin Socket G34 Supports up to two 16/12/8-Core ready AMD OpteronTM 6000 Series processors HT3.0 Link support AMD chipset SR5690 SR5690 / SP5100 SP5100 Proprietary 12.8" x 16.5" , AMD SP5100 SP5100 (RAID 0, 1, 10) Support for Intelligent Platform Management Interface v.2.0 IPMI 2.0 with ... | Original |
1 pages, |
datasheet abstract |
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| Abstract: Processor 2 MB 3000 MHz 6000+ Table 7: AMD AthlonTM 64 X2 Dual-Core Processor Power Limit OPN , 2 AMD AthlonTM 64 X2 Dual-Core Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 AMD AthlonTM 64 X2 Dual-Core Processor Ordering Part Number Description . . . . , . . . 11 2.2 AMD Athlon 64 X2 Dual-Core Processor Thermal and Power Table Guide . . . . . . 16 2.3 AMD Athlon 64 X2 Dual-Core Processor Thermal and Power Specifications . . . . . 17 2.3.1 ADA mmmsvtc ... | Original |
71 pages, |
ADO3800IAA5CU ADA5600IAA6CZ AMD Athlon 64 X2 4400 AMD Athlon 64 X2 5000 AMD ATHLON X2 5200 AM2 AMD Athlon 64 X2 dual 4800 pin out ado4000iaa5dd amd am2 socket pin diagram ADO4600IAA5CZ ADO4400IAA5DD AMD AM2 Athlon 64 pin diagram ADX6000IAA6CZ datasheet abstract |
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| Abstract: ICS950410 ICS950410 Integrated Circuit Systems, Inc. Preliminary Product Preview AMD - K8TM System , X2 3.3V GND · 9 - PCICLK (Including 1 free running) @ 3.3V *ModeA/HTTCLK0 · 3 - Selectable , Recommended Application: AMD K8 System Clock with AMD, VIA or ALI Chipset 2X PCICLK6 23 PCICLK7 24 , 233.33 266.67 300.00 HTT MHz 67.27 66.95 67.20 67.33 66.80 66.75 66.68 66.80 60.00 60.00 70.00 60.00 67.50 66.67 66.67 75.00 PCI MHz 33.63 33.48 33.60 33.67 33.40 33.38 33.34 ... | Original |
16 pages, |
SEL24 ICS950410 ALI chipset ICS950410 abstract |
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| Abstract: ICS950410 ICS950410 Integrated Circuit Systems, Inc. Advance Information AMD - K8TM System Clock , Output Features: VDDHTT · 3 - Differential pair push-pull CPU clocks @ X1 3.3V X2 · 9 - PCICLK , Recommended Application: AMD K8 System Clock with AMD, VIA or ALI Chipset 23 24 48 47 46 45 44 43 , HTT MHz 67.27 66.95 67.20 67.33 66.80 66.75 66.68 66.80 60.00 60.00 70.00 60.00 67.50 , 19 20 21 22 ~*FS0/REF0 VDDHTT X1 X2 GND *ModeA/HTTCLK0 *ModeB/PCICLK8/HTTCLK1 PCICLK9 ... | Original |
15 pages, |
SEL24 ICS950410 ICS950410 abstract |
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| Abstract: ICS950405 ICS950405 Integrated Circuit Systems, Inc. AMD - K8TM System Clock Chip Recommended Application: AMD K8 System Clock with AMD, VIA or ALI Chipset Support I2C Index read/write and block read , 66.95 67.20 67.33 66.80 66.75 66.68 66.80 60.00 60.00 70.00 60.00 67.50 66.67 66.67 75.00 , 33.33 33.33 37.50 Pin Configuration *FS0/REF0 VDDHTT X1 X2 GND *ModeA/HTTCLK0 *ModeB/PCICLK8 , 20 21 22 *FS0/REF0 VDDHTT X1 X2 GND *ModeA/HTTCLK0 *ModeB/PCICLK8/HTTCLK1 PCICLK9/HTTCLK2 ... | Original |
16 pages, |
SEL24 ICS950405 ClawHammer ALI chipset 7404 pin configuration ICS950405 abstract |
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| Abstract: PRELIMINARY PLL208-101 PLL208-101 Programmable Clock Generator for AMD K8 TM and VIA K8 PIN , /REF0*^ VDDREF X1 X2 GND ^(PCICLK7/HTTCLK0)ModeA ^PCICLK8/HTTCLK1/ModeB PCICLK9/HTTCLK2 VDDPCI , Page 1 PRELIMINARY PLL208-101 PLL208-101 Programmable Clock Generator for AMD K8 TM and VIA K8 TM , PLL208-101 PLL208-101 Programmable Clock Generator for AMD K8 TM and VIA K8 VDDCPU 35,38 PWR 3.3V power , Generator for AMD K8 TM and VIA K8 TM FREQUENCY (MHz) SELECTION TABLE Bit4 Bit3 Bit2 ... | Original |
22 pages, |
PLL208-101 Analog devices 24033 48MHZ PLL208-101 abstract |
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| Abstract: ICS950403 ICS950403 Integrated Circuit Systems, Inc. Advance Information AMD - K8TM System Clock Chip Recommended Application: AMD K8 System Clock with AMD, VIA or ALI Chipset Pin Configuration , pair push-pull CPU clocks @ X1 3 46 VDDREF 3.3V X2 4 45 REF2/FS2* · 9 - PCICLK (Including 1 free , has 2X Drive Strength Block Diagram Functionality PLL2 48MHz 24_48MHz /2 X1 X2 XTAL , Logic Config. X2 PCICLK/HTTCLK (3:1) Reg. HTTCLK0 FS3 FS2 FS1 FS0 0 0 0 0 ... | Original |
18 pages, |
SEL24 ALI chipset ICS950403 ICS950403 abstract |
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| Abstract: RD_IR RxD Pin2, RxD RD_UART X1 18046-1 VCC X2 3.6842 MHz Figure 1. TOIM4232-RS232 , 6000 series are compatible to the described interface circuits. NSCPC87108 NSCPC87108 The configuration shown , TD 232 S2 V CC SD S1 X1 NC X2 RD LED GND TD LED C10 16 2 + 15 , ANALOG DEVICES ADSP-BF561 ADSP-BF561 Embedded Processor ANALOG DEVICES Elan SC400 SC400 Microprocessor AMD Elan SC520 SC520 Microprocessor AMD Alchemy AU1000 AU1000 & 1100 Microprocessor AMD Geode SC Family Microprocessor AMD Geode GX533 GX533 & ... | Original |
7 pages, |
STIR423 pci vfir ite tech VFIR BCM213 USBRS232 SCH3116 SIGMATEL IrDA CY8C21123 EP9302 IrDA msp430 IT8702F SC14428 STIR4230N STIR4210 RS232 RS232 abstract |
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| Abstract: RD_IR RxD Pin2, RxD RD_UART X1 18046-1 VCC X2 3.6842 MHz Figure 1. TOIM4232-RS232 , 6000 series are compatible to the described interface circuits. NSCPC87108 NSCPC87108 The configuration shown , S1 X1 NC X2 RD LED GND TD LED C10 16 2 + 15 R6 TFDU4100 TFDU4100 C11 , Microprocessor AMD Elan SC520 SC520 Microprocessor AMD Alchemy AU1000 AU1000 & 1100 Microprocessor AMD Geode SC Family Microprocessor AMD Geode GX533 GX533 & GX500 GX500 Microprocessor AMD Vr4100 Processor Family NEC WV8307 WV8307 VolP Chipset ... | Original |
7 pages, |
TFDU5307 SIGMATEL IrDA STIR4200 MCP2155 VJ1206Y474 ITE IT8705F Broadcom RECEIVER EP9302 Stir4200 USB/IrDA Bridge Controller IT8705F IT8702F msp430 RS232 SC14428 TOSHIBA DIODE CATALOG RS232 RS232 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| (0x555) #define ADDR1 (0x2AA) #define ADDR3 (0x001) #else #define ADDR0 (0x _parity_odd(unsigned char x) { x ^= x >> 4; x ^= x >> 2; x ^= x >> 1; return (x & 0x1) != 0; } #endif /* 0 _WORD_SIZE * addr2; #endif #if 0 /* write autoselect sequence */ flash[0x5555] = 0xaa; flash[0x2aaa] = 0 ], flash[0x2 + 14 * i]); #endif switch(pflinfo->flash_id & FLASH_TYPEMASK) { case FLASH ->start[j] = base_address + 0x00010000 * j; pflinfo->protect[j] = flash[(j www.datasheetarchive.com/download/49104857-995987ZC/xapp542.zip (flash.c) |
Xilinx | 11/11/2004 | 9180.01 Kb | ZIP | xapp542.zip |
| (0x555) #define ADDR1 (0x2AA) #define ADDR3 (0x001) #else #define ADDR0 (0x char x) { x ^= x >> 4; x ^= x >> 2; x ^= x >> 1; return (x & 0x1) != 0; } #endif /* 0 */ static ; flash[0x2aaa] = 0x55; flash[0x5555] = 0x90; #else flash[0xAAA ], flash[0x2 + 14 * i]); #endif switch (pflinfo->flash_id & FLASH_TYPEMASK) { case FLASH_AM040 AM040 AM040 AM040 ->start[j] = base_address + 0x00010000 * j; pflinfo->protect[j] = flash[(j www.datasheetarchive.com/download/49104857-995987ZC/xapp542.zip (flash.c) |
Xilinx | 11/11/2004 | 9180.01 Kb | ZIP | xapp542.zip |
| {Dialect RS274X RS274X RS274X RS274X} {m.n 2.4} {Mode Absolute} {ZeroSuppression Leading} {Terminator 0x2a } {Flags 0} } } {Layer 2 {File art02.pho} {LyrName 2a} {ApList $x2.map} {Visibility {Dialect RS274X RS274X RS274X RS274X} {m.n 2.4} {Mode Absolute} {ZeroSuppression Leading} {Terminator 0x2a {Dialect RS274X RS274X RS274X RS274X} {m.n 2.4} {Mode Absolute} {ZeroSuppression Leading} {Terminator 0x2a {Dialect RS274X RS274X RS274X RS274X} {m.n 2.4} {Mode Absolute} {ZeroSuppression Leading} {Terminator 0x2a www.datasheetarchive.com/download/45642549-9307ZC/972r0grb.zip (LPLUSLV1.GTD) |
AMD | 21/07/1998 | 290.03 Kb | ZIP | 972r0grb.zip |
| {Dialect RS274X RS274X RS274X RS274X} {m.n 2.4} {Mode Absolute} {ZeroSuppression Leading} {Terminator 0x2a } {Flags 0} } } {Layer 2 {File art02.pho} {LyrName 2a} {ApList $x2.map} {Visibility {Dialect RS274X RS274X RS274X RS274X} {m.n 2.4} {Mode Absolute} {ZeroSuppression Leading} {Terminator 0x2a {Dialect RS274X RS274X RS274X RS274X} {m.n 2.4} {Mode Absolute} {ZeroSuppression Leading} {Terminator 0x2a {Dialect RS274X RS274X RS274X RS274X} {m.n 2.4} {Mode Absolute} {ZeroSuppression Leading} {Terminator 0x2a www.datasheetarchive.com/download/25803507-9150ZC/wcd00312.zip (LPLUSLV1.GTD) |
AMD | 28/04/1999 | 290.03 Kb | ZIP | wcd00312.zip |
| ; 0.025' SQ. POST AMP 87224-3 JP32,JP33 26.0 1.0 JP4 HEADER 3X2 TH-2X3 2x3 HEADER; 0.025' SQ. POST AMP 103186-3 27.0 1.0 JP34 HEADER 2X1 TH-1X2 1x2 HEADER; 0.025' SQ. POST AMP 87224-2 28.0 1.0 J1 KYBD . (800) 222-9323 5204 E. Ben White Blvd. Austin, TX 78741 AMD Proprietary/All Rights Reserved Bill Of 32(0.6")(SOCKET) AMD Am29F010-90PC Am29F010-90PC 94.0 1.0 U15 74F04 74F04 74F04 74F04 SO14 SIGNETICS 74F04D 74F04D 74F04D 74F04D 95.0 1.0 U17 IMI SC464 SC464 SC464 SC464 -PGA PGA169 PGA169 PGA169 PGA169 AMD (AMP SOCKET1 916504-2) 100.0 11.0 U26,U28,U30,U31,U32,U36, 74ABT16244 74ABT16244 74ABT16244 74ABT16244 SSOP48 SSOP48 SSOP48 SSOP48 SIGNETICS www.datasheetarchive.com/download/34605408-7936ZC/am486bom_21.xls |
AMD | 13/08/1999 | 36 Kb | XLS | am486bom_21.xls |
| (0x2AA*2) #define UNLOCK_CMD1 (0xAA) #define UNLOCK_CMD2 (0x55) #define ERASE_SUSPEND_CMD (0xB0 ) + flashtest) { case AMD_MANUFACT: info->flash_id = FLASH_MAN_AMD & FLASH_VENDMASK; break; case FUJ ) { case AMD_ID_LV160B LV160B LV160B LV160B: info->flash_id += (FLASH_AM160LV AM160LV AM160LV AM160LV | FLASH_AM160B AM160B AM160B AM160B) & FLASH_TYPEMASK; info ->start[2] = baseaddr + 0x6000; info->start[3] = baseaddr + 0x8000; for (i = 1; i < info FLASH type\n"); return; } switch (info->flash_id & FLASH_VENDMASK) { case FLASH_MAN_AMD: printf www.datasheetarchive.com/download/49104857-995987ZC/xapp542.zip (flash.c) |
Xilinx | 11/11/2004 | 9180.01 Kb | ZIP | xapp542.zip |
| xaa ); my_out_8( (unsigned char * ) (ulong)addr+0x2aa) , 0x55 ); my_out_8( (unsigned char ( (unsigned char *) (ulong)addr+0x2aa),0x55 ); my_out_8( (unsigned char *) (ulong)addr+0x555),0x80 )addr+0x2aa),0x55 ); /* Start erase on unprotected sectors */ for (sect = s_first; sect * ) (addr+0x2aa) , 0x55 ); my_out_8( (unsigned char * ) (addr+0x555) , 0x90 ); in_mid=my_in_8( (unsigned 555),0xaa); my_out_8(unsigned char *) (addr+0x2aa),0x55); my_out_8( (unsigned char *) (addr+0x www.datasheetarchive.com/download/49104857-995987ZC/xapp542.zip (flash.c) |
Xilinx | 11/11/2004 | 9180.01 Kb | ZIP | xapp542.zip |
| select command: read Manufacturer ID */ *(addr2 + 0x555) = 0xaa; *(addr2 + 0x2aa) = 0x55; *(addr2 + 0x = disable_interrupts(); *(addr + 0x555) = (uchar)0xAA; *(addr + 0x2aa) = (uchar)0x55; *(addr + 0x555) = (uchar)0x80; *(addr + 0x555) = (uchar)0xAA; *(addr + 0x2aa) = (uchar)0x55 _interrupts(); *(addr2 + 0x555) = (uchar)0xAA; *(addr2 + 0x2aa) = (uchar)0x55; *(addr2 + 0x555) = (uchar)0xA0; dest2 FLASH type\n"); return; } switch (info->flash_id & FLASH_VENDMASK) { case FLASH_MAN_AMD www.datasheetarchive.com/download/49104857-995987ZC/xapp542.zip (flash.c) |
Xilinx | 11/11/2004 | 9180.01 Kb | ZIP | xapp542.zip |
| #define OFFS_INT_IREQ 0x2e // Interrupt request register #define OFFS_INT_INSV 0x2c // In-service register #define OFFS_INT_PMSK 0x2a // Priority mask register #define OFFS IN-SERVICE REGISTER BITS (INSERV - 0x2c) // #define INT_INSV_SPRT0 0x0400 // serial ) // - // INTERRUPT REQUEST REGISTER BITS (REQST - 0x2e) #define INT_REQ_SPRT0 INT_INSV_SP0 #define INT 1 // trace trap #define ITYPE_NMI 0x2 // non-maskable interrupt www.datasheetarchive.com/download/94587045-7823ZC/ck000403.zip (Am186msr.h) |
AMD | 22/02/1999 | 197.65 Kb | ZIP | ck000403.zip |
| #define OFFS_INT_IREQ 0x2e // Interrupt request register #define OFFS_INT_INSV 0x2c // In-service register #define OFFS_INT_PMSK 0x2a // Priority mask register #define OFFS IN-SERVICE REGISTER BITS (INSERV - 0x2c) // #define INT_INSV_SPRT0 0x0400 // serial ) // - // INTERRUPT REQUEST REGISTER BITS (REQST - 0x2e) #define INT_REQ_SPRT0 INT_INSV_SP0 #define INT 1 // trace trap #define ITYPE_NMI 0x2 // non-maskable interrupt www.datasheetarchive.com/download/95141983-7744ZC/ck001100.zip (am186msr.h) |
AMD | 22/02/1999 | 242.03 Kb | ZIP | ck001100.zip |