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adc interfaces with 8088 microprocessor

Catalog Datasheet MFG & Type PDF Document Tags

design adc interfaces with 8088 microprocessor

Abstract: adc interfaces with 8088 microprocessor interfaces include 8085A, 8088, Z80, STD BUS and 6800. Packaged in a 28-pin dip, the HS 9460 offers a space , hybrid systems uo o/icn w w corporation |â'"| ^ mt^qm Microprocessor Compatible Analog I/O Subsystem FEATURES â  4 Analog Input Channels â  8-Bit ADC â  4-, 8-Bit DAC Outputs â  Complete ^P Interface â  28-Pin Package DESCRIPTION The HS 9460 is a complete microprocessor compatible analog I/O subsystem. The HS 9460 contains a 4-channel multiplexer, CMOS ADC, logic timing and control circuitry, and 4
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8088 microprocessor circuit diagram

Abstract: SAB 8155 p SAB 8088 8-Bit Microprocessor Preliminary SAB 8088 5 MHz SAB 8088-2 8 MHz â'¢ 8-bit data bus , MHz for SAB 8088 8 MHz for SAB 8088-2 10 MHz for SAB 8088-1 â'¢ Compatible with industry standard , compatible with the industry standard 8088. With features like string handling, 16-bit arithmetic with , mode in SAB 8088 systems are sufficiently different that they cannot be met efficiently with 40 uniquely defined pins. Consequently, the SAB 8088 is equipped with a strap pin (MN/MX) which defines the
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instruction set of 8088 microprocessor

Abstract: Hardware and Software Interrupts of 8086 and 8088 8088 8-BIT HMOS MICROPROCESSOR 8088 8088-2 Y 8-Bit Data Bus Interface Y Byte Word and , -Bit Register Set with Symmetrical Operations Two Clock Rates 5 MHz for 8088 8 MHz for 8088-2 Y , Modes The Intel 8088 is a high performance microprocessor implemented in N-channel depletion load , maximum 8088 systems are sufficiently different that they cannot be done efficiently with 40 uniquely defined pins Consequently the 8088 is equipped with a strap pin (MN MX) which defines the system con
Intel
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SAB8284A

Abstract: Sab8284 8088-2 10 MHz for SAB 8088-1 * Compatible with industry standard 8088 â'¢ Available in a 40 , -pin plastic dual-in-line package (P-DIP-40). It is 100 percent compatible with the industry standard 8088 , efficiently with 40 uniquely defined pins. Conse­ quently, the SAB 8088 is equipped with a strap pin (M N /M , 8088 can be used with either a multiplexed or demultiplexed bus. The multiplexed bus configuration is , lock, queue status, and two request/grant interfaces are provided by the SAB 8088 in maximum mode
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SAB8284A Sab8284 8288 bus controller definition 8288/8288A AD7-A00 A15-A8
Abstract: 8088 8-Bit Microprocessor CPU ¡APX86 Family FINAL DISTIN C TIVE CHARA CTERISTICS â'¢ â'¢ â , of execu­ tion time. The 8088 is made with N-channel silicon gate technology and is packaged in a , Blank « 5 MHz - 2 - 8 MHz -1 » 10 MHz C. DEVICE NUMBER/DESCRIPTION 8088 8 -Bit Microprocessor , Microprocessor CPU Valid Combinations Valid Combinations 8088 8088-2 /BO A Valid Combinations list , addresses I/O with an 8-bit address on both halves of the 16-bit address bus. The 8088 uses a full 16 -
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D003750

8088 microprocessor circuit diagram

Abstract: ta 8268 ah AMD 8088 8-Bit Microprocessor CPU ¡APX86 Family FINAL DISTINCTIVE â'¢ 8-bit data bus, 16 , processors will appear identical to the software engineer, with the exception of execution time. The 8088 is , MHz -1-10 MHz c. DEVICE NUMBER/DESCRIPTION 8088 8-Bit Microprocessor CPU b. PACKAGE TYPE P - 40 , B b. SPEED OPTION Blank - 5 MHZ -2-8 MHZ a. DEVICE NUMBER/DESCRIPTION 8088 8-Bit Microprocessor , minimum mode when entering HALT, to allow the status to be latched with ALE. I/O Addressing In the 8088
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8088 microprocessor circuit diagram ta 8268 ah 8088 instruction set 8088 microprocessor iAPX 88 Book pin diagram of ic 8088 BD003750 16-BII

intel 8288

Abstract: intel 8288 bus controller , 8088, 8089 Multiprocessing Systems with the 8289 Bus Arbiter . A-lll AP , (8086) CPU + IOP (8086 + 8089) CPU with Math Extension (8088, 8087) iAPX 88121 - CPU with Math Extension + lOP (8088, 8087 + 8089) This improved numbering system will enable us to provide you with a , 100% code compatible with iAPX 86, yet it interfaces to an 8-bit wide data bus BIU. The bus interface , than is possible with a single microprocessor. This technique has been used successfully in the
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intel 8288 intel 8288 bus controller 8085 MICROCOMPUTER SYSTEMS USERS MANUAL 8086 interrupt structure design fire alarm 8088 microprocessor RCA SK CROSS-REFERENCE SA/C-258

ta 8268 ah

Abstract: instruction set of 8088 microprocessor AMD 8088 8-Bit Microprocessor CPU ¡APX86 Family FINAL DISTINCTIVE â'¢ 8-bit data bus, 16 , processors will appear identical to the software engineer, with the exception of execution time. The 8088 is , . SPEED OPTION Blank-5 MHz -2-8 MHz -1-10 MHz DEVICE NUMBER/DESCRIPTION 8088 8-Bit Microprocessor CPU b , or start up is accomplished with activation (HIGH) of the RESET pin. The 8088 RESET is required to be , and DEN are provided by the 8088. A write cycle also begins with the assertion of ALE and the emission
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instruction set of 8088 microprocessor 16 bit 8088 structure Hardware and Software Interrupts of 8086 and 8088 8088F 101010 8268 ah
Abstract: in te i 8088 8-BIT HMOS MICROPROCESSOR 8088/ 8088-2 8-Bit Data Bus Interface Byte, Word, and , Two Clock Rates: â'" 5 MHz for 8088 â'" 8 MHz for 8088-2 Direct Software Compatibility with 8086 , . Consequently, the 8088 is equipped with a strap pin (MN/MX) which defines the system con­ The minimum mode 8088 can be used with either a multiplexed or demultiplexed bus. The multiplexed bus configuration is , user with a minimum chip count system. This architecture provides the 8088 processing power in a -
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A18/SS A17/S4 A19/S6

processor intel 8088

Abstract: intel 8008 cpu 8088 8-BIT HMOS MICROPROCESSOR 8088/ 8088-2 â  8-Bit Data Bus Interface â  Byte, Word , Temperature Range The Intel 8088 is a high performance microprocessor implemented in N-channel, depletion , and maxi­ mum 8088 systems are sufficiently different that they cannot be done efficiently with 40 uniquely de­ fined pins. Consequently, the 8088 is equipped with a strap pin (MN/MX) which defines the system con­ The minimum mode 8088 can be used with either a multiplexed or demultiplexed bus. The
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processor intel 8088 intel 8008 cpu A16/S3
Abstract: in te i 8088 8-BIT HMOS MICROPROCESSOR 8088/8088-2 8-Bit Data Bus Interface Byte, Word , The Intel 8088 is a high performance microprocessor implemented in N-channel, depletion load, silicon , different that they cannot be done efficiently with 40 uniquely de­ fined pins. Consequently, the 8088 is , FFFFOH 3FFH 3F0H 4H 3H The minimum mode 8088 can be used with either a multiplexed or , . Hardware lock, queue status, and two request/grant interfaces are provid­ ed by the 8088 in maximum mode -
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SAB 8155 p

Abstract: how to interface 8085 with 8155 SAB8088 8-Bit Microprocessor Preliminary SAB 8088 5 MHz SAB 8088-2 8 MHz · 8-bit data bus , 8088-2 10 MHz for SAB 8088-1 · Compatible with industry standard 8088 · Available in a 40-pin plastic , is 100 percent compatible with the industry standard 8088. With features like string handling, 16 , maximum mode in SAB 8088 systems are sufficiently different that they cannot be met efficiently with 40 uniquely defined pins. Conse quently, the SAB 8088 is equipped with a strap pin (M N /M X ) which defines
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SAB 8155 p how to interface 8085 with 8155 SAB 8085 A-P SAB 8088-1-P 8287a 8283a PL-CC-44 A19/S6-A16/S3 A19/SE-A16/S3 8088-P 8088-2-P 8088-1-P

8X305

Abstract: 8X305 assembly manual firmware portion of the DCA and IBM interfaces This allows the MPA-II system to run with a variety of , unshielded twisted pair cable to the ADC Twisted Pair Plug provided with the MPA-II kit Then connect the , proliferation of the IBM and DCA interfaces coupled with the availability of detailed technical information , generally done Both the Smart Alec and IRMA interfaces are implemented with 74LS670 dual-ported register , System Core PC Interface Front End Interfaces Miscellaneous Support 6 0 SOFTWARE ARCHITECTURE Kernel
National Semiconductor
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8X305 8X305 assembly manual HP1650A Specification of seven segment 5250 d3800 dp8340 DP8344B D-82256

intel 8086 bus buffering and latching

Abstract: iAPX 86 88 user manual 8088 8-Bit Microprocessor CPU iAPX86 Family DISTINCTIVE CHARACTERISTICS · · · · · 8 -bit , to the software engineer, with the exception of execu tion time. The 8088 is made with N-channel , Information on Military Devices 8088 Status bits S3 through S6 are multiplexed with high order address , approximately 7 clock cycles. After this interval the 8088 operates normally, beginning with the instruction in , and DEN are provided by the 8088. A write cycle also begins with the assertion of ALE and the emission
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intel 8086 bus buffering and latching iAPX 86 88 user manual WF00682 c5cr intel 8284 clock generator intel 8284 02338B A18/S5

transistor A1011

Abstract: A1266 80C186EC/80C188EC Microprocessor User's Manual 80C186EC/80C188EC Microprocessor User , Intel Corporation. Intel Corporation and Intel's FASTPATH are not affiliated with Kinetics, a division , .3-5 3.3 MEMORY AND I/O INTERFACES , CONSIDERATIONS WITH THE INTERRUPT CONTROL UNIT. 8-42 8.6.1 Interrupt Latency and Response Time , .10-26 10.2.3 Using the DMA Unit with the Serial Ports
Intel
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transistor A1011 A1266 a1273 transistor scheme a1273 a1273 transistor DATA a1273 transistor 82C59A

8 stage pipeline architecture of ARMv7

Abstract: STM32F10x ADC is a small CPU with many support devices built into the chip ï'§ Self Contained (CPU, Memory, I/O , Architecture Memory Clock ADC - DAC I/O Port CPU BUS DMA TIMERs USARTx 7 CPU â , (Intel 8051, Motorola 6800, ATMEL AVR ) 16 bit (Intel 8088, Motorola 68000, TI MSP430) 32 bit (x86 , 17 Architecture Variations FFFFh Independent data and code memory but with one shared bus , executed with a single level pipelining. 21 CPU Internal Registers Program Counter (PC) Points to
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8 stage pipeline architecture of ARMv7 STM32F10x ADC STM32 STM32F103 STM32F102 128KB STM32F101 STM32F100

A1306 TRANSISTOR

Abstract: A1266 80C186EC/80C188EC Microprocessor User's Manual 80C186EC/80C188EC Microprocessor User , or trademark of Intel Corporation. Intel Corporation and Intel's FASTPATH are not affiliated with , .3-5 3.3 MEMORY AND I/O INTERFACES , CONSIDERATIONS WITH THE INTERRUPT CONTROL UNIT. 8-42 8.6.1 Interrupt Latency and Response Time , .10-26 10.2.3 Using the DMA Unit with the Serial Ports
Intel
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A1306 TRANSISTOR transistor a1266 a1232 transistor A1267 transistor a1276 a1273 y transistor

AD1674 AND APPLICATION NOTES

Abstract: AD574AJN Converter with Reference and Clock 8- and 16-Bit Microprocessor Bus Interface Guaranteed Linearity Over , alternate approach is to use the AD1674, which combines the ADC and SHA on one chip, with a total throughput , Higher Speed, Pinout-Compatible Versions (15|1s AD674B, 8|xs AD774B; 10|as (with SHA) AD1674) Available in Versions Compliant with MIL-STD-883 and JAN QPL. PRODUCT DESCRIPTION The AD574A is a complete 12-bit successive-approximation analog-to-digital converter with 3-state output buffer circuitry for direct interface to an 8- or
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AD574AJ AD574AS AD1674 AND APPLICATION NOTES AD574AJN ADS74A 68000a D83 ZENER Z80 PROCESSOR ADS74AL ADS74AU 8086-AD574A AD574

transistor A1046

Abstract: A1046 transistor 80C186EA/80C188EA Microprocessor User's Manual 80C186EA/80C188EA Microprocessor User , Intel Corporation. Intel Corporation and Intel's FASTPATH are not affiliated with Kinetics, a division , .3-5 3.3 MEMORY AND I/O INTERFACES , .8-7 8.3.3 Cascading with External 8259As , .11-7 11.4 MICROPROCESSOR AND COPROCESSOR OPERATION. 11-7 11.4.1
Intel
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transistor A1046 A1046 transistor TRANSISTOR A1048 A1048 transistor replacement of transistor A1006 80C186 programming

transistor A1046

Abstract: A1046 80C186XL/80C188XL Microprocessor User's Manual 80C186XL/80C188XL Microprocessor User , or trademark of Intel Corporation. Intel Corporation and Intel's FASTPATH are not affiliated with , .3-5 3.3 MEMORY AND I/O INTERFACES , .8-7 8.3.3 Cascading with External 8259As , .11-7 11.4 MICROPROCESSOR AND COPROCESSOR OPERATION. 11-7 11.4.1
Intel
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A1046 A1267 8085 assembly language A1516 A1015 A1300 transistor
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