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accumulator xilinx v7.0

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Abstract: 0 Accumulator v7.0 DS213 DS213 April 28, 2005 0 Product Specification 0 Features · , purpose. DS213 DS213 April 28, 2005 Product Specification www.xilinx.com 1 Accumulator v7.0 , Product Specification Accumulator v7.0 - - Constant Value: When this check box is checked Port , flip-flops. This www.xilinx.com 3 Accumulator v7.0 - The default setting is Sync Controls , . www.xilinx.com DS213 DS213 April 28, 2005 Product Specification Accumulator v7.0 Table 2 shows the XCO file ... Xilinx
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6 pages,
77.65 Kb

false DS213 accumulator xilinx v7.0 TEXT
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Abstract: 31 IP Release Notes Guide XTP025 XTP025 (v1.8) December 2, 2009 Xilinx Intellectual Property (IP) cores including LogiCORETM IP cores are delivered through software updates available from the Xilinx , " Embedded Wireless · "Embedded IP" · "CPRITM" · "OBSAI" © 2007-2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the , v3.1 32234 11.1 April 27, 2009 v3.0 31521 10.1 IP Update 3 September 19, 2008 ... Xilinx
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31 pages,
685.72 Kb

1000BASE-X 30291 8B10B CORDIC v4.0 defective pixel correction DSP48 DSP48 spartan 6 DVB-s2 ldpc encoder fir compiler v5 GT11 LDPC encoder decoder ip core 223-28 3GPP LTE MIMO Decoder LDPC encoder XTP025 XTP025 XTP025 LDPC decoder timing 24604 lte turbo encoder 33258 LDPC decoder ip core TEXT
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Abstract: Horizontal Accumulator Product Page Version Release Note Initial Release Date v11.0 32138 , Accumulator (MACC) Product Page Version Release Note Initial Release Date v2.0 30161 11.1 , 30 IP Release Notes Guide XTP025 XTP025 (v1.6) June 24, 2009 Xilinx Intellectual Property (IP) cores including LogiCORETM IP cores are delivered through software updates available from the Xilinx Download , " · "Serial RapidIO" Wireless · "CPRITM" · "OBSAI" © 2007-2009 Xilinx, Inc. XILINX, the Xilinx ... Xilinx
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30 pages,
656.21 Kb

23919 convolutional cpri v6.1 cpri 4.2 H.264 encoder chip lte xilinx turbo xilinx FFT v6.0 CORDIC v4.0 pci express SPARTAN-6 GTP dvb-s encoder design with fpga LTE DL Channel Encoder 25160 XTP025 24604 XTP025 LDPC encoder decoder ip core XTP025 LDPC decoder ip core XTP025 XTP025 XTP025 xilinx lte TURBO decoder its 31567 data sheet lte turbo encoder TEXT
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Abstract: predictable performance Incorporates Xilinx Smart-IPTM technology for utmost V Phase Accumulator T1 , customized such that the 0-cycle latency phase accumulator option is selected, and the sine-cosine look-up , 0 DDS v5.0 DS246 DS246 April 28, 2005 0 Product Specification 0 Features · · · · , implementation For use with v7.1i and later of the Xilinx CORE GeneratorTM system Applications · · · · , accumulator) 4 to 32-bit two's complement output sample precision Optional phase offset capability providing ... Xilinx
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26 pages,
1813.5 Kb

XIP166 lm 8712 quantizer verilog code verilog code of sine rom vhdl code for dds DS246 verilog code to generate sine wave verilog code for sine wave using FPGA DS246 equivalent XILINX vhdl code NCO vhdl code dds vhdl code to generate sine wave vhdl code for msk modulation TEXT
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Abstract: LogiCORE IP Multiply Accumulator v3.0 DS716 DS716 March 20, 2013 Product Specification , Specification www.xilinx.com 1 LogiCORE IP Multiply Accumulator v3.0 Pinout Signal names for the core , Accumulator v3.0 GUI Core Parameters The core parameters for this module are described below: â , Product Specification www.xilinx.com 3 LogiCORE IP Multiply Accumulator v3.0 Pipelined Operation , Performance and resource numbers for the Multiply Accumulator are not available for v3.0 of the core. They ... Xilinx
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5 pages,
143.54 Kb

DS716 TEXT
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Abstract: 0 Multiply Accumulator v2.0 DS716 DS716 April 24, 2009 0 Product Specification 0 Introduction Pinout The Xilinx® LogiCORETM IP Multiply Accumulator core provides implementations of , Specification www.xilinx.com 1 Multiply Accumulator v2.0 CORE Generator Graphical User Interface , 2 www.xilinx.com DS716 DS716 April 24, 2009 Product Specification Multiply Accumulator v2.0 , April 24, 2009 Product Specification Multiply Accumulator v2.0 Table 4: XtremeDSP Slice Multiply ... Xilinx
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5 pages,
145.77 Kb

vhdl code of pipelined adder DS716 DSP48Es vhdl code for accumulator TEXT
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Abstract: , which maps the 0 to 2 phase range into a digital word. Thus, for an n-bit accumulator, 2 = 2n, and the , R phase_inc Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 , resolution is controlled via phase accumulator word length (3-30 bits) Controllable phase noise via , ) mapping and placement technology Incorporates Xilinx Smart-IP technology for maximum performance To be used with version 2.1i and later of the Xilinx CORE Generator System Figure 1: Main ... Xilinx
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5 pages,
116.29 Kb

analog to digital converter vhdl coding VHDL code for dac phase change converter circuit design vhdl for 8 point fft in xilinx XC4000 XC4000E vhdl code for accumulator matlab precision Sine Wave Generator programmable Sine Wave Generator quadrature phase sine wave generator XILINX vhdl code NCO vhdl code for FFT 4096 point vhdl code to generate staircase wave X9025 vhdl code for FFT 16 point Numerically Controlled Oscillator vhdl code to generate sine wave TEXT
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Abstract: Direct Digital Synthesizer (DDS) V4.0 October 4, 2001 Product Specification · · Xilinx , architecture is shown in Figure 20. October 4, 2001 Xilinx, Inc. Phase Accumulator Phase Increment , the 0-cycle latency phase accumulator option is selected, and the sinecosine look-up table is in , longer present. October 4, 2001 Xilinx, Inc. 0 = 10 bits -60 dB -60 (23) dB , placement technology for maximum and predictable performance Incorporates Xilinx Smart-IP technology for ... Xilinx
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22 pages,
1007.98 Kb

2061d xilinx dds DAC 5754 FPGA FAMILY precision waveform generator dds vhdl direct digital synthesizer quadrature phase sine wave generator precision Sine Wave Generator xilinx logicore core dds PHASE SHIFT KEYING PSK TEXT
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Abstract: . These files contain designs in which the accumulator is implemented using basic Xilinx primitives. Note , primitive (MULT18X18 MULT18X18 and MULT18X18S MULT18X18S) implemented in VHDL and Verilog. In addition, an accumulator unit has , Standard Design Speed Grade -5 Device 81 162 MHz © 2003-2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at , : Xilinx is providing this design, code, or information "as is." By providing the design, code, or ... Xilinx
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16 pages,
117.9 Kb

XC2V250 4 bit multiplier VERILOG 8 bit multiplier using verilog code MULT18X18 vhdl code for 18x18 SIGNED MULTIPLIER verilog code for 16*16 multiplier multiplier and accumulator XAPP636 MULT18X18S verilog code for 16 bit multiplier addition accumulator MAC code verilog multiplier accumulator unit with VHDL 16 bit multiplier VERILOG circuit vhdl code for accumulator multiplier accumulator MAC code verilog multiplier accumulator MAC code VHDL 16 bit multiplier VERILOG TEXT
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Abstract: asserted, the accumulator will be reset to 0. On the first cycle following the disassertion of SCLR, the , 0 DDS Compiler v2.0 DS558 DS558 May 17, 2007 0 Product Specification 0 Features , -bit phase accumulator) · 4-bit to 20-bit two's complement output sample precision · Optional phase offset , frequency option · Incorporates Xilinx SmartIPTM technology for utmost parameterization and optimum implementation A high-level view of the DDS core is presented in Figure 1. · For use with Xilinx CORE ... Xilinx
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27 pages,
777.51 Kb

XIP166 XC3SD3400A DS558 vhdl code for accumulator DSP48 DSP48 spartan 6 phase shift keying EP-2000 spartan 3a 018HZ vhdl code for msk modulation vhdl code dds xilinx logicore core dds TEXT
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Xilinx 12/07/2004 223.08 Kb ZIP xapp264.zip
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Xilinx 13/07/1998 813.13 Kb ZIP wcd02eb0.zip
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Xilinx 05/09/1996 813.13 Kb ZIP xamfir.zip
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Xilinx 12/02/1999 813.13 Kb ZIP wcd036d7.zip
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Xilinx 09/04/1997 813.13 Kb ZIP xamfir.zip
Xilinx  11/9/95  FD Base Register V1.0 LogiCORE Xilinx 12/17/99 LD Base Latch V1.0 LogiCORE Xilinx   7/17/98  Accumulator LogiBLOX Xilinx  5/25/97  Accumulator LogiCORE Xilinx  12/17/99 Scaled by 1/2 Accumulator LogiCORE Xilinx  7/17/98  Adder/Subtractor
/datasheets/files/xilinx/docs/rp00005/rp00589.htm
Xilinx 29/02/2000 59.56 Kb HTM rp00589.htm
  Binary Decoder  LogiCORE Xilinx  Single Output Gate V1.0   Bus Gate V1.0 LogiCORE Xilinx  Bus Gated With Control Bit V1.0 LogiCORE Xilinx  FD Base Register V1.0 LogiCORE Xilinx  LD Base Latch V1.0 LogiCORE Xilinx  Bit Multiplexer   Accumulator LogiCORE Xilinx  Adder/Subtractor LogiCORE
/datasheets/files/xilinx/docs/rp00001/rp0017b.htm
Xilinx 29/02/2000 38.34 Kb HTM rp0017b.htm
Decoder LogiCORE Xilinx Single Output Gate V1.0 LogiCORE Xilinx Binary Counter LogiCORE Xilinx Bus Gate V1.0 LogiCORE Xilinx Bus Gated With Control Bit V1.0 LogiCORE Xilinx FD Base Register V1.0 LogiCORE Xilinx LD Base Latch V1.0 LogiCORE Xilinx Bit Multiplexer LogiCORE
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Xilinx 06/03/2000 31.57 Kb HTM rp001ef.htm
No abstract text available
/download/23745346-995959ZC/xapp284.zip ()
Xilinx 24/07/2002 59.12 Kb ZIP xapp284.zip
  PCI32 PCI32 4000XLA 4000XLA V3.0  7/7/99  Xilinx and AllianceCORE partners announce PDF files below. February 2/28/00 Xilinx and Xentec Announce Image Alpha Data Parallel Systems 2/14/00 Xilinx and AllianceCORE Xilinx below $10 LogiCORE Reed-Solomon Decoder LogiCORE Reed-Solomon Encoder January 1/31/00 Xilinx Extends its Lead in PCI
/datasheets/files/xilinx/docs/rp00005/rp00575.htm
Xilinx 06/03/2000 30.5 Kb HTM rp00575.htm