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SN74LS681N Texas Instruments 4-Bit Parallel Binary Accumulator 20-PDIP 0 to 70 visit Texas Instruments
PMP7804 Texas Instruments Xilinx 7 Series Power Module Reference design visit Texas Instruments
PMP6776 Texas Instruments Xilinx Kintex 7 Low Cost reference design visit Texas Instruments
PMP8251.3 Texas Instruments Power Solution for Xilinx FPGA Zynq 7 visit Texas Instruments
PMP6577.3 Texas Instruments Power Solution for Xilinx 7-Series MGT with 5V input voltage (1.8V @ 2.6A) visit Texas Instruments
PMP7804.6 Texas Instruments Xilinx 7 Series Power Module Reference design(1V@6A) visit Texas Instruments

accumulator xilinx v7.0

Catalog Datasheet MFG & Type PDF Document Tags

accumulator xilinx v7.0

Abstract: false 0 Accumulator v7.0 DS213 April 28, 2005 0 Product Specification 0 Features · , purpose. DS213 April 28, 2005 Product Specification www.xilinx.com 1 Accumulator v7.0 , Product Specification Accumulator v7.0 - - Constant Value: When this check box is checked Port , flip-flops. This www.xilinx.com 3 Accumulator v7.0 - The default setting is Sync Controls , . www.xilinx.com DS213 April 28, 2005 Product Specification Accumulator v7.0 Table 2 shows the XCO file
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accumulator xilinx v7.0 false low power and area efficient carry select adder

LDPC decoder ip core

Abstract: 33258 31 IP Release Notes Guide XTP025 (v1.8) December 2, 2009 Xilinx Intellectual Property (IP) cores including LogiCORETM IP cores are delivered through software updates available from the Xilinx , " Embedded Wireless · "Embedded IP" · "CPRITM" · "OBSAI" © 2007-2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the , v3.1 32234 11.1 April 27, 2009 v3.0 31521 10.1 IP Update 3 September 19, 2008
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LDPC decoder ip core 33258 24604 lte turbo encoder LDPC decoder timing 3GPP LTE MIMO Decoder 8B10B 64B/66B

lte turbo encoder

Abstract: its 31567 data sheet Horizontal Accumulator Product Page Version Release Note Initial Release Date v11.0 32138 , Accumulator (MACC) Product Page Version Release Note Initial Release Date v2.0 30161 11.1 , 30 IP Release Notes Guide XTP025 (v1.6) June 24, 2009 Xilinx Intellectual Property (IP) cores including LogiCORETM IP cores are delivered through software updates available from the Xilinx Download , " · "Serial RapidIO" Wireless · "CPRITM" · "OBSAI" © 2007-2009 Xilinx, Inc. XILINX, the Xilinx
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its 31567 data sheet xilinx lte TURBO decoder LDPC encoder decoder ip core dvb-s encoder design with fpga 25160 LTE DL Channel Encoder 1000BASE-X

vhdl code for msk modulation

Abstract: vhdl code to generate sine wave predictable performance Incorporates Xilinx Smart-IPTM technology for utmost V Phase Accumulator T1 , customized such that the 0-cycle latency phase accumulator option is selected, and the sine-cosine look-up , 0 DDS v5.0 DS246 April 28, 2005 0 Product Specification 0 Features · · · · , implementation For use with v7.1i and later of the Xilinx CORE GeneratorTM system Applications · · · · , accumulator) 4 to 32-bit two's complement output sample precision Optional phase offset capability providing
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vhdl code for msk modulation vhdl code to generate sine wave vhdl code dds XILINX vhdl code NCO DS246 equivalent verilog code for sine wave using FPGA
Abstract: LogiCORE IP Multiply Accumulator v3.0 DS716 March 20, 2013 Product Specification , Specification www.xilinx.com 1 LogiCORE IP Multiply Accumulator v3.0 Pinout Signal names for the core , Accumulator v3.0 GUI Core Parameters The core parameters for this module are described below: â , Product Specification www.xilinx.com 3 LogiCORE IP Multiply Accumulator v3.0 Pipelined Operation , Performance and resource numbers for the Multiply Accumulator are not available for v3.0 of the core. They Xilinx
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vhdl code for accumulator

Abstract: vhdl code for SIGNED MULTIPLIER accumulator 0 Multiply Accumulator v2.0 DS716 April 24, 2009 0 Product Specification 0 Introduction Pinout The Xilinx® LogiCORETM IP Multiply Accumulator core provides implementations of , Specification www.xilinx.com 1 Multiply Accumulator v2.0 CORE Generator Graphical User Interface , 2 www.xilinx.com DS716 April 24, 2009 Product Specification Multiply Accumulator v2.0 , April 24, 2009 Product Specification Multiply Accumulator v2.0 Table 4: XtremeDSP Slice Multiply
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vhdl code for accumulator vhdl code for SIGNED MULTIPLIER accumulator DSP48Es vhdl code of pipelined adder

vhdl code to generate sine wave

Abstract: Numerically Controlled Oscillator , which maps the 0 to 2 phase range into a digital word. Thus, for an n-bit accumulator, 2 = 2n, and the , R phase_inc Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 , resolution is controlled via phase accumulator word length (3-30 bits) Controllable phase noise via , ) mapping and placement technology Incorporates Xilinx Smart-IP technology for maximum performance To be used with version 2.1i and later of the Xilinx CORE Generator System Figure 1: Main
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XC4000E X9025 Numerically Controlled Oscillator vhdl code for FFT 16 point matlab precision Sine Wave Generator vhdl code to generate staircase wave quadrature phase sine wave generator

sine cosine phase quadrant look-up address

Abstract: PHASE SHIFT KEYING PSK Direct Digital Synthesizer (DDS) V4.0 October 4, 2001 Product Specification · · Xilinx , architecture is shown in Figure 20. October 4, 2001 Xilinx, Inc. Phase Accumulator Phase Increment , the 0-cycle latency phase accumulator option is selected, and the sinecosine look-up table is in , longer present. October 4, 2001 Xilinx, Inc. 0 = 10 bits -60 dB -60 (23) dB , placement technology for maximum and predictable performance Incorporates Xilinx Smart-IP technology for
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sine cosine phase quadrant look-up address PHASE SHIFT KEYING PSK is706 xilinx logicore core dds dds vhdl xilinx dds

multiplier accumulator MAC code VHDL

Abstract: 16 bit multiplier VERILOG . These files contain designs in which the accumulator is implemented using basic Xilinx primitives. Note , primitive (MULT18X18 and MULT18X18S) implemented in VHDL and Verilog. In addition, an accumulator unit has , Standard Design Speed Grade -5 Device 81 162 MHz © 2003-2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at , : Xilinx is providing this design, code, or information "as is." By providing the design, code, or
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XAPP636 multiplier accumulator MAC code VHDL 16 bit multiplier VERILOG multiplier accumulator MAC code verilog addition accumulator MAC code verilog 16 bit multiplier VERILOG circuit multiplier accumulator unit with VHDL 159MH 183MH 202MH

xilinx logicore core dds

Abstract: vhdl code dds asserted, the accumulator will be reset to 0. On the first cycle following the disassertion of SCLR, the , 0 DDS Compiler v2.0 DS558 May 17, 2007 0 Product Specification 0 Features , -bit phase accumulator) · 4-bit to 20-bit two's complement output sample precision · Optional phase offset , frequency option · Incorporates Xilinx SmartIPTM technology for utmost parameterization and optimum implementation A high-level view of the DDS core is presented in Figure 1. · For use with Xilinx CORE
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DSP48 spartan 3a 018HZ EP-2000 phase shift keying DSP48 spartan 6 BRAM18

1 bit register truth table

Abstract: XC4000E placement technology Available in Xilinx CORE Generator C S X 0 No Change 0 _/ No , /2 Accumulator Table 2: Core Signal Pinout Signal L B[n:0] Cl CE C S[n+1:0 , 1/2 Accumulator Xilinx , dsp_acc2s.fm Page 105 Wednesday, March 4, 1998 2:51 PM Scaled By 1/2 Accumulator March 16, 1998 Product Specification R Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778
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1 bit register truth table

XILINX vhdl code NCO

Abstract: low pass Filter VHDL code accumulator, which maps the 0 to 2 phase range into a digital word. Thus, for an n-bit accumulator, 2 = 2n , phase_inc amp load >c Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 , phase accumulator word length (3-30 bits) User can control phase noise via programmable phase , Incorporates Xilinx Smart-IP technology for maximum performance Figure 1: Parameterization Window To be used with version 2.1i and later of the Xilinx CORE Generator System Functional Description The
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low pass Filter VHDL code VHDL code for dac amplitude demodulation using xilinx system generator 3 phase generator sine vhdl for 8 point fft in xilinx VHDL code for band pass Filter

VHDL code for polyphase decimation filter using D

Abstract: verilog code for decimation filter to accumulate the remainder as the accumulator wraps around its max/min values. Xilinx System , decimating filter architectures and discusses the fractional rate decimator, its Xilinx System Generator , block. There are a few requirements on the appropriate sampling frequency, and © 2006-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers , subject to change without notice. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or
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XAPP936 VHDL code for polyphase decimation filter using D verilog code for decimation filter VHDL code for polyphase decimation filter 16 QAM modulation verilog code qpsk modulation VHDL CODE 16 QAM modulation matlab 16-QAM DSP48E UG073 UG193

vhdl code for accumulator

Abstract: VHDL code for dac is governed by the phase accumulator, which maps the 0 to 2 phase range into a digital word. Thus , amp load clr Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax , Frequency resolution is controlled via phase accumulator word length (3 to 30 bits) User can control phase , Figure 1: Parameterization Window · placement technology Available in Xilinx CORE Generator Tool , increment register, a phase accumulator, and a sine/cosine ROM look-up table (LUT). The increment register
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vhdl code for FFT 4096 point code for NCO 8 point fft code in vhdl free fft vhdl code DAC spartan 3 X8820

XC4000E

Abstract: Acoustics register, an "integrate and dump" accumulator is realized. This versatile ADD Q S[m:0] 0 CE , Specification R Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 , Clock Enable for internal register Can be used as a general purpose parameterized accumulator for , Macro (RPM) mapping and placement technology Available in Xilinx CORE Generator device can serve as , and described in Table 1. D B[n:0] The ideal integrator transfer function HI(z)=1/(1-z-1), has
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ASSP29 Acoustics

quadrature phase sine wave generator

Abstract: vhdl code to generate staircase wave accumulator, which maps the 0 to 2 phase range into a digital word. Thus, for an n-bit accumulator, 2 = 2n , phase_inc amp load Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax , via phase accumulator word length (3 to 30 bits) User can control phase noise via programmable phase , ) mapping and placement technology Available in Xilinx CORE Generator Tool Functional Description The , increment register, a phase accumulator, and a sine/cosine ROM look-up table (LUT). The increment register
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analog to digital converter vhdl coding vhdl for 8 point fft X8824 amplitude demodulation matlab code

1 bit register truth table

Abstract: register with truth table placement technology Available in Xilinx CORE Generator CE C S X X 0 No Change X 0 _/ No Change 0 Features LOAD 1 _/ 1/2S + B + CI 1 1 _/ B , Scaled By 1/2 Accumulator Table 2: Core Signal Pinout Signal L B[n:0] Cl CE C S[n+1:0 , dsp_acc2s.fm Page 105 Tuesday, July 14, 1998 7:43 AM Scaled By 1/2 Accumulator July 17, 1998 Product Specification R Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778
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register with truth table

verilog code for fir filter using DA

Abstract: implementation of 16-tap fir filter using fpga Accumulator Ci LOOKUP TABLE PS_BITS_0 D S-REG Di Figure 20. LUT-Based 2-Bit Parallel , Processing Performance Gregory Ray Goslin Digital Signal Processing Program Manager Xilinx, Inc. 2100 , the 16-Tap FIR filter implemented in a state-of-the-art fixed-point DSP with that of the Xilinx FPGA , "Reconfigurable Computing" technique is beginning to impact design methodologies. © 1995 XILINX, Inc. All , -3 @CLK=66MHz 20 2-Bit Parallel DA @16MHz 15 10 5 8-Bit Serial DA @8MHz DSP Region 0 1
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XC6200 verilog code for fir filter using DA implementation of 16-tap fir filter using fpga xilinx code for 8-bit serial adder 4 tap fir filter based on mac vhdl code 16-Tap, 8-Bit FIR Filter Application Guide," Xilinx Publications, design of FIR filter using vhdl abstract

integrator

Abstract: ASSP29 Specification R Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 , Clock Enable for internal register Can be used as a general purpose parameterized accumulator for , Macro (RPM) mapping and placement technology Available in Xilinx CORE Generator Functional Description The ideal integrator transfer function HI(z)=1/(1-z-1), has a pole at f=0. It is ideal in the , susceptible to overflow and adequate word growth of the accumulator register must be provided
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integrator

low power and area efficient carry select adder

Abstract: Accumulator V1.0.3 December 17, 1999 Product Specification · R · · · Xilinx Inc , none 0 clear_overrides_set December 17, 1999 Xilinx , : www.xilinx.com/support/techsup/appinfo www.xilinx.com/ipcenter · Functional Description The Accumulator , User programmable feedback scaling Figure 1: Main Accumulator Parameterization Screen Fi December , output Optional Bypass (Load) capability Incorporates Xilinx Smart-IP technology for maximum
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