ZXFV4583 SO16N ZXFV4583N16TA ZXFV4583N16TC TJMAX150C 120C/W 27BSC 050BSC - Datasheet Archive

 

SYNC SEPARATOR WITH VARIABLE FILTER DEVICE DESCRIPTION FEATURES AND BENEFITS The ZXFV4583 provides the ability to separate out

 

ZXFV4583 ZXFV4583 SYNC SEPARATOR WITH VARIABLE FILTER DEVICE DESCRIPTION FEATURES AND BENEFITS The ZXFV4583 ZXFV4583 provides the ability to separate out video synchronisation signals for a wide variety of TV and CRT display systems, standard and non-standard. · PAL, NTSC, SECAM, other TV systems · Variable filter for outputs: composite, horizontal, Vertical, back porch, odd / even · No-signal detector Flexibility arises from the use of just three external resistors to adapt to each application. One resistor controls a fully integrated internal color carrier filter with variable bandwidth. This filter avoids disturbance from the color carrier, permitting accurate threshold slicing for timing extraction. · On chip sample / hold capacitors · +5V single supply · Default vertical output where there are no serration pulses · Pin compatible with industry standard part SO16N SO16N A second resistor controls the voltage threshold for loss of signal detection after a time-out interval. The third resistor controls the timing functions. surface mount package APPLICATIONS DC restoration for displays is facilitated by the Back Porch synch output, which can be used to drive an external circuit to clamp the blanking voltage to a fixed level. · Digital image capture · Video input systems requiring separation of picture timing · Video distribution ORDERING INFORMATION Part Number Container ZXFV4583N16TA ZXFV4583N16TA Reel 7 ZXFV4583N16TC ZXFV4583N16TC Reel 13 · CCTV surveillance Increment · Digital multimedia 500 · Timing for black level clamp 2500 CONNECTION DIAGRAM ISSUE 1 - MARCH 2003 1 SEMICONDUCTORS ZXFV4583 ZXFV4583 ABSOLUTE MAXIMUM RATINGS Supply voltage VCC -0.5V to +7V Inputs to ground* -0.5V to VCC +0.5V Operating Temperature Range -40C to 85C Storage -65C to +150C Operating Ambient Junction temperature TJMAX150C TJMAX150C* *The thermal resistance from the semiconductor die to ambient is typically 120C/W 120C/W when the SO16 package is mounted on a PCB in free air. The power dissipation of the device when loaded must be designed to keep the device junction temperature below TJMAX. *During power-up and power-down, these voltage ratings require that signals be applied only when the power supply is connected. ELECTRICAL CHARACTERISTICS VCC = 5V, RSET = 680k, RFILT = 22k, RNOSIG = 82k, Tamb = 25C unless otherwise stated. Test level: P = 100% production test C = Characterised only PARAMETER CONDITIONS TEST MIN TYP MAX UNIT P 2 4.5 6.5 1.2 1.35 1.5 DC Characteristics Supply current mA Clamp voltage Pin 4 unloaded P Discharge current at FILTIN Pin 4, Vin = 2V pk-pk C Discharge current at FILTIN Pin 4, no signal C 3 6 12 A Clamp charge current at FILTIN Pin 4, Vin = 1V pk-pk P 2 3 4 mA Clamp voltage at FVIDIN Pin 8 unloaded P 1.2 1.35 1.5 V Discharge current at FVIDIN Pin 8, Vin = 2V pk-pk C Discharge current at FVIDIN Pin 8, no signal C 3 6 12 Clamp charge current at FVIDIN Pin 8, Vin = 1V pk-pk P 2 3 4 mA R SET voltage, pin 12 P 1.5 1.75 2 V R FILT voltage, pin 1 P 0.35 0.5 0.65 V RNOSIG current, pin 2 P 1.5 2.5 3.5 A 0.35 0.8 V Logic output Low voltage, V OL I OL = 1.6mA Logic output High voltage, V OH I OH = 1.6mA P 1 P 2.4 4 V A 1 V ISSUE 1 - MARCH 2003 SEMICONDUCTORS 2 ZXFV4583 ZXFV4583 ELECTRICAL CHARACTERISTICS (CONT) VCC = 5V, RSET = 681k, RFILT = 22k, Tamb = 258C unless otherwise stated. PARAMETER CONDITIONS TEST MIN TYP MAX UNIT AC Characteristics FILTIN function input voltage range PAL/NTSC P 0.5 Filter voltage gain FILTIN to FILOUT P 4.9 5.7 Filter attenuation 4.4MHz for PAL, 3.6MHz for NTSC P P 15 10 19 14 40 Slice level Vin = 1V pk-pk P CSYNC prop. Delay, t CS VSYNC delay Relative to pin 4 input P C VSYNC default delay, t VSD P HSYNC delay P BKPCH delay, t BD Relative to pin 4 input 60 % 400 ns ns s s 195 45 s 5 6.2 s 250 30 400 ns 36 250 3.8 P ns 2.7 3.7 4.7 s P 450 540 680 mV P Input 1 Vpk-pk, pin 4 NOSIG time-out delay after loss of signal Note: dB dB P BKPCH pulse width, t B VLEV output dB 165 P HSYNC pulse width, t HSYNC V pk-pk 250 C VSYNC pulse width, t VSYNC (NTSC) 50 250 C VSYNC pulse width, t VSYNC (PAL) 2 6.5 400 600 800 s In order to avoid coupling between high speed logic output signals and analog inputs, the test circuit layout uses connections from the logic output pins routed away from the analog pins. In the application, similar care in the layout is required, keeping resistors RFILT, RNOSIG and RSET close to their respective pins, in particular routing signal CSYNC away from pins 1, 2 and 12. ISSUE 1 - MARCH 2003 3 SEMICONDUCTORS ZXFV4583 ZXFV4583 CONNECTIONS PIN No. 1 2 PIN NAME TYPE Resistor control RFILT FUNCTION Controls the input color carrier filter characteristic. An external resistor R FILT connected from this pin to 0V sets the bandwidth. Smaller R FILT gives increased bandwidth. See the detailed operating description below. Resistor control RNOSIG Controls the no-signal detector level. An external resistor R NOSIG connected from this pin to 0V sets the threshold voltage level, according to the equation V PMIN = 0.75 R NOSIG / R SET where V PMIN is the minimum detected sync pulse amplitude at pin 4 and R SET is the resistor value at pin 12. Composite sync logic output. Includes all sync pulses derived from the input video. Input to color carrier filter. This is the main analog (unfiltered) composite video input used when color carrier filtering is required. A Analog in voltage clamp circuit and adaptive current source are also included at this node. See the detailed operating description. When the filter is not used, this pin must be left open circuit. Vertical sync output. This is an active low pulse commencing on the first Logic out vertical sync pulse trailing (rising) edge and ending near the second next equalising pulse. See timing diagram. 3 CSYNC Logic out 4 FILTIN 5 VSYNC 6 OVD 7 FILTOUT Analog out Analog output signal from color carrier filter. The filter voltage gain is nominally 2. This output is normally capacitor-coupled to pin 8. 8 FVIDIN Input for filtered analog video signal input. This is the direct input to the sample/hold and sync slicing comparator providing the logic timing Analog in edges. This input is normally coupled via an external capacitor from FILTOUT, pin 7. It may be used as the signal input where the color carrier filter is not required. Includes a clamp similar that of pin 4. 9 VLEV Analog out Analog output, a positive voltage typically equal to twice the (negative) peak sync pulse amplitude if the filter is used. 10 NOSIG Ground Logic out 11 BKPCH Logic out 12 RSET Resistor control 13 ODDFLD Logic out 14 V+ Power in 15 HSYNC Logic out 16 OVA Ground Provides ground return path for internal logic output buffer circuits. Normally connected externally to a common PCB ground plane. Logic output, which goes high after a time-out delay when no signal is present. The threshold level is controlled at pin 2. Burst or Back Porch logic output, an active low monostable pulse triggered from rising composite sync pulse edges. The width is set by R SET to overlap most of the steady part of the back porch, assuming the color carrier burst has been attenuated sufficiently by filtering. This pulse is then suitable for controlling an external black level clamping circuit. See the timing diagram. Controls the timing interval of the sample/hold circuit and the monostable interval for the sync outputs according to the application. An external resistor, R SET connected from this pin to 0V establishes the timing parameter, to which these times are scaled together. See the detailed operating description. Odd field logic output. High during an odd numbered field, low during even. This output is timed with the start of the VSYNC pulse. Power supply input, +5V. Horizontal sync logic output. Monostable output derived from CSYNC falling edges, it achieves a steady stream of 5µs pulses. The half line events during the field blanking interval are eliminated. See timing diagram. Analog ground. Normally connected externally to a common PCB ground plane. ISSUE 1 - MARCH 2003 SEMICONDUCTORS 4 ZXFV4583 ZXFV4583 DETAIL DESCRIPTION The vertical sync output VSYNC is derived from the Field pulse group. Where there are short equalisation pulses in the standard systems, these short pulses are ignored. Essentially, a pulse width discriminator circuit senses the first of the Field pulses, as they are wider than those of the rest of the sequence. The trailing edge of the first negative-going Frame Pulse (i.e. the rising edge of the first "serration" pulse) triggers the VSYNC output. In systems with a frame interval with no serration pulses, a vertical sync output is provided after a default delay as in Figure 4. Also provided is an ODDFLD logic output, which is high during an odd-numbered field and low during an even one. Introduction This device includes all the functions required to separate out the critical timing points of most types of video signal. A sample-and-hold process is used to establish accurately the 50% point of the sync pulse. The input is also filtered to avoid the effect of the color carrier. The filter is coupled externally. The following paragraphs give a simplified description of the signal processing. Color Carrier Filter This is a low-pass filter providing adjustable attenuation of the color carrier with low distortion of the remaining sync pulses so as to ensure accurate timing of the extracted logic outputs. The control is via an external resistor RFILT connected from pin 1 to ground. RFILT=22k gives corner frequency of 1.3MHz c o r r e s p ondi ng t o ~ 1 2 dB a t t e nu a t i o n @ 3.58MHz.(Corner freq. Proportional to 1/RF, minimum value 18k). A graph shows how the bandwidth varies with the resistor value (Graph to be provide in future issue). The horizontal sync HSYNC is a monostable output derived from the leading edge of the composite sync. The pulse width is about 5 µs. Also, during the Field blanking sequence, the additional half-line pulses are removed by a timing circuit with a pulse interval discrimination function controlled by RSET. RSET =680k for standard PAL or NTSC timings. The timings in datasheet tables correspond to this value. (Pulse widths, Delays etc proportional to RSET, ie scan rate proportional to 1/RSET Clamping Circuits Clamping circuits are use to limit the signal swing excursion after AC coupling at both the input to the filter, FILTIN and the timing extractor input, FVIDIN. In each case, the sync tip level is maintained at a value of nominally 1.35V. The Back Porch monostable output BKPCH is initiated from the trailing edge of the composite sync. The pulse is active low and the width is set according to RSET. Sync Timing Extraction Circuits The waveforms are depicted in Timing Diagrams, Figure 1 for PAL (625 lines) and Figure 2 for NTSC (525 lines). Sample-and-hold circuits are used to obtain time-delayed voltage values of the sync tip and the back porch. The sample gates are controlled by a comparator sensing the video input relative to a threshold at a fixed offset above the sync tip clamp level. The sampled voltages are combined in a potential divider to derive the mean voltage (50% amplitude), which is used as the sync pulse threshold. A second comparator then provides CSYNC, the logic version of the composite sync signal. This is delayed slightly as shown in Figure 3. The time delay comprises that of the input filter and also the smaller delay of the comparator and logic. The timing of the sample hold and other time parameters are all controlled together in unison by the external resistor RSET. A 1% resistor tolerance is recommended. The sync tip voltage level from the sample-and-hold is buffered and provided as an analog output, VLEV. Loss-of-Signal Detector Loss of signal is indicated by a logic high level at the output NOSIG. The decision threshold is set by an external resistor RNOSIG connected from pin 2 to ground. RNOSIG =100k gives a shut off threshold of 250mV of sync amplitude at FVIDIN or ~130mV on FILTIN (Threshold proportional to RNOSIG, minimum value 82k) The table of connections above gives the equation used to determine a suitable resistor value. A waiting time of nominally 600 µs occurs before the loss of signal is flagged. ISSUE 1 - MARCH 2003 5 SEMICONDUCTORS ZXFV4583 ZXFV4583 Figure 1: PAL 625 TIMING DIAGRAM VIDEO INPUT 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 CSYNC OUTPUT VSYNC OUTPUT HSYNC OUTPUT BACK PORCH OUTPUT, BKPCH Figure 2: NTSC TIMING DIAGRAM ISSUE 1 - MARCH 2003 SEMICONDUCTORS 6 ZXFV4583 ZXFV4583 BD Figure 3: SYNC SLICING & OUTPUT DETAIL Figure 4: VERTICAL SYNC DEFAULT ISSUE 1 - MARCH 2003 7 SEMICONDUCTORS ZXFV4583 ZXFV4583 TYPICAL CHARACTERISTICS ISSUE 1 - MARCH 2003 SEMICONDUCTORS 8 ZXFV4583 ZXFV4583 TYPICAL CHARACTERISTICS (Cont.) ISSUE 1 - MARCH 2003 9 SEMICONDUCTORS ZXFV4583 ZXFV4583 PACKAGE OUTLINE L E H D Pin1 A c A1 Seating Plane e b Millimetres Inches DIM MIN MAX MIN MAX A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.008 0.010 D 9.80 10.00 0.386 0.394 E 3.80 4.00 0.150 0.157 e H 1.27BSC 27BSC 5.80 0.050BSC 050BSC 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 0° 8° 0° 8° Conforms to JEDEC MS-012AC MS-012AC Iss C (SO16N SO16N) © Zetex plc 2003 Americas Asia Pacific Zetex GmbH Streitfeldstraße 19 D-81673 D-81673 München Zetex Inc 700 Veterans Memorial Hwy Hauppauge, NY 11788 Germany Telefon: (49) 89 45 49 49 0 Fax: (49) 89 45 49 49 49 europe.sales@zetex.com USA Telephone: (1) 631 360 2222 Fax: (1) 631 360 8222 usa.sales@zetex.com Zetex (Asia) Ltd 3701-04 Metroplaza Tower 1 Hing Fong Road Kwai Fong Hong Kong Telephone: (852) 26100 611 Fax: (852) 24250 494 asia.sales@zetex.com Europe Zetex plc Fields New Road Chadderton Oldham, OL9 8NP United Kingdom Telephone (44) 161 622 4444 Fax: (44) 161 622 4446 hq@zetex.com These offices are supported by agents and distributors in major countries world-wide. This publication is issued to provide outline information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose or form part of any order or contract or be regarded as a representation relating to the products or services concerned. The Company reserves the right to alter without notice the specification, design, price or conditions of supply of any product or service. For the latest product information, log on to www.zetex.com ISSUE 1 - MARCH 2003 SEMICONDUCTORS 10