ZL50409 10/100M 256KB ZL50409GDC IEEE-1149 PVMAP00 HASH10 HASH32 HASH54 HASH76 - Datasheet Archive

 

Managed 9-Port 10/100M Ethernet Switch Data Sheet Features · · · · · · ·

 

ZL50409 ZL50409 Managed 9-Port 10/100M 10/100M Ethernet Switch Data Sheet Features · · · · · · · · · · · November 2003 8 10/100 Mbps auto-negotiating ports with RMII, MII & GPSI interface options 1 10/100 Mbps auto-negotiating MII port (port 9) that can be used as a WAN uplink or as a 9th port Supports both managed and unmanaged options · Supports 8/16-bit parallel or serial+MII interface in managed mode · Serial interface in lightly managed or unmanaged mode Internal 2Mbit (256KB 256KB) buffer memory Up to 4K MAC addresses Provides port based and ID tagged VLAN support (IEEE 802.1Q), up to 4K VLANs Supports IP Multicast with IGMP snooping, up to 4K IP Multicast groups Supports spanning tree with CPU, on per port basis 8 port trunking groups with up to 8 ports per group Failover Backplane Features · Link Heart Beat Rate Control (both ingress and egress) · Bandwidth rationing, Bandwidth on demand, SLA (Service Level Agreement) · Smooth out traffic to uplink ports · Ingress Rate Control C P U EEPROM Ordering Information ZL50409GDC ZL50409GDC 208 Pin LBGA -40°C to +85°C · · · · · - Back pressure - Flow Control - WRED (Weighted Random Early Discard) · Egress Rate Control - per queue shaper (Port 9) - WRED · Down to 16kbps Rate Control granularity Packet Filtering and Port Security · Static address filtering for source and/or destination MAC · Static MAC address not subject to aging · Secure mode freezes MAC address learning (each port may independently use this mode) Full Duplex Ethernet IEEE 802.3x Flow Control Backpressure flow control for Half Duplex ports Supports Ethernet multicasting and broadcasting and flooding control Supports per-system option to enable flow control 8/16-bit or Serial ZL50409 ZL50409 MII Managed 9-Port 10/100M 10/100M Ethernet Switch MII 10/100 PHY I2C RMII / MII / GPSI Quad 10/100 PHY Quad 10/100 PHY Figure 1 - System Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved. ZL50409 ZL50409 · · · · · · · · · Data Sheet for best effort frames even on QoS enabled ports QoS Support · Supports IEEE 802.1p/Q Quality of Service with 2 transmission priority queues (4 for MII port), with strict priority and WFQ service disciplines · Provides 2 levels of dropping precedence with WRED mechanism · User controls the WRED thresholds. · Buffer management: per class and per port buffer reservations · Port-based priority: VLAN priority in a tagged frame can be overwritten by the priority of Port VLAN ID Classification based on: · Port based priority · VLAN Priority field in VLAN tagged frame · DS/TOS field in IP packet · UDP/TCP logical ports: 8 hard-wired and 8 programmable ports, including one programmable range The precedence of the above classifications is programmable MIB Statistics counters for all ports Hardware auto-negotiation through serial management interface (MDIO) for Ethernet ports I2C EEPROM for configuration in unmanaged mode Built-in reset logic triggered by system malfunction Built-In Self Test for internal SRAM IEEE-1149 IEEE-1149.1 (JTAG) test port Description The ZL50409 ZL50409 is a low density, low cost, high performance, non-blocking Ethernet switch chip. A single chip provides 9 ports at 10/100 Mbps and a CPU interface for managed and unmanaged switch applications. The chip supports up to 4K MAC addresses and up to 4K port-based Virtual LANs (VLANs). With strict priority and/or WFQ transmission scheduling and WRED dropping schemes, the ZL50409 ZL50409 provides powerful QoS functions for various multimedia and mission-critical applications. The chip provides 2 transmission priorities (4 priorities for MII port) and 2 levels of dropping precedence. Each packet is assigned a transmission priority and dropping precedence based on the VLAN priority field in a VLAN tagged frame, or the DS/TOS field, or the UDP/TCP logical port fields in IP packets. The ZL50409 ZL50409 recognizes a total of 16 UDP/TCP logical ports, 8 hard-wired and 8 programmable (including one programmable range). The ZL50409 ZL50409 supports 8 groups of port trunking/load sharing. Each group can contain up to 8 ports. Port trunking/load sharing can be used to group ports between interlinked switches to increase the effective network bandwidth. In half-duplex mode, all ports support backpressure flow control, to minimize the risk of losing data during long activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The ZL50409 ZL50409 also supports a per-system option to enable flow control for best effort frames, even on QoS-enabled ports. Statistical information for SNMP and the Remote Monitoring Management Information Base (RMON MIB) are collected independently for all ports. Access to these statistical counters/registers is provided via the CPU interface. SNMP Management frames can be received and transmitted via the CPU interface, creating a complete network management solution. The ZL50409 ZL50409 is fabricated using 0.18 micron technology. The ZL50409 ZL50409 is packaged in a 208-pin Ball Grid Array package. 2 Zarlink Semiconductor Inc. ZL50409 ZL50409 Data Sheet Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 1.0 BGA and Ball Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 1.1 BGA Views (Top-View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2 Power and Ground Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 Ball Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4 Signal Mapping and Internal Pull Up/Down Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.5 Bootstrap Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.0 Block Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.1 Internal Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2 MII MAC Module (MMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3 RMII MAC Module (RMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4 Management Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.5 Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.6 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.7 Other Internal Memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.8 Management and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.9 Register Configuration, Frame Transmission, and Frame Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.9.1 Register Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.9.2 Rx/Tx of Standard Ethernet Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.9.3 Control Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.10 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.10.1 Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.10.2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.10.3 Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.10.4 Acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.10.5 Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.10.6 Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.11 Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.11.1 Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.11.2 Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.12 Timeout Reset Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.13 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.0 ZL50409 ZL50409 Data Forwarding Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.1 Unicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2 Multicast Data Frame Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3 Frame Forwarding To and From CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.0 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 4.1 Search Engine Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.2 Basic Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3 Search, Learning, and Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3.1 MAC Search. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3.2 Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3.3 Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.4 MAC Address Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.5 Protocol Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.6 Logical Port Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.7 Quality of Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.8 Priority Classification Rule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.9 Port and Tag Based VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.9.1 Port-Based VLAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.9.2 Tag-Based VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3 Zarlink Semiconductor Inc. ZL50409 ZL50409 Data Sheet Table of Contents 5.0 Frame Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 5.1 Data Forwarding Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.2 Frame Engine Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.2.1 FCB Manager. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.2.2 Rx Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.2.3 RxDMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.2.4 TxQ Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.2.5 Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.2.6 TxDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.0 Quality of Service and Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 6.1 Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.2 Two QoS Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.2.1 Strict Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.2.2 Weighted Fair Queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.3 WRED Drop Threshold Management Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.4 Shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.5 Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.6 Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.6.1 Dropping When Buffers Are Scarce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.7 ZL50409 ZL50409 Flow Control Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.7.1 Unicast Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.7.2 Multicast Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.8 Mapping to IETF Diffserv Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.9 Failover Backplane Feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.0 Port Trunking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 7.1 Features and Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.2 Unicast Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.3 Multicast Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.0 Port Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 8.1 Mirroring Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.2 Using port mirroring for loop back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.0 GPSI (7WS) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 9.1 GPSI connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.0 Clock Speed Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 10.1 System Clock (SCLK) speed requirement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.2 RMAC Reference Clock (M_CLK) speed requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.3 MMAC Reference Clock (REF_CLK) speed requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.0 Hardware Statistics Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 11.1 Hardware Statistics Counters List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11.2 IEEE 802.3 HUB Management (RFC 1516) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.2.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.2.1.1 ReadableOctet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 11.2.1.2 ReadableFrame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 11.2.1.3 FCSERRORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 11.2.1.4 AlignmentErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 11.2.1.5 FrameTooLongs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 11.2.1.6 ShortEvents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 11.2.1.7 Runts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 11.2.1.8 Collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 11.2.1.9 LateEvents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 11.2.1.10 VeryLongEvents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 4 Zarlink Semiconductor Inc. ZL50409 ZL50409 Data Sheet Table of Contents 11.2.1.11 DataRateMisatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 11.2.1.12 AutoPartitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 11.2.1.13 TotalErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 11.3 IEEE ­ 802.1 Bridge Management (RFC 1286) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.3.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.3.1.1 InFrames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 11.3.1.2 OutFrames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 11.3.1.3 InDiscards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 11.3.1.4 DelayExceededDiscards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 11.3.1.5 MtuExceededDiscards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 11.4 RMON ­ Ethernet Statistic Group (RFC 1757) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.4.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.4.1.1 Drop Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 11.4.1.2 Octets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 11.4.1.3 BroadcastPkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 11.4.1.4 MulticastPkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 11.4.1.5 CRCAlignErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 11.4.1.6 UndersizePkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 11.4.1.7 OversizePkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 11.4.1.8 Fragments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 11.4.1.9 Jabbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 11.4.1.10 Collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 11.4.1.11 Packet Count for Different Size Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 11.5 Miscellaneous Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.0 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 12.1 ZL50409 ZL50409 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.2 Directly Accessed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.2.1 INDEX_REG0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.2.2 INDEX_REG1 (only needed for 8-bit mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.2.3 DATA_FRAME_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.2.4 CONTROL_FRAME_REG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.2.5 COMMAND&STATUS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12.2.6 Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12.2.7 Control Command Frame Buffer1 Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12.2.8 Control Command Frame Buffer2 Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12.3 Indirectly Accessed Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12.3.1 (Group 0 Address) MAC Ports Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12.3.1.1 ECR1Pn: Port N Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 12.3.1.2 ECR2Pn: Port N Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 12.3.1.3 ECR3Pn: Port N Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 12.3.1.4 ECR4Pn: Port N Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 12.3.1.5 BUF_LIMIT ­ Frame Buffer Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 12.3.1.6 FCC ­ Flow Control Grant Period. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 12.3.2 (Group 1 Address) VLAN Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12.3.2.1 AVTCL ­ VLAN Type Code Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 12.3.2.2 AVTCH ­ VLAN Type Code Register High. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 12.3.2.3 PVMAP00 PVMAP00_0 ­ Port 0 Configuration Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 12.3.2.4 PVMAP00 PVMAP00_1 ­ Port 0 Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 12.3.2.5 PVMAP00 PVMAP00_3 ­ Port 0 Configuration Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 12.3.2.6 PVMAPnn_0,1,3 ­ Ports 1~9 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 12.3.2.7 PVMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 12.3.3 (Group 2 Address) Port Trunking Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5 Zarlink Semiconductor Inc. ZL50409 ZL50409 Data Sheet Table of Contents 12.3.3.1 TRUNKn­ Trunk Group 0~7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 12.3.3.2 TRUNKn_HASH10 HASH10 ­ Trunk group 0~7 hash result 1/0 destination port number . . . . . . . . . .70 12.3.3.3 TRUNKn_HASH32 HASH32 ­ Trunk group 0~7 hash result 3/2 destination port number . . . . . . . . . .71 12.3.3.4 TRUNKn_HASH54 HASH54 ­ Trunk group 0~7 hash result 5/4 destination port number . . . . . . . . . .71 12.3.3.5 TRUNKn_HASH76 HASH76 ­ Trunk group 0~7 hash result 7/6 destination port number . . . . . . . . . .71 12.3.4 Multicast Hash Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 12.3.4.1 MULTICAST_HASHn-0 ­ Multicast hash result 0~7 mask byte 0 . . . . . . . . . . . . . . . . . . . . .72 12.3.4.2 MULTICAST_HASHn-1 ­ Multicast hash result 0~7 mask byte 1 . . . . . . . . . . . . . . . . . . . . .72 12.3.5 (Group 3 Address) CPU Port Configuration Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.3.5.1 MAC0 ­ CPU Mac address byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 12.3.5.2 MAC1 ­ CPU Mac address byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 12.3.5.3 MAC2 ­ CPU Mac address byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 12.3.5.4 MAC3 ­ CPU Mac address byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 12.3.5.5 MAC4 ­ CPU Mac address byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 12.3.5.6 MAC5 ­ CPU Mac address byte 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 12.3.5.7 INT_MASK0 ­ Interrupt Mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 12.3.5.8 INTP_MASK0 ­ Interrupt Mask for MAC Port 0,1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 12.3.5.9 INTP_MASKn ­ Interrupt Mask for MAC Ports 2~9 Registers . . . . . . . . . . . . . . . . . . . . . . . .74 12.3.5.10 RQS ­ Receive Queue Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 12.3.5.11 RQSS ­ Receive Queue Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 12.3.5.12 MAC01 MAC01 ­ Increment MAC port 0,1 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 12.3.5.13 MAC23 MAC23 ­ Increment MAC port 2,3 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 12.3.5.14 MAC45 MAC45 ­ Increment MAC port 4,5 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 12.3.5.15 MAC67 MAC67 ­ Increment MAC port 6,7 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 12.3.5.16 MAC9 ­Increment MAC port 9 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 12.3.6 CPUQINS0 - CPUQINS6 - CPU Queue Insertion Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 12.3.7 CPUQINSRPT ­ CPU Queue Insertion Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.3.8 CPUGRNHDL0- CPUGRNHDL1 ­ CPU Allocated Granule Pointer . . . . . . . . . . . . . . . . . . . . . . . 77 12.3.9 CPURLSINFO0- CPURLSINFO4 ­ Receive Queue Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.3.10 CPUGRNCTR ­ CPU Granule Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12.3.11 (Group 4 Address) Search Engine Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12.3.11.1 AGETIME_LOW ­ MAC address aging time Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 12.3.11.2 AGETIME_HIGH ­MAC address aging time High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 12.3.11.3 SE_OPMODE ­ Search Engine Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 12.3.12 (Group 5 Address) Buffer Control/QOS Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.3.12.1 QOSC ­ QOS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 12.3.12.2 UCC ­ Unicast Congestion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 12.3.12.3 MCC ­ Multicast Congestion Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 12.3.12.4 MCCTH ­ Multicast Threshold Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 12.3.12.5 RDRC0 ­ WRED Rate Control 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 12.3.12.6 RDRC1 ­ WRED Rate Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 12.3.12.7 RDRC2 ­ WRED Rate Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 12.3.12.8 SFCB ­ Share FCB Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 12.3.12.9 C1RS ­ Class 1 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 12.3.12.10 C2RS ­ Class 2 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 12.3.12.11 C3RS ­ Class 3 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 12.3.12.12 AVPML ­ VLAN Tag Priority Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 12.3.12.13 AVPMM ­ VLAN Priority Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 12.3.12.14 AVPMH ­ VLAN Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 12.3.12.15 AVDM ­ VLAN Discard Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 12.3.12.16 TOSPML ­ TOS Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 12.3.12.17 TOSPMM ­ TOS Priority Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 6 Zarlink Semiconductor Inc. ZL50409 ZL50409 Data Sheet Table of Contents 12.3.12.18 TOSPMH ­ TOS Priority Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 12.3.12.19 TOSDML ­ TOS Discard Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 12.3.12.20 USER_PROTOCOL_[7:0] ­ User Define Protocol 0~7 . . . . . . . . . . . . . . . . . . . . . . . . . . .85 12.3.12.21 USER_PROTOCOL_FORCE_DISCARD[7:0] ­ User Define Protocol 0~7 Force Discard 86 12.3.13 User Defined Logical Ports and Well Known Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12.3.13.1 WELL_KNOWN_PORT[1:0]_PRIORITY- Well Known Logic Port 1 and 0 Priority . . . . . . .87 12.3.13.2 WELL_KNOWN_PORT[3:2]_PRIORITY- Well Known Logic Port 3 and 2 Priority . . . . . . .87 12.3.13.3 WELL_KNOWN_PORT[5:4]_PRIORITY- Well Known Logic Port 5 and 4 Priority . . . . . . .87 12.3.13.4 WELL_KNOWN_PORT[7:6]_PRIORITY- Well Known Logic Port 7 and 6 Priority . . . . . . .87 12.3.13.5 WELL_KNOWN_PORT_ENABLE[7:0] ­ Well Known Logic Port 0 to 7 Enables. . . . . . . . .88 12.3.13.6 WELL_KNOWN_PORT_FORCE_DISCARD[7:0] ­ Well Known Logic Port 0~7 Force Discard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 12.3.13.7 USER_PORT[7:0]_[LOW/HIGH] ­ User Define Logical Port 0~7 . . . . . . . . . . . . . . . . . . . .89 12.3.13.8 USER_PORT_[1:0]_PRIORITY - User Define Logic Port 1 and 0 Priority . . . . . . . . . . . . . .89 12.3.13.9 USER_PORT_[3:2]_PRIORITY - User Define Logic Port 3 and 2 Priority . . . . . . . . . . . . . .89 12.3.13.10 USER_PORT_[5:4]_PRIORITY - User Define Logic Port 5 and 4 Priority . . . . . . . . . . . . .89 12.3.13.11 USER_PORT_[7:6]_PRIORITY - User Define Logic Port 7 and 6 Priority . . . . . . . . . . . . .90 12.3.13.12 USER_PORT_ENABLE[7:0] ­ User Define Logic Port 0 to 7 Enables . . . . . . . . . . . . . . .90 12.3.13.13 USER_PORT_FORCE_DISCARD[7:0] ­ User Define Logic Port 0~7 Force Discard . . . .90 12.3.13.14 RLOWL ­ User Define Range Low Bit 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 12.3.13.15 RLOWH ­ User Define Range Low Bit 15:8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 12.3.13.16 RHIGHL ­ User Define Range High Bit 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 12.3.13.17 RHIGHH ­ User Define Range High Bit 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 12.3.13.18 RPRIORITY ­ User Define Range Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 12.3.14 (Group 6 Address) MISC Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 12.3.14.1 MII_OP0 ­ MII Register Option 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 12.3.14.2 MII_OP1 ­ MII Register Option 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 12.3.14.3 FEN ­ Feature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 12.3.14.4 MIIC0 ­ MII Command Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 12.3.14.5 MIIC1 ­ MII Command Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 12.3.14.6 MIIC2 ­ MII Command Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 12.3.14.7 MIIC3 ­ MII Command Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 12.3.14.8 MIID0 ­ MII Data Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 12.3.14.9 MIID1 ­ MII Data Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 12.3.14.10 USD ­ One Micro Second Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 12.3.14.11 DEVICE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 12.3.14.12 CHECKSUM - EEPROM Checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 12.3.14.13 LHBTimer ­ Link Heart Beat Timeout Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 12.3.14.14 LHBReg0, LHBReg1 - Link Heart Beat OpCode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 12.3.14.15 fMACCReg0, fMACCReg1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 12.3.14.16 FCB Base Address Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 12.3.14.17 FCB Base Address Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 12.3.14.18 FCB Base Address Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 12.3.15 (Group 7 Address) Port Mirroring Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 12.3.15.1 MIRROR CONTROL ­ Port Mirror Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 12.3.15.2 MIRROR_DEST_MAC[5:0] ­ Mirror Destination Mac Address 0~5 . . . . . . . . . . . . . . . . . . .97 12.3.15.3 MIRROR_SRC _MAC[5:0] ­ Mirror Destination Mac Address 0~5 . . . . . . . . . . . . . . . . . . .97 12.3.15.4 RMAC_MIRROR0 ­ RMAC Mirror 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 12.3.15.5 RMAC_MIRROR1 ­ RMAC Mirror 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 12.3.16 (Group 8 Address) Per Port QOS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 12.3.16.1 FCRn ­ Port 0~9 Flooding Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 12.3.16.2 BMRCn - Port 0~9 Broadcast/Multicast Rate Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 7 Zarlink Semiconductor Inc. ZL50409 ZL50409 Data Sheet Table of Contents 12.3.16.3 PR100 PR100_n ­ Port 0~7 Reservation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 12.3.16.4 PR100 PR100_CPU ­ Port CPU Reservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 12.3.16.5 PRM ­ Port MMAC Reservation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 12.3.16.6 PTH100 PTH100_n ­ Port 0~7 Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 12.3.16.7 PTH100 PTH100_CPU ­ Port CPU Threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 12.3.16.8 PTHM ­ Port MMAC Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 12.3.16.9 QOSC00 QOSC00, QOSC01 QOSC01 - Classes Byte Limit port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 12.3.16.10 QOSC02 QOSC02, QOSC15 QOSC15 - Classes Byte Limit port 1-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 12.3.16.11 QOSC16 QOSC16 - QOSC21 QOSC21 - Classes Byte Limit CPU port. . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 12.3.16.12 QOSC22 QOSC22 - QOSC27 QOSC27 - Classes Byte Limit MMAC port . . . . . . . . . . . . . . . . . . . . . . . . . . .100 12.3.16.13 QOSC28 QOSC28 - QOSC31 QOSC31 - Classes WFQ Credit For MMAC. . . . . . . . . . . . . . . . . . . . . . . . . .101 12.3.16.14 QOSC36 QOSC36 - QOSC39 QOSC39 - Shaper Control Port MMAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 12.3.17 (Group E Address) System Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 12.3.17.1 DTSRL ­ Test Output Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 12.3.17.2 DTSRM ­ Test Output Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 12.3.17.3 TESTOUT0, TESTOUT1 ­ Testmux Output [7:0], [15:8] . . . . . . . . . . . . . . . . . . . . . . . . . .102 12.3.17.4 MASK0-MASK4 ­ Timeout Reset Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 12.3.17.5 BOOTSTRAP0 ­ BOOTSTRAP2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 12.3.17.6 PRTFSMST0 ­ PRTFSMST9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 12.3.17.7 PRTQOSST0-PRTQOSST7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 12.3.17.8 PRTQOSST8A, PRTQOSST8B (CPU port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 12.3.17.9 PRTQOSST9A, PRTQOSST9B (MMAC port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 12.3.17.10 CLASSQOSST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 12.3.17.11 PRTINTCTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 12.3.17.12 QMCTRL[9:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 12.3.17.13 QCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 12.3.17.14 BMBISTR0, BMBISTR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 12.3.17.15 BMControl. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 12.3.17.16 BUFF_RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 12.3.17.17 FCB_HEAD_PTR0, FCB_HEAD_PTR1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 12.3.17.18 FCB_TAIL_PTR0, FCB_TAIL_PTR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 12.3.17.19 FCB_NUM0, FCB_NUM1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 12.3.17.20 BM_RLSFF_CTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 12.3.17.21 BM_RSLFF_INFO[5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 12.3.18 (Group F Address) CPU Access Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 12.3.18.1 GCR - Global Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 12.3.18.2 DCR - Device Status and Signature Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 12.3.18.3 DCR1 - Device Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 12.3.18.4 DPST ­ Device Port Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 12.3.18.5 DTST ­ Data read back register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 12.3.18.6 DA ­ DA Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 13.0 Characteristics and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 13.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 13.2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 13.3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 13.4 AC Characteristics and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 13.4.1 Typical Reset & Bootstrap Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 13.4.2 Typical CPU Timing Diagram for a CPU Write Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 13.4.3 Typical CPU Timing Diagram for a CPU Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 13.4.4 Reduced Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 13.4.5 Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 13.4.6 General Purpose Serial Interface (7-wire) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 8 Zarlink Semiconductor Inc. ZL50409 ZL50409 Data Sheet Table of Contents 13.4.7 MDIO Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.8 I²C Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.9 Serial Interface Setup Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.10 JTAG (IEEE 1149.1-2001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Zarlink Semiconductor Inc. 120 121 122 123 ZL50409 ZL50409 1.0 BGA and Ball Signal Descriptions 1.1 Data Sheet BGA Views (Top-View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A SCLK P_CS # P_RD # P_WE # P_DA TA1 P_DA TA3 P_DA TA5 P_DA TA7 P_DA TA9 P_DA TA11 P_DA TA13 P_DA TA15 REF_ CLK RSVD M9_M TXCK M9_T XEN A B P_INT # P_A0 P_A1 P_A2 P_DA TA0 P_DA TA2 P_DA TA4 P_DA TA6 P_DA TA8 P_DA TA10 P_DA TA12 P_DA TA14 TCK TMS RSVD M9_R XCK B C RESE TOUT # TSTO UT1 TSTO UT3 TSTO UT5 TSTO UT6 TSTO UT7 TSTO UT9 TSTO UT11 TSTO UT12 TSTO UT14 TSTO UT15 TRST # TDI RSVD M9_C RS M9_C OL C D RESI N# TSTO UT0 TSTO UT2 TSTO UT4 3.3V SCAN _EN TSTO UT8 TSTO UT10 1.8V TSTO UT13 TDO 3.3V RSVD RSVD M9_R XDV RSVD D E M2_C OL M0_C OL M1_C OL 3.3V 3.3V RSVD RSVD RSVD E F M_M DC M_M DIO M0_R XD2 M0_R XD3 M9_R XD2 M9_R XD3 RSVD RSVD F G M0_R XD0 M0_R XD1 M0_R XCK M0_T XD3 GND GND GND GND M9_R XD0 M9_R XD1 M9_T XD2 M9_T XD3 G H M0_C RS M0_T XEN M0_T XD2 1.8V GND GND GND GND 1.8V M7_C OL M9_T XD0 M9_T XD1 H J M0_T XD0 M0_T XD1 M0_T XCK M1_R XD3 GND GND GND GND M7_T XD3 M7_T XCK M7_T XD1 M7_T XD0 J K M1_R XD0 M1_R XD1 M1_R XD2 M1_R XCK GND GND GND GND M7_T XD2 M7_R XD2 M7_T XEN M7_C RS K L M1_C RS M1_T XEN M1_T XD2 M1_T XD3 M7_R XD3 M7_R XCK M7_R XD1 M7_R XD0 L M M1_T XD0 M1_T XD1 M1_T XCK 3.3V 3.3V M6_C OL M5_C OL M4_C OL M N M2_R XD3 M2_T XCK M2_T XD3 M3_R XD3 3.3V M3_T XD3 1.8V M4_R XD3 M4_T XCK M4_T XD3 M5_R XD3 M5_T XCK M5_T XD3 M6_R XD3 M6_T XCK M6_T XD3 N P M2_R XD2 M2_R XCK M2_T XD2 M3_R XD2 M3_R XCK M3_T XD2 M3_C OL M4_R XD2 M4_R XCK M4_T XD2 M5_R XD2 M5_R XCK M5_T XD2 M6_R XD2 M6_R XCK M6_T XD2 P R M2_R XD1 M2_T XEN M2_T XD1 M3_R XD1 M3_T XEN M3_T XD1 M_CL K M4_R XD1 M4_T XEN M4_T XD1 M5_R XD1 M5_T XEN M5_T XD1 M6_R XD1 M6_T XEN M6_T XD1 R T M2_R XD0 M2_C RS M2_T XD0 M3_R XD0 M3_C RS M3_T XD0 M3_T XCK M4_R XD0 M4_C RS M4_T XD0 M5_R XD0 M5_C RS M5_T XD0 M6_R XD0 M6_C RS M6_T XD0 T 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1.2 Power and Ground Distribution G7-10 G7-10, H7-10 H7-10, J7-10 J7-10, K7-10 K7-10 GND VSS Ground D5, D12, E4, E13, M4, M13, N5 3.3V VCC I/O Power D9, H4, H13, N7 1.8V VDD Core Power 10 Zarlink Semiconductor Inc. ZL50409 ZL50409 1.3 Data Sheet Ball Signal Descriptions All pins are CMOS type; all Input Pins are 5 Volt tolerance; and all Output Pins are 3.3 CMOS drive. Notes #= Active low signal Input = Input signal Input-ST = Input signal with Schmitt-Trigger Output = Output signal (Tri-State driver) I/O-TS = Input & Output signal with Tri-State driver pull up = Weak internal pull up (refer to Section 1.4 on page 16 as some internal pull ups are not enabled in certain configurations) pull down = Weak internal pull down (refer to Section 1.4 on page 16 as some internal pull downs are not enabled in certain configurations) Ball Signal Description Table Ball No(s) Symbol I/O Description CPU BUS Interface in 16-Bit Managed Mode A12, B12, A11, B11, A10, B10, A9, B9, A8, B8, A7, B7, A6, B6, A5, B5 P_DATA[15:0] I/O-TS w/ pull up Processor Bus Data Bit [15:0]. P_DATA[7:0] is used in 8-bit mode. B4, B3, B2 P_A[2:0] Input w/ pull up Processor Bus Address Bit [2:0] A4 P_WE# Input w/ pull up CPU Bus-Write Enable A3 P_RD# Input CPU Bus-Read Enable A2 P_CS# Input w/ pull up Chip Select B1 P_INT# Output CPU Interrupt Fast Ethernet Access Ports [7:0] MII L13, K14, L15, L16, N14, P14, R14, T14, N11, P11, R11, T11, N8, P8, R8, T8, N4, P4, R4, T4, N1, P1, R1, T1, J4, K3, K2, K1, F4, F3, G2, G1 M[7:0]_RXD[3:0] Input w/ pull up Ports [7:0] ­ Receive Data Bit [3:0] K16, T15, T12, T9, T5, T2, L1, H1 M[7:0]_CRS_DV Input w/ pull up Ports [7:0] ­ Carrier Sense and Receive Data Valid K15, R15, R12, R9, R5, R2, L2, H2 M[7:0]_TXEN Ports [7:0] ­ Transmit Enable Output, slew These pins also serve as bootstrap pins. 11 Zarlink Semiconductor Inc. ZL50409 ZL50409 Data Sheet Ball Signal Description Table (continued) Ball No(s) Symbol I/O Description J13, K13, J15, J16, N16, P16, R16, T16, N13, P13, R13, T13, N10, P10, R10, T10, N6, P6, R6, T6, N3, P3, R3, T3, L4, L3, M2, M1, G4, H3, J2, J1 M[7:0]_TXD[3:0] Output, slew Ports [7:0] ­ Transmit Data Bit [3:0] H14, M14, M15, M16, P7, E1, E3, E2 M[7:0]_COL Input w/ pull down Ports[7:0] ­ Collision J14, N15, N12, N9, T7, N2, M3, J3 M[7:0]_TXCLK Input or Output w/ pull up Ports[7:0] ­ Transmit Clock This pin in an output if ECR4Pn[0]='1' L14, P15, P12, P9, P5, P2, K4, G3 M[7:0]_RXCLK Input or Output w/ pull up Ports[7:0] ­ Receive Clock This pin in an output if ECR4Pn[1]='1' MII Ethernet Access Port G16, G15, H16, H15 M9_TXD[3:0] Output Transmit Data Bit [3:0] D15 M9_RXDV Input w/ pull up Receive Data Valid C15 M9_CRS Input w/ pull down Carrier Sense C16 M9_COL Input w/ pull down Collision Detected B16 M9_RXCLK Input or Output w/ pull up Receive Clock This pin in an output if ECR4P9[1]='1' F14, F13, G14, G13 M9_RXD[3:0] Input w/ pull up Receive Data Bit [3:0] A16 M9_TXEN Output w/ pull up Transmit Data Enable A15 M9_ MTXCLK Input w/ pull up Transmit Clock A13 REF_CLK Input w/ pull up MMAC Reference Clock 12 Zarlink Semiconductor Inc. ZL50409 ZL50409 Data Sheet Ball Signal Description Table (continued) Ball No(s) Symbol I/O Description Test Interface C11, C10, D10, C9, C8, D8, C7, D7, C6, C5, C4, D4, C3, D3, C2, D2 TSTOUT[15:0] Output [15:4] Reserved [3] EEPROM checksum is good [2] Initialization Completed [1] Memory Self Test in progress [0] Initialization started These pins also serve as bootstrap pins. Test Facility C13 TDI Input w/pull up JTAG - Test Data In C12 TRST# Input w/pull up JTAG - Test Reset B13 TCK Input w/pull up JTAG - Test Clock B14 TMS Input w/pull up JTAG - Test Mode State D11 TDO Output JTAG - Test Data Out D6 SCAN_EN Input Scan Enable. Manufacturing test option. Must be externally pulled-down Should be externally pulled-down for proper operation. System Clock, Power, and Ground Pins A1 SCLK Input System Clock. Based on system requirement, SCLK needs to operate at difference frequency. SCLK requires 40/60% duty cycle clock D9, H4, H13, N7 VDD Power +1.8 Volt DC Supply D5, D12, E4, E13, M4, M13, N5 VCC Power +3.3 Volt DC Supply Power Ground Ground G7-10 G7-10, H7-10 H7-10, J7-10 J7-10, VSS K7-10 K7-10 Misc D1 RESIN# Input Reset Input C1 RESETOUT# Output Reset PHY F1 M_MDC Output MII Management Data Clock F2 M_MDIO I/O-TS w/ pull up MII Management Data I/O 13 Zarlink Semiconductor Inc. ZL50409 ZL50409 Data Sheet Ball Signal Description Table (continued) Ball No(s) Symbol I/O Description R7 M_CLK Input RMAC Reference Clock F15, F16, E15, E16, E14, D13, D14, C14, A14, B15, D16 RSVD NC Reserved Pins. Leave unconnected. Bootstrap Pins (1= pull up 0= pull down)1 D2 TSTOUT[0] Input (Reset Only) Enable Debounce of STROBE signal Pullup ­ Enabled Pulldown - Disabled C3, D3, C2 TSTOUT[3:1] Input (Reset Only) Management interface operation mode: 000 ­ 16-bit parallel interface 001 ­ 8-bit parallel interface 010 ­ Serial with MII as Ethernet frame transfer interface. 011 ­ Serial only. CPU can transmit/receive frames with the serial interface. 111 ­ Unmanaged Serial. No CPU packet can be transmit or received with the serial interface. EEPROM can be used to configure the device at bootup. A one (1) indicates pullup. A zero (0) indicates pulldown.TSTOUT[1] is the Least Significant Bit (LSB). C5, C4, D4 TSTOUT[6:4] Input (Reset Only) Device ID. Default address of the device for serial interface. Up to 8 device can be sharing the serial management bus with different device ID. A one (1) indicates pullup. A zero (0) indicates pulldown. TSTOUT[4] is the Least Significant Bit (LSB). C6 TSTOUT7 Input (Reset Only) EEPROM not installed. Pullup: Not installed Pulldown: Installed D7 TSTOUT8 Input (Reset Only) Manufacturing Option. Must be pulled-up. Must be externally pulled-up C7 TSTOUT9 Input (Reset Only) Module Detect Pullup: Enable. In this mode, the device will detect the existence of a PHY (for hot swap purpose). Pulldown: Disable 14 Zarlink Semiconductor Inc. ZL50409 ZL50409 Data Sheet Ball Signal Description Table (continued) Ball No(s) D8 Symbol TSTOUT10 TSTOUT10 I/O Description Input (Reset Only) Reserved. Must be pulled-down. Must be externally pulled-down C8 TSTOUT11 TSTOUT11 Input (Reset Only) Power Saving Pullup: Enable Mac power saving mode Pulldown: Disable Mac power saving mode C9 TSTOUT12 TSTOUT12 Input (Reset Only) Timeout Reset Enable Pullup: Enable Pulldown: Disable C11, C10, D10 TSTOUT[15:13] Input (Reset Only) Manufacturing Options. Must be pulled-up. Must be externally pulled-up K15, R15, R12, R9, R5, R2, L2, H2 M[7:0]_TXEN Input (Reset Only) User Defined Bootstrap: Usually used in conjuction with Module Detect to determine what interface to use for the inserted module. Can be read from BOOTSTRAP2 register 1. External pull-up/down resistors are required on all bootstrap pins for proper operation. Recommend 10K for pull-ups and 1K for pull-downs. 15 Zarlink Semiconductor Inc. ZL50409 ZL50409 1.4 Data Sheet Signal Mapping and Internal Pull Up/Down Configuration The ZL50409 ZL50409 Fast Ethernet ports (0-7) support 3 interface options: RMII, MII & GPSI. The table below summarizes the interface signals required for each interface and how they relate back to the Pin Symbol name shown in Table , "Ball Signal Description Table" on page 11. It also specifies whether the internal pull up/down resistor is present for each pin in the specific operating mode. Notes: I ­ Input O ­ Output U ­ Pullup D - Pulldown Fast Ethernet Ports Pin Symbol No Module (Bootstrap TSTOUT9='1') RMII Mode MII Mode GPSI Mode (ECR4Pn[4:3]='11') (ECR4Pn[4:3]='01') (ECR4Pn[4:3]='00') M[7:0]_RXD0 (U) M[7:0]_RXD0 (I) M[7:0]_RXD0 (I) M[7:0]_RXD (I) M[7:0]_RXD1 (U) M[7:0]_RXD1 (I) M[7:0]_RXD1 (I) NC (U) M[7:0]_RXD2 (U) NC (U) M[7:0]_RXD2 (I) NC (U) M[7:0]_RXD3 (U) NC (U) M[7:0]_RXD3 (I) NC (U) M[7:0]_TXEN (O) M[7:0]_TXEN (O) M[7:0]_TXEN (O) M[7:0]_TXEN (O) M[7:0]_CRS_DV (U) M[7:0]_CRS_DV (I) M[7:0]_DV (I) M[7:0]_CRS (I) M[7:0]_TXD0 (O) M[7:0]_TXD0 (O) M[7:0]_TXD0 (O) M[7:0]_TXD (O) M[7:0]_TXD1 (O) M[7:0]_TXD1 (O) M[7:0]_TXD1 (O) NC (O) M[7:0]_TXD2 (O) NC (O) M[7:0]_TXD2 (O) NC (O) M[7:0]_TXD3 (O) NC (O) M[7:0]_TXD3 (O) NC (O) M[7:0]_COL (D) NC (D) M[7:0]_COL (I) M[7:0]_COL (I) M[7:0]_TXCLK (U) NC (U) M[7:0]_TXCLK (IO) M[7:0]_TXCLK (IO) M[7:0]_RXCLK (U) NC (U) M[7:0]_RXCLK (IO) M[7:0]_RXCLK (IO) Table 1 - Signal Mapping In Different Operation Mode 16 Zarlink Semiconductor Inc. ZL50409 ZL50409 Data Sheet The ZL50409 ZL50409 Fast Ethernet port (port 9) supports 1 interface options: MII. The table below summarizes the interface signals required for the interface, and how they relate back to the Pin Symbol name shown in Table , "Ball Signal Description Table" on page 11. Fast Ethernet Port Pin Symbol No Module MII Mode (ECR4P9[4:3]='00') (Bootstrap TSTOUT9='1') M9_RXD0 (U) M9_RXD0 (I) M9_RXD1 (U) M9_RXD1 (I) M9_RXD2 (U) M9_RXD2 (I) M9_RXD3 (U) M9_RXD3 (I) M9_RXDV (U) M9_RXDV (I) M9_CRS (D) M9_CRS (I) M9_COL (D) M9_COL (I) M9_RXCLK (U) M9_RXCLK (IO) M9_TXD0 (O) M9_TXD0 (O) M9_TXD1 (O) M9_TXD1 (O) M9_TXD2 (O) M9_TXD2 (O) M9_TXD3 (O) M9_TXD3 (O) M9_TXEN (U) M9_TXEN (O) REF_CLK (U) REF_CLK (I) M9_MTXCLK (U) M9_MTXCLK (I) Table 2 - Signal Mapping In Different Operation Mode 17 Zarlink Semiconductor Inc. ZL50409 ZL50409 Data Sheet The ZL50409 ZL50409 CPU access support 5 interface options: 8 or 16-bit parallel, serial+MII (port 8), serial only, and unmanaged serial (with optional EEPROM). The table below summarizes the interface signals required for each interface, and how they relate back to the Pin Symbol name shown in Table , "Ball Signal Description Table" on page 11. Management Interface Pin Symbol 16-bit CPU 8-bit CPU Serial with MII Serial Only (TSTOUT[3:1]='000') (TSTOUT[3:1]='001') (TSTOUT[3:1]='010') (TSTOUT[3:1]='011' or `111') P_A[0] P_A[0] (I) P_A[0] (I) NC (U) SDA (IOU) (111 only) P_A[1] P_A[1] (I) P_A[1] (I) NC (U) SCL (OU) (111 only) P_A[2] P_A[2] (I) P_A[2] (I) NC (U) NC (U) P_WE# P_WE# (I) P_WE# (I) STROBE (IU) STROBE (IU) P_RD# P_RD# (I) P_RD# (I) DATAOUT (O) DATAOUT (O) P_CS# P_CS# (I) P_CS# (I) DATAIN (IU) DATAIN (IU) P_INT# P_INT# (O) P_INT# (O) P_INT# (O) P_INT# (O) P_DATA0 P_DATA0 (IOU) P_DATA0 (IOU) CPU_MII_TXD0 (O) NC (U) P_DATA1 P_DATA1 (IOU) P_DATA1 (IOU) CPU_MII_TXD1 (O) NC (U) P_DATA2 P_DATA2 (IOU) P_DATA2 (IOU) CPU_MII_TXD2 (O) NC (U) P_DATA3 P_DATA3 (IOU) P_DATA3 (IOU) CPU_MII_TXD3 (O) NC (U) P_DATA4 P_DATA4 (IOU) P_DATA4 (IOU) CPU_MII_TXCLK (O) NC (U) P_DATA5 P_DATA5 (IOU) P_DATA5 (IOU) CPU_MII_TXEN (O) NC (U) P_DATA6 P_DATA6 (IOU) P_DATA6 (IOU) NC (U) NC (U) P_DATA7 P_DATA7 (IOU) P_DATA7 (IOU) NC (U) NC (U) P_DATA8 P_DATA8 (IOU) NC (U) CPU_MII_RXD0 (I) NC (U) P_DATA9 P_DATA9 (IOU) NC (U) CPU_MII_RXD1 (I) NC (U) P_DATA10 DATA10 P_DATA10 DATA10 (IOU) NC (U) CPU_MII_RXD2 (I) Nc (U) P_DATA11 DATA11 P_DATA11 DATA11 (IOU) NC (U) CPU_MII_RXD3 (I) NC (U) P_DATA12 DATA12 P_DATA12 DATA12 (IOU) NC (U) CPU_MII_RXCLK (O) NC (U) P_DATA13 DATA13 P_DATA13 DATA13 (IOU) NC (U) CPU_MII_RXDV (I) NC (U) P_DATA14 DATA14 P_DATA14 DATA14 (IOU) NC (U) NC (U) NC (U) P_DATA15 DATA15 P_DATA15 DATA15 (IOU) NC (U) NC (U) NC (U) Table 3 - Signal Mapping In Different Operation Mode 18 Zarlink Semiconductor Inc. ZL50409 ZL50409 1.5 Data Sheet Bootstrap Options TSTOUT[15:0] and M[7:0]_TXEN pins serve as bootstrap pins during device power-up or reset. Please refer to "Typical Reset & Bootstrap Timing Diagram" on page 114 for more information on when the bootstrap pins are sampled. The bootstrap pins require external pull-up/down resistors for proper operation. The table below summarizes the bootstrap options. Feature CPU Interface Description The ZL50409 ZL50409 allows the selection of 5 different management interfaces: 8/16-bit parallel, serial with MII, serial only and unmanaged serial with I2C EEPROM. TSTOUT[3:1] is used to select the interface options mentioned above. If the serial interface is selected, addition bootstrap options are required: · TSTOUT[0] enables or disables the DEBOUNCE feature (refer to "Synchronous Serial Interface" on page 27) · TSTOUT[6:4] selects the device ID Also, an optional I2C EEPROM can be used to configure the device at power-up or reset. TSTOUT[7] selects the EEPROM option. Ethernet Interface The ZL50409 ZL50409 supports module hotswap on all it's ports. This is enabled via TSTOUT[9]. When enabled, bootstrap pins M[7:0]_TXEN (ports 0-7) are used to specify the module type to support multiple ethernet interfaces during module hotswap. Another feature is the ZL50409 ZL50409 MAC power savings mode. When enabled via TSTOUT[11], each port's MAC will detect inactivity on the port and go into a power savings state. Once activity is detected once again on the port, the MAC will come out of this state. Misc. Features One other feature selected via bootstrap is Timeout Reset Enable (TSTOUT[12]). This enables a monitoring block with the device which will detect if any hardware state machine is in a non-idle state for more than 5 seconds. Refer to section 2.12 for more details on this feature. Table 4 - Bootstrap Features 19 Zarlink Semiconductor Inc. ZL50409 ZL50409 2.0 Data Sheet Block Functionality MMAC RMAC X 8 Frame Engine Search Engine Other Internal Memory Block Management Module Internal Memory Figure 2 - Functional Block Diagram 2.1 Internal Memory Two Megabit of internal memory is provided for ethernet Frame Data Buffering (FDB) and for storing of Mac Control Table database (MCT). The MCT is used for storing MAC addresses and their physical port number. The FDB is used for storing the received frame data contents. The contents are stored in this memory until it is ready to be transmitted to the egress port. A memory arbiter is used to arbitrary the memory access requests from various sources. Build in self test is used to detect any error in the memory array when the device is powered up. Build in self test can also be requested by the writing the GCR register. 2.2 MII MAC Module (MMAC) The MII Media Access Control (MMAC) module provides the necessary buffers and control interface between the Frame Engine (FE) and the external physical device (PHY). The ZL50409 ZL50409 MMAC implements the MII interface and meets the IEEE 802.3Z specification. It is able to operate in 10M/100M 10M/100M either Half or Full Duplex mode with a back pressure/flow control mechanism. Furthermore, it will automatically retransmit upon collision for up to 16 total transmissions. This port is denoted as port 9. The PHY address for the PHY device connected to the MMAC port has to be 10h. 2.3 RMII MAC Module (RMAC) The RMII Media Access Control (RMAC) module provides the necessary buffers and control interface between the Frame Engine (FE) and the external physical device (PHY). It has three interfaces, MII, RMII or GPSI (only for 10M). The RMAC of the ZL50409 ZL50409 device meets the IEEE 802.3 specification. It is able to operate in either Half or Full Duplex mode with a back pressure/flow control mechanism. In addition, it will automatically retransmit upon collision for up to 16 total transmissions. These eight ports are denoted as ports 0 to 7. The PHY addresses for the PHY devices connected to the 8 RMAC ports has to be from 08h (port 0) to 0Fh (port 7). 20 Zarlink Semiconductor Inc. ZL50409 ZL50409 2.4 Data Sheet Management Module The CPU can send a control frame to access or configure the internal network management database. The Management Module decodes the control frame and executes the functions requested by the CPU. This Module is only active in managed mode. In unmanaged mode, no control frame is accepted by the device. 2.5 Frame Engine The main function of the frame engine is to forward a frame to its proper destination port or ports. When a frame arrives, the frame engine parses the frame header (64 bytes) and formulates a switching request, sent to the search engine, to resolve the destination port. The arriving frame is moved to the internal memory. After receiving a switch response from the search engine, the frame engine performs transmission scheduling based on the frame's priority. The frame engine forwards the frame to the MAC module when the frame is ready to be sent. 2.6 Search Engine The Search Engine resolves the frame's destination port or ports according to the destination MAC address (L2) or IP multicast address (IP multicast packet) by searching the database. It also performs MAC learning, priority assignment, and trunking functions. 2.7 Other Internal Memory blocks Several internal tables are required and are described as follows: · · Network Management (NM) Database - The NM database contains the information in the statistics counters and MIB. MAC address Control (MCLT) Link Table - The MCT Link Table stores the linked list of MCT entries that have collisions in the external MAC Table. 2.8 Management and Configuration One extra port is dedicated to the CPU via the CPU interface module. Two modes this port can operate: managed or unmanaged mode. The different between these modes is tx/rx Ethernet frame and receiving interrupt due to the lack of constant attention or processing power from the CPU. The CPU interface utilizes a 16/8-bit bus in managed mode. It also supports a serial and an I2C interface, which provides an easy and lower cost way to configure the system for reduced management. Supported CPU interface modes are Operation Mode ISA Interface Serial MII I²C 16-bit CPU 16-bit NA NA NA 8-bit CPU 8-bit NA NA NA Serial with MII interface NA Yes Yes No Serial NA Yes No No Unmanaged Serial NA Yes No Yes Table 1 - Supported CPU interface modes 1. 16-bit CPU interface similar to the Industry Standard Architecture (ISA) specification. 2. 8-bit CPU interface similar to ISA. 3. Serial with MII. A synchronous serial interface (SSI) bus is used for accessing the configuration register and control frame. MII is used for sending and receiving CPU packets. 21 Zarlink Semiconductor Inc. ZL50409 ZL50409 Data Sheet 4. Serial only. Configuration registers access, Control frame and CPU transmit/receive packets are sent through a synchronous serial interface (SSI) bus. 5. Unmanaged. The ZL50409 ZL50409 can be configured by EEPROM using an I²C interface at bootup, or via a synchronous serial interface (SSI) otherwise. All configuration registers and internal control blocks are accessible by the interface. However, the CPU cannot receive or transmit frames nor will it receive any interrupt information. The ZL50409 ZL50409 CPU interface provides for easy and effective management of the switching system. Figure 3 on page 22 provides an overview of the 8/16-bit interface. Figure 4 on page 23 provides an overview of the SSI interface. Figure 5 on page 24 provides an overview of the SSI+MII interface. Processor WR 3-bit Address Bus 8/16-bit Data Bus ZL50409 ZL50409 Address Index Reg 1 (Addr = 1) Index Reg 0 (Addr = 0) Config Data Reg (Addr = 2) I/O Data MUX Command/ Status Reg (Addr = 4) CPU Frame Reg (Addr = 3) Interrupt Reg (Addr = 5) Control Command 1 Reg (Addr = 6) Control Command 2 Reg (Addr = 7) 8/16-bit Data Bus 16-bit Address 8-bit Data Bus Internal Registers Inderect Access 8/16-bit Data Bus Control Control Command 1 Command 1Transmit Receive FIFO FIFO CPU frame Transmit CPU frame Receive FIFO FIFO Interrupt Figure 3 - Overview of the ZL50409 ZL50409 8/16-bit Interface 22 Zarlink Semiconductor Inc. Control Command 2 Transmit FIFO ZL50409 ZL50409 Data Sheet Processor Serial Out Serial In Strobe ZL50409 ZL50409 Synchronous Serial Interface 3-bit Address Bus 16-bit Data Bus Address Index Reg 1 (Addr = 1) Index Reg 0 (Addr = 0) Config Data Reg (Addr = 2) CS W R I/O Data MUX Command/ Status Reg (Addr = 4) CPU Frame Reg (Addr = 3) Interrupt Reg (Addr = 5) Control Command 1 Reg (Addr = 6) Control Command 2 Reg (Addr = 7) 8/16-bit Data Bus 16-bit Address 8-bit Data Bus Internal Registers Inderect Access 8/16-bit Data Bus Control Control Command 1 Command 1Transmit Receive FIFO FIFO CPU frame Transmit CPU frame Receive FIFO FIFO Interrupt Figure 4 - Overview of the ZL50409 ZL50409 SSI Interface 23 Zarlink Semiconductor Inc. Control Command 2 Transmit FIFO ZL50409 ZL50409 Data Sheet Processor Tclk Txd Txen Rxd Rxdv Rclk Serial Out Serial In Strobe ZL50409 ZL50409 MII Interface Synchronous Serial Interface 3-bit Address Bus 16-bit Data Bus Address Index Reg 1 (Addr = 1) 8/16-bit Data Bus Index Reg 0 (Addr = 0) 16-bit Address CPU frame Transmit CPU frame Receive FIFO FIFO CS W R I/O Data MUX Config Data Reg (Addr = 2) Command/ Status Reg (Addr = 4) Interrupt Reg (Addr = 5) 8-bit Data Bus Control Command 1 Reg (Addr = 6) Control Command 2 Reg (Addr = 7) 8/16-bit Data Bus Control Control Command 1 Command 1Transmit Receive FIFO FIFO Internal Registers Inderect Access Control Command 2 Transmit FIFO Interrupt Figure 5 - Overview of the ZL50409 ZL50409 SSI+MII Interface 2.9 2.9.1 Register Configuration, Frame Transmission, and Frame Reception Register Configuration The ZL50409 ZL50409 has many programmable parameters, covering such functions as QoS weights, VLAN control, and port mirroring setup. In managed mode, the CPU interface provides an easy way of configuring these parameters. The parameters are contained in 8-bit configuration registers. The ZL50409 ZL50409 allows indirect access to these registers, as follows: · · · · In serial mode, address, command and data are shifted in serially. To access the configuration register, only one "index" registers (addresses 000b) needs to be written with the configuration register address. The desired data can be written into "configure data" register (address 010b). For example, if "XX" is required to be written to register "YY", a write of "YY" is required to write to address "000b" (Index register). Then, a write of "XX" is required to write to address "010b" (Conig Data Register). This completes the register write and register "YY" will contain the value of "XX". If operating in 8-bit interface mode, two "index" registers (addresses 000b and 001b) need to be written, to indicate the desired 8-bit register address. In 16-bit mode, only one register (address 000b) needs to be written for the desired 16-bit register address. To indirectly configure the register addressed by the index register(s), a "configure data" register (address 010b) must be written with the desired 8-bit data. Similarly, to read the value in the register addressed by the index register(s), the "configure data" register can now simply be read. 24 Zarlink Semiconductor Inc. ZL50409 ZL50409 · · Data Sheet ZL50409 ZL50409 supports incremental read/write. If CPU requires to read or write to the configuration register incrementally, CPU only has to write to index register once with the MSB of configuration register address set and then CPU can continuously reading or writing to "configure data" register (010b). ZL50409 ZL50409 supports special register-write in serial and 16-bit mode. This allows CPU to write to two consecutive configuration registers in a single write operation. By writing to bit[14] of configuration register address, CPU can write 16-bit data to address 010b. Lower 8 bit of data is for the address specified in index register and upper 8 bit of data is for the address + 1. In 8-bit mode, this special feature will be ignored. 15 14 INC R/W SP W 13 12 0 11 Reserved 12 Bit Register Address In summary, access to the many internal registers is carried out simply by directly accessing only two registers ­ one register to indicate the index of the desired parameter, and one register to read or write a value. Of course, because there is only one bus master, there can never be any conflict between reading and writing the configuration registers. 2.9.2 Rx/Tx of Standard Ethernet Frames In serial mode with MII, the MII interface is used for CPU to transmit and receive Ethernet frames. In 8/16-bit or serial only mode, the Ethernet frame is transmitted and received through the CPU interface. To transmit a frame from the CPU in 8/16-bit or serial only mode: · · The CPU writes a "data frame" register (address 011) with the data it wants to transmit (minimum 64 bytes). After writing all the data, it then writes the frame size, destination port number, and frame status. The ZL50409 ZL50409 forwards the Ethernet frame to the desired destination port, no longer distinguishing the fact that the frame originated from the CPU. To receive a frame into the CPU in 8/16-bit or serial only mode: · · · The CPU receives an interrupt when an Ethernet frame is available to be received. Frame information arrives first in the data frame register. This includes source port number, frame size, and VLAN tag. The actual data follows the frame information. The CPU uses the frame size information to read the frame out. To transmit a frame from the CPU with MII interface: · · · ZL50409 ZL50409 acts as a PHY to provide receive clock (RXCLK) to CPU so the CPU will depend on this receive clock to send packets to ZL50409 ZL50409 ZL50409 ZL50409 has the ability to halt the receive clock if the receive FIFO of ZL50409 ZL50409 is overflow. Transmitting from CPU to ZL50409 ZL50409 will resume once the receive FIFO of ZL50409 ZL50409 is no longer overflow Follow the standard Ethernet transmission format. CPU assert receive data valid (RXDV) before transmitting data to ZL50409 ZL50409 and de-assert RXDV after transmitting the last data To receive a frame into the CPU with MII interface: · · · ZL50409 ZL50409 acts as a PHY to provide transmit clock (TXCLK) to CPU so the CPU will depend on the transmit clock to receive packets from ZL50409 ZL50409 ZL50409 ZL50409 has the ability to halt the transmit clock if the transmit FIFO of ZL50409 ZL50409 is under-run. CPU will resume receiving packets from ZL50409 ZL50409 once the transmit FIFO of ZL50409 ZL50409 is no longer under-run Follow the standard Ethernet transmission format. CPU will see transmit enable (TXEN) be asserted by ZL50409 ZL50409 and CPU can start receiving data. CPU will stop receiving data once TXEN is de-asserted by ZL50409 ZL50409. In summary, in 8/16-bit or serial only mode, receiving and transmitting frames to and from the CPU is a simple process that uses one direct access register only. In serial mode with MII interface, the CPU will be allowed to transmit and receive frames using standard 802.3 Ethernet transmission format. 25 Zarlink Semiconductor Inc. ZL50409 ZL50409 2.9.3 Data Sheet Control Frames In addition to standard Ethernet frames described in the preceding section, the CPU is also called upon to handle special "Control frames," generated by the ZL50409 ZL50409 and sent to the CPU. These proprietary frames are related to such tasks as statistics collection, MAC address learning, and aging, etc. All Control frames are up to 40 bytes long. Transmitting and receiving these frames is similar to transmitting and receiving Ethernet frames, except that the register accessed is the "Control frame data" register (address 111). Specifically, there are eleven types of control frames generated by the CPU and sent to the ZL50409 ZL50409: - Memory read request Memory write request Learn Unicast MAC address Delete Unicast MAC address Search Unicast MAC address Learn IP Multicast address Delete IP Multicast address Search IP Multicast address Learn Multicast MAC address Delete Multicast MAC address Search Multicast MAC address Note: Memory read and write requests by the CPU may include all internal memories which include statistic counters, Mac address control link table and the 2Mbit (256KB 256KB) memory block. In addition, there are nine types of Control frames generated by the ZL50409 ZL50409 and sent to the CPU: - Interrupt CPU when statistics counter rolls over Response to memory read request from CPU Learn Unicast MAC address Delete Unicast MAC address Delete Multicast MAC address Delete IP Multicast address Response to search Unicast MAC address request from CPU Response to search IP Multicast address request from CPU Response to search Multicast Mac address request from CPU The format of the Control Frame is described in the processor interface application note. 2.10 I2C Interface The I²C interface serves the function of configuring the ZL50409 ZL50409 at boot time. The master is the ZL50409 ZL50409, and the slave is the EEPROM memory. The I²C interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries the control signals that facilitate the transfer of information from EEPROM to the switch. Data transfer is 8-bit serial and bidirectional, at 50 Kbps. Data transfer is performed between master and slave IC using a request / acknowledgment style of protocol. The master IC generates the timing signals and terminates data transfer. Figure 6 on page 26 depicts the data transfer format. The slave address is the memory address of the EEPROM. Refer to "ZL50409 ZL50409 Register Description" on page 52 for I²C address for each register. START SLAVE ADDRESS R/W ACK DATA 1 (8bits) ACK DATA 2 ACK DATA M Figure 6 - Data Transfer Format for I²C Interface 26 Zarlink Semiconductor Inc. ACK STOP ZL50409 ZL50409 2.10.1 Data Sheet Start Condition Generated by the master (in our case, the ZL50409 ZL50409). The bus is considered to be busy after the Start condition is generated. The Start condition occurs if while the SCL line is High, there is a High-to-Low transition of the SDA line. Other than in the Start condition (and Stop condition), the data on the SDA line must be stable during the High period of SCL. The High or Low state of SDA can only change when SCL is Low. In addition, when the I²C bus is free, both lines are High. 2.10.2 Address The first byte after the Start condition determines which slave the master will select. The slave in our case is the EEPROM. The first seven bits of the first data byte make up the slave address. 2.10.3 Data Direction The eighth bit in the first byte after the Start condition determines the direction (R/W) of the message. A master transmitter sets this bit to W; a master receiver sets this bit to R. 2.10.4 Acknowledgment Like all clock pulses, the acknowledgment-related clock pulse is generated by the master. However, the transmitter releases the SDA line (High) during the acknowledgment clock pulse. Furthermore, the receiver must pull down the SDA line during the acknowledge pulse so that it remains stable Low during the High period of this clock pulse. An acknowledgment pulse follows every byte transfer. If a slave receiver does not acknowledge after any byte, then the master generates a Stop condition and aborts the transfer. If a master receiver does not acknowledge after any byte, then the slave transmitter must release the SDA line to let the master generate the Stop condition. 2.10.5 Data After the first byte containing the address, all bytes that follow are data bytes. Each byte must be followed by an acknowledge bit. Data is transferred MSB first. 2.10.6 Stop Condition Generated by the master. The bus is considered to be free after the Stop condition is generated. The Stop condition occurs if while the SCL line is High, there is a Low-to-High transition of the SDA line. 2.11 Synchronous Serial Interface The synchronous serial interface (SSI) serves the function of configuring the ZL50409 ZL50409 not at boot time but via a PC. The PC serves as master and the ZL50409 ZL50409 serves as slave. The protocol for the synchronous serial interface is nearly identical to the I²C protocol. The main difference is that there is no acknowledgment bit after each byte of data transferred. Debounce logic on the clock signal (STROBE) can be turned off to speedup command time. 3 ID bits are used to allow up to eight ZL50409 ZL50409 devices to share the same synchronous serial interface. The ID of each device can be setup by bootstrap. To reduce the number of signals required, the register address, command and data are shifted in serially through the DATAIN pin. STROBE- pin is used as the shift clock. DATAOUT pin is used as data return path. 27 Zarlink Semiconductor Inc. ZL50409 ZL50409 Data Sheet Each command consists of four parts. · · · · START pulse Register Address Read or Write command Data to be written or read back Write operation can be aborted in the middle by sending an ABORT pulse to the ZL50409 ZL50409. Read operation can only be aborted before issuing the read command to the ZL50409 ZL50409. A START command is detected when DATAIN is sampled high when STROBE- rise and DATAIN is sampled low when STROBE- fall. An ABORT command is detected when DATAIN is sampled low when STROBE- rise and DATAIN is sampled high when STROBE- fall. 2.11.1 Write Command STROBE2 Extra clocks after last transfer D0 ID0 ID1 START ID2 A0 ID A1 ADDR A2 W D0 D1 D2 CMD D3 . D12 D13 D14 D15 DATA Figure 7 - Serial Interface Write Command Functional Timing 2.11.2 Read Command All registers in ZL50409 ZL50409 can be modified through this synchronous serial interface. STROBE- D0 ID0 START ID1 ID ID2 A0 A1 A2 R ADDR CMD AUTOFD- DATA D0 D1 D2 . D12 D13 D14 D15 Figure 8 - Serial Interface Read Command Functional Timing 2.12 Timeout Reset Monitor The ZL50409 ZL50409 supports a state machine monitoring block which can trigger a reset or interrupt if any state machine is determined to be stuck in a non-idle state for more than 5 seconds. This feature is enabled via a bootstrap pin (TSTOUT12 TSTOUT12). It also requires some register configuration via the CPU interface. See Programming Timeout Reset application note for more information. 28 Zarlink Semiconductor Inc. ZL50409 ZL50409 2.13 Data Sheet JTAG An IEEE1149 IEEE1149.1 compliant test interface is provided for boundary scan. 3.0 ZL50409 ZL50409 Data Forwarding Protocol 3.1 Unicast Data Frame Forwarding When a frame arrives, it is assigned a handle in memory by the Frame Control Buffer Manager (FCB Manager). An FCB handle will always be available, because of advance buffer reservations. The memory (SRAM) interface is a 64-bit bus, connected to internal memory block. The Receive DMA (RxDMA) is responsible for multiplexing the data and the address. On a port's "turn," the RxDMA will move 8 bytes (or up to the end-of-frame) from the port's associated RxFIFO into memory (Frame Data Buffer, or FDB). Once an entire frame has been moved to the FDB, and a good end-of-frame (EOF) has been received, the Rx interface makes a switch request. The RxDMA arbitrates among multiple switch requests. The switch request consists of the first 64 bytes of a frame, containing among other things, the source and destination MAC addresses of the frame. The search engine places a switch response in the switch response queue of the frame engine when done. Among other information, the search engine will have resolved the destination port of the frame and will have determined that the frame is unicast. After processing the switch response, the Transmission Queue Manager (TxQ manager) of the frame engine is responsible for notifying the destination port that it has a frame to forward. But first, the TxQ manager has to decide whether or not to drop the frame, based on global FDB reservations and usage, as well as TxQ occupancy at the destination. If the frame is not dropped, then the TxQ manager links the frame's FCB to the correct per-port-per-class TxQ. The switch response will come with 8 classified results. The TxQ manager will map this result into the per-port-per-class queue. Unicast TxQ's are linked lists of transmission jobs, represented by their associated frames' FCB's. There is one linked list for each transmission class for each port. There are 2 transmission classes for each of the 8 RMAC ports, and 4 classes for the MMAC port ­ a total of 24 unicast queues. The TxQ manager is responsible for scheduling transmission among the queues representing different classes for a port. When the port control module determines that there is room in the MAC Transmission FIFO (TxFIFO) for another frame, it requests the handle of a new frame from the TxQ manager. The TxQ manager chooses among the head-of-line (HOL) frames from the per-class queues for that port, using a Zarlink Semiconductor scheduling algorithm. The Transmission DMA (TxDMA) is responsible for multiplexing the data and the address. On a port's turn, the TxDMA will move 8 bytes (or up to the EOF) from memory into the port's associated TxFIFO. After reading the EOF, the port control requests a FCB release for that frame. The TxDMA arbitrates among multiple buffer release requests. The frame is transmitted from the TxFIFO to the line. 3.2 Multicast Data Frame Forwarding After receiving the switch response, the TxQ manager has to make the dropping decision. A global decision to drop can be made, based on global FDB utilization and reservations. If so, then the FCB is released and the frame is dropped. In addition, a selective decision to drop can be made, based on the TxQ occupancy at some subset of the multicast packet's destinations. If so, then the frame is dropped at some destinations but not others, and the FCB is not released. If the frame is not dropped at a particular destination port, then the TxQ manager formats an entry in the multicast queue for that port and class. Multicast queues are physical queues (unlike the linked lists for unicast frames). There are 2 multicast queues for each of the 8 RMAC ports. There are 4 multicast queues for the MMAC port. The mapping from the classified result to the priority queue is the same as the unicast traffic. By default, for the RMAC ports to map the 8 transmit priorities into 2 multicast queues, the 2 LSB are discarded. For the MMAC port, to map the 8 transmit priorities into 4 multicast queues, the LSB are discarded. The priority mapping can be modified 29 Zarlink Semiconductor Inc. ZL50409 ZL50409 Data Sheet through memory configuration command. The multicast queue that is in FIFO format shares the space in the 2M bits internal memory block. The size and starting address can also be programmed through memory configuration command. During scheduling, the TxQ manager treats the unicast queue and the multicast queue of the same class as one logical queue. The older head of line of the two queues is forwarded first. The port control requests a FCB release only after the EOF for the multicast frame has been read by all ports to which the frame is destined. 3.3 Frame Forwarding To and From CPU Frame forwarding from the CPU port to a regular transmission port is nearly the same as forwarding between transmission ports. The only difference is that the physical destination port must be indicated in addition to the destination MAC address. Frame forwarding to the CPU port is nearly the same as forwarding to a regular transmission port. The only difference is in frame scheduling. Instead of using the patent-pending Zarlink Semiconductor scheduling algorithms, scheduling for the CPU port is simply based on strict priority. That is, a frame in a high priority queue will always be transmitted before a frame in a lower priority queue. There are four output queues to the CPU and one receive queue. 4.0 Search Engine 4.1 Search Engine Overview The ZL50409 ZL50409 search engine is optimized for high throughput searching, with enhanced features to support: - 4.2 Up to 4K of Unicast MAC addresses/Multicast MAC addresses and IP Multicast MAC addresses Up to 4K VLANs 8 groups of port trunking Traffic classification into 2 (or 4 for MMAC) transmission priorities, and 2 drop precedence levels Packet filtering based on Mac address, Protocol or Logical Port number Security Up to 4K IP Multicast groups Individual Flooding, Broadcast, Multicast Storm Control MAC address learning and aging Basic Flow Shortly after a frame enters the ZL50409 ZL50409 and is written to the Frame Data Buffer (FDB), the frame engine generates a Switch Request, which is sent to the search engine. The switch request consists of the first 64 bytes of the frame, which contain all the necessary information for the search engine to perform its task. When the search engine is done, it writes to the Switch Response Queue, and the frame engine uses the information provided in that queue for scheduling and forwarding. In performing its task, the search engine extracts and compresses the useful information from the 64-byte switch request. Among the information extracted are the source and destination MAC addresses, the packet's VLAN ID, and whether the frame is unicast or multicast or broadcast. Requests are sent to the SRAM to locate the associated entries in the MCT table. When all the information has been collected from the SRAM, the search engine has to compare the MAC address on the current entry with the MAC address for which it is searching. If it is not a match, the process is repeated on the internal MCT Table. All MCT entries other than the first of each linked list are maintained internal to the chip. If the desired MAC address is still not found, then the result is either learning (source MAC address unknown) or flooding (destination MAC address unknown). In addition, VLAN information is used to select the correct set of destination ports for the frame (for multicast), or to verify that the frame's destination port is associated with the VLAN (for unicast). 30 Zarlink Semiconductor Inc. ZL50409 ZL50409 Data Sheet If the destination MAC address belongs to a port trunk, then the trunk number is retrieved instead of the port number. But on which port of the trunk will the frame be transmitted? This is easily computed using a hash of the source and destination MAC addresses. When all the information is compiled, the switch response is generated, as stated earlier. The search engine also interacts with the CPU with regard to learning and aging. 4.3 4.3.1 Search, Learning, and Aging MAC Search The search block performs source MAC address and destination MAC address (or destination IP address for IP multicast) searching. As we indicated earlier, if a match is not found, then the next entry in the linked list must be examined, and so on until a match is found or the end of the list is reached. In tag based VLAN mode, if the frame is unicast, and the destination port is not a member of the correct VLAN, then the frame is forwarded to all the members in the VLAN domain; otherwise, the frame is forwarded. If the frame is multicast or broadcast, the frame is forwarded to all the members in the VLAN. Moreover, if port trunking is enabled, this block selects the destination port (among those in the trunk group). In port based VLAN mode, a bitmap is used to determine whether the frame should be forwarded to the outgoing port. The main difference in this mode is that the bitmap is not dynamic. Ports cannot enter and exit groups because of real-time learning made by a CPU. The MAC search block is also responsible for updating the source MAC address timestamp used for aging. 4.3.2 Learning The learning module learns new MAC addresses and performs port change operations on the MCT database. The goal of learning is to update this database as the networking environment changes over time. When CPU reporting is enabled, learning and port change will be performed when the CPU request queue has room, and a "Learn MAC Address" message is sent to the CPU. When fast learning mode is enabled, learning and port change will be performed when and a latter "Learn MAC Address" message is sent to the CPU when CPU queue has room. 4.3.3 Aging Aging time is controlled by register 400h and 401h. The aging module scans and ages MCT entries based on a programmable "age out" time interval. As we indicated earlier, the search module updates the source MAC address timestamps for each frame it processes. When an entry is ready to be aged, the entry is removed from the table, and a "Delete MAC Address" message is sent to inform the CPU. Supported MAC entry types are: dynamic, static, source filter, destination filter, IP multicast, source and destination filter, secure and multicast MAC address. Only dynamic entries can be aged; all others are static. The MAC entry type is stored in the "status" field of the MCT data structure. 4.4 MAC Address Filtering The ZL50409 ZL50409's implementation of intelligent traffic switching provides filters for source and destination MAC addresses. This feature filters unnecessary traffic, thereby providing intelligent control over traffic flows and broadcast traffic. Broadcast, unknown unicast and unknown multicast MAC address can also be filter on per VLAN basis. MAC address filtering allows the ZL50409 ZL50409 to block an incoming packet to an interface when it sees a specified MAC address in either the source address or destination address of the incoming packet. For example, if your network is 31 Zarlink Semiconductor Inc. ZL50409 ZL50409 Data Sheet congested because of high utilization from a MAC address, you can filter all traffic transmitted from that address and restore network flow, while you troubleshoot the problem. 4.5 Protocol Filtering Packet filtering can be performed based on protocol type field in the packets. Up to eight protocols can be programmed to filter or allow packet to pass through the