ZL50115/16/17/18/19/20 ZL50110 ZL50111 ZL50114 ZL50115GAG ZL50116GAG ZL50117GAG - Datasheet Archive

 

32, 64 and 128 Channel CESoP Processors Data Sheet Features November 2004 Ordering Information General · · On chip

 

ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 32, 64 and 128 Channel CESoP Processors Data Sheet Features November 2004 Ordering Information General · · On chip timing & synchronization recovery across a packet network · Grooming capability for Nx64 Kbps trunking · Fully compatible with Zarlink's ZL50110 ZL50110, ZL50111 ZL50111 and ZL50114 ZL50114 CESoP processors 324 324 324 324 324 324 Ball Ball Ball Ball Ball Ball PBGA PBGA PBGA PBGA PBGA PBGA trays, trays, trays, trays, trays, trays, bake bake bake bake bake bake & & & & & & dry dry dry dry dry dry pack pack pack pack pack pack On chip dual reference Stratum 3 DPLL · ZL50115GAG ZL50115GAG ZL50116GAG ZL50116GAG ZL50117GAG ZL50117GAG ZL50118GAG ZL50118GAG ZL50119GAG ZL50119GAG ZL50120GAG ZL50120GAG Circuit Emulation Services over Packet (CESoP) transport for MPLS, IP and Ethernet networks -40°C to +85°C · Direct connection to LIUs, framers, backplanes Customer Side Packet Interfaces · 100 Mbps MII Fast Ethernet (ZL50118/19/20 ZL50118/19/20 only) (may also be used as a second provider side packet interface) Circuit Emulation Services · Complies with ITU-T recommendation Y.1413 · Complies with IETF PWE3 draft standards CESoPSN and SAToP · Complies with CESoP Implementation Agreements from MEF 8 and MFA 8.0.0 Provider Side Packet Interfaces · Structured, synchronous CESoP · · Unstructured, asynchronous CESoP with integral per-stream clock recovery 100 Mbps MII Fast Ethernet or 1000 Mbps GMII/TBI Gigabit Ethernet System Interfaces Flexible 32 bit Motorola host interface · Up to 4 T1/E1, 1 J2, 1 T3/E3, or 1 STS-1 ports · · H.110, H-MVIP, ST-BUS backplane On-chip packet memory with jitter buffer compensation for over 128 ms of packet delay variation · Up to 128 bi-directional 64 Kbps channels 100 Mbps MII Fast Ethernet Backplane Clocks TDM Interface (LIU, Framer, Backplane) Per Port DCO for Clock Recovery Multi-Protocol Packet Processing Engine PW, RTP, UDP, IPv4, IPv6, MPLS, ECID, VLAN, User Defined, Others Dual Packet Interface MAC (MII, GMII, TBI) 100 Mbps MII Fast Ethernet or 1000 Mbps GMII/TBI Gigabit Ethernet · 4 T1/E1, 1 J2/T3/E3 or 1 STS-1 ports H.110, H-MVIP, ST-BUS backplanes Customer Side TDM Interfaces On Chip Packet Memory (Jitter Buffer Compensation for 128 ms of Packet Delay Variation) Dual Reference Stratum 3 DPLL Host Processor Interface JTAG 32-bit Motorola compatible DMA for signaling packets Figure 1 - ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 High Level Overview 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved. ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Data Sheet Packet Processing Functions · Flexible, multi-protocol packet encapsulation including IPv4, IPv6, RTP, MPLS, L2TPv3, ITU-T Y.1413, IETF CESoPSN, IETF SAToP and user programmable · Packet re-sequencing to allow lost packet detection and re-ordering · Four classes of service with programmable priority mechanisms (WFQ and SP) using egress queues · Programmable classification of incoming packets at layers 2 through 5 · Wire speed processing of all packets regardless of classification providing low latency · Supports up to 128 separate CESoP connections across the Packet Switched Network Applications · Circuit Emulation Services over Packet Networks · Leased Line support over packet networks · TDM over Cable · TDM over WiFi (802.11x) · TDM over WiMAX (802.16) · Fibre To The Premises G/E-PON · Layer 2 VPN services · Customer-premise and Provider Edge Routers and Switches · Ethernet and IP based IADs 2 Zarlink Semiconductor Inc. ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 1.0 Data Sheet Device Line Up There are three products within the ZL5011x family, with capacities as shown in Table 1. Product Number Provider Side Packet Interface TDM Interface Customer Side Packet Interface ZL50115 ZL50115 1 T1 or 1 E1 stream or 1 MVIP/ST-BUS stream at 2.048 Mbps or 1 H.110/H-MVIP/ST-BUS 110/H-MVIP/ST-BUS streams at 8.192 Mbps (Maximum of 32 DS0 or Nx64 kbps channels) 100 Mbps MII or 1000 Mbps GMII/TBI None ZL50116 ZL50116 2 T1 or 2 E1 streams or 2 MVIP/ST-BUS streams at 2.048 Mbps or 1 H.110/H-MVIP/ST-BUS 110/H-MVIP/ST-BUS streams at 8.192 Mbps (Maximum of 64 DS0 or Nx64 kbps channels) 100 Mbps MII or 1000 Mbps GMII/TBI None ZL50117 ZL50117 4 T1 or 4 E1 streams or 1 J2, 1 T3, 1 E3 or 1 STS-1 stream or 4 MVIP/ST-BUS streams at 2.048 Mbps or 1 H.110/H-MVIP/ST-BUS 110/H-MVIP/ST-BUS streams at 8.192 Mbps 100 Mbps MII or 1000 Mbps GMII/TBI None ZL50118 ZL50118 1 T1 or 1 E1 stream or 1 MVIP/ST-BUS stream at 2.048 Mbps or 1 H.110/H-MVIP/ST-BUS 110/H-MVIP/ST-BUS streams at 8.192 Mbps (Maximum of 32 DS0 or Nx64 kbps channels) 100 Mbps MII or 1000 Mbps GMII/TBI 100 Mbps MII ZL50119 ZL50119 2 T1 or 2 E1 streams or 2 MVIP/ST-BUS streams at 2.048 Mbps or 1 H.110/H-MVIP/ST-BUS 110/H-MVIP/ST-BUS streams at 8.192 Mbps (Maximum of 64 DS0 or Nx64 kbps channels) 100 Mbps MII or 1000 Mbps GMII/TBI 100 Mbps MII ZL50120 ZL50120 4 T1 or 4 E1 streams or 1 J2, 1 T3, 1 E3 or 1 STS-1 stream or 4 MVIP/ST-BUS streams at 2.048 Mbps or 1 H.110/H-MVIP/ST-BUS 110/H-MVIP/ST-BUS streams at 8.192 Mbps 100 Mbps MII or 1000 Mbps GMII/TBI 100 Mbps MII Table 1 - Capacity of Devices in the ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Family 3 Zarlink Semiconductor Inc. ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 2.0 Data Sheet Description The ZL5011x family (ZL50115 ZL50115, ZL50116 ZL50116, ZL50117 ZL50117, ZL50118 ZL50118, ZL50119 ZL50119, ZL50120 ZL50120) of CESoP processors are highly functional TDM to Packet bridging devices. The ZL5011x provides both structured and unstructured circuit emulation services (CESoP) for T1 and E1 streams across a packet network based on MPLS, IP or Ethernet. The ZL50117/20 ZL50117/20 also supports unstructured J2, T3, E3 and STS-1. The circuit emulation features in the ZL5011x family comply with the ITU Recommendation Y.1413, as well as the Implementation Agreements for CESoP from the Metro Ethernet Forum (MEF 8) and the MPLS and Frame Relay Alliance (MFA 8.0.0). The ZL5011x also complies with the standards currently being developed within the IETF's PWE3 working group, listed below. · Structure-Agnostic TDM over Packet (SAToP) - draft-ietf-pwe3-satop · Structure-aware TDM Circuit Emulation Service over Packet Switched Network (CESoPSN) draft-ietf-pwe3-cesopsn The ZL50118/19/20 ZL50118/19/20 provides a customer side 100 Mbps MII port to aggregate data traffic with voice traffic to the provider side 1000 Mbps GMII/TBI port, thereby eliminating the need for an external Ethernet switch. The ZL5011x incorporates a range of powerful clock recovery mechanisms for each TDM stream, allowing the frequency of the source clock to be faithfully generated at the destination, enabling greater system performance and quality. Timing is carried using RTP or similar protocols, and both adaptive and differential clock recovery schemes are included, allowing the customer to choose the correct scheme for the application. An externally supplied clock may also be used to drive the TDM interface of the ZL5011x. The ZL5011x incur very low latency for the data flow, thereby increasing QoS when carrying voice services across the Packet Switched Network. Voice, when carried using CESoP, which typically has latencies of less than 10 ms, does not require expensive processing such as compression and echo cancellation. The ZL5011x are cost effective devices aimed at the low density applications such as customer premise routers, IADs, ePON termination and Broadband DLCs. For network systems, the ZL5011x is fully compatible and interoperable with the ZL50110/11/14 ZL50110/11/14 family. The ZL5011x is capable of assembling user-defined packets of TDM traffic from the TDM interface and transmitting them out the packet interfaces using a variety of protocols. The ZL5011x supports a range of different packet switched networks, including Ethernet VLANs, IP (both versions 4 and 6) and MPLS. The devices also supports four different classes of service on packet egress, allowing priority treatment of TDM-based traffic. This can be used to help minimize latency variation in the TDM data. Packets received from the packet interfaces are parsed to determine the egress destination, and are appropriately queued to the TDM interface, they can also be forwarded to the host interface, or back toward the packet interface. Packets queued to the TDM interface can be re-ordered based on sequence number, and lost packets filled in to maintain timing integrity. The ZL5011x includes on-chip memory sufficient for all applications, thereby reducing system costs, board area, power, and design complexity. A comprehensive evaluation system is available upon request from your local Zarlink representative or distributor. This system includes the CESoP processor, various TDM interfaces and a fully featured evaluation software GUI that will run on a Windows PC. 4 Zarlink Semiconductor Inc. ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Data Sheet Table of Contents 1.0 Device Line Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.0 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.0 Physical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.0 External Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.1 TDM stream connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.2 TDM Signals common to ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2 PAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3 Packet Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.4 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.5 System Function Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.6 Test Facilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.6.1 Administration, Control and Test Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.6.2 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.7 Miscellaneous Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.8 Power and Ground Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.9 Internal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.10 No Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.11 Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.0 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.1 Leased Line Provision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.2 Remote Concentrator Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.3 FTTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.4 Wireless - WiFi or WiMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.5 Digital Loop Carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.6 Integrated Access Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.2 Data and Control Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.3 TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.3.1 TDM Interface Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.3.2 Structured TDM Port Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.3.3 TDM Clock Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.3.3.1 Synchronous TDM Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.3.3.2 Asynchronous TDM Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.4 Payload Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.4.1 Structured Payload Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.4.1.1 Payload Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.4.2 Unstructured Payload Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.5 Protocol Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.6 Packet Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.7 Packet Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.8 TDM Formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.9 Ethernet Traffic Aggregation (ZL50118/19/20 ZL50118/19/20 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.0 Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.1 Differential Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.2 Adaptive Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.0 System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.1 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.2 Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.3 Host Packet Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5 Zarlink Semiconductor Inc. ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Data Sheet Table of Contents 8.4 Loss of Service (LOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.5 Power Up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.6 JTAG Interface and Board Level Test Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.7 External Component Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.8 Miscellaneous Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.9 Test Modes Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.9.1.1 System Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.9.1.2 System Tri-State Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.9.2 Test Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.9.3 System Normal Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.9.4 System Tri-state Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.0 DPLL Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.1.1 Locking Mode (normal operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.1.2 Holdover Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.1.3 Freerun Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.1.4 Powerdown Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.2 Reference Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.3 Locking Mode Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.4 Locking Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.5 Locking Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.6 Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.7 Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.7.1 Acceptance of Input Wander . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.7.2 Intrinsic Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.7.3 Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.7.4 Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.8 Maximum Time Interval Error (MTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.0 Memory Map and Register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11.0 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.0 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12.1 TDM Interface Timing - ST-BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12.1.1 ST-BUS Slave Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12.1.2 ST-BUS Master Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 12.2 TDM Interface Timing - H.110 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 12.3 TDM Interface Timing - H-MVIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 12.4 TDM LIU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12.5 PAC Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 12.6 Packet Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 12.6.1 MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 12.6.2 MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.6.3 GMII Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 12.6.4 GMII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.6.5 TBI Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12.6.6 Management Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 12.7 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.8 System Function Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 12.9 JTAG Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13.0 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 14.0 Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6 Zarlink Semiconductor Inc. ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Data Sheet Table of Contents 14.1 High Speed Clock & Data Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 14.1.1 GMAC Interface - Special Considerations During Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 14.1.2 TDM Interface - Special Considerations During Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 14.1.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 14.2 CPU TA Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 15.0 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 15.1 External Standards/Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 15.2 Zarlink Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 16.0 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7 Zarlink Semiconductor Inc. ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Data Sheet List of Figures Figure 1 - ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 High Level Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1 - ZL50115 ZL50115 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 2 - ZL50116 ZL50116 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 3 - ZL50117 ZL50117 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 4 - ZL50118 ZL50118 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 5 - ZL50119 ZL50119 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6 - ZL50120 ZL50120 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 7 - Leased Line Services Over a Circuit Emulation Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 8 - Remote Concentrator Unit using CESoP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 9 - EPON using CESoP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 10 - Wi-Fi and WiMAX using CESoP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 11 - Digital Loop Carrier using CESoP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 12 - Integrated Access Device Using CESoP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 13 - ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Family Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 14 - ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Data and Control Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 15 - Synchronous TDM Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 16 - ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Packet Format - Structured Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 17 - Channel Order for Packet Formation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 18 - ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Packet Format - Unstructured Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 19 - Differential Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 20 - Adaptive Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 21 - Powering Up the ZL5011x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 22 - Jitter Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 23 - Jitter Transfer Function - Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 24 - TDM ST-BUS Slave Mode Timing at 8.192 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 25 - TDM ST-BUS Slave Mode Timing at 2.048 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 26 - TDM Bus Master Mode Timing at 8.192 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 27 - TDM Bus Master Mode Timing at 2.048 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 28 - H.110 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 29 - TDM - H-MVIP Timing Diagram for 16 MHz Clock (8.192 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 30 - TDM-LIU Structured Transmission/Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 31 - MII Transmit Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 32 - MII Receive Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 33 - GMII Transmit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 34 - GMII Receive Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 35 - TBI Transmit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 36 - TBI Receive Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 37 - Management Interface Timing for Ethernet Port - Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 38 - Management Interface Timing for Ethernet Port - Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 39 - CPU Read - MPC8260 MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 40 - CPU Write - MPC8260 MPC8260. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 41 - CPU DMA Read - MPC8260 MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 42 - CPU DMA Write - MPC8260 MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 43 - JTAG Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 44 - JTAG Clock and Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 45 - ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Power Consumption Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 46 - CPU_TA Board Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8 Zarlink Semiconductor Inc. ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Data Sheet List of Tables Table 1 - Capacity of Devices in the ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Table 1 - ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Ball Signal Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 2 - TDM Interface Stream Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 3 - TDM Interface Common Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 4 - PAC Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 5 - Packet Interface Signal Mapping - MII to GMII/TBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 6 - MII Management Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 7 - MII Port 0 Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 8 - MII Port 1 Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 9 - CPU Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 10 - System Function Interface Package Ball Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 11 - Administration/Control Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 12 - JTAG Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 13 - Miscellaneous Inputs Package Ball Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 14 - Power and Ground Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 15 - Internal Connections Package Ball Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 16 - Miscellaneous Inputs Package Ball Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 17 - Device ID Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 18 - Standard Device Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 19 - TDM Services Offered by the ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 20 - Some of the TDM Port Formats Accepted by the ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Family . . . . . . . . . . . . . . . 49 Table 21 - DMA Maximum Bandwidths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 22 - Test Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 23 - DPLL Input Reference Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 24 - TDM ST-BUS Master Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 25 - TDM H.110 Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 26 - TDM H-MVIP Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 27 - TDM - LIU Structured Transmission/Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 28 - PAC Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 29 - MII Transmit Timing - 100 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 30 - MII Receive Timing - 100 Mbps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 31 - GMII Transmit Timing - 1000 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 32 - GMII Receive Timing - 1000 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 33 - TBI Timing - 1000 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 34 - MAC Management Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 35 - CPU Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 36 - System Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 37 - JTAG Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 9 Zarlink Semiconductor Inc. ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 3.0 Physical Specification The ZL5011x will be packaged in a PBGA device. Features: · Body Size: 23 mm x 23 mm (typ) · Ball Count: 324 · Ball Pitch: 1.00 mm (typ) · Ball Matrix: 22 x 22 · Ball Diameter: 0.60 mm (typ) · Total Package Thickness: 2.03 mm (typ) 10 Zarlink Semiconductor Inc. Data Sheet ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Data Sheet ZL50115 ZL50115 Package view from TOP side. Note that ball A1 is non-chamfered corner. 1 2 3 4 5 6 7 8 9 10 11 12 13 M0_GTX_C M0_TXEN DEVICE_ID CPU_DATA[CPU_DATA[GND LK [4] 28] 24] 14 15 CPU_DATA[ GND 23] 16 17 18 19 20 21 22 A VDD_IO NC M0_TXCLK M0_RXD[7] M0_RXD[6] M0_RXD[4] M0_COL B NC VDD_IO GND NC NC M0_CRS M0_RXD[0] M0_RBC1 M0_RBC0 M0_TXER GND C NC GND VDD_IO NC NC NC M0_RXDV M0_RXD[3] M0_RXD[1] M0_RXCLK M0_TXD[7] M0_TXD[4] M0_TXD[0] VDD_IO D NC NC NC VDD_IO NC M0_RXER VDD_IO E NC M0_GIGABI NC T_LED F NC NC G M_MDIO DEVICE_ID M0_LINKU VDD_IO [0] P_LED VDD_IO H M_MDC GND NC VDD_COR E CPU_DATA[CPU_DATA[CPU_DATA[ IC 10] 1] 4] J NC NC NC VDD_COR E GND GND GND GND GND GND VDD_COR CPU_DATA[CPU_DATA[ CPU_IREQ E 5] 3] 0 K NC NC NC VDD_IO GND GND GND GND GND GND GND L GND AUX_CLKO AUX_CLKI VDD_COR E GND GND GND GND GND GND CPU_CLK GND M NC NC NC VDD_IO GND GND GND GND GND GND GND CPU_TS_A CPU_WE LE CPU_OE N NC NC NC VDD_COR E GND GND GND GND GND GND VDD_IO CPU_ADD CPU_CS R[22] CPU_ADDR [19] P NC GND VDD_IO VDD_COR E GND GND GND GND GND GND VDD_COR CPU_ADD CPU_ADDR CPU_ADDR E R[17] [18] [21] R NC NC TDM_CLKI[ NC 0] GND CPU_ADD CPU_ADDR CPU_ADDR R[11] [13] [20] T NC NC TDM_FRMI VDD_IO _REF VDD_IO VDD_IO U TDM_STI[0]VDD_IO GND TDM_CLKi S VDD_COR JTAG_TMS CPU_ADDR CPU_ADDR E [15] [12] V TDM_STO[ TDM_CLKO TDM_CLKO TDM_CLKi 0] [0] _REF P DEVICE_ID JTAG_TCK CPU_ADDR CPU_ADDR [3] [10] [9] M0_TXD[5] M0_TXD[3] M0_TXD[2] NC VDD_IO CPU_DATA[ CPU_DATA[ CPU_DATA[CPU_DATA[CPU_DATA[CPU_SDAC VDD_IO 19] 12] 9] 8] 7] K1 CPU_DATA[CPU_DATA[ CPU_DATA[CPU_DATA[GND 27] 22] 20] 13] VDD_IO CPU_TA CPU_DATA[NC 31] GND CPU_DRE Q1 M0_RXD[5] VDD_COR M0_RXD[2] M0_REFCL M0_TXD[6] M0_TXD[1] VDD_COR VDD_COR VDD_IO E K E E CPU_DATA[CPU_DATA[VDD_IO 29] 26] M0_ACTIV VDD_COR VDD_IO E_LED E NC CPU_DATA[CPU_ADDR CPU_DATA[ 25] [23] 6] CPU_DATA[CPU_DATA[CPU_DATA[ CPU_DATA[ 30] 21] 15] 14] DEVICE_ID VDD_COR [1] E VDD_COR CPU_DATA[CPU_DATA[ CPU_DATA[ E 18] 17] 16] W IC TDM_CLKI TDM_FRM VDD_IO _REF O_REF VDD_IO VDD_COR VDD_IO E VDD_IO VDD_COR PLL_SEC E IC_GND GND SYSTEM_C VDD_COR GPIO[9] LK E VDD_IO GPIO[15] Y IC GND VDD_IO IC IC VDD_COR IC E IC PLL_PRI IC IC_GND IC GND AA IC VDD_IO GND VDD_IO VDD_IO IC GND A1VDD_PL IC L1 IC AB VDD_IO IC IC IC GND IC IC IC GPIO[3] GPIO[0] DEVICE_ID VDD_IO [2] CPU_IREQ CPU_DATA[ CPU_DATA[ 1 11] 0] CPU_DATA[IC 2] CPU_DRE Q0 CPU_SDAC IC_VDD_IO K2 CPU_ADDR CPU_ADDR [14] [16] JTAG_TDO CPU_ADDR CPU_ADDR [4] [8] GND GPIO[8] GPIO[14] TEST_MOD JTAG_TRS IC_GND E[1] T VDD_IO GND CPU_ADDR [7] SYSTEM_D SYSTEM_R GPIO[1] EBUG ST GPIO[2] GPIO[7] GPIO[12] TEST_MOD JTAG_TDI IC_GND E[0] GND VDD_IO CPU_ADDR [6] GPIO[4] GPIO[10] GPIO[11] GPIO[13] TEST_MOD IC_GND E[2] GPIO[5] GPIO[6] Figure 1 - ZL50115 ZL50115 Package View and Ball Positions 11 Zarlink Semiconductor Inc. CPU_ADD CPU_ADD CPU_ADDR VDD_IO R[2] R[3] [5] ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Data Sheet ZL50116 ZL50116 Package view from TOP side. Note that ball A1 is non-chamfered corner. 1 2 3 4 5 6 7 8 9 10 11 12 13 M0_GTX_C M0_TXEN DEVICE_ID CPU_DATA[CPU_DATA[GND LK [4] 28] 24] 14 15 CPU_DATA[ GND 23] 16 17 18 19 20 21 22 A VDD_IO NC M0_TXCLK M0_RXD[7] M0_RXD[6] M0_RXD[4] M0_COL B NC VDD_IO GND NC NC M0_CRS M0_RXD[0] M0_RBC1 M0_RBC0 M0_TXER GND C NC GND VDD_IO NC NC NC M0_RXDV M0_RXD[3] M0_RXD[1] M0_RXCLK M0_TXD[7] M0_TXD[4] M0_TXD[0] VDD_IO D NC NC NC VDD_IO NC M0_RXER VDD_IO E NC M0_GIGABI NC T_LED F NC NC G M_MDIO DEVICE_ID M0_LINKU VDD_IO [0] P_LED VDD_IO H M_MDC GND NC VDD_COR E CPU_DATA[CPU_DATA[CPU_DATA[ IC 10] 1] 4] J NC NC NC VDD_COR E GND GND GND GND GND GND VDD_COR CPU_DATA[CPU_DATA[ CPU_IREQ E 5] 3] 0 K NC NC NC VDD_IO GND GND GND GND GND GND GND L GND AUX_CLKO AUX_CLKI VDD_COR E GND GND GND GND GND GND CPU_CLK GND M NC NC NC VDD_IO GND GND GND GND GND GND GND CPU_TS_A CPU_WE LE CPU_OE N NC NC NC VDD_COR E GND GND GND GND GND GND VDD_IO CPU_ADD CPU_CS R[22] CPU_ADDR [19] P NC GND VDD_IO VDD_COR E GND GND GND GND GND GND VDD_COR CPU_ADD CPU_ADDR CPU_ADDR E R[17] [18] [21] R NC TDM_STI[1]TDM_CLKI[ TDM_STO[ 0] 1] T M0_TXD[5] M0_TXD[3] M0_TXD[2] NC VDD_IO CPU_DATA[ CPU_DATA[ CPU_DATA[CPU_DATA[CPU_DATA[CPU_SDAC VDD_IO 19] 12] 9] 8] 7] K1 CPU_DATA[CPU_DATA[ CPU_DATA[CPU_DATA[GND 27] 22] 20] 13] VDD_IO CPU_TA CPU_DATA[NC 31] GND CPU_DRE Q1 M0_RXD[5] VDD_COR M0_RXD[2] M0_REFCL M0_TXD[6] M0_TXD[1] VDD_COR VDD_COR VDD_IO E K E E CPU_DATA[CPU_DATA[VDD_IO 29] 26] M0_ACTIV VDD_COR VDD_IO E_LED E NC CPU_DATA[CPU_ADDR CPU_DATA[ 25] [23] 6] CPU_DATA[CPU_DATA[CPU_DATA[ CPU_DATA[ 30] 21] 15] 14] DEVICE_ID VDD_COR [1] E VDD_COR CPU_DATA[CPU_DATA[ CPU_DATA[ E 18] 17] 16] CPU_IREQ CPU_DATA[ CPU_DATA[ 1 11] 0] CPU_DATA[IC 2] CPU_DRE Q0 CPU_SDAC IC_VDD_IO K2 GND CPU_ADD CPU_ADDR CPU_ADDR R[11] [13] [20] TDM_CLKI[ TDM_CLKO TDM_FRMI VDD_IO 1] [1] _REF VDD_IO VDD_IO U TDM_STI[0]VDD_IO TDM_CLKi S VDD_COR JTAG_TMS CPU_ADDR CPU_ADDR E [15] [12] V TDM_STO[ TDM_CLKO TDM_CLKO TDM_CLKi 0] [0] _REF P DEVICE_ID JTAG_TCK CPU_ADDR CPU_ADDR [3] [10] [9] GND W IC TDM_CLKI TDM_FRM VDD_IO _REF O_REF VDD_IO VDD_COR VDD_IO E VDD_IO VDD_COR PLL_SEC E IC_GND GND SYSTEM_C VDD_COR GPIO[9] LK E VDD_IO GPIO[15] Y IC GND VDD_IO IC IC VDD_COR IC E IC PLL_PRI IC IC_GND IC GND AA IC VDD_IO GND VDD_IO VDD_IO IC GND A1VDD_PL IC L1 IC AB VDD_IO IC IC IC GND IC IC IC GPIO[3] GPIO[0] DEVICE_ID VDD_IO [2] CPU_ADDR CPU_ADDR [14] [16] JTAG_TDO CPU_ADDR CPU_ADDR [4] [8] GND GPIO[8] GPIO[14] TEST_MOD JTAG_TRS IC_GND E[1] T VDD_IO GND CPU_ADDR [7] SYSTEM_D SYSTEM_R GPIO[1] EBUG ST GPIO[2] GPIO[7] GPIO[12] TEST_MOD JTAG_TDI IC_GND E[0] GND VDD_IO CPU_ADDR [6] GPIO[4] GPIO[10] GPIO[11] GPIO[13] TEST_MOD IC_GND E[2] GPIO[5] GPIO[6] Figure 2 - ZL50116 ZL50116 Package View and Ball Positions 12 Zarlink Semiconductor Inc. CPU_ADD CPU_ADD CPU_ADDR VDD_IO R[2] R[3] [5] ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Data Sheet ZL50117 ZL50117 Package view from TOP side. Note that ball A1 is non-chamfered corner. 1 2 3 4 5 6 7 8 9 10 11 12 13 M0_GTX_C M0_TXEN DEVICE_ID CPU_DATA[CPU_DATA[GND LK [4] 28] 24] 14 15 CPU_DATA[ GND 23] 16 17 18 19 20 21 22 A VDD_IO NC M0_TXCLK M0_RXD[7] M0_RXD[6] M0_RXD[4] M0_COL B NC VDD_IO GND NC NC M0_CRS M0_RXD[0] M0_RBC1 M0_RBC0 M0_TXER GND C NC GND VDD_IO NC NC NC M0_RXDV M0_RXD[3] M0_RXD[1] M0_RXCLK M0_TXD[7] M0_TXD[4] M0_TXD[0] VDD_IO D NC NC NC VDD_IO NC M0_RXER VDD_IO E NC M0_GIGABI NC T_LED F NC NC G M_MDIO DEVICE_ID M0_LINKU VDD_IO [0] P_LED VDD_IO H M_MDC GND NC VDD_COR E CPU_DATA[CPU_DATA[CPU_DATA[ IC 10] 1] 4] J NC NC NC VDD_COR E GND GND GND GND GND GND VDD_COR CPU_DATA[CPU_DATA[ CPU_IREQ E 5] 3] 0 K NC NC NC VDD_IO GND GND GND GND GND GND GND L GND AUX_CLKO AUX_CLKI VDD_COR E GND GND GND GND GND GND CPU_CLK GND M TDM_CLKI[ TDM_STO[ TDM_STI[3]VDD_IO 3] 3] GND GND GND GND GND GND GND CPU_TS_A CPU_WE LE CPU_OE N TDM_STO[ TDM_CLKO TDM_STI[2]VDD_COR 2] [3] E GND GND GND GND GND GND VDD_IO CPU_ADD CPU_CS R[22] CPU_ADDR [19] P TDM_CLKI[ GND 2] GND GND GND GND GND GND VDD_COR CPU_ADD CPU_ADDR CPU_ADDR E R[17] [18] [21] R TDM_CLKO TDM_STI[1]TDM_CLKI[ TDM_STO[ [2] 0] 1] GND CPU_ADD CPU_ADDR CPU_ADDR R[11] [13] [20] T TDM_CLKI[ TDM_CLKO TDM_FRMI VDD_IO 1] [1] _REF VDD_IO VDD_IO U TDM_STI[0]VDD_IO TDM_CLKi S VDD_COR JTAG_TMS CPU_ADDR CPU_ADDR E [15] [12] V TDM_STO[ TDM_CLKO TDM_CLKO TDM_CLKi 0] [0] _REF P DEVICE_ID JTAG_TCK CPU_ADDR CPU_ADDR [3] [10] [9] M0_TXD[5] M0_TXD[3] M0_TXD[2] NC VDD_IO CPU_DATA[ CPU_DATA[ CPU_DATA[CPU_DATA[CPU_DATA[CPU_SDAC VDD_IO 19] 12] 9] 8] 7] K1 CPU_DATA[CPU_DATA[ CPU_DATA[CPU_DATA[GND 27] 22] 20] 13] VDD_IO CPU_TA CPU_DATA[NC 31] GND CPU_DRE Q1 M0_RXD[5] VDD_COR M0_RXD[2] M0_REFCL M0_TXD[6] M0_TXD[1] VDD_COR VDD_COR VDD_IO E K E E CPU_DATA[CPU_DATA[VDD_IO 29] 26] M0_ACTIV VDD_COR VDD_IO E_LED E NC CPU_DATA[CPU_DATA[CPU_DATA[ CPU_DATA[ 30] 21] 15] 14] DEVICE_ID VDD_COR [1] E VDD_IO GND CPU_DATA[CPU_ADDR CPU_DATA[ 25] [23] 6] VDD_COR CPU_DATA[CPU_DATA[ CPU_DATA[ E 18] 17] 16] VDD_COR E W IC TDM_CLKI TDM_FRM VDD_IO _REF O_REF VDD_IO VDD_COR VDD_IO E VDD_IO VDD_COR PLL_SEC E IC_GND GND SYSTEM_C VDD_COR GPIO[9] LK E VDD_IO GPIO[15] Y IC GND VDD_IO IC IC VDD_COR IC E IC PLL_PRI IC IC_GND IC GND AA IC VDD_IO GND VDD_IO VDD_IO IC GND A1VDD_PL IC L1 IC AB VDD_IO IC IC IC GND IC IC IC GPIO[3] GPIO[0] DEVICE_ID VDD_IO [2] CPU_IREQ CPU_DATA[ CPU_DATA[ 1 11] 0] CPU_DATA[IC 2] CPU_DRE Q0 CPU_SDAC IC_VDD_IO K2 CPU_ADDR CPU_ADDR [14] [16] JTAG_TDO CPU_ADDR CPU_ADDR [4] [8] GND GPIO[8] GPIO[14] TEST_MOD JTAG_TRS IC_GND E[1] T VDD_IO GND CPU_ADDR [7] SYSTEM_D SYSTEM_R GPIO[1] EBUG ST GPIO[2] GPIO[7] GPIO[12] TEST_MOD JTAG_TDI IC_GND E[0] GND VDD_IO CPU_ADDR [6] GPIO[4] GPIO[10] GPIO[11] GPIO[13] TEST_MOD IC_GND E[2] GPIO[5] GPIO[6] Figure 3 - ZL50117 ZL50117 Package View and Ball Positions 13 Zarlink Semiconductor Inc. CPU_ADD CPU_ADD CPU_ADDR VDD_IO R[2] R[3] [5] ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Data Sheet ZL50118 ZL50118 Package view from TOP side. Note that ball A1 is non-chamfered corner. 1 2 3 4 A VDD_IO B M1_TXD[2] VDD_IO C M1_TXD[3] GND D M1_RXD[1] M1_RXD[0] M1_RXD[2] E 5 6 7 8 9 10 11 12 14 15 GND CPU_DATA[ 23] GND 16 17 18 M1_RXD[3] M0_GIGABI M1_TXCLK M1_RXER T_LED F NC M1_TXEN M0_TXCLK M0_RXD[7] M0_RXD[6] M0_RXD[4] M0_COL M0_GTX_C M0_TXEN DEVICE_ID CPU_DATA[CPU_DATA[ LK [4] 28] 24] 13 GND M1_TXD[0] M1_TXD[1] M0_CRS M0_RXD[0] M0_RBC1 M0_RBC0 M0_TXER VDD_IO M1_RXCLK M1_COL VDD_IO GND VDD_IO 20 VDD_IO GND VDD_IO CPU_DATA[ M1_LINKU CPU_DATA[CPU_DATA[ VDD_IO 31] P_LED 29] 26] M0_RXD[5] VDD_COR M0_RXD[2] M0_REFCL M0_TXD[6] M0_TXD[1] VDD_COR VDD_COR E K E E 21 22 CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[ CPU_SDAC VDD_IO 19] 12] 9] 8] 7] K1 M0_TXD[5] M0_TXD[3] M0_TXD[2] M1_ACTIV CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[ E_LED 27] 22] 20] 13] M1_TXER M0_RXDV M0_RXD[3] M0_RXD[1] M0_RXCLK M0_TXD[7] M0_TXD[4] M0_TXD[0] M1_RXDV M0_RXER 19 VDD_IO M0_ACTIV VDD_COR E_LED E VDD_IO CPU_TA GND CPU_DRE Q1 VDD_IO CPU_DATA[CPU_ADDR CPU_DATA[ 25] [23] 6] CPU_DATA[CPU_DATA[ CPU_DATA[ CPU_DATA[ 30] 21] 15] 14] M1_CRS DEVICE_ID VDD_COR [1] E VDD_COR CPU_DATA[ CPU_DATA[ CPU_DATA[ E 18] 17] 16] G M_MDIO DEVICE_ID M0_LINKU [0] P_LED VDD_IO VDD_IO CPU_IREQ CPU_DATA[ CPU_DATA[ 1 11] 0] H M_MDC GND NC VDD_COR E J NC NC NC VDD_COR E GND GND GND GND GND GND K NC NC NC VDD_IO GND GND GND GND GND GND GND CPU_DATA[ 2] L GND GND GND GND GND GND GND CPU_CLK GND M NC NC NC VDD_IO GND GND GND GND GND GND GND N NC NC NC VDD_COR E GND GND GND GND GND GND VDD_IO P NC GND VDD_IO VDD_COR E GND GND GND GND GND GND R NC NC TDM_CLKI[ 0] NC GND CPU_ADD CPU_ADDR CPU_ADDR R[11] [13] [20] T NC NC TDM_FRMI _REF VDD_IO VDD_IO VDD_IO CPU_ADDR CPU_ADDR [14] [16] GND CPU_DATA[CPU_DATA[ CPU_DATA[ 10] 1] 4] AUX_CLKO AUX_CLKI VDD_COR E IC VDD_COR CPU_DATA[ CPU_DATA[ CPU_IREQ E 5] 3] 0 IC CPU_SDAC IC_VDD_IO K2 CPU_TS_A CPU_WE LE CPU_ADD R[22] CPU_DRE Q0 CPU_OE CPU_CS CPU_ADDR [19] VDD_COR CPU_ADD CPU_ADDR CPU_ADDR E R[17] [18] [21] U TDM_STI[0] VDD_IO TDM_CLKi S VDD_COR JTAG_TMS CPU_ADDR CPU_ADDR E [15] [12] V TDM_STO[ TDM_CLKO TDM_CLKO TDM_CLKi 0] [0] _REF P DEVICE_ID JTAG_TCK CPU_ADDR CPU_ADDR [3] [10] [9] W IC TDM_CLKI TDM_FRM _REF O_REF VDD_IO VDD_IO VDD_COR E VDD_IO VDD_IO Y IC GND AA IC AB VDD_IO VDD_COR PLL_SEC E VDD_IO IC IC VDD_COR E IC IC PLL_PRI IC VDD_IO GND VDD_IO VDD_IO IC GND A1VDD_PL L1 IC IC IC IC IC GND IC IC IC GPIO[0] GPIO[3] IC_GND GND IC_GND IC SYSTEM_C VDD_COR LK E GND SYSTEM_D SYSTEM_R GPIO[1] EBUG ST GPIO[4] GPIO[5] GPIO[6] GPIO[9] VDD_IO GPIO[15] DEVICE_ID VDD_IO [2] GND GPIO[8] GPIO[14] TEST_MOD JTAG_TRS E[1] T IC_GND VDD_IO GPIO[2] GPIO[7] GPIO[12] TEST_MOD JTAG_TDI E[0] IC_GND GND GPIO[10] GPIO[11] GPIO[13] TEST_MOD IC_GND E[2] Figure 4 - ZL50118 ZL50118 Package View and Ball Positions 14 Zarlink Semiconductor Inc. JTAG_TDO CPU_ADDR CPU_ADDR [4] [8] GND CPU_ADDR [7] VDD_IO CPU_ADDR [6] CPU_ADD CPU_ADD CPU_ADDR VDD_IO R[2] R[3] [5] ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Data Sheet ZL50119 ZL50119 Package view from TOP side. Note that ball A1 is non-chamfered corner. 1 2 3 4 A VDD_IO B M1_TXD[2] VDD_IO C M1_TXD[3] GND D M1_RXD[1] M1_RXD[0] M1_RXD[2] E 5 6 7 8 9 10 11 12 14 15 GND CPU_DATA[ 23] GND 16 17 18 M1_RXD[3] M0_GIGABI M1_TXCLK M1_RXER T_LED F NC M1_TXEN M0_TXCLK M0_RXD[7] M0_RXD[6] M0_RXD[4] M0_COL M0_GTX_C M0_TXEN DEVICE_ID CPU_DATA[CPU_DATA[ LK [4] 28] 24] 13 GND M1_TXD[0] M1_TXD[1] M0_CRS M0_RXD[0] M0_RBC1 M0_RBC0 M0_TXER VDD_IO M1_RXCLK M1_COL VDD_IO GND VDD_IO 20 VDD_IO GND VDD_IO CPU_DATA[ M1_LINKU CPU_DATA[CPU_DATA[ VDD_IO 31] P_LED 29] 26] M0_RXD[5] VDD_COR M0_RXD[2] M0_REFCL M0_TXD[6] M0_TXD[1] VDD_COR VDD_COR E K E E 21 22 CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[ CPU_SDAC VDD_IO 19] 12] 9] 8] 7] K1 M0_TXD[5] M0_TXD[3] M0_TXD[2] M1_ACTIV CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[ E_LED 27] 22] 20] 13] M1_TXER M0_RXDV M0_RXD[3] M0_RXD[1] M0_RXCLK M0_TXD[7] M0_TXD[4] M0_TXD[0] M1_RXDV M0_RXER 19 VDD_IO M0_ACTIV VDD_COR E_LED E VDD_IO CPU_TA GND CPU_DRE Q1 VDD_IO CPU_DATA[CPU_ADDR CPU_DATA[ 25] [23] 6] CPU_DATA[CPU_DATA[ CPU_DATA[ CPU_DATA[ 30] 21] 15] 14] M1_CRS DEVICE_ID VDD_COR [1] E VDD_COR CPU_DATA[ CPU_DATA[ CPU_DATA[ E 18] 17] 16] G M_MDIO DEVICE_ID M0_LINKU [0] P_LED VDD_IO VDD_IO CPU_IREQ CPU_DATA[ CPU_DATA[ 1 11] 0] H M_MDC GND NC VDD_COR E J NC NC NC VDD_COR E GND GND GND GND GND GND K NC NC NC VDD_IO GND GND GND GND GND GND GND CPU_DATA[ 2] L GND GND GND GND GND GND GND CPU_CLK GND M NC NC NC VDD_IO GND GND GND GND GND GND GND N NC NC NC VDD_COR E GND GND GND GND GND GND VDD_IO P NC GND VDD_IO VDD_COR E GND GND GND GND GND GND R NC CPU_DATA[CPU_DATA[ CPU_DATA[ 10] 1] 4] AUX_CLKO AUX_CLKI VDD_COR E IC VDD_COR CPU_DATA[ CPU_DATA[ CPU_IREQ E 5] 3] 0 IC CPU_SDAC IC_VDD_IO K2 CPU_TS_A CPU_WE LE CPU_ADD R[22] CPU_DRE Q0 CPU_OE CPU_CS CPU_ADDR [19] VDD_COR CPU_ADD CPU_ADDR CPU_ADDR E R[17] [18] [21] TDM_STI[1] TDM_CLKI[ TDM_STO[ 0] 1] GND VDD_IO VDD_IO CPU_ADDR CPU_ADDR [14] [16] T TDM_CLKI[ TDM_CLKO TDM_FRMI 1] [1] _REF U TDM_STI[0] VDD_IO TDM_CLKi S VDD_COR JTAG_TMS CPU_ADDR CPU_ADDR E [15] [12] V TDM_STO[ TDM_CLKO TDM_CLKO TDM_CLKi 0] [0] _REF P DEVICE_ID JTAG_TCK CPU_ADDR CPU_ADDR [3] [10] [9] W IC Y IC GND AA IC AB VDD_IO GND TDM_CLKI TDM_FRM _REF O_REF VDD_IO CPU_ADD CPU_ADDR CPU_ADDR R[11] [13] [20] VDD_IO VDD_IO VDD_COR E VDD_IO VDD_IO VDD_COR PLL_SEC E VDD_IO IC IC VDD_COR E IC IC PLL_PRI IC VDD_IO GND VDD_IO VDD_IO IC GND A1VDD_PL L1 IC IC IC IC IC GND IC IC IC GPIO[0] GPIO[3] IC_GND GND IC_GND IC SYSTEM_C VDD_COR LK E GND SYSTEM_D SYSTEM_R GPIO[1] EBUG ST GPIO[4] GPIO[5] GPIO[6] GPIO[9] VDD_IO GPIO[15] DEVICE_ID VDD_IO [2] GND GPIO[8] GPIO[14] TEST_MOD JTAG_TRS E[1] T IC_GND VDD_IO GPIO[2] GPIO[7] GPIO[12] TEST_MOD JTAG_TDI E[0] IC_GND GND GPIO[10] GPIO[11] GPIO[13] TEST_MOD IC_GND E[2] Figure 5 - ZL50119 ZL50119 Package View and Ball Positions 15 Zarlink Semiconductor Inc. JTAG_TDO CPU_ADDR CPU_ADDR [4] [8] GND CPU_ADDR [7] VDD_IO CPU_ADDR [6] CPU_ADD CPU_ADD CPU_ADDR VDD_IO R[2] R[3] [5] ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Data Sheet ZL50120 ZL50120 Package view from TOP side. Note that ball A1 is non-chamfered corner. 1 2 3 4 A VDD_IO B M1_TXD[2] VDD_IO C M1_TXD[3] GND D M1_RXD[1] M1_RXD[0] M1_RXD[2] E 5 6 7 8 9 10 11 12 14 15 GND CPU_DATA[ 23] GND 16 17 18 M1_RXD[3] M0_GIGABI M1_TXCLK M1_RXER T_LED F NC M1_TXEN M0_TXCLK M0_RXD[7] M0_RXD[6] M0_RXD[4] M0_COL M0_GTX_C M0_TXEN DEVICE_ID CPU_DATA[CPU_DATA[ LK [4] 28] 24] 13 GND M1_TXD[0] M1_TXD[1] M0_CRS M0_RXD[0] M0_RBC1 M0_RBC0 M0_TXER VDD_IO M1_RXCLK M1_COL VDD_IO GND VDD_IO 20 VDD_IO GND VDD_IO CPU_DATA[ M1_LINKU CPU_DATA[CPU_DATA[ VDD_IO 31] P_LED 29] 26] M0_RXD[5] VDD_COR M0_RXD[2] M0_REFCL M0_TXD[6] M0_TXD[1] VDD_COR VDD_COR E K E E 21 22 CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[ CPU_SDAC VDD_IO 19] 12] 9] 8] 7] K1 M0_TXD[5] M0_TXD[3] M0_TXD[2] M1_ACTIV CPU_DATA[CPU_DATA[CPU_DATA[CPU_DATA[ E_LED 27] 22] 20] 13] M1_TXER M0_RXDV M0_RXD[3] M0_RXD[1] M0_RXCLK M0_TXD[7] M0_TXD[4] M0_TXD[0] M1_RXDV M0_RXER 19 VDD_IO M0_ACTIV VDD_COR E_LED E VDD_IO CPU_TA GND CPU_DRE Q1 VDD_IO CPU_DATA[CPU_ADDR CPU_DATA[ 25] [23] 6] CPU_DATA[CPU_DATA[ CPU_DATA[ CPU_DATA[ 30] 21] 15] 14] M1_CRS DEVICE_ID VDD_COR [1] E VDD_COR CPU_DATA[ CPU_DATA[ CPU_DATA[ E 18] 17] 16] G M_MDIO DEVICE_ID M0_LINKU [0] P_LED VDD_IO VDD_IO CPU_IREQ CPU_DATA[ CPU_DATA[ 1 11] 0] H M_MDC GND NC VDD_COR E J NC NC NC VDD_COR E GND GND GND GND GND GND K NC NC NC VDD_IO GND GND GND GND GND GND GND CPU_DATA[ 2] L GND GND GND GND GND GND GND CPU_CLK GND CPU_DATA[CPU_DATA[ CPU_DATA[ 10] 1] 4] AUX_CLKO AUX_CLKI VDD_COR E IC VDD_COR CPU_DATA[ CPU_DATA[ CPU_IREQ E 5] 3] 0 IC CPU_DRE Q0 CPU_SDAC IC_VDD_IO K2 M TDM_CLKI[ TDM_STO[ TDM_STI[3] VDD_IO 3] 3] GND GND GND GND GND GND GND N TDM_STO[ TDM_CLKO TDM_STI[2] VDD_COR 2] [3] E GND GND GND GND GND GND VDD_IO P TDM_CLKI[ 2] GND GND GND GND GND GND R TDM_CLKO TDM_STI[1] TDM_CLKI[ TDM_STO[ [2] 0] 1] T TDM_CLKI[ TDM_CLKO TDM_FRMI 1] [1] _REF U TDM_STI[0] VDD_IO TDM_CLKi S VDD_COR JTAG_TMS CPU_ADDR CPU_ADDR E [15] [12] V TDM_STO[ TDM_CLKO TDM_CLKO TDM_CLKi 0] [0] _REF P DEVICE_ID JTAG_TCK CPU_ADDR CPU_ADDR [3] [10] [9] GND W IC Y IC GND AA IC AB VDD_IO VDD_IO GND TDM_CLKI TDM_FRM _REF O_REF VDD_COR E CPU_TS_A CPU_WE LE CPU_ADD R[22] CPU_OE CPU_CS CPU_ADDR [19] VDD_COR CPU_ADD CPU_ADDR CPU_ADDR E R[17] [18] [21] GND VDD_IO VDD_IO VDD_IO VDD_IO VDD_COR E VDD_IO VDD_IO VDD_COR PLL_SEC E VDD_IO IC IC VDD_COR E IC IC PLL_PRI IC VDD_IO GND VDD_IO VDD_IO IC GND A1VDD_PL L1 IC IC IC IC IC GND IC IC IC GPIO[0] GPIO[3] IC_GND GND IC_GND IC SYSTEM_C VDD_COR LK E GND SYSTEM_D SYSTEM_R GPIO[1] EBUG ST GPIO[4] GPIO[5] GPIO[6] Zarlink Semiconductor Inc. VDD_IO CPU_ADDR CPU_ADDR [14] [16] GPIO[9] VDD_IO GPIO[15] DEVICE_ID VDD_IO [2] GND GPIO[8] GPIO[14] TEST_MOD JTAG_TRS E[1] T IC_GND VDD_IO GPIO[2] GPIO[7] GPIO[12] TEST_MOD JTAG_TDI E[0] IC_GND GND GPIO[10] GPIO[11] GPIO[13] TEST_MOD IC_GND E[2] Figure 6 - ZL50120 ZL50120 Package View and Ball Positions 16 CPU_ADD CPU_ADDR CPU_ADDR R[11] [13] [20] JTAG_TDO CPU_ADDR CPU_ADDR [4] [8] GND CPU_ADDR [7] VDD_IO CPU_ADDR [6] CPU_ADD CPU_ADD CPU_ADDR VDD_IO R[2] R[3] [5] ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Ball # ZL50115 ZL50115 Signal Name ZL50116 ZL50116 Signal Name ZL50117 ZL50117 Signal Name ZL50118 ZL50118 Signal Name ZL50119 ZL50119 Signal Name Data Sheet ZL50120 ZL50120 Signal Name Variant A1 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All A10 DEVICE_ID[4] DEVICE_ID[4] DEVICE_ID[4] DEVICE_ID[4] DEVICE_ID[4] DEVICE_ID[4] All A11 CPU_DATA[28] CPU_DATA[28] CPU_DATA[28] CPU_DATA[28] CPU_DATA[28] CPU_DATA[28] All A12 CPU_DATA[24] CPU_DATA[24] CPU_DATA[24] CPU_DATA[24] CPU_DATA[24] CPU_DATA[24] All A13 GND GND GND GND GND GND All A14 CPU_DATA[23] CPU_DATA[23] CPU_DATA[23] CPU_DATA[23] CPU_DATA[23] CPU_DATA[23] All A15 GND GND GND GND GND GND All A16 CPU_DATA[19] CPU_DATA[19] CPU_DATA[19] CPU_DATA[19] CPU_DATA[19] CPU_DATA[19] All A17 CPU_DATA[12] CPU_DATA[12] CPU_DATA[12] CPU_DATA[12] CPU_DATA[12] CPU_DATA[12] All A18 CPU_DATA[9] CPU_DATA[9] CPU_DATA[9] CPU_DATA[9] CPU_DATA[9] CPU_DATA[9] All A19 CPU_DATA[8] CPU_DATA[8] CPU_DATA[8] CPU_DATA[8] CPU_DATA[8] CPU_DATA[8] All A20 CPU_DATA[7] CPU_DATA[7] CPU_DATA[7] CPU_DATA[7] CPU_DATA[7] CPU_DATA[7] All A21 CPU_SDACK1 CPU_SDACK1 CPU_SDACK1 CPU_SDACK1 CPU_SDACK1 CPU_SDACK1 All A22 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All A2 NC NC NC M1_TXEN M1_TXEN M1_TXEN ZL50118/19/20 ZL50118/19/20 A3 M0_TXCLK M0_TXCLK M0_TXCLK M0_TXCLK M0_TXCLK M0_TXCLK All A4 M0_RXD[7] M0_RXD[7] M0_RXD[7] M0_RXD[7] M0_RXD[7] M0_RXD[7] All A5 M0_RXD[6] M0_RXD[6] M0_RXD[6] M0_RXD[6] M0_RXD[6] M0_RXD[6] All A6 M0_RXD[4] M0_RXD[4] M0_RXD[4] M0_RXD[4] M0_RXD[4] M0_RXD[4] All A7 M0_COL M0_COL M0_COL M0_COL M0_COL M0_COL All A8 M0_GTX_CLK M0_GTX_CLK M0_GTX_CLK M0_GTX_CLK M0_GTX_CLK M0_GTX_CLK All A9 M0_TXEN M0_TXEN M0_TXEN M0_TXEN M0_TXEN M0_TXEN All B1 NC NC NC M1_TXD[2] M1_TXD[2] M1_TXD[2] ZL50118/19/20 ZL50118/19/20 B10 M0_TXER M0_TXER M0_TXER M0_TXER M0_TXER M0_TXER All B11 GND GND GND GND GND GND All B12 M0_TXD[5] M0_TXD[5] M0_TXD[5] M0_TXD[5] M0_TXD[5] M0_TXD[5] All B13 M0_TXD[3] M0_TXD[3] M0_TXD[3] M0_TXD[3] M0_TXD[3] M0_TXD[3] All B14 M0_TXD[2] M0_TXD[2] M0_TXD[2] M0_TXD[2] M0_TXD[2] M0_TXD[2] All B15 NC NC NC M1_ACTIVE_LED M1_ACTIVE_LED M1_ACTIVE_LED ZL50118/19/20 ZL50118/19/20 B16 CPU_DATA[27] CPU_DATA[27] CPU_DATA[27] CPU_DATA[27] CPU_DATA[27] CPU_DATA[27] All B17 CPU_DATA[22] CPU_DATA[22] CPU_DATA[22] CPU_DATA[22] CPU_DATA[22] CPU_DATA[22] All B18 CPU_DATA[20] CPU_DATA[20] CPU_DATA[20] CPU_DATA[20] CPU_DATA[20] CPU_DATA[20] All B19 CPU_DATA[13] CPU_DATA[13] CPU_DATA[13] CPU_DATA[13] CPU_DATA[13] CPU_DATA[13] All B20 GND GND GND GND GND GND All B21 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All B22 CPU_TA CPU_TA CPU_TA CPU_TA CPU_TA CPU_TA All B2 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All B3 GND GND GND GND GND GND All B4 NC NC NC M1_TXD[0] M1_TXD[0] M1_TXD[0] ZL50118/19/20 ZL50118/19/20 B5 NC NC NC M1_TXD[1] M1_TXD[1] M1_TXD[1] ZL50118/19/20 ZL50118/19/20 B6 M0_CRS M0_CRS M0_CRS M0_CRS M0_CRS M0_CRS All B7 M0_RXD[0] M0_RXD[0] M0_RXD[0] M0_RXD[0] M0_RXD[0] M0_RXD[0] All B8 M0_RBC1 M0_RBC1 M0_RBC1 M0_RBC1 M0_RBC1 M0_RBC1 All Table 1 - ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Ball Signal Assignment 17 Zarlink Semiconductor Inc. ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Ball # ZL50115 ZL50115 Signal Name ZL50116 ZL50116 Signal Name ZL50117 ZL50117 Signal Name ZL50118 ZL50118 Signal Name ZL50119 ZL50119 Signal Name Data Sheet ZL50120 ZL50120 Signal Name Variant B9 M0_RBC0 M0_RBC0 M0_RBC0 M0_RBC0 M0_RBC0 M0_RBC0 All C1 NC NC NC M1_TXD[3] M1_TXD[3] M1_TXD[3] ZL50118/19/20 ZL50118/19/20 C10 M0_RXCLK M0_RXCLK M0_RXCLK M0_RXCLK M0_RXCLK M0_RXCLK All C11 M0_TXD[7] M0_TXD[7] M0_TXD[7] M0_TXD[7] M0_TXD[7] M0_TXD[7] All C12 M0_TXD[4] M0_TXD[4] M0_TXD[4] M0_TXD[4] M0_TXD[4] M0_TXD[4] All C13 M0_TXD[0] M0_TXD[0] M0_TXD[0] M0_TXD[0] M0_TXD[0] M0_TXD[0] All C14 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All C15 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All C16 CPU_DATA[31] CPU_DATA[31] CPU_DATA[31] CPU_DATA[31] CPU_DATA[31] CPU_DATA[31] All C17 NC NC NC M1_LINKUP_LED M1_LINKUP_LED M1_LINKUP_LED ZL50118/19/20 ZL50118/19/20 C18 CPU_DATA[29] CPU_DATA[29] CPU_DATA[29] CPU_DATA[29] CPU_DATA[29] CPU_DATA[29] All C19 CPU_DATA[26] CPU_DATA[26] CPU_DATA[26] CPU_DATA[26] CPU_DATA[26] CPU_DATA[26] All C20 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All C21 GND GND GND GND GND GND All C22 CPU_DREQ1 CPU_DREQ1 CPU_DREQ1 CPU_DREQ1 CPU_DREQ1 CPU_DREQ1 All C2 GND GND GND GND GND GND All C3 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All C4 NC NC NC M1_RXCLK M1_RXCLK M1_RXCLK ZL50118/19/20 ZL50118/19/20 C5 NC NC NC M1_COL M1_COL M1_COL ZL50118/19/20 ZL50118/19/20 C6 NC NC NC M1_TXER M1_TXER M1_TXER ZL50118/19/20 ZL50118/19/20 C7 M0_RXDV M0_RXDV M0_RXDV M0_RXDV M0_RXDV M0_RXDV All C8 M0_RXD[3] M0_RXD[3] M0_RXD[3] M0_RXD[3] M0_RXD[3] M0_RXD[3] All C9 M0_RXD[1] M0_RXD[1] M0_RXD[1] M0_RXD[1] M0_RXD[1] M0_RXD[1] All D1 NC NC NC M1_RXD[1] M1_RXD[1] M1_RXD[1] ZL50118/19/20 ZL50118/19/20 D10 M0_RXD[2] M0_RXD[2] M0_RXD[2] M0_RXD[2] M0_RXD[2] M0_RXD[2] All D11 M0_REFCLK M0_REFCLK M0_REFCLK M0_REFCLK M0_REFCLK M0_REFCLK All D12 M0_TXD[6] M0_TXD[6] M0_TXD[6] M0_TXD[6] M0_TXD[6] M0_TXD[6] All D13 M0_TXD[1] M0_TXD[1] M0_TXD[1] M0_TXD[1] M0_TXD[1] M0_TXD[1] All D14 VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE All D15 VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE All D16 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All D17 M0_ACTIVE_LED M0_ACTIVE_LED M0_ACTIVE_LED M0_ACTIVE_LED M0_ACTIVE_LED M0_ACTIVE_LED All D18 VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE All D19 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All All D20 CPU_DATA[25] CPU_DATA[25] CPU_DATA[25] CPU_DATA[25] CPU_DATA[25] CPU_DATA[25] D21 CPU_ADDR[23] CPU_ADDR[23] CPU_ADDR[23] CPU_ADDR[23] CPU_ADDR[23] CPU_ADDR[23] All D22 CPU_DATA[6] CPU_DATA[6] CPU_DATA[6] CPU_DATA[6] CPU_DATA[6] CPU_DATA[6] All D2 NC NC NC M1_RXD[0] M1_RXD[0] M1_RXD[0] ZL50118/19/20 ZL50118/19/20 D3 NC NC NC M1_RXD[2] M1_RXD[2] M1_RXD[2] ZL50118/19/20 ZL50118/19/20 D4 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All D5 NC NC NC M1_RXDV M1_RXDV M1_RXDV ZL50118/19/20 ZL50118/19/20 D6 M0_RXER M0_RXER M0_RXER M0_RXER M0_RXER M0_RXER All D7 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All Table 1 - ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Ball Signal Assignment (continued) 18 Zarlink Semiconductor Inc. ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Ball # ZL50115 ZL50115 Signal Name ZL50116 ZL50116 Signal Name ZL50117 ZL50117 Signal Name ZL50118 ZL50118 Signal Name ZL50119 ZL50119 Signal Name Data Sheet ZL50120 ZL50120 Signal Name Variant D8 M0_RXD[5] M0_RXD[5] M0_RXD[5] M0_RXD[5] M0_RXD[5] M0_RXD[5] All D9 VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE All E1 NC NC NC M1_RXD[3] M1_RXD[3] M1_RXD[3] ZL50118/19/20 ZL50118/19/20 E19 CPU_DATA[30] CPU_DATA[30] CPU_DATA[30] CPU_DATA[30] CPU_DATA[30] CPU_DATA[30] All E20 CPU_DATA[21] CPU_DATA[21] CPU_DATA[21] CPU_DATA[21] CPU_DATA[21] CPU_DATA[21] All E21 CPU_DATA[15] CPU_DATA[15] CPU_DATA[15] CPU_DATA[15] CPU_DATA[15] CPU_DATA[15] All E22 CPU_DATA[14] CPU_DATA[14] CPU_DATA[14] CPU_DATA[14] CPU_DATA[14] CPU_DATA[14] All E2 M0_GIGABIT_LED M0_GIGABIT_LED M0_GIGABIT_LED M0_GIGABIT_LED M0_GIGABIT_LED M0_GIGABIT_LED All E3 NC NC NC M1_TXCLK M1_TXCLK M1_TXCLK ZL50118/19/20 ZL50118/19/20 E4 NC NC NC M1_RXER M1_RXER M1_RXER ZL50118/19/20 ZL50118/19/20 F1 NC NC NC NC NC NC All F19 VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE All F20 CPU_DATA[18] CPU_DATA[18] CPU_DATA[18] CPU_DATA[18] CPU_DATA[18] CPU_DATA[18] All F21 CPU_DATA[17] CPU_DATA[17] CPU_DATA[17] CPU_DATA[17] CPU_DATA[17] CPU_DATA[17] All F22 CPU_DATA[16] CPU_DATA[16] CPU_DATA[16] CPU_DATA[16] CPU_DATA[16] CPU_DATA[16] All F2 NC NC NC M1_CRS M1_CRS M1_CRS ZL50118/19/20 ZL50118/19/20 F3 DEVICE_ID[1] DEVICE_ID[1] DEVICE_ID[1] DEVICE_ID[1] DEVICE_ID[1] DEVICE_ID[1] All F4 VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE All G1 M_MDIO M_MDIO M_MDIO M_MDIO M_MDIO M_MDIO All G19 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All G20 CPU_IREQ1 CPU_IREQ1 CPU_IREQ1 CPU_IREQ1 CPU_IREQ1 CPU_IREQ1 All G21 CPU_DATA[11] CPU_DATA[11] CPU_DATA[11] CPU_DATA[11] CPU_DATA[11] CPU_DATA[11] All G22 CPU_DATA[0] CPU_DATA[0] CPU_DATA[0] CPU_DATA[0] CPU_DATA[0] CPU_DATA[0] All G2 DEVICE_ID[0] DEVICE_ID[0] DEVICE_ID[0] DEVICE_ID[0] DEVICE_ID[0] DEVICE_ID[0] All G3 M0_LINKUP_LED M0_LINKUP_LED M0_LINKUP_LED M0_LINKUP_LED M0_LINKUP_LED M0_LINKUP_LED All G4 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All H1 M_MDC M_MDC M_MDC M_MDC M_MDC M_MDC All H19 CPU_DATA[10] CPU_DATA[10] CPU_DATA[10] CPU_DATA[10] CPU_DATA[10] CPU_DATA[10] All H20 CPU_DATA[1] CPU_DATA[1] CPU_DATA[1] CPU_DATA[1] CPU_DATA[1] CPU_DATA[1] All H21 CPU_DATA[4] CPU_DATA[4] CPU_DATA[4] CPU_DATA[4] CPU_DATA[4] CPU_DATA[4] All H22 IC IC IC IC IC IC All H2 GND GND GND GND GND GND All H3 NC NC NC NC NC NC All H4 VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE All All J1 NC NC NC NC NC NC J10 GND GND GND GND GND GND All J11 GND GND GND GND GND GND All J12 GND GND GND GND GND GND All J13 GND GND GND GND GND GND All J14 GND GND GND GND GND GND All J19 VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE All J20 CPU_DATA[5] CPU_DATA[5] CPU_DATA[5] CPU_DATA[5] CPU_DATA[5] CPU_DATA[5] All J21 CPU_DATA[3] CPU_DATA[3] CPU_DATA[3] CPU_DATA[3] CPU_DATA[3] CPU_DATA[3] All Table 1 - ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Ball Signal Assignment (continued) 19 Zarlink Semiconductor Inc. ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Ball # ZL50115 ZL50115 Signal Name ZL50116 ZL50116 Signal Name ZL50117 ZL50117 Signal Name ZL50118 ZL50118 Signal Name ZL50119 ZL50119 Signal Name Data Sheet ZL50120 ZL50120 Signal Name Variant J22 CPU_IREQ0 CPU_IREQ0 CPU_IREQ0 CPU_IREQ0 CPU_IREQ0 CPU_IREQ0 All J2 NC NC NC NC NC NC All J3 NC NC NC NC NC NC All J4 VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE All J9 GND GND GND GND GND GND All K1 NC NC NC NC NC NC All K10 GND GND GND GND GND GND All K11 GND GND GND GND GND GND All K12 GND GND GND GND GND GND All K13 GND GND GND GND GND GND All K14 GND GND GND GND GND GND All K19 GND GND GND GND GND GND All K20 CPU_DATA[2] CPU_DATA[2] CPU_DATA[2] CPU_DATA[2] CPU_DATA[2] CPU_DATA[2] All K21 IC IC IC IC IC IC All K22 CPU_DREQ0 CPU_DREQ0 CPU_DREQ0 CPU_DREQ0 CPU_DREQ0 CPU_DREQ0 All K2 NC NC NC NC NC NC All K3 NC NC NC NC NC NC All K4 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All K9 GND GND GND GND GND GND All L1 GND GND GND GND GND GND All L10 GND GND GND GND GND GND All L11 GND GND GND GND GND GND All L12 GND GND GND GND GND GND All L13 GND GND GND GND GND GND All L14 GND GND GND GND GND GND All L19 CPU_CLK CPU_CLK CPU_CLK CPU_CLK CPU_CLK CPU_CLK All L20 GND GND GND GND GND GND All L21 CPU_SDACK2 CPU_SDACK2 CPU_SDACK2 CPU_SDACK2 CPU_SDACK2 CPU_SDACK2 All L22 IC_VDD_IO IC_VDD_IO IC_VDD_IO IC_VDD_IO IC_VDD_IO IC_VDD_IO All L2 AUX_CLKO AUX_CLKO AUX_CLKO AUX_CLKO AUX_CLKO AUX_CLKO All L3 AUX_CLKI AUX_CLKI AUX_CLKI AUX_CLKI AUX_CLKI AUX_CLKI All L4 VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE All L9 GND GND GND GND GND GND All M1 NC NC TDM_CLKI[3] NC NC TDM_CLKI[3] ZL50117/20 ZL50117/20 M10 GND GND GND GND GND GND All M11 GND GND GND GND GND GND All M12 GND GND GND GND GND GND All M13 GND GND GND GND GND GND All M14 GND GND GND GND GND GND All M19 GND GND GND GND GND GND All M20 CPU_TS_ALE CPU_TS_ALE CPU_TS_ALE CPU_TS_ALE CPU_TS_ALE CPU_TS_ALE All M21 CPU_WE CPU_WE CPU_WE CPU_WE CPU_WE CPU_WE All M22 CPU_OE CPU_OE CPU_OE CPU_OE CPU_OE CPU_OE All Table 1 - ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Ball Signal Assignment (continued) 20 Zarlink Semiconductor Inc. ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Ball # ZL50115 ZL50115 Signal Name ZL50116 ZL50116 Signal Name ZL50117 ZL50117 Signal Name ZL50118 ZL50118 Signal Name ZL50119 ZL50119 Signal Name Data Sheet ZL50120 ZL50120 Signal Name Variant M2 NC NC TDM_STO[3] NC NC TDM_STO[3] ZL50117/20 ZL50117/20 M3 NC NC TDM_STI[3] NC NC TDM_STI[3] ZL50117/20 ZL50117/20 M4 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All M9 GND GND GND GND GND GND All ZL50117/20 ZL50117/20 N1 NC NC TDM_STO[2] NC NC TDM_STO[2] N10 GND GND GND GND GND GND All N11 GND GND GND GND GND GND All N12 GND GND GND GND GND GND All N13 GND GND GND GND GND GND All N14 GND GND GND GND GND GND All N19 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All N20 CPU_ADDR[22] CPU_ADDR[22] CPU_ADDR[22] CPU_ADDR[22] CPU_ADDR[22] CPU_ADDR[22] All N21 CPU_CS CPU_CS CPU_CS CPU_CS CPU_CS CPU_CS All N22 CPU_ADDR[19] CPU_ADDR[19] CPU_ADDR[19] CPU_ADDR[19] CPU_ADDR[19] CPU_ADDR[19] All N2 NC NC TDM_CLKO[3] NC NC TDM_CLKO[3] ZL50117/20 ZL50117/20 N3 NC NC TDM_STI[2] NC NC TDM_STI[2] ZL50117/20 ZL50117/20 N4 VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE All N9 GND GND GND GND GND GND All P1 NC NC TDM_CLKI[2] NC NC TDM_CLKI[2] ZL50117/20 ZL50117/20 P10 GND GND GND GND GND GND All P11 GND GND GND GND GND GND All P12 GND GND GND GND GND GND All P13 GND GND GND GND GND GND All P14 GND GND GND GND GND GND All P19 VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE All P20 CPU_ADDR[17] CPU_ADDR[17] CPU_ADDR[17] CPU_ADDR[17] CPU_ADDR[17] CPU_ADDR[17] All P21 CPU_ADDR[18] CPU_ADDR[18] CPU_ADDR[18] CPU_ADDR[18] CPU_ADDR[18] CPU_ADDR[18] All P22 CPU_ADDR[21] CPU_ADDR[21] CPU_ADDR[21] CPU_ADDR[21] CPU_ADDR[21] CPU_ADDR[21] All P2 GND GND GND GND GND GND All P3 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All P4 VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE All P9 GND GND GND GND GND GND All R1 NC NC TDM_CLKO[2] NC NC TDM_CLKO[2] ZL50117/20 ZL50117/20 R19 GND GND GND GND GND GND All R20 CPU_ADDR[11] CPU_ADDR[11] CPU_ADDR[11] CPU_ADDR[11] CPU_ADDR[11] CPU_ADDR[11] All R21 CPU_ADDR[13] CPU_ADDR[13] CPU_ADDR[13] CPU_ADDR[13] CPU_ADDR[13] CPU_ADDR[13] All R22 CPU_ADDR[20] CPU_ADDR[20] CPU_ADDR[20] CPU_ADDR[20] CPU_ADDR[20] CPU_ADDR[20] All R2 NC TDM_STI[1] TDM_STI[1] NC TDM_STI[1] TDM_STI[1] ZL50116/17/19/20 ZL50116/17/19/20 R3 TDM_CLKI[0] TDM_CLKI[0] TDM_CLKI[0] TDM_CLKI[0] TDM_CLKI[0] TDM_CLKI[0] All R4 NC TDM_STO[1] TDM_STO[1] NC TDM_STO[1] TDM_STO[1] ZL50116/17/19/20 ZL50116/17/19/20 T1 NC TDM_CLKI[1] TDM_CLKI[1] NC TDM_CLKI[1] TDM_CLKI[1] ZL50116/17/19/20 ZL50116/17/19/20 T19 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All T20 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All Table 1 - ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Ball Signal Assignment (continued) 21 Zarlink Semiconductor Inc. ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Ball # ZL50115 ZL50115 Signal Name ZL50116 ZL50116 Signal Name ZL50117 ZL50117 Signal Name ZL50118 ZL50118 Signal Name ZL50119 ZL50119 Signal Name Data Sheet ZL50120 ZL50120 Signal Name Variant T21 CPU_ADDR[14] CPU_ADDR[14] CPU_ADDR[14] CPU_ADDR[14] CPU_ADDR[14] CPU_ADDR[14] All T22 CPU_ADDR[16] CPU_ADDR[16] CPU_ADDR[16] CPU_ADDR[16] CPU_ADDR[16] CPU_ADDR[16] All T2 NC TDM_CLKO[1] TDM_CLKO[1] NC TDM_CLKO[1] TDM_CLKO[1] ZL50116/17/19/20 ZL50116/17/19/20 T3 TDM_FRMI_REF TDM_FRMI_REF TDM_FRMI_REF TDM_FRMI_REF TDM_FRMI_REF TDM_FRMI_REF All T4 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All U1 TDM_STI[0] TDM_STI[0] TDM_STI[0] TDM_STI[0] TDM_STI[0] TDM_STI[0] All U19 VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE All U20 JTAG_TMS JTAG_TMS JTAG_TMS JTAG_TMS JTAG_TMS JTAG_TMS All U21 CPU_ADDR[15] CPU_ADDR[15] CPU_ADDR[15] CPU_ADDR[15] CPU_ADDR[15] CPU_ADDR[15] All U22 CPU_ADDR[12] CPU_ADDR[12] CPU_ADDR[12] CPU_ADDR[12] CPU_ADDR[12] CPU_ADDR[12] All U2 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All U3 GND GND GND GND GND GND All U4 TDM_CLKiS TDM_CLKiS TDM_CLKiS TDM_CLKiS TDM_CLKiS TDM_CLKiS All V1 TDM_STO[0] TDM_STO[0] TDM_STO[0] TDM_STO[0] TDM_STO[0] TDM_STO[0] All V19 DEVICE_ID[3] DEVICE_ID[3] DEVICE_ID[3] DEVICE_ID[3] DEVICE_ID[3] DEVICE_ID[3] All V20 JTAG_TCK JTAG_TCK JTAG_TCK JTAG_TCK JTAG_TCK JTAG_TCK All V21 CPU_ADDR[10] CPU_ADDR[10] CPU_ADDR[10] CPU_ADDR[10] CPU_ADDR[10] CPU_ADDR[10] All V22 CPU_ADDR[9] CPU_ADDR[9] CPU_ADDR[9] CPU_ADDR[9] CPU_ADDR[9] CPU_ADDR[9] All V2 TDM_CLKO[0] TDM_CLKO[0] TDM_CLKO[0] TDM_CLKO[0] TDM_CLKO[0] TDM_CLKO[0] All V3 TDM_CLKO_REF TDM_CLKO_REF TDM_CLKO_REF TDM_CLKO_REF TDM_CLKO_REF TDM_CLKO_REF All V4 TDM_CLKiP TDM_CLKiP TDM_CLKiP TDM_CLKiP TDM_CLKiP TDM_CLKiP All W1 IC IC IC IC IC IC All W10 PLL_SEC PLL_SEC PLL_SEC PLL_SEC PLL_SEC PLL_SEC All W11 IC_GND IC_GND IC_GND IC_GND IC_GND IC_GND All W12 GND GND GND GND GND GND All W13 SYSTEM_CLK SYSTEM_CLK SYSTEM_CLK SYSTEM_CLK SYSTEM_CLK SYSTEM_CLK All W14 VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE All W15 GPIO[9] GPIO[9] GPIO[9] GPIO[9] GPIO[9] GPIO[9] All W16 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All W17 GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] GPIO[15] All W18 DEVICE_ID[2] DEVICE_ID[2] DEVICE_ID[2] DEVICE_ID[2] DEVICE_ID[2] DEVICE_ID[2] All W19 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All W20 JTAG_TDO JTAG_TDO JTAG_TDO JTAG_TDO JTAG_TDO JTAG_TDO All W21 CPU_ADDR[4] CPU_ADDR[4] CPU_ADDR[4] CPU_ADDR[4] CPU_ADDR[4] CPU_ADDR[4] All W22 CPU_ADDR[8] CPU_ADDR[8] CPU_ADDR[8] CPU_ADDR[8] CPU_ADDR[8] CPU_ADDR[8] All W2 TDM_CLKI_REF TDM_CLKI_REF TDM_CLKI_REF TDM_CLKI_REF TDM_CLKI_REF TDM_CLKI_REF All W3 TDM_FRMO_REF TDM_FRMO_REF TDM_FRMO_REF TDM_FRMO_REF TDM_FRMO_REF TDM_FRMO_REF All W4 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All W5 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All W6 VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE All W7 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All W8 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All W9 VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE All Table 1 - ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Ball Signal Assignment (continued) 22 Zarlink Semiconductor Inc. ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Ball # ZL50115 ZL50115 Signal Name ZL50116 ZL50116 Signal Name ZL50117 ZL50117 Signal Name ZL50118 ZL50118 Signal Name ZL50119 ZL50119 Signal Name Data Sheet ZL50120 ZL50120 Signal Name Variant Y1 IC IC IC IC IC IC All Y10 IC IC IC IC IC IC All Y11 IC_GND IC_GND IC_GND IC_GND IC_GND IC_GND All Y12 IC IC IC IC IC IC All Y13 GND GND GND GND GND GND All Y14 GND GND GND GND GND GND All Y15 GPIO[8] GPIO[8] GPIO[8] GPIO[8] GPIO[8] GPIO[8] All Y16 GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] GPIO[14] All Y17 TEST_MODE[1] TEST_MODE[1] TEST_MODE[1] TEST_MODE[1] TEST_MODE[1] TEST_MODE[1] All Y18 JTAG_TRST JTAG_TRST JTAG_TRST JTAG_TRST JTAG_TRST JTAG_TRST All Y19 IC_GND IC_GND IC_GND IC_GND IC_GND IC_GND All Y20 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All Y21 GND GND GND GND GND GND All Y22 CPU_ADDR[7] CPU_ADDR[7] CPU_ADDR[7] CPU_ADDR[7] CPU_ADDR[7] CPU_ADDR[7] All Y2 GND GND GND GND GND GND All Y3 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All Y4 IC IC IC IC IC IC All Y5 IC IC IC IC IC IC All Y6 VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE All Y7 IC IC IC IC IC IC All Y8 IC IC IC IC IC IC All Y9 PLL_PRI PLL_PRI PLL_PRI PLL_PRI PLL_PRI PLL_PRI All AA1 IC IC IC IC IC IC All AA10 IC IC IC IC IC IC All AA11 SYSTEM_DEBUG SYSTEM_DEBUG SYSTEM_DEBUG SYSTEM_DEBUG SYSTEM_DEBUG SYSTEM_DEBUG All AA12 SYSTEM_RST SYSTEM_RST SYSTEM_RST SYSTEM_RST SYSTEM_RST SYSTEM_RST All AA13 GPIO[1] GPIO[1] GPIO[1] GPIO[1] GPIO[1] GPIO[1] All AA14 GPIO[2] GPIO[2] GPIO[2] GPIO[2] GPIO[2] GPIO[2] All AA15 GPIO[7] GPIO[7] GPIO[7] GPIO[7] GPIO[7] GPIO[7] All AA16 GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] All AA17 TEST_MODE[0] TEST_MODE[0] TEST_MODE[0] TEST_MODE[0] TEST_MODE[0] TEST_MODE[0] All AA18 JTAG_TDI JTAG_TDI JTAG_TDI JTAG_TDI JTAG_TDI JTAG_TDI All AA19 IC_GND IC_GND IC_GND IC_GND IC_GND IC_GND All AA20 GND GND GND GND GND GND All AA21 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All AA22 CPU_ADDR[6] CPU_ADDR[6] CPU_ADDR[6] CPU_ADDR[6] CPU_ADDR[6] CPU_ADDR[6] All AA2 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All AA3 GND GND GND GND GND GND All AA4 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All AA5 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All AA6 IC IC IC IC IC IC All AA7 GND GND GND GND GND GND All AA8 A1VDD_PLL1 A1VDD_PLL1 A1VDD_PLL1 A1VDD_PLL1 A1VDD_PLL1 A1VDD_PLL1 All Table 1 - ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Ball Signal Assignment (continued) 23 Zarlink Semiconductor Inc. ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Ball # ZL50115 ZL50115 Signal Name ZL50116 ZL50116 Signal Name ZL50117 ZL50117 Signal Name ZL50118 ZL50118 Signal Name ZL50119 ZL50119 Signal Name Data Sheet ZL50120 ZL50120 Signal Name Variant AA9 IC IC IC IC IC IC All AB1 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All AB10 GPIO[3] GPIO[3] GPIO[3] GPIO[3] GPIO[3] GPIO[3] All AB11 GPIO[4] GPIO[4] GPIO[4] GPIO[4] GPIO[4] GPIO[4] All AB12 GPIO[5] GPIO[5] GPIO[5] GPIO[5] GPIO[5] GPIO[5] All AB13 GPIO[6] GPIO[6] GPIO[6] GPIO[6] GPIO[6] GPIO[6] All AB14 GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] All AB15 GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] All AB16 GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] GPIO[13] All AB17 TEST_MODE[2] TEST_MODE[2] TEST_MODE[2] TEST_MODE[2] TEST_MODE[2] TEST_MODE[2] All AB18 IC_GND IC_GND IC_GND IC_GND IC_GND IC_GND All AB19 CPU_ADDR[2] CPU_ADDR[2] CPU_ADDR[2] CPU_ADDR[2] CPU_ADDR[2] CPU_ADDR[2] All AB20 CPU_ADDR[3] CPU_ADDR[3] CPU_ADDR[3] CPU_ADDR[3] CPU_ADDR[3] CPU_ADDR[3] All AB21 CPU_ADDR[5] CPU_ADDR[5] CPU_ADDR[5] CPU_ADDR[5] CPU_ADDR[5] CPU_ADDR[5] All AB22 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO All AB2 IC IC IC IC IC IC All AB3 IC IC IC IC IC IC All AB4 IC IC IC IC IC IC All AB5 GND GND GND GND GND GND All AB6 IC IC IC IC IC IC All AB7 IC IC IC IC IC IC All AB8 IC IC IC IC IC IC All AB9 GPIO[0] GPIO[0] GPIO[0] GPIO[0] GPIO[0] GPIO[0] All Table 1 - ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Ball Signal Assignment (continued) NC - Not Connected - leave open circuit. IC - Internally Connected - leave open circuit. IC_GND - Internally Connected - tie to ground IC_VDD_IO - Internally Connected - tie to VDD_IO 24 Zarlink Semiconductor Inc. ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 4.0 Data Sheet External Interface Description The following key applies to all tables: I O Output D Internal 100 k pull-down resistor present U Internal 100 k pull-up resistor present T 4.1 Input Tri-state Output TDM Interface All TDM Interface signals are 5 V tolerant. All TDM Interface outputs are high impedance while System Reset is LOW. All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be safely left unconnected if not used. 4.1.1 TDM stream connections There are three interfaces possible among the ZL5011x. The ZL50117/20 ZL50117/20 supports four TDM ports [3:0] at 2 Mbps, or one TDM port [0] at 8 Mbps or one unstructured TDM port [0] for J2/E3/T3/STS-1. The ZL50116/19 ZL50116/19 supports two TDM ports [1:0] at 2 Mbps, or one TDM port [0] at 8 Mbps (up to 64 DS0). The ZL50115/18 ZL50115/18 supports one TDM port [0] at 2 Mbps, or one TDM port [0] at 8 Mbps (up to 32 DS0) Signal I/O TDM_STi[3:0] ID Package Balls [3] [2] [1] [0] M3 N3 R2 U1 Description TDM port serial data input streams. For different standards these pins are given different identities: ST-BUS: TDM_STi[3:0] H.110: TDM_D[3:0] H-MVIP: TDM_HDS[3:0] Triggered on rising edge or falling edge depending on standard. At 8.192 Mbps only stream [0] is used. Stream [0] is used for unstructured J2, T3/E3 or STS-1 on the ZL50117/20 ZL50117/20. Table 2 - TDM Interface Stream Pin Definition 25 Zarlink Semiconductor Inc. ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Signal I/O Package Balls Data Sheet Description TDM_STo[3:0] OT [3] [2] [1] [0] M2 N1 R4 V1 TDM port serial data output streams. For different standards these pins are given different identities: ST-BUS: TDM_STo[3:0] H.110: TDM_D[3:0] H-MVIP: TDM_HDS[3:0] Triggered on rising edge or falling edge depending on standard. At 8.192 Mbps only stream [0] is used. Stream [0] is used for unstructured J2, T3/E3 or STS-1 on the ZL50117/20 ZL50117/20. TDM_CLKi[3:0] ID [3] [2] [1] [0] M1 P1 T1 R3 TDM port clock inputs programmable as active high or low. Can accept frequencies of 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 6.312 MHz or 16.384 MHz depending on standard used. At 8.192 Mbps only stream [0] is used. Stream [0] is used for unstructured J2, T3/E3 or STS-1 on the ZL50117/20 ZL50117/20. TDM_CLKo[3:0] OT [3] [2] [1] [0] N2 R1 T2 V2 TDM port clock outputs. Will generate 1.544 MHz, 2.048 MHz, 4.096 MHz, 6.312 MHz, 8.192 MHz or 16.384 MHz depending on standard used. At 8.192 Mbps only stream [0] is used. Stream [0] is used for unstructured J2, T3/E3 or STS-1 on the ZL50117/20 ZL50117/20. Table 2 - TDM Interface Stream Pin Definition Note: Speed modes: 2.048 Mbps - 32 channels per stream. 8.192 Mbps - 128 channels per stream. J2 - 98 channels per stream E3 - 537 channels per stream T3 - 699 channels per stream Note: All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be safely left unconnected if not used. 26 Zarlink Semiconductor Inc. ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 4.1.2 Data Sheet TDM Signals common to ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Signal I/O Package Balls Description TDM_CLKi_REF ID W2 TDM port reference clock input for backplane operation TDM_CLKo_REF O V3 TDM port reference clock output for backplane operation TDM_FRMi_REF ID T3 TDM port reference frame input. For different standards this pin is given a different identity: ST-BUS: TDM_F0i H.110: TDM_FRAME H-MVIP: TDM_F0 Signal is normally active low, but can be active high depending on standard. Indicates the start of a TDM frame by pulsing every 125 µs. Normally will straddle rising edge or falling edge of clock pulse, depending on standard and clock frequency. TDM_FRMo_REF O W3 TDM port reference frame output. For different standards this pin is given a different identity: ST-BUS: TDM_F0o H.110: TDM_FRAME H-MVIP: TDM_F0 Signal is normally active low, but can be active high depending on standard. Indicates the start of a TDM frame by pulsing every 125 µs. Normally will straddle rising edge or falling edge of clock pulse, depending on standard and clock frequency. AUX_CLKI ID L3 Auxiliary clock input. Typically connected to AUX_CLKO. AUX_CLKO OT L2 Auxiliary clock output. Typically connected to AUX_CLKI. Table 3 - TDM Interface Common Pin Definition 27 Zarlink Semiconductor Inc. ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 4.2 Data Sheet PAC Interface All PAC Interface signals are 5 V tolerant. All PAC Interface outputs are high impedance while System Reset is LOW. Signal I/O Package Balls Description TDM_CLKiP ID V4 Primary reference clock input. Should be driven by external clock source to provide locking reference to internal / optional external DPLL in TDM master mode. Also provides PRS clock for RTP timestamps in synchronous modes. Acceptable frequency range: 8 kHz 34.368 MHz. TDM_CLKiS ID U4 Secondary reference clock input. Backup external reference for automatic switch-over in case of failure of TDM_CLKiP source. PLL_PRI OT Y9 Primary reference output to optional external DPLL. Multiplexed & frequency divided reference output for support of optional external DPLL. Expected frequency range: 8 kHz - 16.384 MHz. PLL_SEC OT W10 Secondary reference output to optional external DPLL Multiplexed & frequency divided reference output for support of optional external DPLL. Expected frequency range: 8 kHz - 16.384 MHz. Table 4 - PAC Interface Package Ball Definition 28 Zarlink Semiconductor Inc. ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 4.3 Data Sheet Packet Interfaces For the ZL50118/19/20 ZL50118/19/20 variants the packet interface is capable of either 2 MII interfaces, or 1 MII and 1 GMII interfaces, or 1 MII and 1 TBI (1000 Mbps) interfaces. The TBI interface is a PCS interface supported by an integrated 1000BASE-X 1000BASE-X PCS module. The ZL50118/19/20 ZL50118/19/20 supports Port 0 and Port 1. For the ZL50115/16/17 ZL50115/16/17 variants the packet interface is capable of 1 MII or 1 GMII or 1 TBI (1000 Mbps) interface. The TBI interface is a PCS interface supported by an integrated 1000BASE-X 1000BASE-X PCS module. The ZL50115/16/17 ZL50115/16/17 supports Port 0. Data for all three types of packet switching is based on Specification IEEE Std. 802.3 - 2000. Only Port 0 has the 1000 Mbps capability necessary for the GMII/TBI interface. Table 5 maps the signal pins used in the MII interface to those used in the GMII and TBI interface. Table 6 shows all the pins and their related package ball, but is based on the GMII/MII configuration. All Packet Interface signals are 5V tolerant, and all outputs are high impedance while System Reset is LOW. MII GMII TBI (PCS) Mn_LINKUP_LED Mn_LINKUP_LED Mn_LINKUP_LED Mn_ACTIVE_LED Mn_ACTIVE_LED Mn_ACTIVE_LED - Mn_GIGABIT_LED Mn_GIGABIT_LED - Mn_REFCLK Mn_REFCLK Mn_RXCLK Mn_RXCLK Mn_RBC0 Mn_COL Mn_COL Mn_RBC1 Mn_RXD[3:0] Mn_RXD[7:0] Mn_RXD[7:0] Mn_RXDV Mn_RXDV Mn_RXD[8] Mn_RXER Mn_RXER Mn_RXD[9] Mn_CRS Mn_CRS Mn_Signal_Detect Mn_TXCLK - - Mn_TXD[3:0] Mn_TXD[7:0] Mn_TXD[7:0] Mn_TXEN Mn_TXEN Mn_TXD[8] Mn_TXER Mn_TXER Mn_TXD[9] - Mn_GTX_CLK Mn_GTX_CLK Table 5 - Packet Interface Signal Mapping - MII to GMII/TBI Note: Mn can be either M0 or M1 for ZL5011x variants. 29 Zarlink Semiconductor Inc. ZL50115/16/17/18/19/20 ZL50115/16/17/18/19/20 Signal I/O Package Balls Data Sheet Description M_MDC O H1 MII management data clock. Common for all four MII ports. It has a minimum period of 400 ns (maximum freq. 2.5 MHz), and is independent of the TXCLK and RXCLK. M_MDIO ID/ OT G1 MII management data I/O. Common for all four MII ports at up to 2.5 MHz. It is bi-directional between the ZL5011x and the Ethernet station management entity. Data is passed synchronously with respect to M_MDC. Table 6 - MII Management Interface Package Ball Definition MII Port 0 Signal I/O Package Balls Description M0_LINKUP_LED O G3 LED drive for MAC 0 to indicate port is linked up. Logic 0 output = LED on Logic 1 output = LED off M0_ACTIVE_LED O D17 LED drive for MAC 0 to indicate port is transmitting or receiving packet data. Logic 0 output = LED on Logic 1 output = LED off M0_GIGABIT_LED O E2 LED drive for MAC 0 to indicate ope