Z16C35 680X0 CRC-16 AD15-AD0 A31-A16 16C35 Z8530 Z8030 RR13A WR10A WR11A WR12A - Datasheet Archive

 

TABLE OF CONTENTS Chapter 1. General Description 1.1 Introduction

 

Z16C35 Z16C35 ISCCTM USER'S MANUAL TABLE OF CONTENTS Chapter 1. General Description 1.1 Introduction . 1-1 1.2 Features . 1-3 1.3 Pin Description . 1-6 Chapter 2. Interfacing the ISCCTM 2.1 Introduction . 2.2 Bus Interface Unit (BIU) Description . 2.2.1 Non-Multiplexed Bus Operation . 2.2.2 Multiplexed Bus Operation . 2.2.3 Data Transfers . 2.3 I/O Interface Capabilities . 2.3.1 Polling . 2.3.2 Interrupts . 2.3.3 DMA Interrupts . 2.4 Register Access . 2.4.1 SCC Cell Register Access, Multiplexed Bus . 2.4.2 SCC Cell Register Access, Non-Multiplexed Bus . 2.4.3 SCC Cell Register Reset . 2.4.4 DMA Cell Registers . 2.4.5 DMA Register Access, Multiplexed Bus . 2.4.6 DMA Register Access, Non-Multiplexed Bus Mode . 2.4.7 Notes on Pointer Accesses . 2-1 2-1 2-1 2-1 2-2 2-3 2-3 2-3 2-4 2-5 2-5 2-6 2-7 2-7 2-7 2-9 2-9 Chapter 3. ISCCTM DMA and Ancillary Support Circuitry 3.1 Introduction . 3-1 3.2 DMA . 3-1 3.2.1 Receiver DMA Operation . 3-1 3.2.2 Transmitter DMA Operation . 3-2 3.3 Baud Rate Generator . 3-2 3.4 Data Encoding/Decoding . 3-5 3.5 Digital Phase-Locked Loop (DPLL) . 3-6 3.5.1 DPLL Operation in the NRZI Mode . 3-7 3.5.2 DPLL Operation in the FM Modes . 3-8 3.5.3 DPLL Operation and Encoding in the Manchester Mode . 3-9 3.6 Clock Selection . 3-11 3.7 Crystal Oscillators . 3-14 Chapter 4. Data Communication Modes 4.1 Introduction . 4.1.1 General Description of the Transmitter . 4.1.2 General Description of the Receiver . 4.2 Asynchronous Mode . 4.2.1 Asynchronous Transmit . 4.2.2 Asynchronous Reception . i 4-1 4-1 4-2 4-4 4-5 4-6 Z16C35 Z16C35 ISCCTM User's Manual Table of Contents 4.3 4.4 Byte-Oriented Synchronous Mode . 4-7 4.3.1 Byte Oriented Synchronous Transmit . 4-8 4.3.2 Byte-Oriented Synchronous Receive . 4-10 4.3.3 Transmitter/Receiver Synchronization . 4-16 Bit-Oriented Synchronous Mode . 4-17 4.4.1 SDLC Transmit . 4-18 4.4.2 SDLC Receive . 4-20 4.4.3 SDLC LOOP MODE . 4-23 4.4.4 SDLC Loop Mode Receive . 4-25 4.4.5 SDLC Loop Mode Transmit . 4-25 Chapter 5. Register Descriptions 5.1 Introduction . 5-1 5.2 Register Descriptions . 5-1 5.2.1 Write Registers, SCC Cell . 5-1 5.2.2 Read Registers, SCC Cell . 5-2 5.2.3 DMA Registers . 5-2 5.3 SCC Cell Register Overview . 5-2 5.4 Write Registers . 5-3 5.4.1 Write Register 0 (Command Register) . 5-3 5.4.2 Write Register 1 (Transmit/Receive Interrupt and Data Transfer Mode Definition) . 5-5 5.4.3 Write Register 2 (Interrupt Vector) . 5-7 5.4.4 Write Register 3 (Receive Parameters and Control) . 5-8 5.4.5 Write Register 4 (Transmit/Receiver Miscellaneous Parameters and Modes) . 5-9 5.4.6 Write Register 5 (Transmit Parameter and Controls) . 5-11 5.4.7 Write Register 6 (Sync Characters or SDLC Address Field) . 5-12 5.4.8 Write Register 7 (SYNC Character or SDLC Flag) . 5-12 5.4.9 Write Register 8 (Transmit Buffer) . 5-13 5.4.10 Write Register 9 (Master Interrupt Control) . 5-13 5.4.11 Write Register 10 (Miscellaneous Transmitter/Receiver Control Bits) . 5-14 5.4.12 Write Register 11 (Clock Mode Control) . 5-16 5.4.13 Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) . 5-17 5.4.14 Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) . 5-18 5.4.15 Write Register 14 (Miscellaneous Control Bits) . 5-18 5.4.16 Write Register 15 (External/Status Interrupt Control) . 5-19 5.5 Read Registers . 5-20 5.5.1 Read Register 0 (Transmit/receive buffer Status and External Status) . 5-20 5.5.2 Read Register 1 . 5-22 5.5.3 Read Register 2 . 5-23 5.5.4 Read Register 3 . 5-24 5.5.5 Read Register 8 . 5-24 5.5.6 Read Register 10 . 5-24 5.5.7 Read Register 12 . 5-24 5.5.8 Read Register 13 . 5-25 5.5.9 Read Register 15 . 5-25 5.6 DMA Cell Register Descriptions . 5-25 5.6.1 Channel Command/Address Register . 5-25 5.6.2 DMA Status Register . 5-26 5.6.3 Interrupt Control Register . 5-26 5.6.4 Interrupt Vector Register . 5-27 5.6.5 Interrupt Command Register . 5-27 5.6.6 Interrupt Status Register . 5-28 5.6.7 DMA Enable Register . 5-29 5.6.8 DMA Control Register . 5-29 5.6.9 Receive DMA Count Registers A, B . 5-30 5.6.10 Transmit DMA Count Registers A, B . 5-31 5.6.11 Receive DMA Address Registers A, B . 5-32 5.6.12 Transmit DMA Address Registers A, B . 5-33 ii Z16C35 Z16C35 ISCCTM User's Manual Table of Contents 5.6.13 Bus Configuration Register . 5-36 Chapter 6. Interfacing the ISCCTM to the 68000 and 8086 Introduction . ISCC Bus Interface Unit (BIU) . Overview . Modes Description . Non-Multiplexed Bus Operation . Multiplexed Bus Operation . Bus Data Transfers . Data Bus Transfers as a Slave Peripheral . ISCCTM DMA Bus Transfers . Bus Interface Handshaking . Configuring the Bus . Applications Examples . 68000 Interface to the ISCC . 8086 Interface with the ISCC . 6-1 6-1 6-1 6-1 6-2 6-2 6-3 6-3 6-3 6-4 6-5 6-6 6-6 6-6 Chapter 7. Questions and Answers Zilog ISCCTM Controller Questions and Answers. 7-1 iii Z16C35 Z16C35 ISCCTM USER'S MANUAL LIST OF FIGURES Chapter 1 Figure 1-1. Figure 1-2. Figure 1-3. Block Diagram . 1-2 Pin Functions . 1-4 Pin Assignments . 1-5 Chapter 2 Chapter 3 Figure 3-1. Figure 3-2. Figure 3-3. Figure 3-4. Figure 3-5. Figure 3-6. Figure 3-7. Figure 3-8. Figure 3-9. Figure 3-10a. Figure 3-10b. Figure 3-10c. Baud Rate Generator . 3-3 Baud Rate Generator Start-Up . 3-3 Data Encoding Methods . 3-5 Digital Phase Lock Loop . 3-6 DPLL in NRZI Mode . 3-7 DPLL Operating Example (NRZI Mode) . 3-8 DPLL Operation in the FM Mode . 3-8 Encoding Manchester Data . 3-10 Clock Multiplexer . 3-11 Async Transmission, 16x Clock Mode Using External Crystal . 3-12 Async Transmission, 1x Clock Rate, NRZ Data Encoding . 3-13 Asynchronous Transmission, 1x Clock Rate, FM Data Encoding . 3-14 Chapter 4 Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 4-6. Figure 4-7. Figure 4-8. Figure 4-9. Figure 4-10. Figure 4-11. Figure 4-12. Figure 4-13. Figure 4-14. Transmitter Block Diagram . 4-2 Receiver Block Diagram . 4-3 Asynchronous Message Format . 4-4 Monosync Data Character Format . 4-8 Sync Character Programming . 4-11 /SYNC as an Input . 4-11 /SYNC as an Output . 4-12 Changing Character Length . 4-13 Receive CRC Data Path . 4-14 Transmitter to Receiver Synchronization . 4-16 SDLC Message Format . 4-17 /SYNC as an Output . 4-20 Changing Character Length . 4-21 Residue Code 101 Interpretation . 4-22 Chapter 5 Figure 5-1. WR0 in the Non-Multiplexed Bus Mode . 5-3 iv Z16C35 Z16C35 ISCCTM User's Manual Table of Contents Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 5-6. Figure 5-7. Figure 5-8. Figure 5-9. Figure 5-10. Figure 5-11. Figure 5-12. Figure 5-13. Figure 5-14. Figure 5-15. Figure 5-16. Figure 5-17. Figure 5-18. Figure 5-19. Figure 5-20. Figure 5-21. Figure 5-22. Figure 5-23. Figure 5-24. Figure 5-25. Figure 5-26. Figure 5-27. Figure 5-28. Figure 5-29. Figure 5-30. Figure 5-31. Figure 5-32. Figure 5-33. Figure 5-34. Figure 5-35. Figure 5-36. Figure 5-36. Figure 5-37. Figure 5-38. Figure 5-39. WR0 in the Multiplexed Bus Mode . 5-3 Write Register 1 . 5-6 Write Register 2 . 5-7 Write Register 3 . 5-8 Write Register 4 . 5-9 Write Register 5 . 5-11 Write Register 6 . 5-12 Write Register 7 . 5-13 Write Register 9 . 5-13 Write Register 10 . 5-14 NRZ (NRZI), FM1 (FM0) Timing . 5-15 Write Register 11 . 5-16 Write Register 12 . 5-17 Write Register 13 . 5-18 Write Register 14 . 5-18 Write Register 15 . 5-20 Read Register 0 . 5-20 Read Register 1 . 5-22 Read Register 2 . 5-23 Read Register 3 . 5-24 Read Register 10 . 5-24 Read Register 12 . 5-24 Read Register 13 . 5-25 Read Register 15 . 5-25 Channel Command/Address Register . 5-25 DMA Status Register . 5-26 Interrupt Control Register . 5-26 Interrupt Vector Register . 5-27 Interrupt Command Register . 5-27 Interrupt Status Register . 5-28 DMA Enable Register . 5-29 DMA Control Register . 5-29 Receive DMA Count Registers . 5-30 Transmit DMA Count Registers . 5-31 Receive DMA Address Registers . 5-32 Receive DMA Address Registers (Continued) . 5-33 Transmit DMA Address Registers . 5-34 Transmit DMA Address Registers (Continued) . 5-35 Bus Configuration Register . 5-36 v Z16C35 Z16C35 ISCCTM USER'S MANUAL LIST OF TABLES Chapter 2 Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. ISCC Bus Access Summary . SCC Cell Address Map, Multiplexed Bus Mode, Shift Left . SCC Cell Address Map, Multiplexed Bus Mode, Shift Right . SCC Cell Register Address Map Using Pointer (Non-multiplexed Bus Mode) . SCC Cell Reset Value . DMA Address Map . 2-3 2-5 2-6 2-7 2-7 2-8 Chapter 3 Table 3-1. DMA Interrupt Vector Modification . 3-1 Table 3-2. Baud Rates for 2.4576 MHz Clock and 16x Clock Factor . 3-4 Chapter 4 Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table 4-5. Table 4-6. Table 4-7. Table 4-8. Table 4-9. Table 4-10. Table 4-11. Table 4-12. Table 4-13. Table 4-14. Write Register Bits Ignored in Asynchronous Mode . 4-5 Transmit Bits per Character . 4-5 Initialization Sequence for the Transmitter in Asynchronous Mode . 4-6 Initialization Sequence for the Receiver in Asynchronous Mode . 4-7 Registers Used in Character-oriented Modes . 4-9 Transmitter Initialization in Character Oriented Mode . 4-10 Sync Character Length Selection . 4-10 Enabling and Disabling CRC on the Fly . 4-15 Initializing the Receiver in Character Oriented Mode . 4-16 Underrun EOM Bit . 4-19 Initializing the Transmitter in SDLC Mode . 4-19 Residue Codes . 4-21 Initializing the Receiver in SDLC Mode . 4-23 SDLC Loop Mode initialization . 4-25 Chapter 5 Table 5-1. Table 5-2. Table 5-3. Table 5-4. Table 5-5. Table 5-6. Table 5-7. SCC Cell Write Registers . 5-1 SCC Cell Read Registers . 5-2 DMA Cell Register Description . 5-2 SCC Cell Register Address Map Using Pointer (Non-Multiplexed Bus Mode) Using Null Command . 5-5 Receive Bits per Character . 5-8 Transmit Bits per Character . 5-11 Interrupt Vector Modification . 5-14 vi Z16C35 Z16C35 ISCCTM User's Manual Table of Contents Table 5-8. Table 5-9. Table 5-10. Table 5-11. Table 5-12. Table 5-13. Table 5-14. Table 5-15. Table 5-16. Data Encoding . Receive Clock Source . Transmit Clock Source . Transmit External Control Selection . I-Field Bit Selection (8 Bits Only) . Bits per Character Residue Decoding . Interrupt Vector Status Encoding . DMA Priority . Interrupt Acknowledge Programming . vii 5-15 5-17 5-17 5-17 5-23 5-23 5-27 5-30 5-36 Z16C35 Z16C35 ISCCTM User's Manual Table of Contents viii USER'S MANUAL 1 CHAPTER 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The Z16C35 Z16C35, ISCCTM is a CMOS superintegration device with a flexible Bus Interface Unit (BIU) connecting a builtin Direct Memory Access (DMA) cell to the CMOS Serial Communications Control (SCC) cell. The ISCC is a dual-channel, multi-protocol data communications peripheral which easily interfaces to CPU's with either multiplexed or non-multiplexed address and data buses. The advanced CMOS process offers lower power consumption, higher performance, and superior noise immunity. The programming flexibility of the internal registers allow the ISCC to be configured for a wide variety of serial communications applications. The many on-chip features such as streamlined bus interface, four channel DMA, baud rate generators, digital phase-locked loops, and crystal oscillators dramatically reduce the need for external logic. Additional features, including a 10x19 bit status FIFO, are added to support high speed SDLC transfers using onchip DMA controllers. The ISCC can address up to 4 gigabytes per DMA channel by using the /UAS and /AS signals to strobe out 32-bit multiplexed addresses. The ISCC handles asynchronous formats, synchronous byte-oriented protocols such as IBM Bisync, and synchronous bit-oriented protocols such as HDLC and IBM SDLC. This versatile device supports virtually any serial data transfer application (terminals, printers, diskette, tape drives, etc.). The device can generate and check CRC codes in any synchronous mode and can be programmed to check data integrity in various modes. The ISCC also has facilities for modem controls in both channels. In applications where these controls are not needed, the modem controls can be used for general-purpose I/O. The standard Zilog interrupt daisy chain is supported for interrupt hierarchy control. Internally, the SCC cell has higher interrupt priority than the DMA cell. The DMA cell consists of four DMA channels; one for transmit and one for receive to and from each SCC channel, respectively. The DMA cell adopts a simple fly-by-mode DMA transfer, providing a powerful and efficient DMA access. The cell does not support memory-to-memory transfer. Priorities between the four DMA channels are programmable to custom-fit user applications. Arbitration of Bus priority control signals between the ISCC DMA and other system DMA's should be handled outside the ISCC. The BIU has a universal interface to most system/CPU bus structures and timing. The first write to the ISCC after a hardware reset will configure the bus interface type being implemented. 1-1 Z16C35 Z16C35 ISCCTM User's Manual General Description 1.1 INTRODUCTION (Continued) Figure 1-1. Block Diagram 1-2 Z16C35 Z16C35 ISCCTM User's Manual General Description 1.2 FEATURES s Low Power CMOS Technology s Supports all Zilog CMOS SCC Features: s Two General-Purpose SCC Channels, Four DMA Channels; and Universal Bus Interface Unit s s Software Compatible to the Zilog CMOS SCC Two Independent, 0 to 4.0 Mbit/Second, Full-Duplex Channels, Each with a Separate Crystal Oscillator, Baud Rate Generator, and Digital Phase-Locked Loop Circuit for Clock Recovery. s Four DMA Channels; Two Transmit and Two Receive Channels to and from the SCC s Multi-Protocol Operation under Program Control; Programmable for NRZ, NRZI, or FM Data Encoding. s Four Gigabyte Address Range per DMA Channel s s Flyby DMA Transfer Mode s Programmable DMA Channel Priorities Asynchronous Mode with Five to Eight Bits and One, One and One-Half, or Two Stop Bits per Character; Programmable Clock Factor; Break Detection and Generation; Parity, Overrun, and Framing Error Detection. s Independent DMA Register Set s s A Universal Bus Interface Unit Providing Simple Interface to Most CPUs Multiplexed or Non-Multiplexed Bus; Compatible with 680X0 680X0 and 8X86 CPUs Synchronous Mode with Internal or External Character Synchronization on One or Two Synchronous Characters and CRC Generation and Checking with CRC-16 CRC-16 or CRC-CCITT preset to either 1's or 0's. s 32-Bit Addresses Multiplexed to 16-pin Address/Data Lines s s 8-Bit Data Supporting High/Low Byte Swapping SDLC/HDLC Mode with Comprehensive Frame-Level Control, Automatic Zero Insertion and Deletion, I-Field Residue Handling, Abort Generation and Detection, CRC Generation and Checking, and SDLC Loop Mode Operation. s 10 MHz Timing s Local Loopback and Auto Echo modes s 12.5 and 16 MHz Timing Planned s Supports T1 Digital Trunk s 68-Pin PLCC s Enhanced SDLC 10x19 Status FIFO for DMA Support s Full CMOS SCC Register Set 1-3 1 Z16C35 Z16C35 ISCCTM User's Manual General Description 1.2 FEATURES (Continued) Figure 1-2. Pin Functions 1-4 VCC 2 1 68 67 66 65 64 63 62 61 1 /BUSACK N/C 3 /UAS VCC 4 /WR /RESET 5 R//W /CE 6 /RD A0/SCC//DMA 7 /DS AI/A//B 8 /AS /WAIT//READY 9 /INTACK IEI Z16C35 Z16C35 ISCCTM User's Manual General Description IEO 10 60 /BUSREQ /INT 11 59 PCLK /SYNCA 12 58 /SYNCB /RTxCA 13 57 /RTxCB GND 14 56 GND VCC 15 55 VCC AD0 16 54 AD8 53 AD9 ISCC Z16C35 Z16C35 AD1 17 AD2 18 52 AD10 AD3 19 51 AD11 AD4 20 50 AD12 AD5 21 49 AD13 AD6 22 48 AD14 AD7 23 47 AD15 GND 24 46 GND VCC 25 45 VCC N/C 26 44 N/C RxDB /TRxCB TxDB /DTRB /RTSB /CTSB GND /DCDB N/C GND /CTSA /DCDA /RTSA /DTRA TxDA /TRxCA RxDA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Figure 1-3. Pin Assignments 1-5 Z16C35 Z16C35 ISCCTM User's Manual General Description 1.3 PIN DESCRIPTION The following section describes the Z16C35 Z16C35 pin functions. Figures 1-2 and 1-3 detail the respective pin functions and pin assignments. All references to DMA are internal. /CTSA, /CTSB. Clear To Send (inputs, active Low). These pins function as transmitter enables if they are programmed for Auto Enables (WR3, D5). If these pins are programmed as Auto Enables, a Low on the inputs enables the respective transmitters. If not programmed as Auto Enables, they may be used as general-purpose inputs. Both inputs are Schmitt-trigger buffered to accommodate slow rise-time inputs. The SCC cell detects transitions on these inputs and can interrupt the CPU on both low to high and high to low transitions. /DCDA, /DCDB. Data Carrier Detect (inputs, active Low). These pins function as receiver enables if they are programmed for Auto Enables (WR3 D5), otherwise they are used as general-purpose input pins. Both pins are Schmitttrigger buffered to accommodate slow rise time signals. The SCC cell detects transitions on these inputs and can interrupt the CPU on both low to high and high to low transitions. /DTR//REQA, /DTR//REQB. Data Terminal Ready/Request (outputs, active Low). These pins are programmable (WR14, D2) to serve as either general-purpose outputs or as DMA request lines. When programmed for the DTR function These outputs follow the state programmed into the DTR bit of Write Register 5 (WR5, D7). When programmed for the Ready mode, these pins serve as DMA requests for the transmitter. Note that this DMA request is not associated with the on-chip DMA and is intended for use in requesting DMA service from an external DMA. IEI. Interrupt Enable In (input, active High). IEI is used with IEO to form an interrupt daisy chain when there is more than one interrupt driven device. A high IEI indicates that no other higher priority device has an interrupt under service or is requesting an interrupt. IEO. Interrupt Enable Out (output, active High). IEO is High only if IEI is High and the CPU is not servicing the ISCC (SCC or DMA) interrupt or the ISCC is not requesting an interrupt (Interrupt Acknowledge cycle only). IEO is connected to the next lower priority device's IEI input and thus inhibits interrupts from lower priority devices. type of interrupt pending during this acknowledge cycle when /RD or /DS become high. /INTACK may be programmed to accept a status acknowledge, a single pulse acknowledge, or a double pulse acknowledge. This is programmed in the Bus Configuration Register (BCR). The double pulse acknowledge is compatible with 8X86 family microprocessors. PCLK. Clock (input). This is the master SCC cell and DMA cell clock used to synchronize internal signals. PCLK is a TTL level signal. PCLK is not required to have any phase relationship with the master system clock. RxDA, RxDB. Receive Data (inputs, active High). These input signals receive serial data at standard TTL levels. /RTxCA, /RTxCB. Receive/Transmit Clocks (inputs, active Low). These pins can be programmed to several modes of operation. In each channel, /RTxC may supply the receive clock, the transmit clock, the clock for the baud rate generator, or the clock for the Digital Phase-Locked Loop. These pins can also be programmed for use with the respective /SYNC pins as a crystal oscillator. The receive clock may be 1, 16, 32, or 64 times the data rate in asynchronous modes. /RTSA, /RTSB. Request To Send (outputs, active Low). When the Request To Send (RTS) bit in Write Register 5 is set, the /RTS signal goes Low. When the RTS bit is reset in the Asynchronous mode and Auto Enable is on, the signal goes High after the transmitter is empty. In Synchronous mode or in Asynchronous mode with Auto Enable off, the /RTS pin strictly follows the state of the RTS bit. Both pins can be used as general-purpose outputs. /SYNCA, /SYNCB. Synchronization (inputs or outputs, active Low). These pins can act either as inputs, outputs, or part of the crystal oscillator circuit. In the Asynchronous Receive mode (crystal oscillator option not selected), these pins are inputs similar to /CTS and /DCD. In this mode, transitions on these lines affect the state of the Sync/Hunt status bits in Read Register 0 but have no other function. /INT. Interrupt (output, active Low). This signal is activated when the SCC or DMA requests an interrupt. Note that /INT is pulled high and is not an open-drain output. In External Synchronization mode with the crystal oscillator not selected, these lines also act as inputs. In this mode, /SYNC must be driven Low two receive clock cycles after the last bit in the synchronous character is received. Character assembly begins on the rising edge of the receive clock immediately preceding the activation of /SYNC. /INTACK. Interrupt Acknowledge (input, active Low). This is a strobe which indicates that an interrupt acknowledge cycle is in progress. During this cycle, the SCC and DMA interrupt daisy chain is resolved. The device is capable of returning an interrupt vector that may be encoded with the In the Internal Synchronization mode (Monosync and Bisync) with the crystal oscillator not selected, these pins act as outputs and are active only during the part of the receive clock cycle in which sync condition is not latched. These outputs are active each time a sync pattern is recognized 1-6 Z16C35 Z16C35 ISCCTM User's Manual General Description (regardless of character boundaries). In SDLC mode, the pins act as outputs and are valid on receipt of a flag. The output is active for one receive clock period (refer to Chapter 4). TxDA, TxDB. Transmit Data (outputs, active high). These output signals transmit serial data at standard TTL levels. /TRxCA, /TRxCB. Transmit/Receive Clocks (inputs or outputs, active Low). These pins can be programmed in several different modes of operation. /TRxC may supply the receive clock or the transmit clock in the input mode or supply the output of the Digital Phase-Locked Loop, the crystal oscillator, the baud rate generator, or the transmit clock in the output mode. /CE. Chip Enable (input, active Low). This signal selects the ISCC for a peripheral read or write operation. This signal is ignored when the ISCC is bus master. AD15-AD0 AD15-AD0. Data bus (bidirectional, tri-state). These lines carry data and commands to and from the ISCC. /RD. Read (bidirectional, active Low). When the ISCC is a peripheral (i.e., bus slave), this signal indicates a read operation and when the ISCC is selected, enables the ISCC's bus drivers. As an input, /RD indicates that the CPU wants to read from the ISCC read registers. During the Interrupt Acknowledge cycle, /RD gates the interrupt vector onto the bus if the ISCC is the highest priority device requesting an interrupt. When the ISCC is the bus master, this signal is used to read data. As an output, after the ISCC has taken control of the system buses, /RD indicates a DMA-controlled read from a memory or I/O port address. /WR. Write (bidirectional, active Low). When the ISCC is selected, this signal indicates a write operation. As an input, this indicates that the CPU wants to write control or command bytes to the ISCC write registers. As an output, after the ISCC has taken control of the system buses /WR indicates a DMA-controlled write to a memory or I/O port address. /DS. Data Strobe (bidirectional, active Low). A Low on this signal indicates that the AD15-AD0 AD15-AD0 bus is used for data transfer. When the ISCC is not in control of the system bus and the external system is transferring information to or from the ISCC, /DS is a timing input used by the ISCC to move data to or from the AD15-AD0 AD15-AD0 bus. Data is written into the ISCC by the external system on the High to Low /DS transition. Data is read from the ISCC by the external system while /DS is Low. There are no timing requirements between /DS as an input and ISCC clock; this allows use of the ISCC with a system bus which does not have a bussed clock. During a DMA operation when the ISCC is in control of the system, /DS is an output generated by the ISCC and used by the system to move data to or from the AD15-AD0 AD15-AD0 bus. When the ISCC has bus control, it writes to the external system by placing data on the AD15-AD0 AD15-AD0 bus before the High-to-Low /DS transition and holds the data stable until after the Low-to-High /DS transition; while reading from the external system, the Low-to-High transition of /DS inputs data from the AD15-AD0 AD15-AD0 bus into the ISCC. R//W. Read/Write (bidirectional). Read polarity is High and write polarity is Low. When the ISCC is not in control of the system bus and the external system is transferring information to or from the ISCC, R//W is a status input used by the ISCC to determine if data is entering or leaving on the AD15-AD0 AD15-AD0 bus during /DS time. In such a case, Read (High) indicates that the system is requesting data from the ISCC and Write (Low) indicates that the system is presenting data to the ISCC. The only timing requirements for R//W as an input are defined relative to /DS. When the ISCC is in control of the system bus, R//W is an output generated by the ISCC, with Read (high) indicating that data is being requested from the addressed location or device, and Write (low) indicating that data is being presented to the addressed location or device. /UAS. Upper Address Strobe (Output, active Low). This signal is used if the output address is more than 16-bit. The upper address, A31-A16 A31-A16, can be latched externally by the rising edge of this signal. /UAS is active first before /AS becomes active. This signal and /AS are used by the DMA cell. /AS. Lower Address Strobe (bidirectional, active Low). When the ISCC is bus master, this signal is an output, and is used as a lower address strobe for AD15-AD0 AD15-AD0. It is used in conjunction with /UAS since the address is 32-bits. This signal and /UAS are used by the DMA cell when it is bus master. When ISCC is not bus master, this signal is used in the multiplexed bus modes to latch the address on the AD lines. The /AS signal is not used in the non-multiplexed bus modes and should be tied to VCC through a resistor in these cases. /WAIT//RDY. Wait/Ready (bidirectional, active Low). This signal may be programmed to function either as a Wait signal or Ready signal during the BCR write. When the BCR is written to Channel A (A1/A//B High during the BCR write), this signal functions as a /WAIT and thus supports the READY function of 8X86 microprocessors family. When the BCR writes to Channel B (A1/A//B Low), this signal functions as a /READY and supports the /DTACK function of the 680X0 680X0 microprocessor family. This signal is an output when the ISCC in not bus master. In this case, the /Wait//RDY signal indicates when the data is available during a read cycle; when the device is ready to receive data during a write cycle; and when a valid vector is available during an interrupt acknowledge cycle. 1-7 1 Z16C35 Z16C35 ISCCTM User's Manual General Description 1.3 PIN DESCRIPTION (Continued) When the ISCC is the bus master (the DMA cell has taken control of the bus), the /Wait//RDY signal functions as a /WAIT or /READY input. Slow memories and peripheral devices can assert /WAIT to extend /DS during bus transfers. Similarly, memories and peripherals use /READY to indicate that its output is valid or that it is ready to latch input data. /BUSACK. Bus Acknowledge (input, active Low). Signals the bus has been released to the DMA. If the /BUSACK goes inactive before the DMA transfer is completed, the current DMA transfer is aborted. /BUSREQ. Bus Request (output, active Low). This signal is used by the DMA to obtain the bus from the CPU. A0/SCC//DMA. DMA Channel/SCC Select/DMA Select (bidirectional). When this pin is used as input, a high selects the SCC cell and a low selects the DMA cell, (during BCR Write should be kept Low). When this pin is used as output, the signal on this pin is used in conjunction with A1/A//B pin output to identify which DMA channel is active. This information can be used by the user to determine whether to issue a DMA abort command. A0/SCC//DMA and A1/A//B output encoding is shown on the following page. 1-8 A1/A//B A0/SCC//DMA DMA channel 1 1 0 0 1 0 1 0 RxA TxA RxB TxB A1/A//B. DMA Channel/Channel A/Channel B (bidirectional). This signal, when used as input, selects the SCC channel in which the read and write operation occurs. Note that A0/SCC//DMA pin must be held high to select this feature. When this pin is used as an output, it is used in conjunction with the A0/SCC//DMA pin output to identify which DMA channel is active. During a DMA peripheral access, the A1/A//B pin is ignored. /RESET. (input, active Low). This signal resets the device to a known state. The first write to the ISCC after a reset accesses the BCR to select additional bus options for the device. USER'S MANUAL 2 CHAPTER 2 INTERFACING THE ISCCTM 2.1 INTRODUCTION This chapter details the interfacing of the 16C35 16C35 ISCC to a system. Covered in this chapter is a description of the Bus Interface Unit (BIU) and information about the ISCC in nonmultiplexed and multiplexed bus operation. The following section entails the ISCC's capabilities for three types of I/O operations: polling, interrupt (vectored or non-vectored), and DMA Transfer modes. Also included in this chapter is information about the ISCC registers and register access. 2.2 BUS INTERFACE UNIT (BIU) DESCRIPTION The ISCCTM contains a flexible bus interface that is compatible with a variety of microprocessors and microcontrollers. The device is designed to work with 8- or 16-bit bus systems and may be used with address/data multiplexed buses or non-multiplexed buses. The bus interface style is selected by certain actions which take place after a hardware reset. The ISCC contains a Bus Configuration Register, the BCR. This register has no address and is only accessible in the first transaction to the ISCC after a hardware reset; this first transaction must be a write with AØ/sec//DMA Low and is automatically directed to the Bus Configuration Register by the ISCC. The Bus Configuration Register contains bits which program the byte swapping feature, the interrupt acknowledge type and other aspects of the bus interface configuration. Refer to Chapter 5 for BCR details. The multiplexed bus is selected for the ISCC if there is an Address Strobe prior to or during the transaction which writes the BCR. If no Address Strobe is present prior to or during the transaction which writes the BCR, a non-multiplexed bus is selected. The address strobe is recognized whether or not the ISCC Chip Enable is active. 2.2.1 Non-Multiplexed Bus Operation When the ISCC is initialized for non-multiplexed operation, register addressing for the ISCC cell is (with the exception of WR0 and RR0), accomplished using an internal pointer accessed via WR0. Accessing internal registers by this means is a two step operation requiring a write to the pointer followed by access of the desired register. This is described in detail in later sections. Note that when the DMA is not used to address the data, the data registers must be accessed by pointing to Register 8. (This is in contrast to the Z8530 Z8530 which allows direct addressing of the data registers through the C/D pin.) When the ISCC is initialized for non-multiplexed operation, register addressing for the DMA cell (with the exception of CSAR) is accomplished in a manner similar to that used in the SCC cell. In this case the pointer is accessed in the Command Status Address Register (CSAR bits 4 - 0). The SCC cell and DMA cell pointers are independent. Detailed operation is described in a later section. 2.2.2 Multiplexed Bus Operation When the ISCC is initialized for multiplexed bus operation, all registers in the SCC cell are directly addressable with the register address occupying AD5 through AD1, or AD4 through AD0 (Shift Left/Shift Right modes). The A0/SCC //DMA pin controls the SCC cell /DMA selection. The SCC cell channel A/B selection may be controlled either by the A0/A//B pin or by the A/B selection in the address on AD7AD0 that is strobed into the ISCC with /AS. Use of this requires that the unused SCC channel select option to be set to Channel A. That is, if the A0/A//B pin is used to select the channel, then the AD bit for channel selection must select channel A (the actual bit is determined by the Shift Left/Shift Right mode employed) and conversely, if the AD bus bit is used to select the channel, then the A0/A//B pin must select channel A. Refer to the A0/SCC//DMA and A1/A//B pin descriptions for the encoding of these signals. In the multiplexed bus mode of operation, the register pointer in WR0 of the SCC cell is ignored and has no effect 2-1 Z16C35 Z16C35 ISCCTM User's Manual Interfacing the ISCCTM 2.2 BUS INTERFACE UNIT (BIU) DESCRIPTION (Continued) on the accessing of the internal registers. Register access is made solely through the latched address. However, the pointer in the DMA Channel Command/Address Register functions in the multiplexed bus mode and may be used to access DMA registers in a manner identical to that in the non-multiplexed bus mode. To use the DMA pointer in the multiplexed bus mode, the multiplexed address must always address the CCAR of the DMA even though the actual register access will be made according to the pointer. This requires that in the normal multiplexed mode of operation with register access through the latched address, writes to the DMA CCAR must always write zeros to the pointer field. In the multiplexed bus mode in some host configurations, address A0 may be used for byte transfer control in 16-bit systems. Therefore, it may be necessary to ignore A0 in the register decode. This is accommodated in the ISCC by providing an option to decode the multiplexed address from A1 upwards rather than from A0 upwards. This option is the Shift Left/Shift Right mode. The Shift Left/Shift Right modes for the address decoding for the internal registers (multiplexed bus) are separately programmable for the SCC cell and for the DMA cell. For the SCC cell the programming and operation is identical to that in the SCC; programming is accomplished through Write Register 0 (WR0), bits 1 and 0 (Figure 5-2). The programming of the Shift Left/Shift Right modes for the DMA cell is accomplished in the BCR, bit 0. In this case, the shift function is similar to that for the SCC cell; with Shift left, the internal register addresses are decoded from bits AD5 through AD1 and with Shift Right, the internal register addresses are decoded from bits AD4 through AD0. When the multiplexed bus mode is selected, Write Register 0 (WR0) takes on the form of WR0 in the Z8030 Z8030 (Figure 5-2). 2.2.3 Data Transfers All data transfers to and from the ISCC are done in bytes even though the data may at special times occupy the lower or upper byte of the 16-bit bus. Bus transfers as a slave peripheral are done differently than bus transfers when the ISCC is the bus master during DMA transactions. The ISCC is fundamentally an 8-bit peripheral but supports 16bit buses in the DMA mode. Slave peripheral and DMA transactions are described in the next paragraphs. 2-2 Data Bus Transfers as a Slave Peripheral: When accessed as a peripheral device (when the ISCC is not a bus master performing DMA transfers), only 8 bits are transferred. When the ISCC registers are read, the byte data present on the lower 8 bits of the bus is replicated on the upper 8 bits of the bus. Data is accepted by the ISCC only on the lower 8 bits of the bus. ISCC DMA Bus Transfers: During DMA transfers, when the ISCC is bus master, only byte data is transferred. However, data may be transferred from the ISCC on the upper 8 bits of the bus or on the lower 8 bits of the bus. Moreover, odd or even byte transfers may be done on the lower or upper 8 bits of the bus. This is programmable and is described below. During DMA transfers to memory from the ISCC, byte data only is transferred and the data appears on the lower 8 bits and is replicated on the upper 8 bits of the bus. Thus the data may be written to an odd or even byte of the system memory by address decoding and strobe generation. During DMA transfers to the ISCC from memory, byte data only is transferred and normally data is accepted only on the lower 8 bits of the bus. However, the byte swapping feature may be used to enable data to be accepted on either the lower or upper 8 bits of the bus. The byte swapping feature is enabled by programming the Byte Swap Enable bit to a 1 in the BCR. The odd/even byte transfer selection is made by programming the Byte Swap Select bit in the BCR. If Byte Swap Select is a 1, then even address bytes (transfers where the DMA address has A0 equal 0) are accepted on the lower 8 bits of the bus and odd address bytes (transfers where the DMA address has A0 equal 1) are accepted on the upper 8 bits of the bus. If Byte Swap Select is a 0, then even address bytes (transfers where the DMA address has A0 equal 0) are accepted on the upper 8 bits of the bus and odd address bytes (transfers where the DMA address has A0 equal 1) are accepted on the lower 8 bits of the bus. Z16C35 Z16C35 ISCCTM User's Manual Interfacing the ISCCTM Table 2-1. ISCC Bus Access Summary Action on Byte Swap Lower Bus Upper8 Process Enable Select 8 Bits Bits Read X X data same data Write X X data read data ignored DMA Write 0 X data same data DMA Read 0 X data read data ignored DMA Write 1 X data same data DMA Read 1 0 depends upon A0 (see below) In the DMA Read with Byte Swap enabled: Byte Swap Select 0 0 1 1 A0 0 1 0 1 In this table DMA read refers to a DMA controlled transfer from memory to the ISCC and DMA write refers to a DMA controlled transfer from the ISCC to memory. Read refers to a normal peripheral transaction where the CPU reads data from the ISCC and Write refers to a normal peripheral transaction where the CPU writes data to the ISCC. ISCC Accepts Data Upper 8 Bits of Bus Lower 8 Bits of Bus Lower 8 Bits of Bus Upper 8 Bits of Bus 2.3 I/O INTERFACE CAPABILITIES The ISCC offers the choice of Polling, Interrupt (vectored or non-vectored), and DMA Transfer modes to transfer data, status, and control information to and from the CPU. 2.3.1 Polling In this mode all interrupts and the DMA's are disabled. Three status registers in the SCC are automatically updated whenever any function is performed. For example, endof-frame in SDLC mode sets a bit in one of these status registers. With polling, the CPU must periodically read a status register until the register contents indicate the need for some CPU action to be taken. Only one register in the SCC cell needs to be read; depending on the contents of the register, the CPU either reads data, writes data, or satisfies an error condition. Two bits in the register indicate the need for data transfer. An alternative is to poll the Interrupt Pending register to determine the source of an interrupt. The status for both SCC channels resides in one register. 2.3.2 Interrupts When the ISCC responds to an Interrupt Acknowledge signal (INTACK) from the CPU, an interrupt vector is placed on the data bus. Both the SCC and the DMA contain vector registers. Depending on the source of interrupt, one of these vectors is returned, either unmodified or modified by the interrupt status to indicate the exact cause of the interrupt. Each of the six sources of interrupt in the SCC (Transmit, Receive, and External/Status interrupts in both channels) and each DMA channel has three bits associated with the interrupt source: Interrupt Pending (IP), Interrupt Under Service (IUS), and Interrupt Enable (IE). If the IE bit is set for any given source of interrupt, then that source can request interrupts. The only exception to this rule is when the associate Master Interrupt Enable (MIE) bit is reset, then no interrupts are requested. Both the SCC cell and the DMA have an associated MIE bit. The IE bits in the SCC cell are write only, but the IE bits in the DMA are read/write. The ISCC provides for nesting of interrupt sources with an interrupt daisy chain using the IEI, IEO, and /INTACK pins. As a microprocessor peripheral, the ISCC may request an interrupt only when no higher priority device is requesting one, e.g., when IEI is High. If the device in question requests an interrupt, it enables the /INT signal. The CPU then responds with /INTACK, and the interrupting cell places the vector on the data bus. In the ISCC, the IP bit signals a need for interrupt servicing. When an IP bit is 1 and the IEI input pin is High, the /INT signal is activated, requesting an interrupt. In the SCC cell, if the IE bit is not set, then the IP for that source can never be set. The IP bits in the DMA cell are set independent of the IE bit. The IUS bits signal that an interrupt request is being serviced. If an IUS is set, all interrupt sources of lower priority in the ISCC and external to the ISCC are prevented from requesting interrupts. The internal interrupt sources are inhibited by the state of the internal daisy chain, while lower priority devices are inhibited by the IEO output of the ISCC being pulled Low and propagated to 2-3 2 Z16C35 Z16C35 ISCCTM User's Manual Interfacing the ISCCTM 2.3 I/O INTERFACE CAPABILITIES (Continued) subsequent peripherals. Internally, the SCC cell is higher priority than the DMA cell. An IUS bit is set during an Interrupt Acknowledge cycle if there are no higher priority devices requesting interrupts. The IUS bit must be cleared by the CPU. This is usually done at the end of the corresponding interrupt service routine. Within the SCC portion of the ISCC there are three types of interrupts: Transmit, Receive, and External/Status. Each interrupt type is enabled under program control with Channel A having higher priority than Channel B, and with Receive, Transmit, and External/Status interrupts prioritized in that order within each channel. When the Transmit interrupt is enabled, the CPU is interrupted when the transmit buffer becomes empty. This implies that data has shifted from the transmit buffer to the transmitter, thus emptying the transmit buffer. When enabled, the receiver interrupts the CPU in one of three ways: 1. Interrupt on First Receive Character or Special Receive Condition 2. Interrupt on All Receive Characters or Special Receive Condition 3. Interrupt on Special Condition Only Interrupt on First Character or Special Condition, and Interrupt on Special Condition Only, are typically used when doing block transfers with the DMA. A Special Receive Condition is one of the following: receiver overrun, framing error in Asynchronous mode, end-of-frame in SDLC mode and, optionally, a parity error. The Special Receive Condition interrupt is different from an Ordinary Receive Character Available interrupt only by the status placed in the vector during the Interrupt Acknowledge cycle. In Interrupt on First Receive Character, an interrupt occurs from Special Receive Conditions any time after the First Receive Character interrupt. The main function of the External/Status interrupt is to monitor the signal transitions of the /CTS, /DCD, and /SYNC pins; however, an External/Status interrupt is also 2-4 caused by a Transmit Underrun condition, or a zero count in the baud rate generator, or by the detection of a Break (Asynchronous mode), Abort (SDLC mode) or EOP (SDLC Loop mode) sequence in the data stream. The interrupt caused by the Abort or EOP has a special feature allowing the ISCC to interrupt when the Abort or EOP sequence is detected or terminated. This feature facilitates the proper termination of the current message, correct initialization of the next message, and the accurate timing of the Abort condition in external logic. 2.3.3 DMA Interrupts Each DMA in the ISCC has two sources of interrupt, which share an IP bit and an IUS bit, but have independent enables: Terminal Count and Abort. The Abort interrupt is generated when an active DMA channel is forced to terminate its transfers because /BUSACK is de-asserted during a transfer. The Terminal Count interrupt is generated when the DMA transfer count reaches zero. The DMA channels themselves are prioritized in a fixed order: Receive A, Transmit A, Receive B, and Transmit B. When DMA transfers are used, the on-chip DMA channels transfer data directly to the transmit buffers or directly from the receive buffers. No other transfers are possible (for initialization, for example). The request signals from the receivers and transmitters are hard-wired to the request inputs of the DMA channels internally. Each DMA channel provides a 32-bit address which is either incremented or decremented with a 16-bit transfer length. Whenever a DMA channel receives a request from its associated receiver or transmitter and the DMA channel is enabled, the ISCC activates the /BUSREQ signal. Upon receipt of an active /BUSACK, the DMA channel transfers data between memory and the SCC cell. This transfer continues until the receiver or transmitter stops requesting a transfer or until the terminal count is reached, or /BUSACK is deactivated. The four DMA channels operate independently when the Request Per Channel option is selected; otherwise, all requests pending at the time of bus acquisition will be serviced before the bus is released. Each DMA channel is independently enabled and disabled. Z16C35 Z16C35 ISCCTM User's Manual Interfacing the ISCCTM 2.4 REGISTER ACCESS ISCC registers may be accessed explicitly, directly or indirectly. Explicit addressing occurs only for three registers in the ISCC: these are the Bus Configuration Register (for the first write after a hardware reset), the RDR (Receive Data Register) by a fly-by DMA read, and the TDR (Transmit Data Register) by a fly-by DMA write. In the non-multiplexed bus case, only WR0/RR0 of the SCC cell and only the Channel Command/Address Register of the DMA cell are accessed directly. Other registers are accessed using the pointers in these directly accessed registers. In the multiplexed bus case, all registers (except the WR0, RR0 and CCAR) are accessed through a two step address/read-write bus transaction. In this case there are two options available for address decoding: shift right and shift left. These options are independently selectable for both the SCC cell and the DMA cell. 2.4.1 SCC Cell Register Access, Multiplexed Bus The registers in the ISCC in the multiplexed bus mode are addressed via the address on AD7-AD0 which is latched by the rising edge of /AS. As discussed in the paragraphs below, the address contains a bit to select the SCC cell channel (A or B). Although this selection is in the address, the A1/A//B input remains active and must be set to select Channel A for the selection bit in the AD7-AD0 address to function correctly. Conversely, the A1/A//B pin may also be used to select the channel instead of the bit in the AD7AD0 address. In this case, the bit in the AD7-AD0 address must be set to select Channel A for the A1/A//B input to function correctly. There are two address decoding modes: shift left and shift right. In shift left mode, the register address is decoded from AD5-AD1. This mode is set by a hardware reset. In the shift left mode, the register address itself is placed on AD4-AD1 and the Channel Select bit, A/B, is decoded from AD5. The register map for this case is shown in Table 2-2. Table 2-2. SCC Cell Address Map, Multiplexed Bus Mode, Shift Left Address AD5-AD1 10000 10001 10010 10011 10100 Write WR0A WR1A WR2 WR3A WR4A Read RR0A RR1A RR2A RR3A (RR0A) 10101 10110 10111 11000 11001 WR5A WR6A WR7A WR8A WR9 (RR1A) (RR2A) (RR3A) RR8A (RR13A RR13A) 11010 11011 11100 11101 11110 11111 WR10A WR10A WR11A WR11A WR12A WR12A WR13A WR13A WR14A WR14A WR15A WR15A 2 RR10A RR10A (RR15A RR15A) RR12A RR12A RR13A RR13A (RR10A RR10A) RR15A RR15A Note: The above table applies to Channel "B" also. In Shift Right Mode, bits 0-1 in WR0A controls which bits will be decoded to form the register address. It is placed in this register to simplify programming when the current state of the Shift Right/Shift Left bit is not known. The register address is decoded from AD4-AD0. The Shift Right/Shift Left bit is written via command to make the software writing to WR0 independent of the state of the Shift Right/Shift Left bit. AD4-AD0 is the actual register address and AD0 determines the channel selection (A//B). The register map is shown in Table 2-3. Because the ISCC SCC Cell does not contain 16 read registers, the decoding of the read registers is not complete; this is indicated in Table 2-2 and Table 2-3 by parentheses around the register name. These addresses may also be used to access the read registers. Note also that in the multiplexed bus mode, only one WR2 and WR9 are shown in the address map; these registers may be written from either SCC cell channel. 2-5 Z16C35 Z16C35 ISCCTM User's Manual Interfacing the ISCCTM 2.4 REGISTER ACCESS (Continued) Table 2-3. SCC Cell Address Map, Multiplexed Bus Mode, Shift Right Address AD4-AD0 00000 00001 00010 00011 00100 Write WR0B WR0A WR1B WR1A WR2 Read RR0B RR0A RR1B RR1A RR2B 00101 00110 00111 01000 01001 WR2 WR3B WR3A WR4B WR4A RR2A RR3B RR3A RR0B RR0A 01010 01011 01100 01101 01110 WR5B WR5A WR6B WR6A WR7B (RR1B) (RR1A) RR2B RR2A (RR3B) 01111 10000 10001 10010 10011 WR7A WR8B WR8A WR9 WR9 (RR3A) RR8B RR8A (RR13B RR13B) (RR13A RR13A) 10100 10101 10110 10111 11000 WR10B WR10B WR10A WR10A WR11B WR11B WR11A WR11A WR12B WR12B RR10B RR10B RR10A RR10A (RR15B RR15B) (RR15A RR15A) RR12B RR12B 11001 11010 11011 11100 WR12A WR12A WR13B WR13B WR13A WR13A WR14B WR14B RR12A RR12A RR13B RR13B RR13A RR13A (RR10B RR10B) 11101 11110 11111 WR14A WR14A WR15B WR15B WR15A WR15A (RR10A RR10A) RR15B RR15B RR15A RR15A 2-6 2.4.2 SCC Cell Register Access, Non-Multiplexed Bus The registers in the SCC cell in the non-multiplexed bus mode are accessed in a two-step process, using a Register Pointer to perform the addressing. To access a particular register, the pointer bits must be set by writing to WR0 bits 2, 1, and 0 and, if required, using the Point High command to extend the three bit pointer to registers 8 through 15. This write to WR0 to set the pointer bits may be done in either channel. There is only one pointer register and it is used for both A and B channels. After the pointer bits are set, the next read or write cycle to the SCC cell will access the desired register in the channel selected during this read or write cycle. At the conclusion of this read or write cycle, the pointer bits are reset to "0s," so that the next access will be to WR0. The fact that the pointer bits are reset to "0," unless explicitly set otherwise, means that WR0 and RR0 may also be accessed in a single cycle. That is, it is not necessary to write the pointer bits with "0" before accessing WR0 or RR0. There are three pointer bits in WR0, and these allow access to the registers with addresses 0 through 7. Note that a command may be written to WR0 at the same time that the pointer bits are written. To access the registers with addresses 8 through 15, a special command must accompany the pointer bits; WR0(4-3)=001. This precludes concurrently issuing a command when pointing to these registers. The register map for the ISCC in the non-multiplexed bus mode is shown in Table 2-4 below. If, for some reason, the state of the pointer bits is unknown, they may be reset to "0" by performing a read cycle of the SCC cell. Once the pointer bits have been set, the desired channel is selected by the state of the A1/A//B pin during the actual read or write of the desired SCC cell register.) Z16C35 Z16C35 ISCCTM User's Manual Interfacing the ISCCTM Table 2-4. SCC Cell Register Address Map Using Pointer (Non-multiplexed Bus Mode) Using Null Command Table 2-5. SCC Cell Reset Value Register Hardware Reset Channel Reset WR0 WR1 WR2 WR3 WR4 00000000 00x00x00 xxxxxxxx xxxxxxx0 xxxxx1xx 00000000 00x00x00 xxxxxxxx xxxxxxx0 xxxxx1xx WR5 WR6 WR7 WR9 WR10 0xx0000x xxxxxxxx xxxxxxxx 110000xx 00000000 0xx0000x xxxxxxxx xxxxxxxx xx0xxxxx 0xx00000 00001000 xxxxxxxx xxxxxxxx xx100000 11111000 xxxxxxxx xxxxxxxx xxxxxxxx xx1000xx 11111000 01xxx100 00000110 00000000 00000000 01xxx100 00000110 00000000 00000000 A1/A//B 0 0 0 0 Address D2 D1 D0 000 001 010 011 Write Register WR0B WR1B WR2 WR3B Read Register RR0B RR1B RR2B RR3B 0 0 0 0 100 101 110 111 WR4B WR5B WR6B WR7B (RR0B) (RR1B) (RR2B) (RR3B) 1 1 1 1 000 001 010 011 WR0A WR1A WR2 WR3A RR0A RR1A RR2A RR3A WR11 WR12 WR13 WR14 WR15 1 1 1 1 100 101 110 111 WR4A WR5A WR6A WR7A (RR0A) (RR1A) (RR2A) (RR3A) RR0 RR1 RR3 RR10 2.4.4 DMA Cell Registers Using Point High Command A1/A//B 0 0 0 0 Address D2 D1 D0 000 001 010 011 Write Register WR8B WR9 WR10B WR10B WR11B WR11B Read Register RR8B RR13B RR13B RR10B RR10B (RR15B RR15B) The DMA cell contains seventeen registers counting the Bus Configuration Register. All of these registers are read/write except the Bus Configuration Register (write only), the Channel Command Address Register (write only), the DMA Status Register (read only), the Interrupt Command Register (write only), and the Interrupt Status Register (read only). 0 0 0 0 100 101 110 111 WR12B WR12B WR13B WR13B WR14B WR14B WR15B WR15B RR12B RR12B RR13B RR13B (RR10B RR10B) RR15B RR15B The reset content of all of the DMA registers identified in the address map is all zeros. 1 1 1 1 000 001 010 011 WR8A WR9A WR10A WR10A WR11A WR11A RR8A (RR13A RR13A) RR10A RR10A (RR15A RR15A) The registers in the ISCC in the multiplexed bus mode are addressed via the address on AD7-AD0 which is latched by the rising edge of /AS. 1 1 1 1 100 101 110 111 WR12A WR12A WR13A WR13A WR14A WR14A WR15A WR15A RR12A RR12A RR13A RR13A (RR10A RR10A) RR15A RR15A 2.4.3 SCC Cell Register Reset Table 2-5 lists the contents of the SCC cell registers after a hardware reset and after a channel reset. 2.4.5 DMA Register Access, Multiplexed Bus There are two address decoding modes: shift left and shift right. In shift left mode, the register address is decoded from AD5-AD1. This mode is set by a hardware reset. In shift right mode, the register address is decoded from AD4-AD0. The shift right/shift left selection for the DMA is located in the Bus Configuration Register, bit D0. When set, this bit programs the Shift Right mode for the DMA and when reset, this bit programs the Shift Left mode. The address map for the DMA registers is shown in Table 2-6. This Table is also applicable to the non-multiplexed bus mode. 2-7 2 Z16C35 Z16C35 ISCCTM User's Manual Interfacing the ISCCTM 2.4 REGISTER ACCESS (Continued) Table 2-6. DMA Address Map Address* xxxxx 00000 00000 00001 00010 Name BCR CCAR DSR ICR IVR Description Bus Configuration Register Channel Command/Address Register (Write) DMA Status (Read) Interrupt Control Register Interrupt Vector Register 00011 00011 00100 00101 00110 ICSR ISR DER DCR Interrupt Command Register (Write) Interrupt Status Register (Read) DMA Enable/Disable Register DMA Control Register Reserved Address 00111 01000 01001 01010 01011 RDCRA RDCRA TDCRA TDCRA Reserved Address Receive DMA Count Register, Channel A (Low Byte) Receive DMA Count Register, Channel A (High Byte) Transmit DMA Count Register, Channel A (Low Byte) Transmit DMA Count Register, Channel A (High Byte) 01100 01101 01110 01111 10000 RDCRB RDCRB TDCRB TDCRB RDARA Receive DMA Count Register, Channel B (Low Byte) Receive DMA Count Register, Channel B (High Byte) Transmit DMA Count Register, Channel B (Low Byte) Transmit DMA Count Register, Channel B (High Byte) Receive DMA Address Register, Channel A (Bits 0-7) 10001 10010 10011 10100 10101 RDARA RDARA RDARA TDARA TDARA Receive DMA Address Register, Channel A (Bits 8-15) Receive DMA Address Register, Channel A (Bits 16-23) Receive DMA Address Register, Channel A (Bits 24-31) Transmit DMA Address Register, Channel A (Bits 0-7) Transmit DMA Address Register, Channel A (Bits 8-15) 10110 10111 11000 11001 11010 11011 TDARA TDARA RDARB RDARB RDARB RDARB Transmit DMA Address Register, Channel A (Bits 16-23) Transmit DMA Address Register, Channel A (Bits 24-31) Receive DMA Address Register, Channel B (Bits 0-7) Receive DMA Address Register, Channel B (Bits 8-15) Receive DMA Address Register, Channel B (Bits 16-23) Receive DMA Address Register, Channel B (Bits 24-31) 11100 11101 11110 11111 TDARB TDARB TDARB TDARB Transmit DMA Address Register, Channel B (Bits 0-7) Transmit DMA Address Register, Channel B (Bits 8-15) Transmit DMA Address Register, Channel B (Bits 16-23) Transmit DMA Address Register, Channel B (Bits 24-31) Note: * Address in this Table is AD5-AD1 in the Multiplexed Bus with the Shift Left mode selected, AD4-AD0 in the Multiplexed Bus with the Shift Right mode selected, and D4 -D0 of the Channel Command/Address Register in the Non-multiplexed Bus mode. 2-8 Z16C35 Z16C35 ISCCTM User's Manual Interfacing the ISCCTM 2.4.6 DMA Register Access, Non-Multiplexed Bus Mode The registers in the DMA cell in the non-multiplexed bus mode are accessed in a two-step process, using a Register Pointer to perform the addressing. To access a particular register, the pointer bits must be set by writing to the Channel Command /Address Register bits 4 through 0. After the pointer bits are set, the next read or write cycle to the DMA cell will access the desired register. At the conclusion of this read or write cycle, the pointer bits are reset to "0s," so that the next access will be to the Channel Command/Address Register. The fact that the pointer bits are reset to "0," unless explicitly set otherwise, means that the Channel Command/Address Register may be accessed in a single cycle. That is, it is not necessary to write the pointer bits with "0" before accessing the Channel Command/Address Register. This permits single access DMA enabling and resetting the highest IUS through the encoded DMA Commands. 2.4.7 Notes on Pointer Accesses The non-multiplexed bus accesses are accomplished as described in the preceding paragraphs using the DMA pointer for the DMA cell and the SCC cell pointer for channels A and B. These two pointers are completely independent. If one of these pointers is written to with a pointer value in preparation for a read or write to the selected register, the pointer will hold its value until the corresponding cell is accessed. For example, suppose the SCC cell pointer is written to in preparation to read an SCC cell register in the next (or even subsequent) software program steps. Before this SCC cell read takes place, a DMA interrupt occurs and the program enters the interrupt service routine prior to the SCC register read. In the interrupt service routine, several DMA register accesses are made. When the program exits the interrupt service routine and returns to the interrupted process, the register access to the SCC cell register proceeds correctly; the pointer was left unaltered. A converse situation is true for the DMA cell. It should be clear, however, that if an interrupt routine is invoked between the pointer write and the register access, there can be conflict if the same cell is accessed in the interrupt service routine. Assume in the above example that the interrupt service routine accesses the SCC cell also. Since the pointer has already been written, a second write (the one in the interrupt service routine) will not write to the pointer in WR0 but will write to the pointed to register. Subsequent register access will also be incorrect. This suggests that the pointer write and subsequent register access be an uninterruptable pair and that the SCC Cell and DMA cell or the processor interrupts be disabled during the register access sequence. 2-9 2 2-10 USER'S MANUAL 3 CHAPTER 3 ISCCTM DMA AND ANCILLARY SUPPORT CIRCUITRY 3.1 INTRODUCTION The most important feature of the ISCC other than SCC cell is the integrated, four channel DMA controller. As in the original SCC, the serial channels of the ISCC are support- ed by ancillary circuitry for generating clocks and performing data encoding and decoding. This chapter presents a description of these functional blocks. 3.2 DMA The ISCCTM contains four independent DMA Channels, one for each receiver and transmitter. The DMA channels operate in fly-by mode; a 32-bit transfer address is generated along with the bus acquisition signals for executing the DMA transfer. Each DMA consists of a 32-bit address counter, a 16-bit (transfer) counter, and the required sequencing and control circuitry. Per Channel option has been selected, then the bus will be released and subsequently re-requested for each channel. At the completion of the block transfer (terminal count reached), an interrupt will be generated, if enabled. If selected, the interrupt vector will indicate the interrupt source according to Table 3-1. Table 3-1. DMA Interrupt Vector Modification The DMA is set up by initializing the address resisters with the starting address of the DMA transfer and the count registers for the length of the block. Following this, the option to increment or decrement the address after a transfer is selected. Other DMA selections that must be programmed include the DMA priority, if separate bus requests are to be made for each DMA channel, the programming of the interrupt vector and the option to include interrupt status in the vector. Note that a no vector interrupt option is also possible. Following this, the Interrupt On Abort is programmed as desired, the individual channel interrupt enables are programmed, the Master Interrupt Enable is set (if interrupts are used), and lastly the appropriate DMA channels are enabled. 3.2.1 Receiver DMA Operation Assuming the receiver has been appropriately set up, the DMA request will be made when the receive FIFO contains a byte and will continue to hold the bus and transfer bytes until the FIFO is empty. Once started, the DMA for the channel continues until the FIFO is empty even though a request from a higher priority DMA channel arises. Upon completion of the current DMA channel service, the next highest priority DMA channel commences its operation. The ISCC continues to hold the bus until all pending DMA requests have been served. Note that if the Bus Request IV3 0 0 0 0 IV2 0 0 1 1 IV1 0 1 0 1 1 1 1 1 0 0 1 1 0 1 0 1 Interrupt Source No Interrupt Pending Not Possible Not Possible Not Possible Rx A Interrupt Pending Rx B Interrupt Pending Tx A Interrupt Pending Tx B Interrupt Pending An Interrupt Pending only modifies the interrupt vector if the corresponding Interrupt Enable bit is set. Note that software may have to test status bits to determine if the channel interrupt is due to terminal count or an abort. When the receive DMA enable bit is set, a DMA request is made if the receive FIFO contains a character at the time, or no request will be made until a character enters the receive FIFO. Note that DMA requests will follow the state of the receive FIFO even though the receiver is disabled. Thus, if the receiver is disabled and the DMA is still enabled, the DMA will transfer the previously received data correctly. In this mode the DMA requests directly follow the state of the receive FIFO. This operation is essentially equivalent to the DMA requests following the state of the 3-1 Z16C35ISCCTM Z16C35ISCCTM User's Manual ISCCTM DMA and Ancillary Support Circuitry Receive Character Available bit in the SCC cell in Read Register 0. The SCC cell will not generate a DMA request in the case of a special receive condition in the Receive Interrupt on First Character or Special Condition mode, or the Receive Interrupt on Special Condition Only mode. In these two interrupt modes any receive character with a special receive condition is locked at the top of the FIFO until an Error Reset command is issued. This character in the receive FIFO would ordinarily cause additional DMA Requests after the first time it is read. However, the logic in the SCC cell guarantees no extra DMA transfers by terminating DMA requests after the time the character with the special receive condition is read, and the FIFO locked. DMA requests are held off until after the Error Reset command has been issued. Once the FIFO is locked, it allows the checking of the Receive Error FIFO (RR1) to find the cause of the error. Locking the data FIFO therefore, will stop the error status from popping out of the Receive Error FIFO. Also, since DMA request will become inactive, the interrupt (Special Condition) can be serviced. Once the FIFO is unlocked by the Error Reset command, DMA requests again follow the state of the receive FIFO. 3.2.2 Transmitter DMA Operation With the DMA enabled, the status of an empty transmitter FIFO triggers the DMA to request the bus and begin DMA transfer to the transmit FIFO. Once this DMA channel is selected for service, DMA transfers continue until the transmit FIFO is full (or until terminal count is reached if there are not enough bytes remaining to fill the FIFO). Once started, the DMA for the channel continues until the FIFO is full even though a request from a higher priority DMA channel arises. Upon completion of the current DMA channel service, the next highest priority DMA channel commences its operation. The ISCC continues to hold the bus until all pending DMA requests have been served. Note that if the Bus Request Per Channel option has been selected, then the bus will be released and subsequently re-requested for each channel. At the completion of the block transfer (terminal count reached), an interrupt will be generated, if enabled. If selected, the interrupt vector will indicate the interrupt source according to Table 3-1. An Interrupt Pending only modifies the interrupt vector if the corresponding Interrupt Enable bit is set. Note that software may have to test status bits to determine if the channel interrupt is due to terminal count or an abort. Note that the DMA request will follow the state of the transmit FIFO even though the transmitter is disabled. Thus, if the DMA is enabled, the DMA may write data to the SCC cell before the transmitter is enabled. This will not cause a problem in Asynchronous mode but may cause problems in Synchronous mode because the ISCC will send data in preference to flags or sync characters. Thus a data character in the transmit FIFO may get transmitted prior to the frame sync character or opening flag. It may also complicate the CRC initialization, which cannot be done until after the transmitter is enabled. DMA requests essentially follow the Tx Buffer Empty bit in the SCC cell Read Register 0. 3.3 BAUD RATE GENERATOR The Baud Rate Generator (BRG) is essential for asynchronous communications. Each channel in the ISCC contains a programmable baud rate generator. Each generator consists of two 8-bit, time-constant registers forming a 16-bit time constant, a 16-bit down counter, and a flip-flop on the output that makes the output a square wave. On start-up, the flip-flop on the output is set High, so that it starts in a known state, the value in the time-constant register is loaded into the counter, and the counter begins counting down. When a count of zero is reached, the output of the baud rate generator toggles, the value in the time-constant register is loaded into the counter, and the process starts over. A block diagram of the baud rate generator is shown in Figure 3-1. The time-constant can be changed at any time, but the new value does not take effect until the next load of the counter (i.e., after zero count is reached). No attempt is made to synchronize the loading of a new time-constant with the clock used to drive the generator. 3-2 When the time-constant is to be changed, the generator should be stopped first by writing to an enable bit in WR14. After loading the time constant, the BRG can be started again. This ensures the loading of a correct time constant, but loading will not be taking place until zero count or a reset occurs. If neither the transmit clock nor the receive clock are programmed to come from the /TRxC pin, the output of the baud rate generator may be made available for external use on the /TRxC pin. The clock source for the baud rate generator is selected by bit D1 of WR14. When this bit is set to "0," the baud rate generator uses the signal on the /RTxC pin as its clock, independent of whether the /RTxC pin is a simple input or part of the crystal oscillator circuit. When this bit is set to "1," the baud rate generator is clocked by PCLK. To avoid metastable problems in the counter, this bit should be changed only while the baud rate generator is disabled, Z16C35ISCCTM Z16C35ISCCTM User's Manual ISCCTM DMA and Ancillary Support Circuitry since arbitrarily narrow pulses can be generated at the output of the multiplexer when it changes state. The BRG is enabled while bit DO of WR14 is set to 1 and disabled while this bit is set to 0 and it is disabled after a hardware reset. To prevent metastable problems when the baud rate generator is first enabled, the enable bit is synchronized to the baud rate generator clock. This introduces an additional delay when the baud rate generator is first enabled. This is shown in Figure 3-2. The baud rate generator is disabled immediately when bit D0 of WR14 is set to "0," because the delay is only necessary on start-up. The baud rate generator may be enabled and disabled on the fly, but this delay on start-up must be taken into consideration. Figure 3-1. Baud Rate Generator Figure 3-2. Baud Rate Generator Start-Up 3-3 3 Z16C35ISCCTM Z16C35ISCCTM User's Manual ISCCTM DMA and Ancillary Support Circuitry 3.3 BAUD RATE GENERATOR (Continued) The formulas relating the baud rate to the time-constant and vice versa are shown below. The clock mode in the formula is the ratio of the receive clock applied to the ISCC relative to the data rate. The ISCC may be programmed to accept a receive clock that is one, sixteen, thirty-two, or sixty-four times the data rate (refer to the description of WR4 and the descriptions in Chapter 4). Clock Frequency Time Constant = -2 2*(Clock Mode)*(Baud Rate) Clock Frequency Baud Rate = 2*(Clock Mode)*(Time Constant +2) In these formulas, the baud rate generator clock frequency (PCLK or /RTxC) is in Hertz, the desired baud rate in bits/second and the time constant is dimensionless. The example in Table 3-1 assumes a 2.4576 MHz clock (from /RTxC) clock factor of 16 and shows the time constant for a number of popular baud rates. For example: 2.4576 X 10 6 TC = = 510 2X16 X 150 3-4 Table 3-2. Baud Rates for 2.4576 MHz Clock and 16x Clock Factor Time Constant Decimal Hex 0 0000 2 0002 6 0006 Baud Rate 38400 19200 9600 14 30 62 000E 001E 003E 4800 2400 1200 126 254 510 007E 00FE 01FE 600 300 150 Initializing the baud rate generator is done in three steps. First, the time-constant is determined and loaded into WR12 and WR13. Next, the processor must select the clock source for the baud rate generator by setting bit D1 of WR14. Finally, the baud rate generator is enabled by setting bit D0 of WR14 to "1." Note that the first write to WR14 is not necessary after a hardware reset if the clock source is the /RTxC pin. This is because a hardware reset automatically selects the /RTxC pin as the baud rate generator clock source. Z16C35ISCCTM Z16C35ISCCTM User's Manual ISCCTM DMA and Ancillary Support Circuitry 3.4 DATA ENCODING/DECODING The ISCC provides four different data encoding methods, selected by bits D6 and D5 in WR10. An example of these four encoding methods is shown in Figure 3-3. Any encoding method may be used in any X1 mode in the DATA 1 1 0 0 ISCC, asynchronous or synchronous. The data encoding selected is active even though the transmitter or receiver may be idling or disabled. The data encoding methods are shown in Figure 3-3. 1 0 Bit Cell Level: NRZ High = 1 Low = 0 NRZI No Change = 1 Change = 0 FM1 (Biphase Mark) FM0 (Biphase Space) MANCHESTER Figure 3-3. Data Encoding Methods In NRZ, encoding a "1" is represented by a HIGH level and a "0" is represented by a LOW level. In this encoding method, only a minimal amount of clocking information is available in the data stream in the form of transitions on bit-cell boundaries. In an arbitrary data pattern, this may not be sufficient to generate a clock for the data from the data itself. In FM0 encoding, also known as biphase space, a transition is present on every bit cell boundary and an additional transition may be present in the middle of the bit cell. In FM0, a "1" is sent as no transition in the center of the bit cell and a "0" is sent as a transition in the center of the bit cell. FM0 encoded data contains sufficient information to recover a clock from the data. In NRZI, encoding a "1" is represented by no change in the level and a "0" is represented by a change in the level. As in NRZ, only a minimal amount of clocking information is available in the data stream, in the form of transitions on bit cell boundaries. In an arbitrary data pattern this may not be sufficient to generate a clock for the data from the data itself. In the case of SDLC, where the number of consecutive "1s" in the data stream is limited, a minimum number of transitions to generate a clock are guaranteed. Manchester encoding, which is not directly supported, always produces a transition at the center of the bit cell. If the transition is Low to High, the bit is "0." If the transition is High to Low, the bit is "1." ISCC can be used to decode Manchester (biphase level) data by using the DPLL in the FM mode and programming the receiver for NRZ data. (See section 3.5.3.) In FM1 encoding, also known as biphase mark, a transition is present on every bit cell boundary, and an addition transition may be present in the middle of the bit cell. In FM1 a "0" is sent as no transition in the center of the bit cell and a "1" is sent as a transition in the center of the bit cell. FM1 encoded data contains sufficient information to recover a clock from the data. The data encoding method should be selected in the initialization procedure before the transmitter and receiver are enabled, but no other restrictions apply. Note, in Figure 33, that in NRZ and NRZI the receiver samples the data only on one edge. However, in FM1 and FM0 the receiver samples the data on both edges. Also, as shown in Figure 6-4, the transmitter defines bit cell boundaries by one edge in all cases and uses the other edge in FM1 and FM0 to create the mid-bit transition. 3-5 3 Z16C35ISCCTM Z16C35ISCCTM User's Manual ISCCTM DMA and Ancillary Support Circuitry 3.5 DIGITAL PHASE-LOCKED LOOP (DPLL) Each channel of the SCC cell contains a digital phaselocked loop that can be used to recover clock information from a data stream with NRZI, FM or NRZ encoding. The DPLL is driven by a clock nominally 32 (NRZI) or 16 (FM) times the data rate. The DPLL uses this clock, along with the data stream, to construct a receive clock for the data. This clock can then be used as the ISCC receive clock, the transmit clock, or both. Figure 3-4 shows a block diagram of the digital phaselocked loop. It consists of a 5-bit counter, an edge detector, and a pair of output decoders. The clock for the DPLL comes from the output of a two-input multiplexer, and the two outputs go to the transmitter and receive clock multiplexers. The DPLL is controlled by the seven commands that are encoded in bits D7, D6 and D5 of WR14. Edge Detector Count Modifier Decode Receive Clock 5-Bit Counter RxD Decode Transmit Clock Figure 3-4. Digital Phase Lock Loop The clock for the DPLL is selected by two of the commands in WR14, that is: WR14 (7-5) = 100 WR14 (7-5) = 101 BRG Clock Source /RTxC Pin Clock Source The first command selects the baud rate generator as the clock source. The other