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Y51 h 85c

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Y51 h 85c

Abstract: Y176 2.4 to 3.6V, V0=+15.0 to +30.0V, TA = -30 to 85°C , 2.4 to 3.6V, V0=+15.0 to +30.0V, TA = -30 to 85°C , to VSS, VDD = +3.0 to +3.6V, V0=+15.0 to +30.0V, TA = -30 to 85°C , , TA = 35 to 85°C , , TA = -35 to 85°C
Solomon Systech
Original

Y51 h 85c

Abstract: Y52 h 85c 85°C) Symbol TWLP TWLPH Parameter Shift clock period Shift clock H pulse width TSU TH TR , NC Y X S S D 1702Z P ad 1,2,3,. -> 102 G old B um ps face up D ie S ize: D ie H eig h t , Y35 Y36 Y37 Y38 Y39 Y40 Y41 Y42 Y43 Y44 Y45 Y46 Y47 Y48 Y49 Y50 Y51 Y52 Y53 Y54 , Y44 Y45 Y46 Y47 Y48 Y49 Y50 Y51 Y52 Y53 Y54 Y55 Y56 Y57 Y58 Y59 Y60 Y61 Y62 Y63 , Y41 Y42 Y43 Y44 Y45 Y46 Y47 Y48 Y49 Y50 Y51 Y52 Y53 Y54 Y55 Y56 Y57 Y58 Y59 Y60
Solomon Systech
Original
SSD1702T1 SSD1702T2 SSD1702 Y51 h 85c Y52 h 85c Y176 y231 Y230 Y129 SSD1702T3

Y51 h 85c

Abstract: clarostat 44 .-40°C to +85°C Lead Soldering Temperature , ' ft !o h Supply Voltage Range Supply Voltage Range (output pin) Supply Current Drain 4.75 , SUFFIX COMBINATIONS -Y55 · · · -Y51 · · · -Y5F · · · · · · · -Y 11 -Y1F -YFF OptoSwitch · 1500
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OCR Scan
clarostat 44 clarostat 44 series 800-448-2900 clarostat "series 44" s960 transistor y51 S-960/970

Y51 h 85c

Abstract: RY5FD01D ]ned i!lleilsioll, str~lcttlre and ch~lracteristics of 1{ Y51''1I[) 111 iiltrared , +Ll:33fl H 5. Truth Table InQut Tx output Tnfr:irf:({ 1 ,ipht, in I,rcn Rx out , Page -1 I I 7. Rating and Specifications 7 ­ 1 : I{ating h Nlaximurn rating 7­2 : 1 , transnllsslon wave foru~ of H level at IR TX kbps ter]ninal. The frequency is less than lkHz , 1 g? ~~ Ill : l) SIR mode transmission (Itx otlt : H, Tx In : I)llty :i/l(i 115.2kbPs
Sharp
Original
RY5FD01D Y51i marking 1Hc Y5FD01D ry5f RY5FD

Y51 h 85c

Abstract: y249 Y48 Y49 Y50 Y51 Y52 Y53 Y54 Y55 Y56 Y57 Y58 Y59 Y60 Y61 Y62 Y63 Y64 Y65 Y66 Y67 , Y42 Y43 Y44 Y45 Y46 Y47 Y48 Y49 Y50 Y51 Y52 Y53 Y54 Y55 Y56 Y57 Y58 Y59 Y60 Y61 , between Segment and Common mode. It should be set to H when segment mode is used. . It should be , set to L, 4-bit parallel input mode is selected. When MD is set to H, 8-bit parallel input mode is , mode operation is selected. When MD is set to H, Dual mode operation is selected. In Single mode
Solomon Systech
Original
y249 Y298 Y248 ST 62160 Y306 Y268P SSD1703

4560 opamp

Abstract: Y51 h 85c the SAMPLE-HOLD circuit when PS = "H" and becomes HIGH IMPEDANCE when PS = "L". VA,VB,VC Video , SAMPLE-HOLD circuit. Samples in VB, VA, VC order and VC, VB, VA order when it is "H" and "L", respectively , "H" and sets DI01 to start pulse signal input and DI02 to start pulse signal output. Samples video , and output OPOperation-Change Input AMP operation. SAM SAMPLING MODE Change Input ( H: Regular , Setting Input POWER SAVE Setting Terminal. At "H", the video signal output pin outputs the video
Samsung Electronics
Original
240CH KS0606 4560 opamp 7377 y133 Y164 Y1Y240Y240Y1

Y51 h 85c

Abstract: Y107 the SAMPLE-HOLD circuit when PS = "H" and becomes HIGH IMPEDANCE when PS = "L". VA,VB,VC Video , SAMPLE-HOLD circuit. Samples in VB, VA, VC order and VC, VB, VA order when it is "H" and "L", respectively , "H" and sets DI01 to start pulse signal input and DI02 to start pulse signal output. Samples video , and output OPOperation-Change Input AMP operation. SAM SAMPLING MODE Change Input ( H: Regular , Setting Input POWER SAVE Setting Terminal. At "H", the video signal output pin outputs the video
Samsung Electronics
Original
Y107 Y134 transistor+Bc+542 Y228 y-214 DI01

4322 191

Abstract: Y201 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 NAME Y51 Y52 Y53 Y54 Y55 , level H", data is read sequentially from Y1 to Y240. Control input pin for output deselect level . , selection pin . When set to VSS level "L", 8-bit parallel input mode is set. . When set to VDD level "H , `H", segment mode is set. EIO1 EIO2 Input / output pin for chip selection . When L/R input is , level `H", EIO1 is set for input, and EIO2 is set for output. . During output. set to "H" while LP
Samsung Electronics
Original
S6B0796 4322 191 Y201 TBD 234 V12 Y122 Y102

y148

Abstract: Y143 94 95 96 97 98 99 100 NAME Y51 Y52 Y53 Y54 Y55 Y56 Y57 Y58 Y59 Y60 Y61 Y62 Y63 , , data is read sequentially from Y160 to Y1. . When set to VDD level H", data is read sequentially from , to VDD level "H", 8-bit parallel input mode is set. . The relationship between the display data and , `H", segment mode is set. Input/output pin for chip selection . When L/R input is at VSS level `L", EIO1 is set for output, and EIO2 is set for input. . When L/R input is at VDD level `H", EIO1 is set
Samsung Electronics
Original
S6B0794 y148 Y143 Y59 r 130 LCD S6B0794 display 7 seg driver

Y106

Abstract: Y51 h 85c 89 90 91 92 93 94 95 96 97 98 99 100 NAME Y51 Y52 Y53 Y54 Y55 Y56 Y57 Y58 Y59 , level H", data is read sequentially from Y1 to Y160. Control input pin for output deselect level . , input mode is set. . When set to VDD level "H", 8-bit parallel input mode is set. . The relationship , 12 Segment mode / common mode selection pin . When set to VDD level `H", segment mode is set , EIO2 is set for input. . When L/R input is at VDD level `H", EIO1 is set for input, and EIO2 is set
Samsung Electronics
Original
KS0794 Y106 Y147 y105 y141 Y103 Y138

ic 4069 pin configuration

Abstract: 4069 IC 14 pins is read sequentially from Y160 to Y1. When set to VDD level "H", data is read sequentially from Y1 , When set to VSS level "L", 4-bit parallel input mode is set. When set to VDD level "H", 8-bit parallel , Functional Operations. Segment mode/common mode selection pin When set to VDD level "H", segment mode is , , and EIO2 is set for input. When L/R input is at VDD level "H", ElO1 is set for input, and EIO2 is set for output. During output, set to "H" while LP · XCK is "H" and after 160 bits of data have been read
Sitronix
Original
ST8016 ic 4069 pin configuration 4069 IC 14 pins iC 4069 14 pin Sitronix ST8016 Pin Diagram of ic 4069 Y160- 2000-M 2000-J 2000-A 2000-O

Y184

Abstract: Y229 is read sequentially from Y240 to Y1. When set to VDD level "H", data is read sequentially from Y1 , When set to VSS level "L", 8-bit parallel input mode is set. When set to VDD level "H", 4-bit parallel , Functional Operations. Segment mode/common mode selection pin When set to VDD level "H", segment mode is , , and EIO2 is set for input. When L/R input is at VDD level "H", ElO1 is set for input, and EIO2 is set for output. During output, set to "H" while LP · XCK is "H" and after 240 bits of data have been read
Sitronix
Original
ST8024 Y184 Y229 st8024 sitronix XCK 240 Sitronix LCD common driver Y240- Y121- 269-PIN 2000/D ST8024TCP

4525 GE

Abstract: ST8024C is read sequentially from Y240 to Y1. When set to VDD level "H", data is read sequentially from Y1 , is set. When set to VDD level "H", 4-bit parallel input mode is set. Refer to section 7.2.2. Segment mode/common mode selection pin When set to VDD level "H", segment mode is set. Input/output pins , input. When L/R input is at VDD level "H", ElO1 is set for input, and EIO2 is set for output. During output, set to "H" while LP · XCK is "H" and after 240 bits of data have been read, set to "L" for one
Sitronix
Original
4525 GE ST8024C 5375-00 MD 202 SP 1191 342500

Y51 h 85c bo 35

Abstract: AJ25-AJ29 PAD DRIVE_CTRL H/S Input Equivalent Circuit H/S Output Equivalent Circuit Figure 6 , 26 28 L 21 22 24 K 17 18 20 J 13 14 16 VCC 10 12 H , High-Speed Data Output Channel 50, True. Y51 W2 O CML High-Speed Data Output Channel 51, True
Vitesse Semiconductor
Original
VSC837 Y51 h 85c bo 35 AJ25-AJ29 YN40 AG1A G52309

NT7702

Abstract: H117D2 , data is read sequentially from Y240 to Y1 " When set to VDD level "H", data is read sequentially from , set to VSS level "L", 8-bit parallel input mode is set " When set to VDD level "H", 4-bit parallel , mode selection pin " When set to VDD level "H", segment mode is set " When set to VSS level "L" , "L", EIO1 is set for output, and EIO2 is set for input " When L/R input is at VDD level "H", EIO1 is set for input, and EIO2 is set for output " During output, it is set to "H" while LP* XCK is "H" and
Novatek
Original
NT7702 NT7702H-TABF4 H117D2 4407SC 14nm2 Y239 lcd 240 128 ts NT7702H-BDT

TLD 521

Abstract: TO 521 MH "L", data is read sequentially from Y240 to Y1 " When set to VDD level "H", data is read sequentially , set to VDD level "H", 4-bit parallel input mode is set 6 NT7704 Segment mode continued Symbol , VDD level "H", segment mode is set " When set to VSS level "L", common mode is set Input/output pin , input " When L/R input is at VDD level "H", EIO1 is set for input, and EIO2 is set for output " During output, it is set to "H" while LP* XCK is "H" and then after 240-bits of data have been read, it is set
Novatek
Original
TLD 521 TO 521 MH Y12 305 Y215 d 529 d4-450 H30-52359-25 NT7704H-BDT NT7704H-TABF4

Y129

Abstract: nt7705 VSS level "L", data is read sequentially from Y240 to Y1 When set to VDD level "H", data is read , pin When set to VSS level "L", 8-bit parallel input mode is set When set to VDD level "H", 4 , Segment mode/common mode selection pin When set to VDD level "H", segment mode is set When set to , level "H", EIO1 is set for input, and EIO2 is set for output During output, it is set to "H" while LP* XCK is "H" and after 240-bits of data have been read, it is set to "L" for one cycle (from falling
Novatek
Original
NT7706 nt7705 lr3440 Y240 LCD 5310

ROW130

Abstract: 1.5 128x128 CSTN LCD . 57 Table 17 - Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 2.6V to 3.3V) . 58 ° Table 18 - Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 2.6V to 3.3V) . 59 ° Table 19 - Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 2.4V) . 60 ° Table 20 - Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 2.4V) . 61 ° Table 21 - Serial Timing Characteristics (TA = -40 to 85°C, VDD = 2.6V to 3.6V
Solomon Systech
Original
SSD1789A ROW130 1.5 128x128 CSTN LCD an 7591 7628-5.0 128x128 cstn 733 331

Y51 h 85c

Abstract: NT7701HTABF When set to VDD level "H", data is read sequentially from Y1 to Y160 Control input pin for output , set # When set to VDD level "H", 8-bit parallel input mode is set 7 NT7701 Segment mode continued Symbol S/C Function Segment mode/common mode selection pin # When set to VDD level "H , input. # When L/R input is at VDD level "H", EIO1 is set for input, and EIO2 is set for output. # During output, it is set to "H" while LP* XCK is "H" and after 160-bits of data have been read, it is set
Novatek
Original
NT7701HTABF md-2800 Y160 986M NT7701H-BDT NT7701H-TABF3

Y51 h 85c

Abstract: md-2800 VSS level "L", data is read sequentially from Y160 to Y1 # When set to VDD level "H", data is read , pin # When set to VSS level "L", 4-bit parallel input mode is set # When set to VDD level "H", 8 , Segment mode/common mode selection pin # When set to VDD level "H", segment mode is set. # When set to , VDD level "H", EIO1 is set for input, and EIO2 is set for output. # During output, it is set to "H" while LP* XCK is "H" and after 160-bits of data have been read, it is set to "L" for one cycle (from
Novatek
Original
nt7701htab 22-D-6 XCK J NT7701H-TAB
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