XAPP729 PPC405 MT48LC8M32B2 XC4VSX35 ML470 XC4VSX35FF668 DS426 SX35-FF668 - Datasheet Archive

 

R XAPP729 (v1.0.1) March 4, 2007 Interfacing a 64-Bit DDR Memory Bus to a 32-Bit Microprocessor Bus Author: Marc Defossez Summary

 

Application Note: Virtex-4 FPGA Family R XAPP729 XAPP729 (v1.0.1) March 4, 2007 Interfacing a 64-Bit DDR Memory Bus to a 32-Bit Microprocessor Bus Author: Marc Defossez Summary In today's processor, digital signal processor (DSP), and other applications, memory data widths can be 64 bits and higher. This application note shows how the 32-bit MicroBlazeTM processor can easily access these wide memories. This design is also suitable for use with the IBM PowerPCTM (PPC405 PPC405) processor because it connects to the On-chip Peripheral Bus (OPB). The reference design provides a modification to an existing Xilinx EDK SDRAM interface, enabling a 32-bit processor to access a 64-bit data bus. Introduction When available solutions are too wide or narrow, custom memory width designs are created by connecting standard memory devices together in parallel or serial configurations. This application note describes the modifications to the standard EDK 32-bit wide SDRAM interface, widening it to 64 bits. For the PPC405 PPC405 or MicroBlaze processor, the connected memory appears to be 32 bits wide, while in reality the memory is 64 bits wide. The reference design described in this application note uses two 32-bit SDRAMs configured in a 64-bit data setup. These memories share all control and address lines, as shown in Figure 1. In this design, the memory is always accessed in 64-bit mode, using two consecutive memory addresses from the processor. An access must first call the lower addressed 32-bit word followed by the address of the higher 32-bit word. The least-significant (LS) address bit is used as a multiplexer switch between even and odd addresses to the memory. All lower 32-bit data is stored in one SDRAM bank, and the higher 32-bit data is stored in the second SDRAM block. SDRAM_control SDRAM_address [11:0] SDRAM_data [63:0] MT48LC8M32B2 MT48LC8M32B2 SDRAM_2 Micron MT48LC8M32B2 MT48LC8M32B2 SDRAM_data [63:32] Micron SDRAM_data [31:0] SDRAM_1 X729_01_010506 Figure 1: 64-Bit Memory Setup © 2006­2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. XAPP729 XAPP729 (v1.0.1) March 4, 2007 www.xilinx.com 1 R Memory Configurations Memory Configurations Custom-width memory systems are built by interconnecting 32-bit memories. An economic and easy way to double the data bus is to share the address bus and all control signals. Using this method, the data bus is multiplied in size with each additional memory block, as shown in Figure 1. A disadvantage to this method is that the SDRAMs are accessed simultaneously. Data must be assembled and disassembled in the FPGA interface to the SDRAM. An advantage to this method is the easy setup for PCB layout. This method is tested using a VirtexTM-4 XC4VSX35 XC4VSX35 FPGA connected to a set of Micron SDRAMs (MT48LC8M32B2 MT48LC8M32B2: 2 Mb x 32 x 4 banks). "Appendix A," page 17 provides schematics of this setup. FPGA Interface The easiest way to test a memory on a given design is to use a processor system to write and read the memory and compare the results. A system build with the EDK development system cannot be used as provided because its SDRAM controller has a maximum width of 32 bits. There are two solutions to this design problem. One solution is to develop a new 64-bit SDRAM controller to connect into the EDK software. The second solution uses existing IP structures wherever possible. This application note uses the second solution. It describes how to modify the existing SDRAM controller to make a customized 64-bit version. The OPB_SDRAM controller is used because it can interconnect with the MicroBlaze and PPC processors. Solution For wide memories, the address bus and control signal bus remain unchanged as the data width increases. If needed, this concept can be used to construct wider data memories than the 64-bit interface derived from the existing SDRAM controller. This solution ensures that the processor in the FPGA can use its native 32-bit read and write operations as if it is accessing 32-bit memories. To access the 64-bit memory, the processor must issue a Low address (LS address bit = 0) followed by a consecutive High address (LS address bit = 1) for write and read operations. This is not a limitation for this type of memory application, however, for normal 32-bit memory access it can be a limitation since two memory accesses (two consecutive addresses) are always needed. Because all control lines are shared between the two memory devices, operations such as byte write and bursting can be performed as in normal 32-bit use. For byte operations, a byte write happens like a byte write in a 32-bit system. The address accessed determines the memory device on which the byte operation is performed. For bursting, the interface automatically switches between the connected memories as long as the bursting operation lasts. The external 64-bit SDRAM memory is built out of two 32-bit memories with 2 Mb of address space. This needs the construction of a 4-Mb-deep memory interface for the processor. The LS address bit is used as a data multiplexer, where the lower memory data bank is selected when the LS address bit is 0 and the upper data bank is selected when the LS address bit is 1. With this mechanism in place, the memory appears as a 4-Mb-deep by 32-bit-wide memory to the processor, although the external memory is actually 64 bits wide and 2 Mb deep. The bursting must start at an address with the LSB-bit at zero, as single 64-bit assesses. The interface automatically switches between the memory devices as long as the bursting operation lasts. Byte access is done at a 32-bit boundary. Byte access to a 64-bit memory address is accomplished in two steps. 1. The processor accesses the lower address with the correct byte mask in place to access only the wanted byte of the lower 32-bit word. 2. The processor accesses the higher address with the byte mask bits set depending the needed byte of the higher 32-bit word. 2 www.xilinx.com XAPP729 XAPP729 (v1.0.1) March 4, 2007 R SDRAM Interface Assume byte 6 of the 64-bit must be accessed. · Set the byte mask to omit all bytes in the lower address and access the memory. · Set the byte mask to omit bytes 1, 3, and 4 and access the higher memory address. When bursting with byte access, the byte mask will count for all addresses accessed though the bursting operation. The lower and higher addresses representing the 64-bit will be accessed all with the same byte mask. Figure 2 shows the memory layout, and Figure 3 shows the interface setup. Data 0 Address 32 31 11 63 0 0 31 31 11111111111 11111111111 1 0 0 0 0 0 31 31 31 31 00000000001 00000000001 00000000000 00000000000 Address 1 0 1 0 0 Data X729_02_010506 Figure 2: Reference Design Memory Address Layout DDR SDRAM Data 0:31 Data 32:63 1 Address 0:11 CTRL 0 LSB+1:MSB LSB SDRAM Interface Data 0:31 Address 0:31 CoreConnect Bus CTRL X729_03_010506 Figure 3: Reference Design Interface Setup The "SDRAM Interface" section explains the SDRAM interface and modifications, and the "Interface Implementation" section describes the implementation and flow. SDRAM Interface As with all Xilinx OPB controllers, the SDRAM interface controller is built out of a Xilinx Intellectual Property Interface (IPIF) and the interface controller itself, as shown in Figure 4. This reference design modifies the SDRAM controller. Modifications cannot alter the IPIF because this is the standard engine to connect different IP to the IBM CoreConnectTM buses. Details on the OPB-IPIF interface are found in the EDK documentation at http://www.xilinx.com/ise/embedded/edk_docs.htm. XAPP729 XAPP729 (v1.0.1) March 4, 2007 www.xilinx.com 3 R OPB_select OPB_DBus OPB_ABus OPB_BE OPB_RNW OPB_seqAddr Sin_DBus Sin_XferAck Sin_errAck Sin_retry Sin_totSup OPB_Clk OPB_Rst Open SDRAM Interface OPB_select OPB_DBus OPB_ABus OPB_BE OPB_RNW OPB_seqAddr Sin_DBus Sin_XferAck Sin_errAck Sin_retry Sin_totSup OPB_CLK Reset IP2INTC_Irpt Bus2IP_CS Bus2IP_CE Bus2IP_RdCE Bus2IP_WrCE Bus2IP_Data Bus2IP_Addr Bus2IP_AddrValid Bus2IP_BE Bus2IP_RNW Bus2IP_Burst IP2Bus_Data IP2Bus_Ack IP2Bus_AddrAck IP2Bus_Error IP2Bus_Retry IP2Bus_ToutSup IP2Bus_PostedWrinh IP2RFIFO_Data IP2RFIFO_WrMark IP2RFIFO_WrRelease IP2RFIFO_WrReq IP2RFIFO_WrRestore IRFIFO2IP_AlmostFull RFIFO2IP_Full RFIFO2IP_Vacancy RFIFO2IP_WrAck IP2WFIFO_RdMark IP2WFIFO_RdRelease IP2WFIFO_RdReq IP2WFIFO_RdRestore WFIFO2IP_AlmostEmpty WFIFO2IP_Data WFIFO2IP_Empty WFIFO2IP_Occupancy WFIFO2IP_RdAck IP2Bus_IntrEvent Freeze Bus2IP_Freeze Bus2IP_Clk IP2Bus_Clk IPIF Bus2IP_Reset Bus2IP_CS C D Bus2IP_Data Bus2IP_Addr A Bus2IP_BE Bus2IP_RNW Bus2IP_Burst B IP2Bus_Data K IP2Bus_AddrAck IP2Bus_ErrAck IP2Bus_Retry IP2Bus_ToutSup L E F G H open Zero_Data Bus2IP_RdReq Bus2IP_WrReq IP2Bus_RdAck IP2Bus_WrAck Ip2Bus_Busy Open Open Open Open SDRAM_DQ_o SDRAM_DQ_i SDRAM_DQ_t SDRAM_Addr SDRAM_BankAddr SDRAM_DQM SDRAM_WEn SDRAM_CASn SDRAM_RASn SDRAM_CSn SDRAM_CKE SDRAM_Clk SDRAM_init_done Open Open Open Open Open Zero_Intr SDRAM_DQ_o SDRAM_DQ_i SDRAM_DQ_t SDRAM_Addr SDRAM_BankAddr SDRAM_DQM SDRAM_WEn SDRAM_CASn SDRAM_RASn SDRAM_CSn SDRAM_CKE SDRAM_Clk SDRAM_init_done Open Bus2IP_Clk Bus2IP_Reset OPB_Clk OPB_Rst OPB_CLK Reset SDRAM Controller X729_04_010506 Notes: 1. Signals with labels A to H are routed through logic gates. Figure 4: OPB-SDRAM Interface The SDRAM controller has seven different hierarchical levels and is completely parameterized through the use of VHDL generic statements. The values of these generics are set in the Xilinx Processor System (XPS) development tool and are passed to VHDL through intermediate files. The seven hierarchical levels of the SDRAM controller are: 1. Ipic_If Interface between the processor bus and the peripheral. The address bus is split and rewired in this level. 2. Data_statemachine Data handling at read and write operations. In this level, the datapath doubles in width. 3. Command_statemachine State machine handling RAS, CAS, and so forth. 4. Init_statemachine Initialization of the memory. 4 www.xilinx.com XAPP729 XAPP729 (v1.0.1) March 4, 2007 R SDRAM Interface 5. Io_registers Interface to memory/FPGA connections. The data inputs and outputs double in size in this level. 6. Counters Counters used in this interface. 7. Clock_gen Clock generation logic and feedthrough. The Ipic-if, data_statemachine, and Io_registers hierarchical levels and their required logic are described in more detail in these subsections: · "IPIC Interface (ipic-if)" · "Data State Machine (data_statemachine)" · "I/O State Machine (Io_registers)" IPIC Interface (ipic-if) This hierarchical level provides the interface between the IPIF IP block and the SDRAM controller. It is a bus translation and bus size adaptation layer that generates new signals depending on incoming signal states. The incoming address bus is split into row, column, and bank address buses, and the CoreConnect read and write data buses are passed to the correct buses at the SDRAM controller side. This configuration is just a rewiring of the incoming and outgoing buses to the correct sizes. XAPP729 XAPP729 (v1.0.1) March 4, 2007 www.xilinx.com 5 R SDRAM Interface Connection to IPIF Bus2IP_CS Connection to SDRAM_controller Read_Data IPIC_wrdata Row_addr Col_addr Bank_addr Bus2IP_CS Bus2IP_Data Bus2IP_Addr Bus2IP_Data Bus2IP_Addr Bus2IP_BE Bus2IP_RNW Bus2IP_Burst Bus2IP_BE Bus2IP_RNW Bus2IP_Burst IP2Bus_Data IP2Bus_Data IP2Bus_AddrAck IP2BUS_ErrAck IP2Bus_Retry IP2Bus_ToutSup IP2Bus_AddrAck IP2BUS_ErrAck IP2Bus_Retry IP2Bus_ToutSup Bus2Ip_RdReq Bus2Ip_WrReq Bus2Ip_RdReq Bus2Ip_WrReq IP2Bus_RdAck IP2Bus_WrAck IP2Bus_Busy IP2Bus_RdAck IP2Bus_WrAck IP2Bus_Busy IPIC SysClk Rst Clk Rst read_data ipic_wrdata row_addr col_addr bank_addr Read_op Write_op IPIC_be Burst Pend_read Pend_write Rd_Addrack Wr_Addrack ErrAck Retry ToutSup read_op write_op ipic_be burst pend_read pend_write rd_addrack wr_addrack errack retry toutsup RdAck WrAck Init_done Reset_pendrdreq Reset_pendwrreq SDRAM_idle Pend_rdreq Pend_wrreq Same_Row Same_Bank Same_rowbank_regce rdack wrack Init_done reset_pendrdreq reset_pendwrreq sdram_idle pend_rdreq pend_wrreq same_row same_bank same_rowbank_regce X729_05_122105 Figure 5: Top-Level Connections of the IPIC_IF Hierarchical Level In this level, the LS address bit is split from the address bus structure, and the rest of the address bus is shifted. The LS address bit adds a new signal to the IPIC component to allow switching between Low and High memory SDRAM data blocks (generation of the multiplexer enable signal). From the top level "opb_sdram" on, all bus structures are sized through VHDL generic syntax settings. The OPB_SDRAM controller documentation ([Ref 1]) provides a complete description of each generic. Table 1 lists the important generics for this application note. "Appendix B" shows the generic settings for the Micron SDRAM device. Table 1: Important VHDL Generics for Buses OPB_sdram Value Sdram_controller Ipic-if C_OPB_DWIDTH 32 C_IPIF_DWIDTH C_IPIF_DWIDTH C_OPB_AWIDTH 32 C_IPIF_AWIDTH C_IPIF_AWIDTH C_SDRAM_DWIDTH 32 C_SDRAM_DWIDTH C_SDRAM_DWIDTH C_SDRAM_AWIDTH 12 C_SDRAM_AWIDTH C_SDRAM_AWIDTH C_SDRAM_COL_AWIDTH 9 C_SDRAM_COL_AWIDTH C_SDRAM_COL_AWIDTH C_SDRAM_BANK_AWIDTH 2 C_SDRAM_BANK_AWIDTH C_SDRAM_BANK_AWIDTH 6 www.xilinx.com XAPP729 XAPP729 (v1.0.1) March 4, 2007 R SDRAM Interface When examining and calculating the values for the generics: · The data bus at the CoreConnect level is wired to the SDRAM data buses. · The address bus from the CoreConnect bus system is split into row, column, and bank address buses for the SDRAM controller as shown in Table 2 and Figure 6. Table 2: SDRAM Address Calculations Generic Variable Equation SDRAM_ADDR_OFFSET Log2(C_SDRAM_DWIDTH/8) OPB_ADDR_OFFSET Log2(C_OPB_DWIDTH/8) COLADDR_STARTBIT C_OPB_AWIDTH ­ (C_SDRAM_COL_AWIDTH + SDRAM_ADDR_OFFSET) COLADDR_ENDBIT C_OPB_AWIDTH ­ OPB_ADDR_OFFSET-1 NUM_ZEROADDR_BITS OPB_ADDR_OFFSET ­ SDRAM_ADDR_OFFSET ROWADDR_STARTBIT COLADDR_STARTBIT ­ C_SDRAM_AWIDTH ROWADDR_ENDBIT ROWADDR_STARTBIT + C_SDRAM_AWIDTH-1 BANKADDR_STARTBIT ROWADDR_STARTBIT ­ C_SDRAM_BANK_AWIDTH BANKADDR_ENDBIT BANKADDR_STARTBIT + C_SDRAM_BANK_AWIDTH-1 ZERO_COL_PAD (0 to C_SDRAM_AWIDTH ­ C_SDRAM_COL_AWIDTH-1) Column Address ZERO_COL_PAD & OPB_ABus (COLADDR_STARTBIT to COLADDR_ENDBIT) Row Address OPB_ABus (ROWADDR_STARTBIT to ROWADDR_ENDBIT) Bank Address OPB_ABus (BANKADDR_STARTBIT to BANKADDR_ENDBIT) Bus2IP_Addr[0:31] [21:31] 20 [9:19] 8 [0:7] 000 [21:29] Col_Addr[0:11] [9:20] Row_Addr[0:11] [7:8] Bank_Addr[0:1] X729_06_122105 Figure 6: Address Bus Split in IPIC_IF Required Modifications Because the LS address bit is used to switch the data bus between the different SDRAMs, the address bus must be shifted by one bit. The LS address bit, which acts as the multiplexer select bit for the data bus, forms a new output of the "ipic_if" interface. The CoreConnect bus is coded using the big-endian format shown in Figure 7. Byte 0 Byte 1 Byte 2 MS Byte Byte 3 LS Byte 0 31 MS Bit LS Bit X729_07_010706 Figure 7: Big-Endian Data Organization XAPP729 XAPP729 (v1.0.1) March 4, 2007 www.xilinx.com 7 R SDRAM Interface To obtain the shifting effect, a new generic variable called C_SDRAM_WIDE_DBUS is created in the top level of the IP. Legal values for this variable are: 0 and 1. When the variable is: · 0: A normal SDRAM controller is generated with a maximum data width of 32 bits. · 1: A dual-width SDRAM controller is generated following the principle explained in this document. An extra output pin for the "ipic_if" called Sel_Wide_DBus, reflecting the LS address bit status, is created. The generic variable is subtracted from the value calculated for: · SELADDR_MUXBIT = (C_IPIF_AWIDTH ­ IPIF_ADDR_OFFSET ­ 1) · COLADDR_STARTBIT = (C_IPIF_AWIDTH ­ (C_SDRAM_COL_AWIDTH + SDRAM_ADDR_OFFSET) ­ C_SDRAM_WIDE_DBUS · COLADDR_ENDBIT = (C_IPIF_AWIDTH ­ IPIF_ADDR_OFFSET ­ 1) ­ C_SDRAM_WIDE_DBUS All other calculated values use the modified address range values, resulting in an address setup as shown in Figure 8. Bus2IP_Addr[0:31] [21:31] 19 [8:18] 7 [0:6] 29 000 [20:28] Sel_Wide_DBus [8:19] Row_Addr[0:11] [6:7] Bank_Addr[0:1] Col_Addr[0:11] X729_08_122205 Figure 8: Wide Data Bus Address Setup Data State Machine (data_statemachine) This hierarchical level routes the data from the processor bus to the I/O section and vice-versa. It ensures that writing and reading happen at the correct moment and data bus actions are signaled to other parts of the SDRAM controller interface. Figure 9 shows the external connections of this hierarchical level before any modification. The signals of interest are schematically shown in Figure 10. 8 www.xilinx.com XAPP729 XAPP729 (v1.0.1) March 4, 2007 R SDRAM Interface Connection to IPIC read_data ipic_wrdata Bus2IP_CE Bus2IP_RNW Bus2IP_Burst ipic_be pend_read pend_write rdack wrack Twr_end Rst_data_done data_done Sdram_burst_end Read_pause rst_pend_rd rst_pend_wr SysClk Rst Connection to IO_controller Read_Data IPIC_wrdata Bus2IP_CE Bus2IP_RNW Bus2IP_Burst SDRAM_ReadData Write_data Write_data_en Write_data_mask sdram_readdata write_data write_data_en write_data_mask IPIC_be Pend_read Pend_write RdAck WrAck Twr_end Rst_data_done Data_done SDRAM_burst_end Read_pause To and from command state machine and counters Rst_pend_rd Rst_pend_wr Clk Rst Data State Machine X729_09_010506 Figure 9: Top-Level Connections of a 32-Bit Data State Machine Read_data IPIC_wrdata Pipeline & Clocking Options SDRAM_ReadData Write_data X729_10_010506 Figure 10: Data Flow Through the Data State Machine Hierarchical Level A set of generic variables controls the data flow between the processor bus and the I/O registers (pads). The values of these generics are determined and/or changed when the interface is added to a design in the EDK software. All variables determine pipelining (highspeed designs), clocking possibilities, and bursting (see Table 3). XAPP729 XAPP729 (v1.0.1) March 4, 2007 www.xilinx.com 9 R SDRAM Interface Table 3: Generic Variables Involved in Determining the Data State Machine Setup Default Value Generic Variable Equation or Explanation C_SDRAM_BRST_LEN ­ IPIF_DWIDTH / SDRAM_DWIDTH C_SDRAM_CAS_LAT 2 CAS latency determined by memory devices. C_USE_POSEDGE_OUTREGS 0 When set to 1, uses positive-edge registers. When cleared to 0, uses negative-edge registers. C_INCLUDE_HIGHSPEED_PIPE 1 Adds a pipeline stage for high frequency operation. When C_USE_POSEDGE_OUTREGS is set to 1, this variable should be cleared to 0. Required Modifications The size of the incoming and outgoing datapaths must change so that data written from the IPIF side is widened to 64 bits and data from the SDRAM side is reduced to 32 bits for the processor. The control of the datapath sizes is managed by a new signal and a new generic variable created in the IPIC interface logic and by the existing generic variables. An input signal "Sel_Wide_DBus" must be created for use as a multiplexer control signal or a logic enable signal. For write operations, this signal is used to swap the data from the processor's 32-bit data bus onto the Low and High 32-bit SDRAM buses. For read operations, this signal is used to transfer data from the Low and High SDRAM data buses onto the 32-bit processor bus. The modifications to the different data buses comprise all existing generic variables so that the pipeline registers and positive-edge or negative-edge registers are automatically generated for these new extensions. To carry out these modifications in the existing VHDL, a substantial amount of code must be added (mostly cut-and-paste operations). Read Data Flow from SDRAM to Processor The standard read data flow can be customized through a set of generic VHDL values to contain pipeline, burst, and positive- or negative-clocked registers. When the newly introduced generic value C_SDRAM_WIDEBUS is set to "1", this logic is duplicated and the output is passed through a multiplexer controlled by the Sel_Wide_DBus signal. Figure 11 shows how the 64-bit extension is generated. When C_SDRAM_WIDEBUS is 0, only the 32-bit version is generated. SDRAM_ReadData_low 0 ReadData Registers added due to design settings: - C_USE_POSEDGE_OUTREGS - C_INCLUDE_HIGHSPEED_PIPE - C_SDRAM_BRST_LEN 1 Sel_Wide_DBus SDRAM_ReadData_high When C_SDRAM_WIDEBUS is 1, this multiplexer and logic are added. X729_11_010506 Figure 11: Read Datapath and Additions 10 www.xilinx.com XAPP729 XAPP729 (v1.0.1) March 4, 2007 R SDRAM Interface Write Data Flow from Processor to SDRAM Figure 12 shows the write data flow and its modifications. Added by setting of C_SDRAM_BRST_LEN Registers added when C_INCLUDE_HIGHSPEED_PIPE is 1 Writedata_low Writedata_high IPIC_wrdata Sel_Wide_DBus Added when C_SDRAM_WIDEBUS is 1 X729_12_122705 Figure 12: Write Datapath The 32-bit write datapath is customized through the same set of generic VHDL values as used for the read datapath. Output registers, clocking edge polarity, pipeline, and burst registers can be added through these generics. For the 64-bit version, C_SDRAM_WIDEBUS must be set to "1", which duplicates the 32-bit path and adds a demultiplexer and register set. Because all control lines and address lines are shared between the connected SDRAMs, a protection must be built into the interface to prevent the same data to be written into both connected SDRAMs. A switch at the front of the block directs incoming data to the Low or High data bus. Data is then passed through possible register sets added through the use of normal interface generics. A register and data-combining multiplexer are required to combine the data into a 64-bit format. A set of pipeline registers can be added in the path after any extra burst registers. In this case, an additional register and data-combining multiplexer are required in front of the set of pipeline registers to handle the tying together of all control lines. Here is a description of the data-combining register and multiplexer: · When writing the first 32 bits of data to the lower address, data is written into this added register. The SDRAM controller acts as if the data is written into the external memory. · When the second 32 bits of data are written to the high address, this data is combined with the lower-address data, and the full 64 bits are passed to the external SDRAM. XAPP729 XAPP729 (v1.0.1) March 4, 2007 www.xilinx.com 11 R Interface Implementation I/O State Machine (Io_registers) This hierarchical level provides the interface between the memory and I/O, as shown in Figure 13. To modify this level to run in 64-bit mode, a set of output and input registers must be added. Connection to Data State Machine sdram_readdata write_data write_data_en write_data_mask Connection to SDRAM per FPGA I/O SDRAM_ReadData Write_data Write_data_en Write_data_mask SDRAM_DQ_i SDRAM_DQ_o SDRAM_DQ_t dqm_rst dqm_set rasn casn wen DQM_rst DQM_set RASn CASn WEn bankaddr addr SDRAM_DQM SDRAM_RASn SDRAM_CASn SDRAM_WEn SDRAM_BankAddr SDRAM_Addr SDRAM_DQ_i SDRAM_DQ_o SDRAM_DQ_t SDRAM_DQM SDRAM_RASn SDRAM_CASn SDRAM_WEn SDRAM_BankAddr SDRAM_Addr BankAddr Addr SysClk Rst Clk Rst I/O Controller X729_13_010506 Figure 13: I/O State Machine The write-enable output must be combined with the Sel_Wide_Bus signal. Data can be written into the external SDRAM only when Sel_Wide_Bus is High. When C_SDRAM_WIDEBUS is High, registers must be added for the negative- and positiveedge clocked flip-flops and for the DQ_o and DQ_t outputs. Also input registers must be added when the generic variable is set, resulting in an extra set of inputs and outputs from and to the SDRAM. Interface Implementation To complete the whole process and to ease tuning of other cores, this section describes a project where the customized SDRAM controller is used. For this project, the "opb_sdram_v1_00_e" version delivered with EDK 7.1.2i of the OPB_SDRAM controller is used. This version and the "sdram_v1_00_e" version of the SDRAM controller are copied to the local project directory to create a proprietary version of the controller. Project Setup The project is carried as a combined ISE/EDK project. The processor and its peripherals are used as a hierarchical level of a top-level design containing all clocking and I/O connections. Figure 14 shows the created directory setup. 12 www.xilinx.com XAPP729 XAPP729 (v1.0.1) March 4, 2007 R Interface Implementation WideSdram Documents Ise WideSdram ISE Project Directory Synthesys Xst ISE is set so that synthesis is done in this directory Ucf Project UCF File Vhdl Top-Level VHDL Files Xps EDK Project Directory hdl Synthesized VHDL Wrapper End implementation Generated NGC Files (Macros) pcores Customized or Homemade Cores . . . X729_14_010506 Figure 14: Project Directory Setup Processor Project These steps describe how to complete the processor project: 1. An XPS base project is created with the Base System Wizard in the Xps directory (see Figure 14). 2. The standard OPB_SDRAM is defined as one of the peripherals. 3. The processor and all peripherals are given proper names and the automatically included DCM is removed from the Base System Project. This step can be done from within the XPS tool, or a text editor can be used to modify the MHS and MSS files (see "Appendix C"). 4. The project options are set so that the XPS design is generated as a hierarchical level of an already created top-level design. 5. The processor design is passed through the XPS tools, and the VHDL_wrapper and NGC files of this application are built. The processor design's top-level wrapper VHDL file is located in the hdl directory of the XPS project. 64-Bit SDRAM Controller These steps indicate the process to complete the SDRAM controller project: 1. The latest versions of the OPB_SDRAM and SDRAM IP are copied from the EDK installation directory into the pcores directory of the project. The entire directory for each IP core is copied. The IP cores are located in: \hw\XilinxProcessorIPLib\pcores\opb_sdram_v1_00_e \hw\XilinxProcessorIPLib\pcores\sdram_v1_00_e 2. The directories and all top-level files of the OPB_SDRAM and SDRAM controller are renamed. The modifications described in the "SDRAM Interface" section of this application note are performed. 3. The files in the \data directory of each of the cores are also modified. These files are necessary to correctly handle the customer-specific functional blocks. Figure 15 shows the pcores directory setup, and an example in the reference design's included files can be used. XAPP729 XAPP729 (v1.0.1) March 4, 2007 www.xilinx.com 13 R Interface Implementation WideSdram . . . Xps pcores opb_widesdram data .pao .mpd vhdl .vhd files widesdram data .pao vhdl .vhd files X729_15_122205 Figure 15: XPS Project and pcores Subdirectory Setup 4. The created base system XPS project is opened, and the original SDRAM controller is removed. When everything is correctly set up, the customized SDRAM controller is shown as a component that can be added to the processor design. 5. The customized SDRAM controller is added to the design, and the XPS tools are run. Assembling the Project This project is a normal ISE project. The steps to assemble it are: 1. The highest level VHDL file is created, the needed Digital Clock Manager (DCM) resources and all needed input and output buffers are instantiated. 2. The top-level processor design is copied as a component into the top-level HDL file of the design. All necessary connections are made. 3. A UCF file is created that matches the design and the hardware it needs to run on. 4. This design uses two DCM components: one for the system and one for the SDRAM. The DCM for the SDRAM receives its feedback path from the SDRAM as shown in Figure 16. The proper syntax is put into the UCF file to support this form of feedback. Toplevel.vhd Processor_design.vhd SysClk FB In In FB DCM Clk_0 Clk_90 DCM To SDRAM X729_16_010506 Figure 16: Top-Level Design Setup 5. The ISE tools are run. 14 www.xilinx.com XAPP729 XAPP729 (v1.0.1) March 4, 2007 R Reference Design A 32-bit MicroBlaze processor is connected via the OPB CoreConnect bus to an external, 64-bit SDRAM. The MicroBlaze processor can access the memory in two consecutive reads or writes. Reference Design The reference design files are located in a ZIP file, which contains a full project, using the design discussed in this application note and the modified SDRAM controller. The ZIP file is available at: http://www.xilinx.com/bvdocs/appnotes/xapp729.zip. All EDK IP is written in VHDL as is this project and its modified SDRAM controller. Verilog is not supported. This project contains a top-level design comprising a MicroBlaze design as a hierarchical level. The flow uses all Xilinx software tools (ISE and EDK/XPS). This reference design is implemented onto a ML470 ML470 (XITI) Xilinx board having a XC4VSX35FF668 XC4VSX35FF668 Virtex-4 FPGA connected to Micron MT48LC8M32B2 MT48LC8M32B2 SDRAMs. As such, the UCF file of the reference design will reflect the pinout of the FPGA on the ML470 ML470 demo board. Resources When the modified SDRAM controller is synthesized, without the IPIF interface and without the backend processor design, it uses the following resources: · sdram_controller Registers LUTs 390 I/O pads · 512 323 Command_statemachine Registers LUTs · 60 162 Init_statemachine Registers LUTs · 12 5 Data_statemachine Registers LUTs · 186 150 Io_registers Registers LUTs · 213 1 Ipic_interface Registers 8 LUTs XAPP729 XAPP729 (v1.0.1) March 4, 2007 This number also contains registers normally buried in the FPGA because they are connections to the IPIF interface. 13 www.xilinx.com 15 R References References The following documents provide supplemental material useful to this application note: 1. DS426 DS426, OPB Synchronous DRAM (SDRAM) Controller Data Sheet 2. Micron, MT48LC8M32B2 MT48LC8M32B2 256Mb x 32 Synchronous DRAM Data Sheet Conclusion 16 This project shows that existing IP delivered with the EDK tools can be modified and tuned fairly easily. Xilinx provides many powerful IP blocks for free that, due to the open VHDL format, can readily be adapted for a range of different needs. www.xilinx.com XAPP729 XAPP729 (v1.0.1) March 4, 2007 R Appendix A Appendix A This appendix provides two example schematics for connecting two different memory devices to a Virtex-4 SX35-FF668 SX35-FF668 FPGA. SDRAM Data Bus [63:0] SDRAM Address Bus [11:0] SDRAM Control Bus XC4VSX35-10FF668CES XC4VSX35-10FF668CES SDA0 SDA1 SDA2 SDA3 SDA4 SDA5 SDA6 SDA7 SDA8 SDA9 SDA10 SDA10 SDA11 SDA11 SDCKE SDDQM3 SDDQM2 SDDQM1 SDDQM0 SDD18 SDD18 SDD31 SDD31 SDD30 SDD30 SDD17 SDD17 SDD16 SDD16 SDD15 SDD15 SDD14 SDD14 SDD13 SDD13 G8 F8 C7 B7 D5 C5 B9 A9 B3 A3 B4 A4 D4 C4 D6 E7 E5 E6 G7 F7 C10 D10 C1 C2 H7 H8 E4 D3 G5 G6 E2 E3 IO_L10N_6 IO_L10P_6 IO_L11N_6 IO_L11P_6 IO_L12N_VREF_6 IO_L12P_6 IO_L13N_6 IO_L13P_6 IO_L14N_6 IO_L14P_6 IO_L15N_6 IO_L15P_6 IO_L16N_6 IO_L16P_6 IO_L17N_6 IO_L17P_6 IO_L18N_6 IO_L18P_6 IO_L19N_6 IO_L19P_6 IO_L1N_6 IO_L1P_6 IO_L20N_VREF_6 IO_L20P_6 IO_L21N_6 IO_L21P_6 IO_L22N_6 IO_L22P_6 IO_L23N_VRP_6 IO_L23P_VRN_6 IO_L24N_CC_LC_6 IO_L24P_CC_LC_6 IO_L25N_CC_LC_6 IO_L25P_CC_LC_6 IO_L26N_6 IO_L26P_6 IO_L27N_6 IO_L27P_6 IO_L28N_VREF_6 IO_L28P_6 IO_L29N_6 IO_L29P_6 IO_L2N_6 IO_L2P_6 IO_L30N_6 IO_L30P_6 IO_L31N_6 IO_L31P_6 IO_L32N_6 IO_L32P_6 IO_L3N_6 IO_L3P_6 IO_L4N_VREF_6 IO_L4P_6 IO_L5N_6 IO_L5P_6 IO_L6N_6 IO_L6P_6 IO_L7N_6 IO_L7P_6 IO_L8N_CC_LC_6 IO_L8P_CC_LC_6 IO_L9N_CC_LC_6 IO_L9P_CC_LC_6 D1 D2 F1 E1 F3 F4 G3 G4 H5 H6 C8 D9 G1 G2 H3 H4 H1 H2 A7 A8 D7 D8 E10 F10 A5 A6 F9 E9 C6 B6 G9 G10 SDD12 SDD12 SDD11 SDD11 SDD10 SDD10 SDD9 SDD8 SDD7 SDD6 SDD29 SDD29 SDD28 SDD28 SDD5 SDD4 SDD3 SDD2 SDD1 SDD0 SDD27 SDD27 SDD26 SDD26 SDD25 SDD25 SDD24 SDD24 SDD23 SDD23 SDD22 SDD22 SDD21 SDD21 SDD20 SDD20 SDD19 SDD19 +3.3V VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 B5 B8 E8 F2 F5 H9 H10 J8 X729_17_122705 Figure 17: Example Schematic (Bank 6) XAPP729 XAPP729 (v1.0.1) March 4, 2007 www.xilinx.com 17 R Appendix A SDRAM Control Bus SDRAM Data Bus [63:0] XC4VSX35-10FF668CES XC4VSX35-10FF668CES SDCKE SDDQM3 SDDQM2 SDDQM1 SDCLK SDCS# SDCAS# SDWE# SDRAS# SDDQM7 SDDQM6 SDDQM5 SDDQM4 SDBA1 SDBA0 SDCKE SDDQM3 SDDQM2 SDDQM1 SDD45 SDD45 SDD44 SDD44 K1 L1 M1 M2 M3 M4 M5 M6 N2 N3 N4 N5 P2 P3 M7 N7 P4 P5 N8 P8 J6 J7 R3 R4 P6 P7 R1 R2 R5 R6 T1 U1 IO_L10N_10 IO_L10P_10 IO_L11N_10 IO_L11P_10 IO_L12N_VREF_10 IO_L12P_10 IO_L13N_10 IO_L13P_10 IO_L14N_10 IO_L14P_10 IO_L15N_10 IO_L15P_10 IO_L16N_10 IO_L16P_10 IO_L17N_10 IO_L17P_10 IO_L18N_10 IO_L18P_10 IO_L19N_10 IO_L19P_10 IO_L1N_10 IO_L1P_10 IO_L20N_VREF_10 IO_L20P_10 IO_L21N_10 IO_L21P_10 IO_L22N_10 IO_L22P_10 IO_L23N_VRP_10 IO_L23P_VRN_10 IO_L24N_CC_LC_10 IO_L24P_CC_LC_10 IO_L25N_CC_LC_10 IO_L25P_CC_LC_10 IO_L26N_10 IO_L26P_10 IO_L27N_10 IO_L27P_10 IO_L28N_VREF_10 IO_L28P_10 IO_L29N_10 IO_L29P_10 IO_L2N_10 IO_L2P_10 IO_L30N_10 IO_L30P_10 IO_L31N_10 IO_L31P_10 IO_L32N_10 IO_L32P_10 IO_L3N_10 IO_L3P_10 IO_L4N_VREF_10 IO_L4P_10 IO_L5N_10 IO_L5P_10 IO_L6N_10 IO_L6P_10 IO_L7N_10 IO_L7P_10 IO_L8N_CC_LC_10 IO_L8P_CC_LC_10 IO_L9N_CC_LC_10 IO_L9P_CC_LC_10 R7 R8 T3 T4 T6 T7 U2 U3 U4 V4 J4 J5 V1 V2 U7 T8 U5 U6 K6 K7 J1 J2 L6 L7 K4 K5 K2 K3 L3 L4 L8 M8 SDD43 SDD43 SDD42 SDD42 SDD39 SDD39 SDD38 SDD38 SDFCLK0 SDD36 SDD36 SDD63 SDD63 SDD62 SDD62 SDD61 SDD61 SDD60 SDD60 SDD59 SDD59 SDD58 SDD58 SDD57 SDD57 SDD56 SDD56 +3.3V VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 K8 L2 L5 N1 R9 T2 T5 U8 X729_18_010506 Figure 18: Example Schematic (Bank 10) 18 www.xilinx.com XAPP729 XAPP729 (v1.0.1) March 4, 2007 R Appendix B Appendix B This appendix provides parameter settings for the Micron MT48LC8M32B2 MT48LC8M32B2 256 Mb x 32 SDRAM. The data sheet for this SDRAM component is included in the reference design's ZIP file. The parameters for the CoreConnect OPB bus are: C_FAMILY C_BASEADDR C_HIGHADDR C_OPB_DWIDTH C_OPB_AWIDTH virtex4 0x00000000 0x007FFFFF 32 32 The parameters for the interface are: C_INCLUDE_BURST_SUPPORT 1 C_INCLUDE_HIGHSPEED_PIPE 1 C_USE_POSEDGE_OUTREGS 0 The parameters for the SDRAM hooked to the interface are: C_SDRAM_DWIDTH C_SDRAM_AWIDTH C_SDRAM_COL_AWIDTH C_SDRAM_BANK_AWIDTH C_SDRAM_WIDEBUS 32 12 9 2 1 The Micron SDRAM parameters from the data sheet are: C_SDRAM_TRAS C_SDRAM_TMRD C_SDRAM_TWR C_SDRAM_TCCD C_SDRAM_TRC C_SDRAM_TRFC C_SDRAM_TRCD C_SDRAM_TRRD C_SDRAM_TRP C_SDRAM_TREF C_SDRAM_CAS_LAT C_SDRAM_REFRESH_NUMROWS XAPP729 XAPP729 (v1.0.1) March 4, 2007 42000 2 15000 1 75000 75000 20000 15000 20000 64 3 4096 www.xilinx.com min. value for -6 and -7 min. 14 ns in -7 SDRAM min. min. min. min. min. 70 70 20 14 20 ns ns ns ns ns in in in in in a -7 SDRAM a -7 SDRAM a -7 SDRAM -7 SDRAM a -7 SDRAM other values are: 1 and 2 19 R Appendix C Appendix C Examples of both MHS and MSS files are located in the pcores directory of the XPS project. MHS File The MHS file contains the following major sections: · A section where all I/O ports are declared The port name should be renamed with a meaningful name. It is best is to give the port the same name as the connected net. For example: PORT my_name = my_name · The same number of sections as there are components in the processor design. Each section starts with BEGIN and ends in END. The INSTANCE name in each section is renamed to a meaningful name for the design. If the component has access to the external world, the port name is changed to the same name as given in the port section of the file. MSS File The file is split into three major sections: · An OS section The "PROC_INSTANCE" parameter is changed to the chosen name of the processor. · A processor section The name of the "HW_INSTANCE" is changed to the name of the processor. · Driver sections for all peripherals The "HW_INSTANCE" name is changed to the chosen peripheral name for all sections. Revision History The following table shows the revision history for this document. Version 02/05/06 1.0 04/04/07 20 Date 1.0.1 Revision Initial Xilinx release. · Modified last paragraph of the "Reference Design" section. · New design files posted with this revision. www.xilinx.com XAPP729 XAPP729 (v1.0.1) March 4, 2007