DS313 XCN07010 DS099 XC3S1000L XC3S1500L XC3S4000L DS099-1 XCF00S XCF00P - Datasheet Archive

 

0 Spartan-3L Low Power FPGA Family R DS313 (v1.2) April 18, 2008 0 0 Product Specification This product is undergoing

 

ds313.fm Page 1 Friday, April 18, 2008 10:26 AM 0 Spartan-3L Low Power FPGA Family R DS313 DS313 (v1.2) April 18, 2008 0 0 Product Specification This product is undergoing discontinuance. Please refer to XCN07010 XCN07010, Product Discontinuation Notice, for more information on last-time purchases and replacement products. Introduction Spartan®-3L Field-Programmable Gate Arrays (FPGAs) consume less static current than corresponding members of the standard Spartan-3 family. Spartan-3L devices provide the identical function, features, timing, and pinout of the original Spartan-3 family. Features include programmable I/Os, Configurable Logic Blocks (CLBs), RAM blocks, Digital Clock Managers (DCMs), and Multiplier blocks. Another power-saving benefit of the Spartan-3L family beyond static current reduction is the Hibernate mode, which lowers device power consumption to the lowest possible levels. For new designs, consider the Spartan-3A family, which offers both Hibernate and Suspend power-saving modes. The three-member Spartan-3L family ranges in density from one to four million system gates and offers as many as 633 I/Os. All devices are specified to meet the ­4 speed grade over the commercial temperature range. This data sheet explains how the Spartan-3L family is different from the Spartan-3 family. For specifications and other technical information not contained in this document, refer to the Spartan-3 data sheet (DS099 DS099). Features · · Power current reduction compared to Spartan-3 family: - Up to 60% less quiescent current - Up to 99% less quiescent current in Hibernate mode Low cost, low power logic solution for high-volume, consumer-oriented applications - Densities as high as 62,000 logic cells · · · · · · · · · · SelectIOTM signaling - Up to 633 I/O pins - Eighteen single-ended signal standards - Eight differential signal standards including LVDS and RSDS - Double Data Rate (DDR) support Logic resources - Abundant logic cells with shift register capability - Wide multiplexers - Fast look-ahead carry logic - Dedicated 18 x 18 multipliers - JTAG logic compatible with IEEE 1149.1/1532 SelectRAMTM hierarchical memory - Up to 1,728 Kbits of total block RAM - Up to 432 Kbits of total distributed RAM Digital Clock Manager (four DCMs) - Clock skew elimination - Frequency synthesis - High-resolution phase shifting Eight global clock lines and abundant routing Pin-compatible with Spartan-3 FPGAs Pb-free packaging options Fully supported by Xilinx ISE® development system - Synthesis, mapping, placement, and routing MicroBlazeTM processor and other cores Power estimation using XPower tools Table 1: Summary of Spartan-3L FPGA Attributes CLB Array Equivalent System Logic Maximum (One CLB = Four Slices) Columns Total CLBs Maximum Differential DCMs User I/O I/O Pairs 4 333 149 Dedicated Distributed RAM bits(1) Block RAM bits(1) Multipliers 432K 24 Device Gates Cells Rows XC3S1000L XC3S1000L 1M 17,280 48 40 1,920 120K XC3S1500L XC3S1500L 1.5M 29,952 64 52 3,328 208K 576K 32 4 487 221 XC3S4000L XC3S4000L 4M 62,208 96 72 6,912 432K 1,728K 96 4 633 300 Notes: 1. By convention, one Kb is equivalent to 1,024 bits. © 2004-2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS313 DS313 (v1.2) April 18, 2008 Product Specification www.xilinx.com 1 ds313.fm Page 2 Friday, April 18, 2008 10:26 AM R Spartan-3L Low Power FPGA Family Architectural Overview The Spartan-3L family architecture consists of five fundamental programmable functional elements: · · · · · Configurable Logic Blocks (CLBs) contain RAM-based Look-Up Tables (LUTs) to implement logic and storage elements that can be used as flip-flops or latches. CLBs can be programmed to perform a wide variety of logical functions as well as to store data. Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. Each IOB supports bidirectional data flow plus 3-state operation. Twenty-six different signal standards, including eight high-performance differential standards, are available, as shown in Table 2. Double Data-Rate (DDR) registers are included. The Digitally Controlled Impedance (DCI) feature provides automatic on-chip terminations, simplifying board designs. Block RAM provides data storage in the form of 18-Kbit dual-port blocks. Multiplier Blocks accept two 18-bit binary numbers as inputs and calculate the product. Digital Clock Manager (DCM) Blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock signals. These elements are organized as shown in Figure 1. A ring of IOBs surrounds a regular array of CLBs. The XC3S1000L XC3S1000L and XC3S1500L XC3S1500L have two columns of block RAM. The XC3S4000L XC3S4000L has four RAM columns. Each column is made up of several 18Kbit RAM blocks; each block is associated with a dedicated multiplier. The DCMs are positioned at the ends of the outer block RAM columns. The Spartan-3L family features a rich network of traces that interconnect all five functional elements, transmitting signals among them. Each functional element has an associated switch matrix that permits multiple connections to the routing. DS099-1 DS099-1_01_032703 Notes: 1. The two additional block RAM columns of the XC3S4000L XC3S4000L devices are shown with dashed lines. Figure 1: Spartan-3L Family Architecture Configuration Spartan-3L FPGAs are programmed by loading configuration data into robust static memory cells that collectively control all functional elements and routing resources. Before powering on the FPGA, configuration data is stored externally in a PROM or some other nonvolatile medium either on or off the board. After applying power, the configuration data is written to the FPGA using any of five different modes: Master Parallel, Slave Parallel, Master Serial, Slave 2 Serial and Boundary Scan (JTAG). The Master and Slave Parallel modes use an 8-bit wide SelectMAP port. The recommended memory for storing the configuration data is the low-cost Xilinx Platform Flash PROM family, which includes the XCF00S XCF00S PROMs for serial configuration and the higher density XCF00P XCF00P PROMs for parallel or serial configuration. www.xilinx.com DS313 DS313 (v1.2) April 18, 2008 Product Specification ds313.fm Page 3 Friday, April 18, 2008 10:26 AM R Spartan-3L Low Power FPGA Family I/O Capabilities The SelectIO feature of Spartan-3L devices provides 18 single-ended standards and eight differential standards as listed in Table 2. Many standards support the DCI feature, which uses integrated terminations to eliminate unwanted signal reflections. Table 3 shows the number of user I/Os as well as the number of differential I/O pairs available for each device/package combination. Table 2: Signal Standards Supported by the Spartan-3L Family Standard Category VCCO (V) Class N/A Description Terminated IOSTANDARD DCI Option Single-Ended GTL Gunning Transceiver Logic Plus HSTL High-Speed Transceiver Logic 1.5 GTL Yes GTLP Yes HSTL_I Yes HSTL_III Yes I HSTL_I_18 Yes II 1.8 I III HSTL_II_18 Yes III Yes N/A LVCMOS12 LVCMOS12 No N/A LVCMOS15 LVCMOS15 Yes 1.8 N/A LVCMOS18 LVCMOS18 Yes 2.5 N/A LVCMOS25 LVCMOS25 Yes 3.3 Low-Voltage CMOS HSTL_III_18 1.2 1.5 LVCMOS N/A LVCMOS33 LVCMOS33 Yes LVTTL Low-Voltage Transistor-Transistor Logic 3.3 N/A PCI Peripheral Component Interconnect 3.0 33 MHz SSTL Stub Series Terminated Logic 1.8 No No N/A (± 6.7 mA) SSTL18 SSTL18_I Yes N/A (± 13.4 mA) SSTL18 SSTL18_II No I SSTL2_I Yes II 2.5 LVTTL PCI33 PCI33_3 SSTL2_II Yes DIFF_HSTL_II_18 Yes Differential HSTL Differential High-Speed Transceiver Logic 1.8 LDT (ULVDS) Lightning Data Transport (HyperTransportTM) 2.5 LVDS Low-Voltage Differential Signaling II N/A Standard Bus Extended Mode LDT_25 LVDS_25 No Yes BLVDS_25 No LVDSEXT_25 Yes LVPECL Low-Voltage Positive Emitter-Coupled Logic 2.5 N/A LVPECL_25 No RSDS Reduced-Swing Differential Signaling 2.5 N/A RSDS_25 No SSTL Differential Stub Series Terminated Logic 2.5 II DIFF_SSTL2_II Yes DS313 DS313 (v1.2) April 18, 2008 Product Specification www.xilinx.com 3 ds313.fm Page 4 Friday, April 18, 2008 10:26 AM R Spartan-3L Low Power FPGA Family Table 3: User I/O and Differential (Diff) I/O Counts FT256 FT256 FTG256 FTG256 FG320 FG320 FGG320 FGG320 FG456 FG456 FGG456 FGG456 FG676 FG676 FGG676 FGG676 FG900 FG900 FGG900 FGG900 Device User Diff User Diff User Diff User Diff User Diff XC3S1000L XC3S1000L 173 76 221 100 333 149 - - - - XC3S1500L XC3S1500L - - 221 100 333 149 487 221 - - XC3S4000L XC3S4000L - - - - - - - - 633 300 Notes: 1. All Spartan-3L and Spartan-3 devices in the same package are pin-compatible. Package Marking Figure 2 shows the package marking for Spartan-3L FPGAs. The markings on the Spartan-3L package are similar to those on the Spartan-3 package. The `L' in the last line, indicating low power, distinguishes the Spartan-3L device. R SPARTAN XC3S1500TM XC3S1500TM FG676xxx0450 xxxxxxxxx L4C R Device Type Package Low Power Date Code Lot Code Speed Grade Temperature Range DS313 DS313_02_102204 Figure 2: Spartan-3L Package Marking 4 www.xilinx.com DS313 DS313 (v1.2) April 18, 2008 Product Specification ds313.fm Page 5 Friday, April 18, 2008 10:26 AM R Spartan-3L Low Power FPGA Family Ordering Information Spartan-3L FPGAs are available in both standard and Pb-free packaging options for all device/package combinations. The Pb-free packages include a `G' character in the ordering code. Spartan-3L FPGAs are available in a single speed grade, ­4, and are specified over the Commercial temperature range. Standard Packaging Example: XC3S1500L XC3S1500L -4 FG 676 C Device Type Temperature Range: C = Commercial (TJ = 0oC to 85oC) Speed Grade Package Type Number of Pins DS313 DS313_03_101204 Pb-Free Packaging For additional information on Pb-free packaging, see XAPP427 XAPP427: Implementation and Solder Reflow Guidelines for Pb-Free Packages. Example: XC3S1500L XC3S1500L -4 FG G 676 C Device Type Temperature Range: C = Commercial (TJ = 0oC to 85oC) Speed Grade Number of Pins Package Type Device Speed Grade XC3S1000L XC3S1000L ­4 Pb-free Package Type / Number of Pins FT(G)256 256-ball Fine-Pitch Thin Ball Grid Array (FTBGA) XC3S1500L XC3S1500L FG(G)320 FG(G)456 456-ball Fine-Pitch Ball Grid Array (FBGA) FG(G)676 676-ball Fine-Pitch Ball Grid Array (FBGA) FG(G)900 Temperature Range (TJ ) 320-ball Fine-Pitch Ball Grid Array (FBGA) XC3S4000L XC3S4000L DS313 DS313_04_101204 900-ball Fine-Pitch Ball Grid Array (FBGA) DS313 DS313 (v1.2) April 18, 2008 Product Specification www.xilinx.com C Commercial (0°C to 85°C) 5 ds313.fm Page 6 Friday, April 18, 2008 10:26 AM R Spartan-3L Low Power FPGA Family Functional Description The Spartan-3L FPGA family is identical to the Spartan-3 FPGA family with respect to device function. See the functional description in Module 2 of the Spartan-3 data sheet (DS099 DS099) for more information. Achieving Low Quiescent Current Levels Because of their lower quiescent current specifications, Spartan-3L devices always consume less power than Spartan-3 devices. For power-sensitive applications that must manage consumption over long periods with no FPGA activity, it is possible to achieve the quiescent current levels specified in Table 4 of the DC and Switching Characteristics section on page 9 by meeting the test conditions described below the table. The easiest way to realize these conditions is by pulling PROG_B Low. This action puts all I/Os into a high-impedance state, ceases all internal switching, and converts the bitmap held in internal memory to all zeros. During and after the Low pulse on PROG_B, disable the internal pull-up resistors on all I/Os by keeping HSWAP_EN High. Reconfiguration is necessary before the FPGA can resume operation in the User mode. As an alternate approach, when it is desirable to retain the programmed bitmap, do not assert PROG_B. If all other test conditions are met (e.g., no internal switching, I/Os are off), quiescent current levels will be very close to or slightly above what is specified in Table 4, page 9. In this case, make sure internal pull-up and pull-down resistors on all I/Os are disabled. Hibernate Mode Hibernate mode starts with the approach described above. This takes power savings one step further by switching off power rails. This mode reduces quiescent power consump- 6 tion to the lowest possible level. The FPGA is put into the Hibernate mode by switching off the VCCINT (core) and VCCAUX (auxiliary) power supplies. Power is supplied to VCCO lines throughout the hibernation period. Figure 3, page 7 is a block diagram that shows how to put Spartan-3L FPGAs into the Hibernate mode. During the Hibernation period, the VCCINT and VCCAUX rails are turned off. It is recommended that power FETs with low on resistance be used to perform the switching action. Configuration data is lost upon entering the Hibernate mode; therefore, reconfiguration is necessary after exiting the mode. In general, it is safest to maintain VCCO power for all banks throughout the Hibernation period. This keeps the power diodes inside the IOBs off when signals are applied to the pins. For each I/O, a power diode extends from the pin (the anode side) to the associated VCCO rail (the cathode side). Power diodes are present on all signal-carrying pins all of the time. In Hibernate mode, the powered VCCO rails account for little current, because the I/Os are in a high-impedance state. It is also possible to switch off the VCCO rail for a particular bank. This action eliminates the VCCO current for those banks-current on the order of a few milliamperes. There are two ways to achieve this. One way is to keep the voltage of all I/Os belonging to that bank under 0.5V. Another way is to disable signals coming from external devices (such as Device 1 in Figure 3). Holding the PROG_B input Low during the transition into Hibernation period keeps all output drivers in a high-impedance state. Release PROG_B after re-applying power to the VCCINT and VCCAUX rails. See Special Considerations, page 8 for recommended levels on Dedicated and Dual-Purpose pins. www.xilinx.com DS313 DS313 (v1.2) April 18, 2008 Product Specification ds313.fm Page 7 Friday, April 18, 2008 10:26 AM R Spartan-3L Low Power FPGA Family 2.5V VCCO Supply 1.2V Power Control I/O Bank VCCAUX VCCINT Spartan-3L FPGA I/O Bank HSWAP_EN LOW PROG_B VCCO Supply Device 1 Device 2 DS313 DS313_01_110304 Figure 3: Hibernate Diagram Hibernate PROG_B I/Os VCCINT VCCAUX VCCO (Banks 0 - 7) INIT_B DONE Undefined CCLK Undefined in Master Mode startup cycles Notes: 1. See Special Considerations, page 8 for recommended levels on Dedicated and Dual-Purpose pins. DS313 DS313_05_110304 Figure 4: Hibernate Mode Waveforms DS313 DS313 (v1.2) April 18, 2008 Product Specification www.xilinx.com 7 ds313.fm Page 8 Friday, April 18, 2008 10:26 AM R Spartan-3L Low Power FPGA Family Figure 4, page 7 shows the waveforms for entering and exiting the Hibernate mode. The steps for entering the Hibernate mode are as follows: 1. Pull the PROG_B pin Low to put all I/Os into a high-impedance state. 2. The FPGA drives the INIT_B and DONE pins Low. 3. External switches are used to turn off the VCCINT and VCCAUX rails. This action resets the FPGA. As described above, it is possible to switch off VCCO for a given bank in cases where the I/O pins of the associated bank are Low or disabled throughout the Hibernation period. 4. The FPGA is now in the Hibernate mode. As long as the FPGA is kept in this state, power consumption rests at the lowest possible level. The steps for exiting the Hibernate mode are as follows: 1. Before FPGA initialization can begin, it is necessary to deassert PROG_B to a High logic level. The rising transition must occur after turning all three power supplies back on. 2. Reapply power to all rails that were switched off. Apply power in any sequence. 3. After logic initialization, the FPGA releases the open-drain INIT_B signal. Now that INIT_B is High, reconfiguration can begin. 4. When configuration is complete, the FPGA enters the Startup phase, asserts DONE, and enables the I/Os, according to how the BitGen options are set. 5. The FPGA is now ready for user operation. 8 Special Considerations In the Hibernate mode, whenever one of the VCCO rails is turned off, keep the voltage on the I/O pins of the associated bank below 0.5V. As an alternative, it is possible to disable any signals that an external device might apply to the bank's I/O pins. Voltages higher than 0.5V can turn on the power diodes. Keeping the diode off prevents "reverse current" from flowing into the VCCO rail. VCCO Bank 4 powers the Dual-Purpose inputs: INIT_B, DIN, BUSY, and D0-D3. VCCO Bank 5 powers the other Dual-Purpose inputs: RDWR_B, CS_B, and D4-D7. The VCCO lines of Banks 0, 1, 4, and 5 power the Global Clock inputs GCLK0 - GCLK1, GCLK2 - GCLK3, GCLK4 - GCLK5, and GCLK6 - GCLK7, respectively. In the Hibernate mode, if any of these rails is turned off, do not apply voltages in excess of 0.5V to any of the associated Dual-Purpose pins. This measure keeps the power diodes off. VCCAUX powers the Dedicated inputs: PROG_B, HSWAP_EN, M0-M2, CCLK (in Slave mode), TDI, TCK, and TMS. Once in the Hibernate mode, do not apply voltages in excess of 0.5V to any of these pins. In this case, keeping the power diode off prevents a "reverse current" from flowing into the VCCAUX rail. VCCAUX powers the Dedicated outputs: DONE, CCLK (in Master mode), and TDO. Once in the Hibernate mode, the states of these pins are undefined. VCCO Bank 4 powers the Dual-Purpose outputs: BUSY/DOUT. Whenever VCCO Bank 4 is turned off during the Hibernation period, the state of this pin is undefined. www.xilinx.com DS313 DS313 (v1.2) April 18, 2008 Product Specification ds313.fm Page 9 Friday, April 18, 2008 10:26 AM R Spartan-3L Low Power FPGA Family DC and Switching Characteristics Like-density Spartan-3L and Spartan-3 devices share the same AC and DC specifications with the exceptions of reduced quiescent supply current consumption and specifications for the Hibernate mode. The reduced quiescent current levels are shown in Table 4. mode, the FPGA only dissipates ICCOH current. The VCCINT and VCCAUX rails are electrically disconnected and will not dissipate power. For all other DC and AC specifications, refer to Module 3 of the Spartan-3 data sheet (DS099 DS099). When in the Hibernate mode, Spartan-3L devices consume still less quiescent current, as shown in Table 5. In this Table 4: Quiescent Supply Current Characteristics Commercial Symbol Typ Max Units 35.0 70.0 mA 45.0 110.0 mA 100.0 290.0 mA mA 2.0 7.5 2.5 8.5 mA XC3S4000L XC3S4000L 3.5 11.0 mA XC3S1000L XC3S1000L 20.0 35.0 mA XC3S1500L XC3S1500L 35.0 50.0 mA XC3S4000L XC3S4000L Quiescent VCCAUX supply current XC3S1000L XC3S1000L XC3S1500L XC3S1500L ICCAUXQ Quiescent VCCO supply current Device XC3S4000L XC3S4000L ICCOQ Description Quiescent VCCINT supply current XC3S1000L XC3S1000L XC3S1500L XC3S1500L ICCINTQ 55.0 80.0 mA Notes: 1. Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads disabled. Typical values are characterized using typical devices measured at ambient room temperature (TA of 25°C at VCCINT = 1.2V, VCCO = 3.3V, and VCCAUX = 2.5V). Maximum values are the production test limits measured for each device at TJ = 85°C and with VCCINT = 1.26V, VCCO = 3.45V, and VCCAUX = 2.625V. The FPGA is programmed with a "blank" configuration data file (i.e., a design with no functional elements instantiated). For conditions other than those described above, (e.g., a design including functional elements, the use of DCI standards, etc.), measured quiescent current levels may be slightly higher than the values in the table. Use the Web Power Tool or XPower for more accurate estimates. See Note 2. 2. There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The Spartan-3 XPower Estimator at http://www.xilinx.com/power provides quick, approximate, typical estimates, and does not require a netlist of the design. b) XPower Analyzer, part of the Xilinx development software, takes a netlist as input to provide more accurate maximum and typical estimates. 3. The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully. Table 5: Supply Current Characteristics for Hibernate Mode Commercial Symbol ICCOH Description Device Quiescent VCCO supply current in Hibernate mode XC3S1000L XC3S1000L Typ Max Units 2.0 7.5 mA XC3S1500L XC3S1500L 2.5 8.5 mA XC3S4000L XC3S4000L 3.5 11.0 mA Notes: 1. Quiescent supply current is measured with all I/O drivers in a high-impedance state and with pull-up/pull-down resistors at all I/O pads disabled. For maximum ICCOH values, TJ = 85°C with VCCO (all banks) = 3.45V. VCCINT = 0V and VCCAUX = 0V. PROG_B is Low. DS313 DS313 (v1.2) April 18, 2008 Product Specification www.xilinx.com 9 ds313.fm Page 10 Friday, April 18, 2008 10:26 AM R Spartan-3L Low Power FPGA Family Pinout Descriptions Spartan-3L and Spartan-3 devices that correspond in density and package have the same pinout. See the Pinout Descriptions in Module 4 of the Spartan-3 data sheet (DS099 DS099) for more information. Related Documentation This data sheet only specifies how the Spartan-3L family differs from the Spartan-3 family. Because the two families are identical with respect to function, features, timing, and pinout, please consult the Spartan-3 FPGA family data sheet for all other information. DS099 DS099, Spartan-3 FPGA Family Data Sheet Revision History The following table shows the revision history for this document. Date 11/03/04 1.0 Initial Xilinx release. 09/15/04 1.1 Added the SSTL18 SSTL18_II, DIFF_SSTL2_II, and DIFF_HSTL_II_18 standards (Table 2). Described option for retaining the bitmap in Achieving Low Quiescent Current Levels, page 6. Removed power sequence restriction for Hibernate mode (page 8). Added or updated quiescent current specifications (Table 4 and Table 5). Updated the worst-case TJ condition in footnote 1 of Table 4. Changed document status to "Preliminary". 04/18/08 10 Version Revision 1.2 Added reference to Discontinuation Notice. Updated links. Removed Preliminary from document status. www.xilinx.com DS313 DS313 (v1.2) April 18, 2008 Product Specification