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XRT83SH314 14-CHANNEL 775/ETS300233 XRT83SH314IB 84-CHANNEL GR-499 32BITS - Datasheet Archive
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT MAY 2006 REV. 1.0.3 GENERAL DESCRIPTION Additional features include RLOS, a
XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT MAY 2006 REV. 1.0.3 GENERAL DESCRIPTION Additional features include RLOS, a 16-bit LCV counter for each channel, AIS, QRSS/PRBS generation/detection, TAOS, DMO, and diagnostic loopback modes. The XRT83SH314 XRT83SH314 is a fully integrated 14-channel short-haul line interface unit (LIU) that operates from a single 3.3V power supply. Using internal termination, the LIU provides one bill of materials to operate in T1, E1, or J1 mode independently on a per channel basis with minimum external components. The LIU features are programmed through a standard microprocessor interface. EXAR's LIU has patented high impedance circuits that allow the transmitter outputs and receiver inputs to be high impedance when experiencing a power failure or when the LIU is powered off. Key design features within the LIU optimize 1:1 or 1+1 redundancy and non-intrusive monitoring applications to ensure reliability without using relays. APPLICATIONS · · · · · · · · · · The on-chip clock synthesizer generates T1/E1/J1 clock rates from a selectable external clock frequency and has five output clock references that can be used for external timing (8kHz, 1.544Mhz, 2.048Mhz, nxT1/J1, nxE1). T1 Digital Cross Connects (DSX-1) ISDN Primary Rate Interface CSU/DSU E1/T1/J1 Interface T1/E1/J1 LAN/WAN Routers Public Switching Systems and PBX Interfaces T1/E1/J1 Multiplexer and Channel Banks Integrated Multi-Service Access Platforms (IMAPs) Integrated Access Devices (IADs) Inverse Multiplexing for ATM (IMA) Wireless Base Stations FIGURE 1. BLOCK DIAGRAM OF THE XRT83SH314 XRT83SH314 1 of 14 Channels Driver Monitor TCLK_n Tx/Rx Jitter Attenuator HDB3/B8ZS Encoder TPOS_n Tx Pulse Shaper & Pattern Gen Timing Control DMO TTIP_n Line Driver TRING_n TNEG_n Remote Loopback TxON Digital Loopback Analog Loopback QRSS Generation & Detection RPOS_n HDB3/B8ZS Decoder RCLK_n Tx/Rx Jitter Attenuator Peak Detector & Slicer Clock & Data Recovery RNEG_n RTIP_n RRING_n RLOS RCLKOUT AIS & LOS Detector RxON RxTSEL 8kHzOUT ICT TEST MCLKE1out Microprocessor Interface Test ATP_TIP Programmable Master Clock Synthesizer MCLKT1out MCLKE1Nout ATP_RING MCLKin Reset [7:0] DATA CS[5:1] [10:0] uPTS0 uPTS1 uPTS2 uPCLK RD_WE WR_R/W CS ALE INT RDY_TA TDO TCK TDI TMS ADDR MCLKT1Nout FEATURES Exar Corporation 48720 Kato Road, Fremont CA, 94538 · (510) 668-7000 · FAX (510) 668-7017 · www.exar.com XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 · Fully integrated 14-Channel short haul transceivers for T1/J1 (1.544MHz) and E1 (2.048MHz) applications. · T1/E1/J1 short haul and clock rate are per port selectable through software without changing components. · Internal Impedance matching on both receive and transmit for 75 (E1), 100 (T1), 110 (J1), and 120 (E1) applications are per port selectable through software without changing components. · Power down on a per channel basis with independent receive and transmit selection. · Five pre-programmed transmit pulse settings for T1 short haul applications per channel. · User programable Arbitrary Pulse mode · On-Chip transmit short-circuit protection and limiting protects line drivers from damage on a per channel basis. · Selectable Crystal-Less digital jitter attenuators (JA) with 32-Bit or 64-Bit FIFO for the receive or transmit path · On-Chip frequency multiplier generates T1 or E1 master clocks from a variety of external clock sources (8, 16, 56, 64, 128, 256kHz and 1X, 2X, 4X, 8X T1 or E1) · Driver failure monitor output (DMO) alerts of possible system or external component problems. · Transmit outputs and receive inputs may be "High" impedance for protection or redundancy applications on a per channel basis. · Support for automatic protection switching. · 1:1 and 1+1 protection without relays. · Receive monitor mode handles 0 to 6dB resistive attenuation (flat loss) along with 0 to 6dB cable loss for both T1 and E1. · Loss of signal (RLOS) according to ITU-T G.775/ETS300233 775/ETS300233 (E1) and ANSI T1.403 (T1/J1). · Programmable data stream muting upon RLOS detection. · On-Chip HDB3/B8ZS encoder/decoder with an internal 16-bit LCV counter for each channel. · On-Chip digital clock recovery circuit for high input jitter tolerance. · QRSS/PRBS pattern generator and detection for testing and monitoring. · Error and bipolar violation insertion and detection. · Transmit all ones (TAOS) Generators and Detectors · Supports local analog, remote, digital, and dual loopback modes · 153mW per channel Power consumption · Single 3.3V supply operation (3V to 5V I/O tolerant) · 304-Pin TBGA package · -40°C to +85°C Temperature Range · Supports gapped clocks for mapper/multiplexer applications PRODUCT ORDERING INFORMATION PRODUCT NUMBER PACKAGE TYPE OPERATING TEMPERATURE RANGE XRT83SH314IB XRT83SH314IB 304 Lead TBGA -40°C to +85°C 2 RESET A[8] TRING_8 RVDD_8 RCLK_8 RCLK_9 TVDD_9 TRING_9 NC NC NC RGND_8 RRING_8 RTIP_8 RVDD_9 RTIP_9 RRING_9 RGND_9 DVDD_8_9_10 DGND_8_9_10 NC TGND_9 RPOS_9 RPOS_8 TGND_8 A[9] DVDD_PRE CS3 CS5 WR_RW 20 3 RNEG_11 RCLK_10 RCLK_11 RVDD_11 RTIP_10 RVDD_10 RTIP_11 RGND_12 RCLK_12 NC UPTS1 A[0] RRING_12 RTIP_12 RVDD_12 DGND_DRV UPTS2 A[4] A[3] UPTS0 RNEG_12 TTIP_12 TXOFF A[5] A[2] DVDD_PRE RPOS_12 TGND_12 TRING_12 RGND_11 TVDD_12 DVDD_DRV DVDD_11_12 DGND_11_12 TRING_11 TGND_11 RPOS_11 RPOS_10 TGND_10 RRING_11 TVDD_11 TTIP_11 RNEG_10 TVDD_10 RRING_10 TTIP_10 DGND_DRV DGND_PRE ATP_RING TTIP_9 RNEG_9 RNEG_8 TTIP_8 TVDD_8 ATP_TIP DVDD_DRV CS1 CS4 TRING_10 CS A[10] 21 18 17 16 15 11 10 RCLK_6 RTIP_6 9 MCLKT1xN TCLK_12 TCLK_13 TNEG_12 TCLK_11 TNEG_13 VDDPLL_11 RVDD_13 RTIP_13 RRING_13 RGND_13 RGND_0 RRING_0 RTIP_0 RVDD_0 RCLK_0 RXTSEL RPOS_13 TGND_13 DGND_13_0 TGND_0 RPOS_0 GNDPLL_12 GNDPLL_11 DGND_PRE DGND_DRV TPOS_0 TCLK_10 DGND_PRE RPOS_7 TGND_7 DVDD_6_7 TGND_6 RPOS_6 DVDD_DRV EIGHT_KHZ BOTTOM VIEW 7 6 5 4 TCLK_0 TNEG_0 TNEG_2 TNEG_1 TCLK_6 TNEG_6 TPOS_6 TCLK_2 TPOS_2 TPOS_1 D[3] TPOS_3 TNEG_3 TCLK_3 TCLK_1 D[0] D[4] DVDD_PRE TNEG_5 TNEG_4 TCLK_4 TVDD_4 TTIP_4 RNEG_4 RNEG_5 TTIP_5 TDO DVDD_PRE INT TCLK_5 3 TVDD_2 TTIP_2 RNEG_2 RNEG_3 TTIP_3 D[1] D[2] D[7] DMO RPOS_1 TGND_1 D[5] D[6] RDY_TA RNEG_1 TTIP_1 TRING_1 TVDD_1 DGND_DRV DGND_1_2 TGND_2 RPOS_2 RPOS_3 TGND_3 RRING_4 RTIP_4 RVDD_4 RTIP_5 RRING_5 RGND_5 TCK TDI 1 NC RRING_2 RTIP_2 RVDD_3 RTIP_3 RRING_3 RGND_3 DVDD_DRV UPCLK RCLK_1 RVDD_1 RGND_1 NC RLOS NC RTIP_1 RRING_1 DVDD_1_2 RGND_2 TRING_2 RVDD_2 RCLK_2 RCLK_3 TVDD_3 TRING_3 NC NC DVDD_3_4_5 RGND_4 TRING_4 RCLK_4 RCLK_5 RVDD_5 TVDD_5 TRING_5 DGND_DRV ICT 2 DGND_PRE AGND_BIAS DGND_3_4_5 AVDD_BIAS DVDD_DRV TGND_4 RPOS_4 RPOS_5 TGND_5 TMS TEST TPOS_5 TPOS_4 RVDD_6 MCLKOUT_T1 MCLKIN MCLKOUT_E1 MCLKE1xN 8 DGND_6_7 TTIP_6 RNEG_6 GNDPLL_22 GNDPLL_21 TRING_7 TRING_6 TVDD_6 RGND_7 RGND_6 RRING_6 12 TPOS_12 TNEG_11 DVDD_DRV DVDD_UP RNEG_13 TTIP_13 DVDD_13_0 TTIP_0 RNEG_0 A[7] RD_DS TPOS_9 TTIP_7 VDDPLL_21 RCLK_7 TVDD_7 TNEG_7 VDDPLL_22 RNEG_7 TCLK_7 13 RTIP_7 RRING_7 14 RXOFF TPOS_11 TPOS_13 VDDPLL_12 DGND_UP RCLK_13 TVDD_13 TRING_13 TRING_0 TVDD_0 A[6] A[1] CS2 ALE_AS TNEG_8 TCLK_9 TPOS_8 TNEG_9 TNEG_10 TCLK_8 TPOS_10 TPOS_7 DGND_DRV RVDD_7 19 AC AB AA Y W V U T R P N M L K J H G F E D C B A REV. 1.0.3 RGND_10 22 23 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PIN OUT OF THE XRT83SH314 XRT83SH314 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 TABLE OF CONTENTS GENERAL DESCRIPTION. 1 APPLICATIONS . 1 FIGURE 1. BLOCK DIAGRAM OF THE XRT83SH314 XRT83SH314 . 1 FEATURES . 1 PRODUCT ORDERING INFORMATION. 2 PIN OUT OF THE XRT83SH314 XRT83SH314. 3 TABLE OF CONTENTS .I PIN DESCRIPTIONS (BY FUNCTION). 4 MICROPROCESSOR . 4 RECEIVER SECTION . 5 TRANSMITTER SECTION. 8 CONTROL FUNCTION . 10 CLOCK SECTION . 10 JTAG SECTION . 10 POWER AND GROUND . 11 NO CONNECTS . 13 1.0 CLOCK SYNTHESIZER .14 TABLE 1: INPUT CLOCK SOURCE SELECT . 14 FIGURE 2. SIMPLIFIED BLOCK DIAGRAM OF THE CLOCK SYNTHESIZER. 15 1.1 ALL T1/E1 MODE . 15 2.0 RECEIVE PATH LINE INTERFACE .15 FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH . 15 2.1 LINE TERMINATION (RTIP/RRING) . 16 2.1.1 CASE 1: INTERNAL TERMINATION. 16 TABLE 2: SELECTING THE INTERNAL IMPEDANCE. 16 FIGURE 4. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION . 16 2.1.2 CASE 2: INTERNAL TERMINATION WITH ONE EXTERNAL FIXED RESISTOR FOR ALL MODES. 17 TABLE 3: SELECTING THE VALUE OF THE EXTERNAL FIXED RESISTOR . 17 FIGURE 5. TYPICAL CONNECTION DIAGRAM USING ONE EXTERNAL FIXED RESISTOR. 17 2.2 CLOCK AND DATA RECOVERY . 18 FIGURE 6. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK. 18 FIGURE 7. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK. 18 TABLE 4: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG. 19 2.2.1 RECEIVE SENSITIVITY . 19 FIGURE 8. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY . 19 2.2.2 INTERFERENCE MARGIN . 20 FIGURE 9. TEST CONFIGURATION FOR MEASURING INTERFERENCE MARGIN . 20 2.2.3 GENERAL ALARM DETECTION AND INTERRUPT GENERATION . 20 FIGURE 10. INTERRUPT GENERATION PROCESS BLOCK . 21 FIGURE 11. ANALOG RECEIVE LOS OF SIGNAL FOR T1/E1/J1. 22 TABLE 5: ANALOG RLOS DECLARE/CLEAR (TYPICAL VALUES) FOR T1/E1 . 22 2.3 JITTER ATTENUATOR . 23 2.4 HDB3/B8ZS DECODER . 23 2.5 RPOS/RNEG/RCLK . 24 FIGURE 12. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN . 24 FIGURE 13. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN . 24 2.6 RXMUTE (RECEIVER LOS WITH DATA MUTING) . 24 FIGURE 14. SIMPLIFIED BLOCK DIAGRAM OF THE RXMUTE FUNCTION . 24 3.0 TRANSMIT PATH LINE INTERFACE .25 FIGURE 15. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH . 25 3.1 TCLK/TPOS/TNEG DIGITAL INPUTS . 25 FIGURE 16. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK . 25 FIGURE 17. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK . 26 TABLE 6: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG. 26 3.2 HDB3/B8ZS ENCODER . 26 TABLE 7: EXAMPLES OF HDB3 ENCODING . 26 TABLE 8: EXAMPLES OF B8ZS ENCODING . 27 3.3 JITTER ATTENUATOR . 27 TABLE 9: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS . 27 3.4 TAOS (TRANSMIT ALL ONES) . 27 I XRT83SH314 XRT83SH314 REV. 1.0.3 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT FIGURE 18. TAOS (TRANSMIT ALL ONES) . 27 3.5 TRANSMIT DIAGNOSTIC FEATURES . 27 3.5.1 ATAOS (AUTOMATIC TRANSMIT ALL ONES). 28 FIGURE 19. SIMPLIFIED BLOCK DIAGRAM OF THE ATAOS FUNCTION . 28 3.5.2 QRSS/PRBS GENERATION. 28 TABLE 10: RANDOM BIT SEQUENCE POLYNOMIALS . 28 3.6 TRANSMIT PULSE SHAPER AND FILTER . 28 3.6.1 T1 SHORT HAUL LINE BUILD OUT (LBO) . 29 TABLE 11: SHORT HAUL LINE BUILD OUT. 29 3.6.2 ARBITRARY PULSE GENERATOR FOR T1 AND E1. 29 FIGURE 20. ARBITRARY PULSE SEGMENT ASSIGNMENT . 29 3.6.3 SETTING REGISTERS TO SELECT AN ARIBTRARY PULSE . 30 TABLE 12: TYPICAL ROM VALUES . 30 3.7 DMO (DIGITAL MONITOR OUTPUT) . 30 3.8 LINE TERMINATION (TTIP/TRING) . 30 FIGURE 21. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION . 31 4.0 T1/E1 APPLICATIONS . 32 4.1 LOOPBACK DIAGNOSTICS . 32 4.1.1 LOCAL ANALOG LOOPBACK . 32 FIGURE 22. SIMPLIFIED BLOCK DIAGRAM OF LOCAL ANALOG LOOPBACK . 32 4.1.2 REMOTE LOOPBACK . 32 FIGURE 23. SIMPLIFIED BLOCK DIAGRAM OF REMOTE LOOPBACK . 32 4.1.3 DIGITAL LOOPBACK . 33 FIGURE 24. SIMPLIFIED BLOCK DIAGRAM OF DIGITAL LOOPBACK . 33 4.1.4 DUAL LOOPBACK . 33 FIGURE 25. SIMPLIFIED BLOCK DIAGRAM OF DUAL LOOPBACK . 33 4.2 84-CHANNEL 84-CHANNEL T1/E1 MULTIPLEXER/MAPPER APPLICATIONS . 34 FIGURE 26. SIMPLIFIED BLOCK DIAGRAM OF AN 84-CHANNEL 84-CHANNEL APPLICATION . 34 TABLE 13: CHIP SELECT ASSIGNMENTS . 34 4.3 LINE CARD REDUNDANCY . 35 4.3.1 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS . 35 4.3.2 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY . 35 FIGURE 27. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR 1:1 AND 1+1 REDUNDANCY . 35 4.3.3 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY. 36 FIGURE 28. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR 1:1 AND 1+1 REDUNDANCY . 36 4.3.4 N+1 REDUNDANCY USING EXTERNAL RELAYS . 36 4.3.5 TRANSMIT INTERFACE WITH N+1 REDUNDANCY . 37 FIGURE 29. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR N+1 REDUNDANCY . 37 4.3.6 RECEIVE INTERFACE WITH N+1 REDUNDANCY . 38 FIGURE 30. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR N+1 REDUNDANCY . 38 4.4 POWER FAILURE PROTECTION . 39 4.5 OVERVOLTAGE AND OVERCURRENT PROTECTION . 39 4.6 NON-INTRUSIVE MONITORING . 39 FIGURE 31. SIMPLIFIED BLOCK DIAGRAM OF A NON-INTRUSIVE MONITORING APPLICATION . 39 4.7 ANALOG BOARD CONTINUITY CHECK . 40 FIGURE 32. ATP TESTING BLOCK DIAGRAM . 40 FIGURE 33. TIMING DIAGRAM FOR ATP TESTING . 40 4.7.1 TRANSMITTER TTIP AND TRING TESTING. 40 4.7.2 RECEIVER RTIP AND RRING . 41 4.8 XRT83SH314 XRT83SH314 JITTER CHARACTERISTICS . 42 4.8.1 JITTER TOLERANCE . 42 FIGURE 34. TEST CIRCUIT FOR DS-1 JITTER TOLERANCE. 42 FIGURE 35. GR-499 GR-499 JITTER TOLERANCE MASK . 42 FIGURE 36. DS-1 JITTER TOLERANCE . 43 FIGURE 37. DS-1 JITTER TRANSFER CURVE VARIABLE AMPLITUDE - T1 JA DISABLE. 44 FIGURE 38. JITTER TRANSFER FUNCTION VARIABLE AMPLITUDE - T1 TX 3HZ 32BITS 32BITS . 45 FIGURE 39. JITTER TRANSFER FUNCTION - T1 TX 3HZ 64BITS 64BITS . 46 FIGURE 40. JITTER TRANSFER FUNCTION - T1 RX 3HZ 32BITS 32BITS . 47 FIGURE 41. JITTER TRANSFER FUNCTION - T1 RX 3HZ 64BITS 64BITS . 48 FIGURE 42. TEST CIRCUIT FOR E1 JITTER TOLERANCE . 49 FIGURE 43. ITU-G.823 JITTER TOLERANCE MASK . 49 FIGURE 44. REVISION C: E1 JITTER TOLERANCE - 6DB CABLE + 6DB FLAT LOSS . 50 FIGURE 45. JITTER TRANSFER FUNCTION - JA DISABLED . 51 FIGURE 46. JITTER TRANSFER FUNCTION - E1 TX 10HZ 32BITS 32BITS . 52 FIGURE 47. JITTER TRANSFER FUNCTION - E1 TX 10HZ 64BITS 64BITS . 53 II XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 FIGURE 48. JITTER TRANSFER FUNCTION - E1 TX 1.5HZ 64BITS 64BITS . 54 FIGURE 49. JITTER TRANSFER FUNCTION - E1 RX 10HZ 32BITS 32BITS . 55 FIGURE 50. JITTER TRANSFER FUNCTION - E1 RX 10HZ 64BITS 64BITS . 56 FIGURE 51. JITTER TRANSFER FUNCTION - E1 RX 1.5HZ 64BITS 64BITS . 57 4.8.2 INTRINSIC JITTER. 57 FIGURE 52. TEST CIRCUIT FOR INTRINSIC JITTER MEASUREMENTS . 58 FIGURE 53. INTRINSIC JITTER - T1 MAX. VALUE MEASURED .019UIPP 019UIPP . 58 FIGURE 54. E1 INTRINSIC JITTER - MAX. VALUE MEASURED .023UIPP 023UIPP . 59 4.8.3 JITTER TRANSFER CURVE . 59 FIGURE 55. TEST CIRCUIT FOR JITTER TRANSFER CURVE . 59 5.0 MICROPROCESSOR INTERFACE BLOCK .60 TABLE 14: SELECTING THE MICROPROCESSOR INTERFACE MODE . 60 FIGURE 56. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK . 60 5.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS . 61 TABLE 15: XRT84SH314S XRT84SH314S MICROPROCESSOR INTERFACE SIGNALS COMMON TO BOTH INTEL AND MOTOROLA MODES . 61 TABLE 16: INTEL MODE: MICROPROCESSOR INTERFACE SIGNALS . 61 TABLE 17: MOTOROLA MODE: MICROPROCESSOR INTERFACE SIGNALS . 62 5.2 INTEL MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) . 63 FIGURE 57. INTEL µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS . 64 TABLE 18: INTEL MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS . 64 5.3 MPC86X MPC86X MODE PROGRAMMED I/O ACCESS (SYNCHRONOUS) . 65 FIGURE 58. MOTOROLA MPC86X MPC86X µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS . 66 TABLE 19: MOTOROLA MPC86X MPC86X MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS . 66 FIGURE 59. MOTOROLA 68K µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS . 67 TABLE 20: MOTOROLA 68K MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS . 67 6.0 REGISTER DESCRIPTIONS .68 6.1 REGISTER LISTS . 68 TABLE 21: MICROPROCESSOR REGISTER ADDRESS (ADDR[7:0]) . 68 TABLE 22: MICROPROCESSOR REGISTER CHANNEL DESCRIPTION. 68 TABLE 23: MICROPROCESSOR REGISTER GLOBAL DESCRIPTION . 69 6.2 DETAIL BIT DESCRIPTIONS . 70 TABLE 24: MICROPROCESSOR REGISTER 0X00H 0X00H BIT DESCRIPTION . 70 TABLE 25: CABLE LENGTH CONTROL . 71 TABLE 26: MICROPROCESSOR REGISTER 0X01H 0X01H BIT DESCRIPTION . 72 TABLE 27: MICROPROCESSOR REGISTER 0X02H 0X02H BIT DESCRIPTION . 73 TABLE 28: MICROPROCESSOR REGISTER 0X03H 0X03H BIT DESCRIPTION . 73 TABLE 29: MICROPROCESSOR REGISTER 0X04H 0X04H BIT DESCRIPTION . 74 TABLE 30: MICROPROCESSOR REGISTER 0X05H 0X05H BIT DESCRIPTION . 75 TABLE 32: MICROPROCESSOR REGISTER 0X07H 0X07H BIT DESCRIPTION . 77 TABLE 31: MICROPROCESSOR REGISTER 0X06H 0X06H BIT DESCRIPTION . 77 TABLE 33: MICROPROCESSOR REGISTER 0X08H 0X08H BIT DESCRIPTION . 78 TABLE 34: MICROPROCESSOR REGISTER 0X09H 0X09H BIT DESCRIPTION . 78 TABLE 35: MICROPROCESSOR REGISTER 0X0AH BIT DESCRIPTION . 78 TABLE 36: MICROPROCESSOR REGISTER 0X0BH BIT DESCRIPTION . 78 TABLE 37: MICROPROCESSOR REGISTER 0X0CH BIT DESCRIPTION . 79 TABLE 38: MICROPROCESSOR REGISTER 0X0DH BIT DESCRIPTION . 79 TABLE 39: MICROPROCESSOR REGISTER 0X0EH BIT DESCRIPTION . 79 TABLE 40: MICROPROCESSOR REGISTER 0X0FH BIT DESCRIPTION . 79 TABLE 41: MICROPROCESSOR REGISTER 0XE0H BIT DESCRIPTION . 80 TABLE 42: MICROPROCESSOR REGISTER 0XE1H BIT DESCRIPTION . 81 TABLE 43: MICROPROCESSOR REGISTER 0XE2H BIT DESCRIPTION . 81 TABLE 44: MICROPROCESSOR REGISTER 0XE3H BIT DESCRIPTION . 82 TABLE 45: MICROPROCESSOR REGISTER 0XE4H BIT DESCRIPTION . 82 TABLE 46: MICROPROCESSOR REGISTER 0XE5H BIT DESCRIPTION . 83 TABLE 47: MICROPROCESSOR REGISTER 0XE6H BIT DESCRIPTION . 84 TABLE 48: MICROPROCESSOR REGISTER 0XE7H BIT DESCRIPTION . 85 TABLE 49: MICROPROCESSOR REGISTER 0XE8H BIT DESCRIPTION . 85 6.2.1 CLOCK SELECT REGISTER. 86 FIGURE 60. REGISTER 0XE9H SUB REGISTERS . 86 TABLE 50: MICROPROCESSOR REGISTER 0XE9H BIT DESCRIPTION . 87 TABLE 51: MICROPROCESSOR REGISTER 0XEAH BIT DESCRIPTION . 88 TABLE 52: MICROPROCESSOR REGISTER 0XEBH BIT DESCRIPTION . 88 TABLE 53: E1 ARBITRARY SELECT . 89 TABLE 54: DEVICE "ID" REGISTER (0XFEH) . 90 TABLE 55: MICROPROCESSOR REGISTER 0XFFH BIT DESCRIPTION . 90 III XRT83SH314 XRT83SH314 REV. 1.0.3 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 7.0 ELECTRICAL CHARACTERISTICS . 91 TABLE 56: TABLE 57: TABLE 58: TABLE 59: TABLE 60: TABLE 61: TABLE 62: TABLE 63: ABSOLUTE MAXIMUM RATINGS . 91 DC DIGITAL INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS. 91 AC ELECTRICAL CHARACTERISTICS . 91 POWER CONSUMPTION . 91 E1 RECEIVER ELECTRICAL CHARACTERISTICS . 92 T1 RECEIVER ELECTRICAL CHARACTERISTICS . 93 E1 TRANSMITTER ELECTRICAL CHARACTERISTICS . 94 T1 TRANSMITTER ELECTRICAL CHARACTERISTICS . 94 ORDERING INFORMATION . 95 PACKAGE DIMENSIONS (DIE DOWN) . 95 REVISION HISTORY . 96 IV XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 PIN DESCRIPTIONS (BY FUNCTION) MICROPROCESSOR NAME PIN TYPE DESCRIPTION CS A22 I Chip Select Input Active low signal. This signal enables the microprocessor interface by pulling chip select "Low". The microprocessor interface is disabled when the chip select signal returns "High". ALE_TS C19 I Address Latch Enable Input (Transfer Start) See the Microprocessor section of this datasheet for a description. WR_R/W A20 I Write Strobe Input (Read/Write) See the Microprocessor section of this datasheet for a description. RD_WE D18 I Read Strobe Input (Write Enable) See the Microprocessor section of this datasheet for a description. RDY_TA AA3 O Ready Output (Transfer Acknowledge) See the Microprocessor section of this datasheet for a description. INT B3 O Interrupt Output Active low signal. This signal is asserted "Low" when a change in alarm status occurs. Once the status registers have been read, the interrupt pin will return "High". GIE (Global Interrupt Enable) must be set "High" in the appropriate global register to enable interrupt generation. NOTE: This pin is an open-drain output that requires an external 10K pull-up resistor. µPCLK AB2 I Micro Processor Clock Input In a synchronous microprocessor interface, µPCLK is used as the internal timing reference for programming the LIU. ADDR10 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 A23 E20 C22 Y18 AA19 AB20 AC21 AB21 AA20 Y19 AC22 I Address Bus Input ADDR[10:8] is used as a chip select decoder. The LIU has 5 chip select output pins for enabling up to 5 additional devices for accessing internal registers. The LIU has the option to select itself (master device), up to 5 additional devices, or all 6 devices simultaneously by setting the ADDR[10:8] pins specified below. ADDR[7:0] is a direct address bus for permitting access to the internal registers. ADDR[10:8] 000 = Master Device 001 = Chip Select Output 1 (Pin B21) 010 = Chip Select Output 2 (Pin D19) 011 = Chip Select Output 3 (Pin C20) 100 = Chip Select Output 4 (Pin A21) 101 = Chip Select Output 5 (Pin B20) 110 = Reserved 111 = All Chip Selects Active Including the Master Device 4 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 MICROPROCESSOR NAME PIN TYPE DESCRIPTION DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 AA4 AB3 AC3 AA5 Y6 AB4 AC4 AB5 I/O µPTS2 µPTS1 µPTS0 AC23 AB22 AA21 I Microprocessor Type Select Input µPTS[2:0] are used to select the microprocessor type interface. 000 = Intel 68HC11 68HC11, 8051, 80C188 80C188 (Asynchronous) 001 = Motorola 68K (Asynchronous) 111 = Motorola MPC8260 MPC8260, MPC860 MPC860 Power PC (Synchronous) Reset B22 I Hardware Reset Input Active low signal. When this pin is pulled "Low" for more than 10µS, the internal registers are set to their default state. See the register description for the default values. Bi-directional Data Bus DATA[7:0] is a bi-directional data bus used for read and write operations. NOTE: Internally pulled "High" with a 50K resistor. CS5 CS4 CS3 CS2 CS1 B20 A21 C20 D19 B21 O Chip Select Output The XRT83SH314 XRT83SH314 can be used to provide the necessary chip selects for up to 5 additional devices by using the 3 MSBs ADDR[10:8] from the 11-Bit address bus. The LIU allows up to 84-channel applications with only using one chip select. See the ADDR[10:0] definition in the pin description. RECEIVER SECTION NAME PIN TYPE DESCRIPTION RxON AB19 I Receive On/Off Input Upon power up, the receivers are powered off. Turning the receivers On or Off can be selected through the microprocessor interface by programming the appropriate channel register if the hardware pin is pulled "High". If the hardware pin is pulled "Low", all channels are automatically turned off. NOTE: Internally pulled "Low" with a 50K resistor. RxTSEL Y15 I Receive Termination Control Upon power up, the receivers are in "High" impedance. Switching to internal termination can be selected through the microprocessor interface by programming the appropriate channel register. However, to switch control to the hardware pin, RxTCNTL must be programmed to "1" in the appropriate global register. Once control has been granted to the hardware pin, it must be pulled "High" to switch to internal termination. NOTE: Internally pulled "Low" with a 50k resistor. 5 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 RECEIVER SECTION NAME PIN TYPE DESCRIPTION RLOS AB1 O Receive Loss of Signal (Global Pin for All 14-Channels) When a receive loss of signal occurs for any one of the 14-channels according to ITU-T G.775, the RLOS pin will go "High" for a minimum of one RCLK cycle. RLOS will remain "High" until the loss of signal condition clears. See the Receive Loss of Signal section of this datasheet for more details. NOTE: This pin is for redundancy applications to initiate an automatic switch to the backup card. For individual channel RLOS, see the register map. RCLK13 RCLK13 RCLK12 RCLK12 RCLK11 RCLK11 RCLK10 RCLK10 RCLK9 RCLK8 RCLK7 RCLK6 RCLK5 RCLK4 RCLK3 RCLK2 RCLK1 RCLK0 AB14 Y22 R22 P22 G22 F22 B14 B9 F2 G2 P2 R2 AA2 AA9 O RPOS13 RPOS13 RPOS12 RPOS12 RPOS11 RPOS11 RPOS10 RPOS10 RPOS9 RPOS8 RPOS7 RPOS6 RPOS5 RPOS4 RPOS3 RPOS2 RPOS1 RPOS0 Y14 W20 P20 N20 H20 G20 D14 D10 G4 H4 N4 P4 W4 Y10 O Receive Clock Output RCLK is the recovered clock from the incoming data stream. If the incoming signal is absent or RxON is pulled "Low", RCLK maintains its timing by using an internal master clock as its reference. RPOS/RNEG data can be updated on either edge of RCLK selected by RCLKE in the appropriate global register. NOTE: RCLKE is a global setting that applies to all 14 channels. RPOS/RDATA Output Receive digital output pin. In dual rail mode, this pin is the receive positive data output. In single rail mode, this pin is the receive non-return to zero (NRZ) data output. 6 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 RECEIVER SECTION NAME PIN TYPE DESCRIPTION RNEG13 RNEG13 RNEG12 RNEG12 RNEG11 RNEG11 RNEG10 RNEG10 RNEG9 RNEG8 RNEG7 RNEG6 RNEG5 RNEG4 RNEG3 RNEG2 RNEG1 RNEG0 AA14 Y21 P21 N21 H21 G21 C14 C10 F3 G3 N3 P3 Y3 AA10 O RNEG/LCV_OF Output In dual rail mode, this pin is the receive negative data output. In single rail mode, this pin is a Line Code Violation / Counter Overflow indicator. If LCV is selected by programming the appropriate global register and if a line code violation, a bi-polar violation, or excessive zeros occur, the LCV pin will pull "High" for a minimum of one RCLK cycle. LCV will remain "High" until there are no more violations. However, if OF is selected the LCV pin will pull "High" if the internal LCV counter is saturated. The LCV pin will remain "High" until the LCV counter is reset. RTIP13 RTIP13 RTIP12 RTIP12 RTIP11 RTIP11 RTIP10 RTIP10 RTIP9 RTIP8 RTIP7 RTIP6 RTIP5 RTIP4 RTIP3 RTIP2 RTIP1 RTIP0 AC14 Y23 T23 P23 G23 E23 A14 A9 E1 G1 P1 T1 Y1 AC9 I Receive Differential Tip Input RTIP is the positive differential input from the line interface. Along with the RRING signal, these pins should be coupled to a 1:1 transformer for proper operation. RRING13 RRING13 RRING12 RRING12 RRING11 RRING11 RRING10 RRING10 RRING9 RRING8 RRING7 RRING6 RRING5 RRING4 RRING3 RRING2 RRING1 RRING0 AC13 W23 U23 N23 H23 D23 A13 A10 D1 H1 N1 U1 W1 AC10 I Receive Differential Ring Input RRING is the negative differential input from the line interface. Along with the RTIP signal, these pins should be coupled to a 1:1 transformer for proper operation. 7 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 TRANSMITTER SECTION NAME PIN TYPE DESCRIPTION TxON AC20 I Transmit On/Off Input Upon power up, the transmitters are powered off. Turning the transmitters On or Off is selected through the microprocessor interface by programming the appropriate channel register if this pin is pulled "High". If the TxON pin is pulled "Low", all 14 transmitters are powered off. NOTES: 1. 2. DMO Y4 O TxON is ideal for redundancy applications. See the Redundancy Applications Section of this datasheet for more details. Internally pulled "Low" with a 50K resistor. Digital Monitor Output (Global Pin for All 14-Channels) When no transmit output pulse is detected for more than 128 TCLK cycles on one of the 14-channels, the DMO pin will go "High" for a minimum of one TCLK cycle. DMO will remain "High" until the transmitter sends a valid pulse. NOTE: This pin is for redundancy applications to initiate an automatic switch to the backup card. For individual channel DMO, see the register map. TCLK13 TCLK13 TCLK12 TCLK12 TCLK11 TCLK11 TCLK10 TCLK10 TCLK9 TCLK8 TCLK7 TCLK6 TCLK5 TCLK4 TCLK3 TCLK2 TCLK1 TCLK0 Y16 Y17 AC18 D16 C17 A19 B16 D7 A3 B5 B6 AC6 AC5 AC7 I TPOS13 TPOS13 TPOS12 TPOS12 TPOS11 TPOS11 TPOS10 TPOS10 TPOS9 TPOS8 TPOS7 TPOS6 TPOS5 TPOS4 TPOS3 TPOS2 TPOS1 TPOS0 AB17 AA18 AB18 A18 D17 B19 A17 B7 C4 B4 D6 AB6 AA6 Y8 I Transmit Clock Input TCLK is the input facility clock used to sample the incoming TPOS/TNEG data. If TCLK is absent, pulled "Low", or pulled "High", the transmitter outputs at TTIP/TRING can be selected to send an all "ones" or an all" zero" signal by programming TCLKCNL in the appropriate global register. TPOS/TNEG data can be sampled on either edge of TCLK selected by TCLKE in the appropriate global register. NOTES: 1. TCLKE is a global setting that applies to all 14 channels. 2. Internally pulled "Low" with a 50k resistor. TPOS/TDATA Input Transmit digital input pin. In dual rail mode, this pin is the transmit positive data input. In single rail mode, this pin is the transmit non-return to zero (NRZ) data input. NOTE: Internally pulled "Low" with a 50K resistor. 8 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 TRANSMITTER SECTION NAME PIN TYPE DESCRIPTION TNEG13 TNEG13 TNEG12 TNEG12 TNEG11 TNEG11 TNEG10 TNEG10 TNEG9 TNEG8 TNEG7 TNEG6 TNEG5 TNEG4 TNEG3 TNEG2 TNEG1 TNEG0 AC17 AC19 AA17 B17 B18 C18 C16 C7 D5 C5 C6 AA7 Y7 AB7 I Transmit Negative Data Input In dual rail mode, this pin is the transmit negative data input. In single rail mode, this pin can be left unconnected. TTIP13 TTIP13 TTIP12 TTIP12 TTIP11 TTIP11 TTIP10 TTIP10 TTIP9 TTIP8 TTIP7 TTIP6 TTIP5 TTIP4 TTIP3 TTIP2 TTIP1 TTIP0 AA13 W21 R21 M21 J21 F21 C13 C11 E3 H3 M3 R3 W3 AA11 O Transmit Differential Tip Output TTIP is the positive differential output to the line interface. Along with the TRING signal, these pins should be coupled to a 1:2 step up transformer for proper operation. TRING13 TRING13 TRING12 TRING12 TRING11 TRING11 TRING10 TRING10 TRING9 TRING8 TRING7 TRING6 TRING5 TRING4 TRING3 TRING2 TRING1 TRING0 AB12 V22 T20 M22 J22 D22 B12 B11 C2 H2 M2 U2 V3 AB11 O Transmit Differential Ring Output TRING is the negative differential output to the line interface. Along with the TTIP signal, these pins should be coupled to a 1:2 step up transformer for proper operation. NOTE: Internally pulled "Low" with a 50K resistor. 9 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 CONTROL FUNCTION NAME PIN TYPE TEST D4 I DESCRIPTION Factory Test Mode For normal operation, the TEST pin should be tied to ground. NOTE: Internally pulled "Low" with a 50k resistor. ICT A2 I In Circuit Testing When this pin is tied "Low", all output pins are forced to "High" impedance for in circuit testing. NOTE: Internally pulled "High" with a 50K resistor. CLOCK SECTION NAME PIN TYPE DESCRIPTION MCLKin A6 I Master Clock Input The master clock input can accept a wide range of inputs that can be used to generate T1 or E1 clock rates on a per channel basis. See the register map for details. 8kHzOUT D8 O 8kHz Output Clock MCLKE1out A5 O 2.048MHz Output Clock MCLKE1Nout A4 O 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz Output Clock See the register map for programming details. MCLKT1out A7 O 1.544MHz Output Clock MCLKT1Nout B8 O 1.544MHz, 3.088MHz, 6.176MHz, or 12.352MHz Output Clock See the register map for programming details. NAME PIN TYPE DESCRIPTION ATP_TIP ATP_RING D21 K21 I/O Analog Test Pin_TIP Analog Test Pin_RING These pins are used to check continuity of the Transmit and Receive TIP and RING connections on the assembled board. JTAG SECTION See SEE"ANALOG BOARD CONTINUITY CHECK" ON PAGE 40. for more detailed description. TMS E4 I Test Mode Select This pin is used as the input mode select for the boundary scan chain. TCK B1 I Test Clock Input This pin is used as the input clock source for the boundary scan chain. 10 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 JTAG SECTION NAME PIN TYPE DESCRIPTION TDI A1 I Test Data In This pin is used as the input data pin for the boundary scan chain. TDO D3 O Test Data Out This pin is used as the output data pin for the boundary scan chain. POWER AND GROUND NAME PIN TYPE DESCRIPTION TVDD13 TVDD13 TVDD12 TVDD12 TVDD11 TVDD11 TVDD10 TVDD10 TVDD9 TVDD8 TVDD7 TVDD6 TVDD5 TVDD4 TVDD3 TVDD2 TVDD1 TVDD0 AB13 V21 T21 N22 H22 E21 B13 B10 D2 J3 N2 T3 U4 AB10 PWR Transmit Analog Power Supply (3.3V ±5%) TVDD can be shared with DVDD. However, it is recommended that TVDD be isolated from the analog power supply RVDD. For best results, use an internal power plane for isolation. If an internal power plane is not available, a ferrite bead can be used. Each power supply pin should be bypassed to ground through an external 0.1µF capacitor. RVDD13 RVDD13 RVDD12 RVDD12 RVDD11 RVDD11 RVDD10 RVDD10 RVDD9 RVDD8 RVDD7 RVDD6 RVDD5 RVDD4 RVDD3 RVDD2 RVDD1 RVDD0 AC15 AA23 T22 R23 F23 E22 A15 A8 E2 F1 R1 T2 Y2 AB9 PWR Receive Analog Power Supply (3.3V ±5%) RVDD should not be shared with other power supplies. It is recommended that RVDD be isolated from the digital power supply DVDD and the analog power supply TVDD. For best results, use an internal power plane for isolation. If an internal power plane is not available, a ferrite bead can be used. Each power supply pin should be bypassed to ground through an external 0.1µF capacitor. DVDD DVDD DVDD DVDD DVDD DVDD J2 V2 D12 AA12 U21 K23 PWR Digital Power Supply (3.3V ±5%) DVDD should be isolated from the analog power supplies. For best results, use an internal power plane for isolation. If an internal power plane is not available, a ferrite bead can be used. Every two DVDD power supply pins should be bypassed to ground through at least one 0.1µF capacitor. 11 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 POWER AND GROUND NAME PIN TYPE DESCRIPTION DVDD_DRV DVDD_DRV DVDD_DRV DVDD_DRV DVDD_DRV DVDD_DRV DVDD_PRE DVDD_PRE DVDD_PRE DVDD_PRE DVDD_UP C21 AC2 K3 D9 AA16 U22 C3 Y5 D20 Y20 AA15 PWR Digital Power Supply (3.3V ±5%) DVDD should be isolated from the analog power supplies. For best results, use an internal power plane for isolation. If an internal power plane is not available, a ferrite bead can be used. Every two DVDD power supply pins should be bypassed to ground through at least one 0.1µF capacitor. AVDD_BIAS AVDD_PLL22 PLL22 AVDD_PLL21 PLL21 AVDD_PLL12 PLL12 AVDD_PLL11 PLL11 K4 C15 B15 AB16 AC16 PWR Analog Power Supply (3.3V ±5%) AVDD should be isolated from the digital power supplies. For best results, use an internal power plane for isolation. If an internal power plane is not available, a ferrite bead can be used. Each power supply pin should be bypassed to ground through at least one 0.1µF capacitor. TGND13 TGND13 TGND12 TGND12 TGND11 TGND11 TGND10 TGND10 TGND9 TGND8 TGND7 TGND6 TGND5 TGND4 TGND3 TGND2 TGND1 TGND0 Y13 V20 R20 M20 J20 F20 D13 D11 F4 J4 M4 R4 V4 Y11 GND Transmit Analog Ground It's recommended that all ground pins of this device be tied together. RGND13 RGND13 RGND12 RGND12 RGND11 RGND11 RGND10 RGND10 RGND9 RGND8 RGND7 RGND6 RGND5 RGND4 RGND3 RGND2 RGND1 RGND0 AC12 W22 V23 M23 J23 C23 A12 A11 C1 J1 M1 V1 W2 AC11 GND Receive Analog Ground It's recommended that all ground pins of this device be tied together. 12 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 POWER AND GROUND NAME PIN TYPE DESCRIPTION DGND DGND DGND DGND DGND DGND L2 T4 C12 Y12 U20 L23 GND Digital Ground It's recommended that all ground pins of this device be tied together. DGND_DRV DGND_DRV DGND_DRV DGND_DRV DGND_DRV DGND_DRV DGND_PRE DGND_PRE DGND_PRE DGND_PRE DGND_UP B2 U3 A16 AA8 L21 AB23 L4 D15 AB8 L20 AB15 GND Digital Ground It's recommended that all ground pins of this device be tied together. AGND_BIAS AGND_PLL22 PLL22 AGND_PLL21 PLL21 AGND_PLL12 PLL12 AGND_PLL11 PLL11 L3 C9 C8 Y9 AC8 GND Analog Ground It's recommended that all ground pins of this device be tied together. NAME PIN TYPE NC NC NC NC NC NC NC NC NC NC K1 L1 AA1 AC1 K2 K20 K22 L22 AA22 B23 NC NO CONNECTS DESCRIPTION No Connect This pin can be left floating or tied to ground. 13 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 1.0 CLOCK SYNTHESIZER In system design, fewer clocks on the network card could reduce noise and interference. Common clock references such as 8kHz are readily available to network designers. Network cards that support both T1 and E1 modes must be able to produce 1.544MHz and 2.048MHz transmission data. The XRT83SH314 XRT83SH314 has a built in clock synthesizer that requires only one input clock reference by programming CLKSEL[3:0] in the appropriate global register. A list of the input clock options is shown in Table 1. TABLE 1: INPUT CLOCK SOURCE SELECT CLKSEL[3:0] INPUT CLOCK REFERENCE 0h (0000) 2.048 MHz 1h (0001) 1.544MHz 2h (0010) 8 kHz 3h (0011) 16 kHz 4h (0100) 56 kHz 5h (0101) 64 kHz 6h (0110) 128 kHz 7h (0111) 256 kHz 8h (1000) 4.096 MHz 9h (1001) 3.088 MHz Ah (1010) 8.192 MHz Bh (1011) 6.176 MHz Ch (1100) 16.384 MHz Dh (1101) 12.352 MHz Eh (1110) 2.048 MHz Fh (1111) 1.544 MHz The single input clock reference is used to generate multiple timing references. The first objective of the clock synthesizer is to generate 1.544MHz and 2.048MHz for each of the 14 channels. This allows each channel to operate in either T1 or E1 mode independent from the other channels. The state of the equalizer control bits in the appropriate channel registers determine whether the LIU operates in T1 or E1 mode. The second objective is to generate additional output clock references for system use. The available output clock references are shown in Figure 2. 14 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 FIGURE 2. SIMPLIFIED BLOCK DIAGRAM OF THE CLOCK SYNTHESIZER Input Clock Clock Synthesizer Internal Reference 1.544MHz 2.048MHz 8kHzOUT 8kHz 1.544Mhz MCLKT1out 2.048MHz MCLKE1out MCLKE1Nout MCLKT1Nout 1.1 Programmable Programmable 2.048/4.096/8.192/16.384 MHz 1.544/3.088/6.176/12.352MHz ALL T1/E1 Mode To reduce system noise and power consumption, the XRT83SH314 XRT83SH314 offers an ALL T1/E1 mode. Since most line card designs are configured to operate in T1 or E1 only, the LIU can be selected to shut off the timing references for the mode not being used by programming the appropriate global register. By default the ALL T1/E1 mode is enabled (ALLT1/E1 bit = "0"). If the LIU is configured for T1, all E1 clock references and the 8kHz reference are shut off internally to the chip. This reduces the amount of internal clocks switching within the LIU, hence reducing noise and power consumption. In E1 mode, the T1 clock references are internally shut off, however the 8kHz reference is available. To disable this feature, the ALLT1/E1 bit must be set to a "1" in the appropriate global register. 2.0 RECEIVE PATH LINE INTERFACE The receive path of the XRT83SH314 XRT83SH314 LIU consists of 14 independent T1/E1/J1 receivers. The following section describes the complete receive path from RTIP/RRING inputs to RCLK/RPOS/RNEG outputs. A simplified block diagram of the receive path is shown in Figure 3. FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH RCLK RPOS RNEG HDB3/B8ZS Decoder Rx Jitter Attenuator Clock & Data Recovery 15 Peak Detector & Slicer RTIP RRING XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 2.1 2.1.1 REV. 1.0.3 Line Termination (RTIP/RRING) CASE 1: Internal Termination The input stage of the receive path accepts standard T1/E1/J1 twisted pair or E1 coaxial cable inputs through RTIP and RRING. The physical interface is optimized by placing the terminating impedance inside the LIU. This allows one bill of materials for all modes of operation reducing the number of external components necessary in system design. The receive termination impedance (along with the transmit impedance) is selected by programming TERSEL[1:0] to match the line impedance. Selecting the internal impedance is shown in Table 2. TABLE 2: SELECTING THE INTERNAL IMPEDANCE TERSEL[1:0] RECEIVE TERMINATION 0h (00) 100 1h (01) 110 2h (10) 75 3h (11) 120 The XRT83SH314 XRT83SH314 has the ability to switch the internal termination to "High" impedance by programming RxTSEL in the appropriate channel register. For internal termination, set RxTSEL to "1". By default, RxTSEL is set to "0" ("High" impedance). For redundancy applications, a dedicated hardware pin (RxTSEL) is also available to control the receive termination for all channels simultaneously. This hardware pin takes priority over the register setting if RxTCNTL is set to "1" in the appropriate global register. If RxTCNTL is set to "0", the state of this pin is ignored. See Figure 4 for a typical connection diagram using the internal termination. FIGURE 4. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION XRT83SH314 XRT83SH314 LIU Receiver Input RTIP 1:1 Line Interface T1/E1/J1 RRING One Bill of Materials Internal Impedance 16 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 2.1.2 CASE 2: Internal Termination With One External Fixed Resistor for All Modes Along with the internal termination, a high precision external fixed resistor can be used to optimize the return loss. This external resistor can be used for all modes of operation ensuring one bill of materials. There are three resistor values that can be used by setting the RxRES[1:0] bits in the appropriate channel register. Selecting the value for the external fixed resistor is shown in Table 3. TABLE 3: SELECTING THE VALUE OF THE EXTERNAL FIXED RESISTOR RXRES[1:0] EXTERNAL FIXED RESISTOR 0h (00) None 1h (01) 240 2h (10) 210 3h (11) 150 By default, RxRES[1:0] is set to "None" for no external fixed resistor. If an external fixed resistor is used, the XRT83SH314 XRT83SH314 uses the parallel combination of the external fixed resistor and the internal termination as the input impedance. See Figure 5 for a typical connection diagram using the external fixed resistor. NOTE: Without the external resistor, the XRT83SH314 XRT83SH314 meets all return loss specifications. This mode was created to add flexibility for optimizing return loss by using a high precision external resistor. FIGURE 5. TYPICAL CONNECTION DIAGRAM USING ONE EXTERNAL FIXED RESISTOR XRT83SH314 XRT83SH314 LIU Receiver Input RTIP 1:1 R RRING R=240, 210, or 150 Internal Impedance 17 Line Interface T1/E1/J1 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 2.2 REV. 1.0.3 Clock and Data Recovery The receive clock (RCLK) is recovered by the clock and data recovery circuitry. An internal PLL locks on the incoming data stream and outputs a clock that's in phase with the incoming signal. This allows for multichannel T1/E1/J1 signals to arrive from different timing sources and remain independent. In the absence of an incoming signal, RCLK maintains its timing by using the internal master clock as its reference. The recovered data can be updated on either edge of RCLK. By default, data is updated on the rising edge of RCLK. To update data on the falling edge of RCLK, set RCLKE to "1" in the appropriate global register. Figure 6 is a timing diagram of the receive data updated on the rising edge of RCLK. Figure 7 is a timing diagram of the receive data updated on the falling edge of RCLK. The timing specifications are shown in Table 4. FIGURE 6. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK R C LK R R DY RCLKF R C LK RPOS or RNEG ROH FIGURE 7. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK RCLKF RDY RCLK RPOS or RNEG ROH 18 RCLKR XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 TABLE 4: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG PARAMETER SYMBOL MIN TYP MAX UNITS RCLK Duty Cycle RCDU 45 50 55 % Receive Data Setup Time RSU 150 - - ns Receive Data Hold Time RHO 150 - - ns RCLK to Data Delay RDY - - 40 ns RCLK Rise Time (10% to 90%) with 25pF Loading RCLKR - - 40 ns RCLK Fall Time (90% to 10%) with 25pF Loading RCLKF - - 40 ns NOTE: VDD=3.3V ±5%, TA=25°C, Unless Otherwise Specified 2.2.1 Receive Sensitivity To meet short haul requirements, the XRT83SH314 XRT83SH314 can accept T1/E1/J1 signals that have been attenuated by 12dB of flat loss in E1 mode or by 655 feet of cable loss along with 6dB of flat loss in T1 mode. However, the XRT83SH314 XRT83SH314 can tolerate cable loss and flat loss beyond the industry specifications. The receive sensitivity in the short haul mode is approximately 4,000 feet without experiencing bit errors, LOF, pattern synchronization, etc. Although data integrity is maintained, the RLOS function (if enabled) will report an RLOS condition according to the receiver loss of signal section in this datasheet. The test configuration for measuring the receive sensitivity is shown in Figure 8. FIGURE 8. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY W&G ANT20 ANT20 Rx Tx Cable Loss Network Analyzer Flat Loss Rx Tx E1 = PRBS 215 - 1 T1 = PRBS 223 - 1 19 External Loopback XRT83SH314 XRT83SH314 14-Channel Long Haul LIU XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 2.2.2 REV. 1.0.3 Interference Margin The interference margin for the XRT83SH314 XRT83SH314 will be added when the first revision of silicon arrives. The test configuration for measuring the interference margin is shown in Figure 9. FIGURE 9. TEST CONFIGURATION FOR MEASURING INTERFERENCE MARGIN E1 = 1,024kHz T1 = 772kHz Sinewave Generator Flat Loss E1 = PRBS 215 - 1 T1 = PRBS 223 - 1 W&G ANT20 ANT20 Network Analyzer Rx Tx Rx 2.2.3 External Loopback Cable Loss Tx XRT83SH314 XRT83SH314 14-Channel LIU General Alarm Detection and Interrupt Generation The receive path detects RLOS, AIS, QRPD and FLS. These alarms can be individually masked to prevent the alarm from triggering an interrupt. To enable interrupt generation, the Global Interrupt Enable (GIE) bit must be set "High" in the appropriate global register. Any time a change in status occurs (it the alarms are enabled), the interrupt pin will pull "Low" to indicate an alarm has occurred. Once the status registers have been read, the INT pin will return "High". The status registers are Reset Upon Read (RUR). The interrupts are categorized in a hierarchical process block. Figure 10 is a simplified block diagram of the interrupt generation process. 20 XRT83SH314 XRT83SH314 REV. 1.0.3 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT FIGURE 10. INTERRUPT GENERATION PROCESS BLOCK Global Interrupt Enable (GIE="1") Global Channel Interrupt Status (Indicates Which Channel(s) Experienced a Change in Status) Individual Alarm Status Change (Indicates Which Alarm Experienced a Change) Individual Alarm Indication (Indicates the Alarm Condition Active/Inactive) NOTE: The interrupt pin is an open-drain output that requires a 10k external pull-up resistor. 21 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 2.2.3.1 REV. 1.0.3 RLOS (Receiver Loss of Signal) In T1 mode, RLOS is declared if an incoming signal has no transitions over a period of 175 +/-75 contiguous pulse intervals. However, the XRT83SH314 XRT83SH314 LIU has a built in analog RLOS so that the user can be notified when the amplitude of the incoming signal has been attenuated -9dB below the equalizer gain setting. For example: In T1 or E1 short haul mode, the gain setting is 15dB. Once the input reaches an amplitude of -24dB below nominal, the LIU will declare RLOS. The RLOS circuitry clears when the input reaches +3dB relative to where it was declared. This +3dB value is a pre-determined hysteresis so that transients will not cause the RLOS to clear. In E1 mode, RLOS is declared if an incoming signal has no transitions for N consecutive pulse intervals, where 10N255 10N255. According to G.775, no transitions in E1 mode is defined between -9dB and -35dB below nominal. Figure 11 is a simplified block diagram of the analog RLOS function. Table 5 summarizes the analog RLOS values for the different equalizer gain settings. FIGURE 11. ANALOG RECEIVE LOS OF SIGNAL FOR T1/E1/J1 Normalized up to EQC[4:0] Setting -9dB Clear LOS +3dB Declare LOS Declare LOS +3dB Clear LOS -9dB Normalized up to EQC[4:0] Setting · TABLE 5: ANALOG RLOS DECLARE/CLEAR (TYPICAL VALUES) FOR T1/E1 GAIN SETTING DECLARE CLEAR 15dB (Short Haul Mode) -24dB -21dB 29dB (Monitoring Gain Mode) -38dB -35dB NOTE: For programming the equalizer gain setting on a per channel basis, see the microprocessor register map for details. 2.2.3.2 EXLOS (Extended Loss of Signal) By enabling the extended loss of signal by programming the appropriate channel register, the digital RLOS is extended to count 4,096 consecutive zeros before declaring RLOS in T1 and E1 mode. By default, EXLOS is disabled and RLOS operates in normal mode. 2.2.3.3 AIS (Alarm Indication Signal) The XRT83SH314 XRT83SH314 adheres to the ITU-T G.775 specification for an all ones pattern. The alarm indication signal is set to "1" if an all ones pattern (at least 99.9% ones density) is present for T, where T is 3ms to 75ms in T1 mode. AIS will clear when the ones density is not met within the same time period T. In E1 mode, the AIS is set to "1" if the incoming signal has 2 or less zeros in a 512-bit window. AIS will clear when the incoming signal has 3 or more zeros in the 512-bit window. 22 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 2.2.3.4 FLSD (FIFO Limit Status Detection) The purpose of the FIFO limit status is to indicate when the Read and Write FIFO pointers are within a predetermined range (over-flow or under-flow indication). The FLSD is set to "1" if the FIFO Read and Write Pointers are within ±3-Bits. 2.2.3.5 LCVD (Line Code Violation Detection) The LIU contains 14 independent, 16-bit LCV counters. When the counters reach full-scale, they remain saturated at FFFFh until they are reset globally or on a per channel basis. For performance monitoring, the counters can be updated globally or on a per channel basis to place the contents of the counters into holding registers. The LIU uses an indirect address bus to access a counter for a given channel. Once the contents of the counters have been placed in holding registers, they can be individually read out from register 0xE8h 8-bits at a time according to the BYTEsel bit in the appropriate global register. By default, the LSB is in register 0xE8h until the BYTEsel is pulled "High" where upon the MSB will be placed in the register for read back. Once both bytes have been read, the next channel may be selected for read back. By default, the LVC/OFD will be set to a "1" if the receiver is currently detecting line code violations or excessive zeros for HDB3 (E1 mode) or B8ZS (T1 mode). In AMI mode, the LCVD will be set to a "1" if the receiver is currently detecting bipolar violations or excessive zeros. However, if the LIU is configured to monitor the 16-bit LCV counter by programming the appropriate global register, the LCV/OFD will be set to a "1" if the counter saturates. 2.3 Jitter Attenuator The jitter attenuator reduces phase and frequency jitter in the recovered clock if it is selected in the receive path. The jitter attenuator uses a data FIFO (First In First Out) with a programmable depth of 32-bit or 64-bit. If the LIU is used for line synchronization (loop timing systems), the JA should be enabled in the receive path. When the Read and Write pointers of the FIFO are within 2-Bits of over-flowing or under-flowing, the bandwidth of the jitter attenuator is widened to track the short term input jitter, thereby avoiding data corruption. When this condition occurs, the jitter attenuator will not attenuate input jitter until the Read/Write pointer's position is outside the 2-Bit window. In T1 mode, the bandwidth of the JA is always set to 3Hz. In E1 mode, the bandwidth is programmable to either 10Hz or 1.5Hz (1.5Hz automatically selects the 64-Bit FIFO depth). The JA has a clock delay equal to ½ of the FIFO bit depth. NOTE: If the LIU is used in a multiplexer/mapper application where stuffing bits are typically removed, the jitter attenuator can be selected in the transmit path to smooth out the gapped clock. See the Transmit Section of this datasheet. 2.4 HDB3/B8ZS Decoder In single rail mode, RPOS can decode AMI or HDB3/B8ZS signals. For E1 mode, HDB3 is defined as any block of 4 successive zeros replaced with OOOV or BOOV, so that two successive V pulses are of opposite polarity to prevent a DC component. In T1 mode, 8 successive zeros are replaced with OOOVBOVB. If the HDB3/B8ZS decoder is selected, the receive path removes the V and B pulses so that the original data is output to RPOS. 23 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 2.5 REV. 1.0.3 RPOS/RNEG/RCLK The digital output data can be programmed to either single rail or dual rail formats. Figure 12 is a timing diagram of a repeating "0011" pattern in single-rail mode. Figure 13 is a timing diagram of the same fixed pattern in dual rail mode. FIGURE 12. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN 0 0 1 1 0 1 0 RCLK RPOS FIGURE 13. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN 0 0 1 RCLK RPOS RNEG 2.6 RxMUTE (Receiver LOS with Data Muting) The receive muting function can be selected by setting RxMUTE to "1" in the appropriate global register. If selected, any channel that experiences an RLOS condition will automatically pull RPOS and RNEG "Low" to prevent data chattering. If RLOS does not occur, the RxMUTE will remain inactive until an RLOS on a given channel occurs. The default setting for RxMUTE is "0" which is disabled. A simplified block diagram of the RxMUTE function is shown in Figure 14. FIGURE 14. SIMPLIFIED BLOCK DIAGRAM OF THE RXMUTE FUNCTION RPOS RNEG RxMUTE RLOS 24 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 3.0 TRANSMIT PATH LINE INTERFACE The transmit path of the XRT83SH314 XRT83SH314 LIU consists of 14 independent T1/E1/J1 transmitters. The following section describes the complete transmit path from TCLK/TPOS/TNEG inputs to TTIP/TRING outputs. A simplified block diagram of the transmit path is shown in Figure 15. FIGURE 15. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH TCLK TPOS TNEG 3.1 HDB3/B8ZS Encoder Tx Jitter Attenuator Timing Control Tx Pulse Shaper & Pattern Gen TTIP Line Driver TRING TCLK/TPOS/TNEG Digital Inputs In dual rail mode, TPOS and TNEG are the digital inputs for the transmit path. In single rail mode, TNEG has no function and can be left unconnected. The XRT83SH314 XRT83SH314 can be programmed to sample the inputs on either edge of TCLK. By default, data is sampled on the falling edge of TCLK. To sample data on the rising edge of TCLK, set TCLKE to "1" in the appropriate global register. Figure 16 is a timing diagram of the transmit input data sampled on the falling edge of TCLK. Figure 17 is a timing diagram of the transmit input data sampled on the rising edge of TCLK. The timing specifications are shown in Table 6. FIGURE 16. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK TCLKR TCLK TPOS or TNEG TSU THO 25 TCLKF XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 FIGURE 17. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK TCLKF TCLKR TCLK TPOS or TNEG TSU THO TABLE 6: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG PARAMETER SYMBOL MIN TYP MAX UNITS TCLK Duty Cycle TCDU 30 50 70 % Transmit Data Setup Time TSU 50 - - ns Transmit Data Hold Time THO 30 - - ns TCLK Rise Time (10% to 90%) TCLKR - - 40 ns TCLK Fall Time (90% to 10%) TCLKF - - 40 ns NOTE: VDD=3.3V ±5%, TA=25°C, Unless Otherwise Specified 3.2 HDB3/B8ZS Encoder In single rail mode, the LIU can encode the TPOS input signal to AMI or HDB3/B8ZS data. In E1 mode and HDB3 encoding selected, any sequence with four or more consecutive zeros in the input will be replaced with 000V or B00V, where "B" indicates a pulse conforming to the bipolar rule and "V" representing a pulse violating the rule. An example of HDB3 encoding is shown in Table 7. In T1 mode and B8ZS encoding selected, an input data sequence with eight or more consecutive zeros will be replaced using the B8ZS encoding rule. An example with Bipolar with 8 Zero Substitution is shown in Table 8. TABLE 7: EXAMPLES OF HDB3 ENCODING NUMBER OF PULSES BEFORE NEXT 4 ZEROS Input 0000 HDB3 (Case 1) Odd 000V HDB3 (Case 2) Even B00V 26 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 TABLE 8: EXAMPLES OF B8ZS ENCODING CASE 1 PRECEDING PULSE NEXT 8 BITS Input + 00000000 B8ZS 000VB0VB 000VB0VB AMI Output + 000+-0-+ Case 2 Input - B8ZS 000VB0VB 000VB0VB AMI Output 3.3 00000000 - 000-+0+- Jitter Attenuator The XRT83SH314 XRT83SH314 LIU is ideal for multiplexer or mapper applications where the network data crosses multiple timing domains. As the higher data rates are de-multiplexed down to T1 or E1 data, stuffing bits are typically removed which can leave gaps in the incoming data stream. The jitter attenuator can be selected in the transmit path with a 32-Bit or 64-Bit FIFO that is used to smooth the gapped clock into a steady T1 or E1 output. The maximum gap width of the 14-Channel LIU is shown in Table 9. TABLE 9: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS FIFO DEPTH MAXIMUM GAP WIDTH 32-Bit 20 UI 64-Bit 50 UI NOTE: If the LIU is used in a loop timing system, the jitter attenuator can be selected in the receive path. See the Receive Section of this datasheet. 3.4 TAOS (Transmit All Ones) The XRT83SH314 XRT83SH314 has the ability to transmit all ones on a per channel basis by programming the appropriate channel register. This function takes priority over the digital data present on the TPOS/TNEG inputs. For example: If a fixed "0011" pattern is present on TPOS in single rail mode and TAOS is enabled, the transmitter will output all ones. In addition, if digital or dual loopback is selected, the data on the RPOS output will be equal to the data on the TPOS input. Figure 18 is a diagram showing the all ones signal at TTIP and TRING. FIGURE 18. TAOS (TRANSMIT ALL ONES) 1 1 1 TAOS 3.5 Transmit Diagnostic Features In addition to TAOS, the XRT83SH314 XRT83SH314 offers multiple diagnostic features for analyzing network integrity such as ATAOS and QRSS on a per channel basis by programming the appropriate registers. These diagnostic features take priority over the digital data present on TPOS/TNEG inputs. The transmitters will send the diagnostic code to the line and will be maintained in the digital loopback if selected. When the LIU is responsible for sending diagnostic patterns, the LIU is automatically placed in the single rail mode. 27 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 3.5.1 REV. 1.0.3 ATAOS (Automatic Transmit All Ones) If ATAOS is selected by programming the appropriate global register, an AMI all ones signal will be transmitted for each channel that experiences an RLOS condition. If RLOS does not occur, the ATAOS will remain inactive until an RLOS on a given channel occurs. A simplified block diagram of the ATAOS function is shown in Figure 19. FIGURE 19. SIMPLIFIED BLOCK DIAGRAM OF THE ATAOS FUNCTION Tx TTIP TRING TAOS ATAOS RLOS 3.5.2 QRSS/PRBS Generation The XRT83SH314 XRT83SH314 can transmit a QRSS/PRBS random sequence to a remote location from TTIP/TRING. To select QRSS or PRBS, see the register map for programming details. The polynomial is shown in Table 10. TABLE 10: RANDOM BIT SEQUENCE POLYNOMIALS RANDOM PATTERN E1 QRSS 220 - 1 220 - 1 PRBS 3.6 T1 215 - 1 215 - 1 Transmit Pulse Shaper and Filter If TCLK is not present, pulled "Low", or pulled "High" the transmitter outputs at TTIP/TRING will automatically send an all ones or an all zero signal to the line by programming the appropriate global register. By default, the transmitters will send all zeros. To send all ones, the TCLKCNL bit must be set "High". 28 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 3.6.1 T1 Short Haul Line Build Out (LBO) The short haul transmitter output pulses are generated using a 7-Bit internal DAC (6-Bit plus the MSB sign bit). The line build out can be set to interface to five different ranges of cable attenuation by programming the appropriate channel register. The pulse shape is divided into eight discrete time segments which are set to fixed values to comply with the pulse template. The short haul LBO settings are shown in Table 11. TABLE 11: SHORT HAUL LINE BUILD OUT LBO SETTING EQC[4:0] 08h (01000) 0 - 133 Feet 09h (01001) 133 - 266 Feet 0Ah (01010) 266 - 399 Feet 0Bh (01011) 399 - 533 Feet 0Ch (01100) 3.6.2 RANGE OF CABLE ATTENUATION 533 - 655 Feet Arbitrary Pulse Generator For T1 and E1 The arbitrary pulse generator divides the pulse into eight individual segments. Each segment is set by a 7-Bit binary word by programming the appropriate channel register. This allows the system designer to set the overshoot, amplitude, and undershoot for a unique line build out. The MSB (bit 7) is a sign-bit. If the sign-bit is set to "0", the segment will move in a positive direction relative to a flat line (zero) condition. If this sign-bit is set to "1", the segment will move in a negative direction relative to a flat line condition. The resolution of the DAC is typically 60mV per LSB. Thus, writing 7-bit = 1111111 will clamp the output at either voltage rail corresponding to a maximum amplitude. A pulse with numbered segments is shown in Figure 20. FIGURE 20. ARBITRARY PULSE SEGMENT ASSIGNMENT 1 2 3 Segment 1 2 3 4 5 6 7 8 4 Register 0xn8 0xn9 0xna 0xnb 0xnc 0xnd 0xne 0xnf 8 7 6 5 NOTE: By default, the arbitrary segments are programmed to 0x00h. The transmitter outputs will result in an all zero pattern to the line interface. 29 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 3.6.3 REV. 1.0.3 Setting Registers to select an Aribtrary Pulse For T1: Address:0x0D hex For E1: Address: 0xF4 hex, bit D0 To program the transmit output pulse, once the arbitrary pulse has been selected, write the appropriate values into the segment registers in Table 12. The transmit output pulse is divided into eight individual segments. Segment 1 corresponds to the beginning of the pulse and segment 8 to end the pulse. The value for each segment can be programed individually through a corresponding 8-bit register. In normal operation, i.e., non-arbitrary mode, codes are stored in an internal ROM are used to generate the pulse shape, as shown in Table 12. Typical ROM values are given below in Hex. TABLE 12: TYPICAL ROM VALUES LINE DISTANCE SEGMENT # FEET 1 2 3 4 5 6 7 8 0 - 133 24 21 20 20 4C 47 44 42 133 - 266 29 23 22 21 4E 4A 47 43 266 - 399 30 25 24 23 59 40 48 44 399 - 525 34 26 24 23 5F 50 48 44 525 - 655 39 28 25 23 59 50 48 44 E1 2C 2A 2A 00 00 00 00 00 NOTE: The same register bank (eight registers in total) holds the values for any given line length. In other words , the user can not load all the desired values for all the line lengths into the device at one time. If the line length is changed, a new code must be loaded into the register bank. 3.7 DMO (Digital Monitor Output) The driver monitor circuit is used to detect transmit driver failures by monitoring the activities at TTIP/TRING outputs. Driver failure may be caused by a short circuit in the primary transformer or system problems at the transmit inputs. If the transmitter of a channel has no output for more than 128 clock cycles, DMO goes "High" until a valid transmit pulse is detected. If the DMO interrupt is enabled, the change in status of DMO will cause the interrupt pin to go "Low". Once the status register is read, the interrupt pin will return "High" and the status register will be reset (RUR). 3.8 Line Termination (TTIP/TRING) The output stage of the transmit path generates standard return-to-zero (RZ) signals to the line interface for T1/ E1/J1 twisted pair or E1 coaxial cable. The physical interface is optimized by placing the terminating impedance inside the LIU. This allows one bill of materials for all modes of operation reducing the number of external components necessary in system design. The transmitter outputs only require one DC blocking capacitor of 0.68µF. For redundancy applications (or simply to tri-state the transmitters), set TxTSEL to a "1" in the appropriate channel register. A typical transmit interface is shown in Figure 21. 30 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 FIGURE 21. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION XRT83SH314 XRT83SH314 LIU TTIP Transmitter Output 1:2 C=0.68uF Line Interface T1/E1/J1 TRING One Bill of Materials Internal Impedance 31 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 4.0 T1/E1 APPLICATIONS This applications section describes common T1/E1 system considerations along with references to application notes available for reference where applicable. 4.1 Loopback Diagnostics The XRT83SH314 XRT83SH314 supports several loopback modes for diagnostic testing. The following section describes the local analog loopback, remote loopback, digital loopback, and dual loopback modes. 4.1.1 Local Analog Loopback With local analog loopback activated, the transmit output data at TTIP/TRING is internally looped back to the analog inputs at RTIP/RRING. External inputs at RTIP/RRING are ignored while valid transmit output data continues to be sent to the line. A simplified block diagram of local analog loopback is shown in Figure 22. FIGURE 22. SIMPLIFIED BLOCK DIAGRAM OF LOCAL ANALOG LOOPBACK QRSS/PRBS TAOS TCLK TPOS TNEG Encoder JA Timing Control RCLK RPOS RNEG Decoder JA Data and Clock Recovery TTIP TRING Tx Rx RTIP RRING NOTE: The transmit diagnostic features such as TAOS and QRSS take priority over the transmit input data at TCLK/TPOS/ TNEG. 4.1.2 Remote Loopback With remote loopback activated, the receive input data at RTIP/RRING is internally looped back to the transmit output data at TTIP/TRING. The remote loopback includes the Receive JA (if enabled). The transmit input data at TCLK/TPOS/TNEG are ignored while valid receive output data continues to be sent to the system. A simplified block diagram of remote loopback is shown in Figure 23. FIGURE 23. SIMPLIFIED BLOCK DIAGRAM OF REMOTE LOOPBACK QRSS/PRBS TAOS TCLK TPOS TNEG Encoder JA Timing Control RCLK RPOS RNEG Decoder JA Data and Clock Recovery 32 TTIP TRING Tx Rx RTIP RRING XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 4.1.3 Digital Loopback With digital loopback activated, the transmit input data at TCLK/TPOS/TNEG is looped back to the receive output data at RCLK/RPOS/RNEG. The digital loopback mode includes the Transmit JA (if enabled). The receive input data at RTIP/RRING is ignored while valid transmit output data continues to be sent to the line. A simplified block diagram of digital loopback is shown in Figure 24. FIGURE 24. SIMPLIFIED BLOCK DIAGRAM OF DIGITAL LOOPBACK QRSS/PRBS TAOS TCLK TPOS TNEG JA Timing Control RCLK RPOS RNEG 4.1.4 Encoder Decoder JA Data and Clock Recovery TTIP TRING Tx Rx RTIP RRING Dual Loopback With dual loopback activated, the remote loopback is combined with the digital loopback. A simplified block diagram of dual loopback is shown in Figure 25. FIGURE 25. SIMPLIFIED BLOCK DIAGRAM OF DUAL LOOPBACK QRSS/PRBS TAOS TCLK TPOS TNEG Encoder JA Timing Control RCLK RPOS RNEG Decoder JA Data and Clock Recovery 33 Tx Rx TTIP TRING RTIP RRING XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 4.2 REV. 1.0.3 84-Channel T1/E1 Multiplexer/Mapper Applications The XRT83SH314 XRT83SH314 has the capability of providing the necessary chip selects for multiple 14-channel LIU devices. The LIU is responsible for selecting itself, up to 5 additional LIU devices, or all 6 devices simultaneously for permitting access to internal registers. The state of the chip select output pins is determined by a chip select decoder controlled by the 3 MSBs of the address bus ADDR[10:8]. Only one LIU (Master) requires the ADDR[10:8]. The other 5 LIU devices use the 8 LSBs for the direct address bus ADDR[7:0]. Figure 26 is a simplified block diagram of connecting six 14-channel LIU devices for 84-channel applications. Selection of the chip select outputs using ADDR[10:8] is shown in Table 13. FIGURE 26. SIMPLIFIED BLOCK DIAGRAM OF AN 84-CHANNEL 84-CHANNEL APPLICATION Master CS[4:0] CS XRT83SH314 XRT83SH314 Slave 1 Slave CS XRT83SH314 XRT83SH314 CS XRT83SH314 XRT83SH314 2 Slave 3 Slave CS XRT83SH314 XRT83SH314 4 Data [7:0] Address A[7:0] Chip Address A[10:8] TABLE 13: CHIP SELECT ASSIGNMENTS ADDR[10:8] ACTIVE CHIP SELECT 0h (000) Current Device (Master) 1h (001) Chip 1 2h (010) Chip 2 3h (011) Chip 3 4h (100) Chip 4 5h (101) Chip 5 6h (110) Reserved 7h (111) All Devices Active 34 CS XRT83SH314 XRT83SH314 Slave XRT83SH314 XRT83SH314 5 6 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 4.3 Line Card Redundancy Telecommunication system design requires signal integrity and reliability. When a T1/E1 primary line card has a failure, it must be swapped with a backup line card while maintaining connectivity to a backplane without losing data. System designers can achieve this by implementing common redundancy schemes with the XRT83SH314 XRT83SH314 LIU. EXAR offers features that are tailored to redundancy applications while reducing the number of components and providing system designers with solid reference designs. RLOS and DMO If an RLOS or DMO condition occurs, the XRT83SH314 XRT83SH314 reports the alarm to the individual status registers on a per channel basis. However, for redundancy applications, an RLOS or DMO alarm can be used to initiate an automatic switch to the back up card. For this application, two global pins RLOS and DMO are used to indicate that one of the 14-channels has an RLOS or DMO condition. Typical Redundancy Schemes · 1:1 One backup card for every primary card (Facility Protection) · 1+1 One backup card for every primary card (Line Protection) · ·N+1 One backup card for N primary cards 4.3.1 1:1 and 1+1 Redundancy Without Relays The 1:1 facility protection and 1+1 line protection have one backup card for every primary card. When using 1:1 or 1+1 redundancy, the backup card has its transmitters tri-stated and its receivers in high impedance. This eliminates the need for external relays and provides one bill of materials for all interface modes of operation. For 1+1 line protection, the receiver inputs on the backup card have the ability to monitor the line for bit errors while in high impedance. The transmit and receive sections of the LIU device are described separately. 4.3.2 Transmit Interface with 1:1 and 1+1 Redundancy The transmitters on the backup card should be tri-stated. Select the appropriate impedance for the desired mode of operation, T1/E1/J1. A 0.68uF capacitor is used in series with TTIP for blocking DC bias. See Figure 27. for a simplified block diagram of the transmit section for a 1:1 and 1+1 redundancy. FIGURE 27. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR 1:1 AND 1+1 REDUNDANCY Backplane Interface Primary Card XRT83SH314 XRT83SH314 1:2 Tx 0.68uF T1/E1 Line Internal Impedence XRT83SH314 XRT83SH314 Backup Card 1:2 Tx 0.68uF Internal Impedence 35 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 4.3.3 REV. 1.0.3 Receive Interface with 1:1 and 1+1 Redundancy The receivers on the backup card should be programmed for "High" impedance. Since there is no external resistor in the circuit, the receivers on the backup card will not load down the line interface. This key design feature eliminates the need for relays and provides one bill of materials for all interface modes of operation. Select the impedance for the desired mode of operation, T1/E1/J1. To swap the primary card, set the backup card to internal impedance, then the primary card to "High" impedance. See Figure 28. for a simplified block diagram of the receive section for a 1:1 redundancy scheme. FIGURE 28. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR 1:1 AND 1+1 REDUNDANCY Backplane Interface Primary Card XRT83SH314 XRT83SH314 1:1 T1/E1 Line Rx Internal Impedence Backup Card XRT83SH314 XRT83SH314 1:1 Rx "High" Impedence 4.3.4 N+1 Redundancy Using External Relays N+1 redundancy has one backup card for N primary cards. Due to impedance mismatch and signal contention, external relays are necessary when using this redundancy scheme. The relays create complete isolation between the primary cards and the backup card. This allows all transmitters and receivers on the primary cards to be configured in internal impedance, providing one bill of materials for all interface modes of operation. The transmit and receive sections of the LIU device are described separately. 36 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 4.3.5 Transmit Interface with N+1 Redundancy For N+1 redundancy, the transmitters on all cards should be programmed for internal impedance. The transmitters on the backup card do not have to be tri-stated. To swap the primary card, close the desired relays, and tri-state the transmitters on the failed primary card. A 0.68uF capacitor is used in series with TTIP for blocking DC bias. See Figure 29 for a simplified block diagram of the transmit section for an N+1 redundancy scheme. FIGURE 29. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR N+1 REDUNDANCY Backplane Interface Line Interface Card Primary Card XRT83SH314 XRT83SH314 1:2 Tx 0.68uF T1/E1 Line Internal Impedence Primary Card XRT83SH314 XRT83SH314 1:2 Tx 0.68uF T1/E1 Line Internal Impedence Primary Card XRT83SH314 XRT83SH314 1:2 Tx 0.68uF T1/E1 Line Internal Impedence Backup Card XRT83SH314 XRT83SH314 Tx 0.68uF Internal Impedence 37 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 4.3.6 REV. 1.0.3 Receive Interface with N+1 Redundancy For N+1 redundancy, the receivers on the primary cards should be programmed for internal impedance. The receivers on the backup card should be programmed for "High" impedance mode. To swap the primary card, set the backup card to internal impedance, then the primary card to "High" impedance. See Figure 30 for a simplified block diagram of the receive section for a N+1 redundancy scheme. FIGURE 30. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR N+1 REDUNDANCY Backplane Interface Line Interface Card Primary Card XRT83SH314 XRT83SH314 1:1 Rx T1/E1 Line Internal Impedence Primary Card XRT83SH314 XRT83SH314 1:1 T1/E1 Line Rx Internal Impedence Primary Card XRT83SH314 XRT83SH314 1:1 Rx T1/E1 Line Internal Impedence Backup Card XRT83SH314 XRT83SH314 Rx "High" Impedence 38 XRT83SH314 XRT83SH314 14-CHANNEL 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. 1.0.3 4.4 Power Failure Protection For 1:1 or 1+1 line card redundancy in T1/E1 applications, power failure could cause a line card to change the characteristics of the line impedance, causing a degradation in system performance. The XRT83SH314 XRT83SH314 was designed