XRT73L02 GR-499-CORE GR-253CORE GR-253-CORE PE-65967 T3001 PE-65966 PE-68629 - Datasheet Archive

 

XRT73L02 PRELIMINARY 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT JUNE 2001 REV. P1.1.2 GENERAL DESCRIPTION FEATURES The XRT73L02

 

áç XRT73L02 XRT73L02 PRELIMINARY 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT JUNE 2001 REV. P1.1.2 GENERAL DESCRIPTION FEATURES The XRT73L02 XRT73L02 Dual Channel E3/DS3/STS-1 Transceiver IC consists of two fully integrated transmitter and receiver line transceivers designed for E3, DS3 or SONET STS-1 applications. · Meets E3/DS3/STS-1 Jitter Tolerance Requirements Each channel can be configured to support the E3 (34.368 Mbps), DS3 (44.736 Mbps) or the SONET STS-1 (51.84 Mbps) rates. Each channel can be configured to operate in a mode/data rate that is independent of the other channel. · Transmit and Receive Power Down Modes In the transmit direction, each channel in the XRT73L02 XRT73L02 encodes input data to either B3ZS or HDB3 format and converts the data into the appropriate pulse shapes for transmission over coaxial cable via a 1:1 transformer. · Operates over -40°C to +85°C Temperature Range · Contains a 4-Wire Microprocessor Serial Interface · Full Loop-back Capability · Full Redundancy Support · Single +3.3V Power Supply · Uses Minimum External components · Available in an 80 pin TQFP package APPLICATIONS · Digital Cross Connect Systems In the receive direction, the XRT73L02 XRT73L02 can perform Equalization on incoming signals, perform Clock Recovery, decode data from either B3ZS or HDB3 format, convert the receive data into TTL/CMOS format, check for LOS or LOL conditions and detect and declare the occurrence of Line Code Violations. · CSU/DSU Equipment · Routers · Fiber Optic Terminals · Multiplexers · ATM Switches XRT73L02 XRT73L02 BLOCK DIAGRAM E3_Ch_(n) STS-1/DS3_Ch_(n) Host/HW RTIP_(n) RRing_(n) AGC/ Equalizer REQEN_(n) RLOL_(n) ExClk_(n) RxClkINV Clock Recovery Slicer Invert Data Recovery Peak Detector RxOFF_(n) LOS Detector LOSTHR_(n) RxClk_(n) HDB3/ B3ZS Decoder RPOS_(n) RNEG_(n) LCV_(n) ENDECDIS SDI SDO SClk CS RLOS_(n) Serial Processor Interface LLB_(n) Loop MUX RLB_(n) REGR TTIP_(n) Pulse Shaping TRing_(n) MTIP_(n) MRing_(n) HDB3/ B3ZS Encoder TAOS_(n) TPData_(n) Transmit Logic TNData_(n) Duty Cycle Adjust Device Monitor Tx Control DMO_(n) TxClk_(n) TxLEV_(n) TxOFF_(n) Channel 0 Channel 1 Notes: 1. (n) = 0 or 1 for the respective channel. 2. Serial Processor Interface pins are shared by both Channels in HOST Mode and are redefined in Hardware Mode. TRANSMIT INTERFACE CHARACTERISTICS Exar Corporation 48720 Kato Road, Fremont CA, 94538 · (510) 668-7000 · FAX (510) 668-7017 · www.exar.com áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 RECEIVE INTERFACE CHARACTERISTICS · Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal · Integrated Pulse Shaping Circuit · Integrated Adaptive Receive Equalization (Optional) and Timing Recovery · Built-in B3ZS/HDB3 Encoder (which can be disabled) · Declares and Clears the LOS alarm per ITU-T G.775 requirements for E3 and DS3 applications · Contains Transmit Clock Duty Cycle Correction Circuit on-chip · Meets Jitter Tolerance Requirements, as specified in ITU-T G.823_1993 for E3 Applications · Generates pulses that comply with the ITU-T G.703 pulse template (E3 applications) · Meets Jitter Tolerance Requirements, as specified in Bellcore GR-499-CORE GR-499-CORE for DS3 Applications · Generates pulses that comply with the DSX-3 pulse template, as specified in Bellcore GR-499-CORE GR-499-CORE and ANSI T1.102_1993 · Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms · Built-in B3ZS/HDB3 Decoder (which can be disabled) · Generates pulses that comply with the STSX-1 pulse template, as specified in Bellcore GR-253CORE GR-253CORE · Recovered Data can be automatically muted while the LOS Condition is declared · Transmitter can be turned off in order to support redundancy designs · Outputs either Single-Rail or Dual-Rail data to the Terminal Equipment · Receiver can be powered down in order to conserve power in redundancy designs 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 TxOFF_0 TxClk_0 TPData_0 TNData_0 MTIP_0 MRing_0 AVDD_0 TTIP_0 TRing_0 AGND_0 AGND_1 TRing_1 TTIP_1 AVDD_1 MRing_1 MTIP_1 TNData_1 TPData_1 TxClk_1 TxOFF_1 PIN OUT OF THE XRT73L02 XRT73L02 80 Lead TQFP 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 STS-1/DS3_Ch_0 ICT LOSTHR_0 LLB_0 RLB_0 AVDD_0 RRing_0 RTIP_0 AGND_0 REQEN_0 REQEN_1 AGND_1 RTIP_1 RRing_1 AVDD_1 RLB_1 LLB_1 LOSTHR_1 E3_Ch_1 SR/DR TxLEV_0 TAOS_0 DVDD_0 DMO_0 DGND_0 AGND_0 DVDD_0 Host/(HW) RxClk_0 RNEG_0 RPOS_0 DGND_0 RLOS_0 LCV_0 RLOL_0 EXClk_0 CS/(ENDECDIS) SClk/(RxOFF_1) SDI/(RxOFF_0) SDO/(E3_Ch_0) 2 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 TxLEV_1 TAOS_1 DVDD_1 DMO_1 DGND_1 AGND_1 DVDD_1 LOSMUTEN RxClk_1 RNEG_1 RPOS_1 DGND_1 RLOS_1 LCV_1 RLOL_1 EXClk_1 VDD GND REGR/(RxClkINV) STS-1/DS3_Ch_1 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 TABLE OF CONTENTS General description . 1 FEATURES . APPLICATIONS . XRT73L02 XRT73L02 BLOCK DIAGRAM . TRANSMIT INTERFACE CHARACTERISTICS . RECEIVE INTERFACE CHARACTERISTICS . PIN OUT OF THE XRT73L02 XRT73L02 . 1 1 1 1 2 2 . TABLE OF CONTENTS I Pin descriptions . 3 ELECTRICAL CHARACTERISTICS . 14 ABSOLUTE MAXIMUM RATINGS . 14 Figure 1.Transmit Pulse Amplitude Test Circuit for E3, DS3 and STS-1 Rates (typical channel shown) . Figure 2.Timing Diagram of the Transmit Terminal Input Interface . Figure 3.Timing Diagram of the Receive Terminal Output Interface . Figure 4.Microprocessor Serial Interface Data Structure . Figure 5.Timing Diagram for the Microprocessor Serial Interface . 16 16 16 20 21 SYSTEM DESCRIPTION . 22 THE TRANSMIT SECTION - CHANNELS 0 AND 1 . 22 THE RECEIVE SECTION - CHANNELS 0 AND 1 . 22 THE MICROPROCESSOR SERIAL INTERFACE . 22 Table 1:Role of Microprocessor Serial Interface pins when the XRT73L02 XRT73L02 is operating in the Hardware Mode 22 Figure 6.Functional Block Diagram of the XRT73L02 XRT73L02 . 23 1.0 SELECTING THE DATA RATE . 23 1.1 CONFIGURING CHANNEL (N) . 23 Table 2:Addresses and Bit Formats of XRT73L02 XRT73L02 Command Registers . 24 Table 3:Selecting the Data Rate for Channel (n) of the XRT73L02 XRT73L02, via the E3_Ch_(n) and STS-1/DS3_Ch_(n) input pins (Hardware Mode) . 24 COMMAND REGISTER CR4-(N) . 25 Table 4:Selecting the Data Rate for Channel (n) of the XRT73L02 XRT73L02 via the STS-1/DS3_Ch_(n) and the E3_Ch_(n) bit-fields in the Appropriate Command Register (HOST Mode) . 25 2.0 THE TRANSMIT SECTION . 25 2.1 THE TRANSMIT LOGIC BLOCK . 25 Accepting Dual-Rail Data from the Terminal Equipment . 25 Figure 7. The typical interface for Data Transmission in Dual-Rail Format from the Transmitting Terminal Equipment to the Transmit Section of a channel of the XRT73L02 XRT73L02 . 26 Figure 8.How the XRT73L02 XRT73L02 Samples the data on the TPData and TNData input pins . 26 Configure Channel (n) to accept Single-Rail Data from the Terminal Equipment . 26 COMMAND REGISTER CR1-(N) . 26 Figure 9.The Behavior of the TPData and TxClk Input Signals while the Transmit Logic Block is Accepting Single-Rail Data from the Terminal Equipment . 27 2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIRCUITRY . 27 2.3 THE HDB3/B3ZS ENCODER BLOCK . 27 B3ZS Encoding . 27 I áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 Figure 10.An Example of B3ZS Encoding . HDB3 Encoding . Figure 11.An Example of HDB3 Encoding . Disabling the HDB3/B3ZS Encoder . 28 28 28 28 COMMAND REGISTER CR2-(N) . 29 2.4 THE TRANSMIT PULSE SHAPING CIRCUITRY . Figure 12.The Bellcore GR-499-CORE GR-499-CORE Transmit Output Pulse Template for DS3 Applications . Figure 13.The Bellcore GR-253-CORE GR-253-CORE Transmit Output Pulse Template for SONET STS-1 Applications . Enabling the Transmit Line Build-Out Circuit . 29 29 30 30 COMMAND REGISTER CR1-(N) . 30 Disabling the Transmit Line Build-Out Circuit . 30 COMMAND REGISTER CR1-(N) . 31 Design Guideline for Setting the Transmit Line Build-Out Circuit . The Transmit Line Build-Out Circuit and E3 Applications . 2.5 INTERFACING THE TRANSMIT SECTIONS OF THE XRT73L02 XRT73L02 TO THE LINE . Figure 14.Recommended Schematic for Interfacing the Transmit Section of the XRT73L02 XRT73L02 to the Line . TRANSFORMER VENDOR INFORMATION . 31 31 31 31 32 3.0 THE RECEIVE SECTION . 32 3.1 INTERFACING THE RECEIVE SECTIONS OF THE XRT73L02 XRT73L02 TO THE LINE . 32 Figure 15.Recommended Schematic for Transformer-Coupling the Receive Section of the XRT73L02 XRT73L02 to the Line . 33 Figure 16.Recommended Schematic for Capacitive-Coupling the Receive Section of the XRT73L02 XRT73L02 to the Line 33 3.2 THE RECEIVE EQUALIZER BLOCK . 34 Figure 17.The Typical Application for the System Installer . 34 COMMAND REGISTER CR2_(N) . 35 3.3 PEAK DETECTOR AND SLICER . 3.4 CLOCK RECOVERY PLL . The Training Mode . The Data/Clock Recovery Mode . 3.5 THE HDB3/B3ZS DECODER . B3ZS Decoding DS3/STS-1 Applications . Figure 18.An Example of B3ZS Decoding . HDB3 Decoding E3 Applications . Figure 19.An Example of HDB3 Decoding . Configuring the HDB3/B3ZS Decoder . 35 35 35 35 35 35 36 36 36 36 COMMAND REGISTER CR2-(N) . 37 3.6 LOS DECLARATION/CLEARANCE . 37 The LOS Declaration/Clearance Criteria for E3 Applications . 37 Figure 20.The Signal Levels at which the XRT73L02 XRT73L02 declares and clears LOS . 38 Figure 21.The Behavior the LOS Output Indicator in response to the Loss of Signal and the Restoration of Signal 38 The LOS Declaration/Clearance Criteria for DS3 and STS-1 Applications . 39 Table 5:The ALOS (Analog LOS) Declaration and Clearance Thresholds for a given setting of LOSTHR and REQEN for DS3 and STS-1 Applications . 39 II áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 COMMAND REGISTER CR0-(N) . 39 COMMAND REGISTER CR2-(N) . 40 COMMAND REGISTER CR0-(N) . 40 COMMAND REGISTER CR2-(N) . 40 Muting the Recovered Data while the LOS is being Declared . 40 COMMAND REGISTER CR3-(N) . 41 3.7 ROUTING THE RECOVERED TIMING AND DATA INFORMATION TO THE RECEIVING TERMINAL EQUIPMENT . 41 Routing Dual-Rail Format Data to the Receiving Terminal Equipment . 41 Figure 22.The typical interface for the Transmission of Data in a Dual-Rail Format from the Receive Section of the XRT73L02 XRT73L02 to the Receiving Terminal Equipment . 41 Figure 23.How the XRT73L02 XRT73L02 outputs data on the RPOS and RNEG output pins . 42 Figure 24.The Behavior of the RPOS, RNEG and RxClk signals when RxClk is inverted . 42 COMMAND REGISTER CR3-(N) . 43 Routing Single-Rail Format (Binary Data Stream) data to the Receive Terminal Equipment . 43 COMMAND REGISTER CR3-(N) . 43 Figure 25.The typical interface for Data Transmission in a Single-Rail Format from the Receive Section of the XRT73L02 XRT73L02 to the Receiving Terminal Equipment . 43 Figure 26.The behavior of the RPOS and RxClk output signals while the XRT73L02 XRT73L02 is transmitting Single-Rail data to the Receiving Terminal Equipment . 44 3.8 SHUTTING OFF THE RECEIVE SECTION . 44 COMMAND REGISTER CR3-(N) . 44 4.0 DIAGNOSTIC FEATURES OF THE XRT73L02 XRT73L02 . 45 4.1 THE ANALOG LOCAL LOOP-BACK MODE . 45 Figure 27. A channel in the XRT73L02 XRT73L02 operating in the Analog Local Loop-Back Mode . 45 COMMAND REGISTER CR4-(N) . 45 4.2 THE DIGITAL LOCAL LOOP-BACK MODE. . 46 Figure 28.The Digital Local Loop-Back path in a given channel of the XRT73L02 XRT73L02 . 46 COMMAND REGISTER CR4-(N) . 46 4.3 THE REMOTE LOOP-BACK MODE . 47 Figure 29.The Remote Loop-Back path in a given XRT73L02 XRT73L02 Channel . 47 COMMAND REGISTER CR4-(n) . 47 4.4 TXOFF FEATURES . 47 COMMAND REGISTER CR1-(N) . 48 Table 6:The Relationship Between the TxOFF Input Pin, the TxOFF Bit Field and the State of the Transmitter 48 4.5 THE TRANSMIT DRIVE MONITOR FEATURES . 48 Figure 30.The XRT73L02 XRT73L02 employing the Transmit Drive Monitor Features . 48 4.6 THE TAOS (TRANSMIT ALL ONES) FEATURE . 49 5.0 THE MICROPROCESSOR SERIAL INTERFACE . 49 5.1 DESCRIPTION OF THE COMMAND REGISTERS . 49 COMMAND REGISTER CR1-(N) . 49 Table 7:Addresses and Bit Formats of XRT73L02 XRT73L02 Command Registers . 50 5.2 DESCRIPTION OF BIT-FIELDS FOR EACH COMMAND REGISTER . 50 III áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 Command Register - CR0-(n) . 50 COMMAND REGISTER CR0-(N) . 50 COMMAND REGISTER CR1-(N) . 51 Command Register CR2-(n) . 52 COMMAND REGISTER CR2-(N) . 52 COMMAND REGISTER CR3-(N) . 52 COMMAND REGISTER CR4-(N) . 53 Table 8:Contents of LLB_(n) and RLB_(n) and the Corresponding Loop-Back Mode for Channel (n) . 5.3 OPERATING THE MICROPROCESSOR SERIAL INTERFACE. . Figure 31.Microprocessor Serial Interface Data Structure . Figure 32.Timing Diagram for the Microprocessor Serial Interface . 54 54 55 56 Ordering information . 57 Package dimensions . 57 REVISION HISTORY . 58 IV áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 PIN DESCRIPTIONS PIN DESCRIPTION PIN # SIGNAL NAME TYPE 1 TxLEV_0 I DESCRIPTION Transmit Line Build-Out Enable/Disable Select - Channel 0: This input pin is used to enable or disable the Transmit Line Build-Out circuit of Channel 0. Setting this pin to "High" disables the Line Build-Out circuit of Channel 0. In this mode, Channel 0 outputs partially-shaped pulses onto the line via the TTIP_0 and TRing_0 output pins. Setting this pin to "Low" enables the Line Build-Out circuit of Channel 0. In this mode, Channel 0 outputs shaped pulses onto the line via the TTIP_0 and TRing_0 output pins. To comply with the Isolated DSX-3/STSX-1 Pulse Template Requirements per Bellcore GR-499-CORE GR-499-CORE or Bellcore GR-253-CORE GR-253-CORE: 1. Set this input pin to "1" if the cable length between the Cross-Connect and the transmit output of Channel 0 is greater than 225 feet. 2. Set this input pin to "0" if the cable length between the Cross-Connect and the transmit output of Channel 0 is less than 225 feet. This pin is active only if the following two conditions are true: a. The XRT73L02 XRT73L02 is configured to operate in either the DS3 or SONET STS-1 Modes. b. The XRT73L02 XRT73L02 is configured to operate in the Hardware Mode. NOTE: If the XRT73L02 XRT73L02 is going to be operating in the HOST Mode, this pin should be tied to GND. 2 TAOS_0 I Transmit All Ones Select - Channel 0: A "High" on this pin causes the Transmit Section of Channel 0 to generate and transmit a continuous AMI all "1's" pattern onto the line. The frequency of this "1's" pattern is determined by TxClk_0. NOTES: 1. This input pin is ignored if the XRT73L02 XRT73L02 is operating in the HOST Mode. 2. If the XRT73L02 XRT73L02 is going to be operating in the HOST Mode, this pin should tie tied to GND. 3 DVDD_0 * 4 DMO_0 O Transmit Digital VDD (for Transmitter 0) Drive Monitor Output - Channel 0: If no transmitted AMI signal is present on MTIP_0 and MRing_0 input pins for 128±32 TxClk periods, then DMO_0 toggles and remains "High" until the next AMI signal is detected. 5 DGND_0 6 AGND_0 7 DVDD_0 * Transmit Digital GND (for Transmitter 0) Analog GND (Substrate Connection) - Channel 0 * Receive Digital VDD (for Receiver 0) 3 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 PIN DESCRIPTION PIN # SIGNAL NAME TYPE 8 Host/(HW) I DESCRIPTION HOST/Hardware Mode Select: This input pin is used to enable or disable the Microprocessor Serial Interface (e.g., consisting of the SDI, SDO, SClk, and CS pins). Setting this input pin "High" enables the Microprocessor Serial Interface (e.g. configures the XRT73L02 XRT73L02 to operate in the HOST Mode). In this mode, configure the XRT73L02 XRT73L02 via the Microprocessor Serial Interface. When the XRT73L02 XRT73L02 is operating in the HOST Mode, then it ignores the states of many of the discrete input pins. Setting this input pin "Low" disables the Microprocessor Serial Interface (e.g., configures the XRT73L02 XRT73L02 to operate in the Hardware Mode). In this mode, many of the external input control pins are functional. 9 RxClk_0 O Receive Clock Output pin - Channel 0: This output pin is the Recovered Clock signal from the incoming line signal for Channel 0. The receive section of Channel 0 outputs data via the RPOS_0 and RNEG_0 output pins on the rising edge of this clock signal. NOTE: The Receive Section of Channel 0 is configured to update the data on the RPOS_0 and RNEG_0 output pins on the falling edge of RxClk_0 by doing one of the following: a. Operating in the Hardware Mode Pull the RClkINV pin to "High". b. Operating in the HOST Mode Write a "1" into the RClkINV bit-field within the Command Register. 10 RNEG_0 O Receive Negative Data Output - Channel 0: This output pin pulses "High" whenever Channel 0 of the XRT73L02 XRT73L02 has received a Negative Polarity pulse in the incoming line signal at the RTIP_0/ RRing_0 inputs. NOTE: If the Channel 0 B3ZS/HDB3 Decoder is enabled, then the zero suppression patterns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V") is not reflected at this output. 11 RPOS_0 O Receive Positive Pulse Output - Channel 0: This output pin pulses "High" whenever Channel 0 of the XRT73L02 XRT73L02 has received a Positive Polarity pulse in the incoming line signal at the RTIP_0/ RRing_0 inputs. NOTE: If the Channel 0 B3ZS/HDB3 Decoder is enabled, then the zero suppression patterns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V") is not reflected at this output. 12 DGND_0 * 13 RLOS_0 O Receive Digital GND - Channel 0 Receive Loss of Signal Output Indicator - Channel 0: This output pin toggles "High" if Channel 0 in the XRT73L02 XRT73L02 has detected a Loss of Signal Condition in the incoming line signal. The criteria the XRT73L02 XRT73L02 uses to declare an LOS Condition depends upon whether it is operating in the E3 or STS-1/DS3 Mode. 4 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 PIN DESCRIPTION PIN # SIGNAL NAME TYPE DESCRIPTION 14 LCV_0 O Line Code Violation Indicator - Channel 0: Whenever the Receive Section of Channel 0 detects a Line Code Violation, it pulses this output pin "High". This output pin remains "Low" at all other times. NOTE: The XRT73L02 XRT73L02 outputs an NRZ pulse via this output pin. It is advisable to sample this output pin via the RxClk_0 clock output signal. 15 RLOL_0 O Receive Loss of Lock Output Indicator - Channel 0: This output pin toggles "High" if Channel 0 of the XRT73L02 XRT73L02 has detected a Loss of Lock Condition. Channel 0 declares an LOL (Loss of Lock) Condition if the recovered clock frequency deviates from the Reference Clock frequency (available at the EXClk_(n) input pin) by more than 0.5%. 16 EXClk_0 I External Reference Clock Input - Channel 0: Apply a 34.368 MHz clock signal for E3 applications, a 44.736 MHz clock signal for DS3 applications or a 51.84 MHz clock signal for SONET STS-1 applications. NOTES: 1. It is permissible to use the same clock which is also driving the TxClk input pin. 2. It is permissible to operate the two Channels at different data rates. 17 CS/(ENDECDIS) I Microprocessor Serial Interface - Chip Select Input/Encoder-Decoder Disable Input: This pin's functionality depends on whether the XRT73L02 XRT73L02 is operating in the HOST or Hardware Mode. HOST Mode - Chip Select Input The Local Microprocessor must assert this pin (set it to "0") in order to enable communication with the XRT73L02 XRT73L02 via the Microprocessor Serial Interface. NOTE: This pin is internally pulled "High". Hardware Mode - Encoder/Decoder Disable Input Setting this input pin "High" disables the B3ZS/HDB3 Encoder & Decoder blocks in the XRT73L02 XRT73L02 and configures it to transmit and receive the line signal in an AMI format. Setting this input pin "Low" enables the B3ZS/HDB3 Encoder & Decoder blocks and configures it to transmit and receive the line signal in the B3ZS format for STS-1/DS3 operation or in the HDB3 format for E3 operation. NOTE: If the XRT73L02 XRT73L02 is operating in the Hardware Mode, this pin setting configures the B3ZS/HDB3 Encoder and Decoder Blocks for both Channels. 18 SClk/(RxOFF_1) I Microprocessor Serial Interface Clock Signal/Channel 1 Receiver Shut OFF Input: The function of this pin depends on whether the XRT73L02 XRT73L02 is operating in the HOST Mode or in the Hardware Mode. HOST Mode - Microprocessor Serial Interface Clock Signal: This signal is used to sample the data on the SDI pin on the rising edge of this signal. Additionally, during Read operations the Microprocessor Serial Interface updates the SDO output on the falling edge of this signal. Hardware Mode - Channel 1 Receiver Shut OFF input pin: Setting this input pin "High" shuts off the Channel 1 receiver. Setting this input pin "Low" enables the Receive Section for full operation. 5 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 PIN DESCRIPTION PIN # SIGNAL NAME TYPE 19 SDI/(RxOFF_0) I DESCRIPTION Serial Data Input for the Microprocessor Serial Interface/Channel 0 Receiver Shut OFF Input pin: The function of this input pin depends on whether the XRT73L02 XRT73L02 is operating in the HOST Mode or in the Hardware Mode. HOST Mode - Serial Data Input for the Microprocessor Serial Interface: To read or write data into the Command Registers over the Microprocessor Serial Interface, apply the Read/Write bit, the Address Values of the Command Registers and Data Value to be written during Write Operations to this pin. This input is sampled on the rising edge of the SClk pin. Hardware Mode - Channel 0 Receiver Shut OFF Input pin: Setting this input pin "High" shuts off the Channel 0 receiver. Setting this input pin "Low" enables the Receive Section for full operation. 20 SDO/(E3_Ch_0) I/O Serial Data Output from the Microprocessor Serial Interface/E3_Mode Select - Channel 0: The function of this pin depends on whether the XRT73L02 XRT73L02 is operating in the HOST Mode or in the Hardware Mode. HOST Mode Operation - Serial Data Output for the Microprocessor Serial Interface: This pin serially outputs the contents of the specified Command Register during Read Operations. The data is updated on the falling edge of the SClk input signal and tri-stated upon completion of data transfer. Hardware Mode Operation - E3 Mode Select - Channel 0: This input pin is used to configure Channel 0 in the XRT73L02 XRT73L02 to operate in the E3 or STS/DS3 Modes. Setting this input pin to "High" configures Channel 0 to operate in the E3 Mode. Setting this input pin to "Low" configures Channel 0 to operate in either the DS3 or STS-1 Modes, depending upon the state of the STS-1/DS3_Ch_0 input pin. 21 STS-1/DS3_Ch_0 I STS-1/DS3 Select Input - Channel 0: Set this input pint to "High" for STS-1 and "Low" for DS3 Operation. The XRT73L02 XRT73L02 ignores this pin if the E3_Ch_0 pin is set to "1". This input pin is ignored if the XRT73L02 XRT73L02 is operating in the HOST Mode. If the XRT73L02 XRT73L02 is operating in the HOST Mode, the pin should be tied to GND. 22 ICT I In-Circuit Test Input: Setting this pin "Low" causes all digital and analog outputs to go into a highimpedance state to allow for in-circuit testing. For normal operation, set this pin "High". NOTE: This pin is internally pulled "High". 23 LOSTHR_0 I Loss of Signal Threshold Control - Channel 0: The voltage forced on this pin controls the input loss of signal threshold for Channel 0. Forcing the LOSTHR_0 pin to GND or VDD provides two settings. This pin must be set to the desired level upon power up and should not be changed during operation. NOTE: This pin is only applicable during DS3 or STS-1 operations. 6 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 PIN DESCRIPTION PIN # SIGNAL NAME TYPE 24 LLB_0 I DESCRIPTION Local Loop-back - Channel 0: This input pin along with RLB_0 dictates the Loop-Back mode in which Channel 0 in the XRT73L02 XRT73L02 is operating. A "High" on this pin with RLB_0 set to "Low" configures Channel 0 of the XRT73L02 XRT73L02 to operate in the Analog Local Loop-back Mode. A "High" on this pin with RLB_0 set to "High" configures Channel 0 of the XRT73L02 XRT73L02 to operate in the Digital Local Loop-back Mode. NOTE: This input pin is ignored and should be connected to GND if the XRT73L02 XRT73L02 is operating in the HOST Mode. 25 RLB_0 I Remote Loop-back - Channel 0: This input pin along with LLB_0 dictates the Loop-Back mode in which Channel 0 in the XRT73L02 XRT73L02 is operating. A "High" on this pin with LLB_0 being set to "Low" configures Channel 0 of the XRT73L02 XRT73L02 to operate in the Remote Loop-back Mode. A "High" on this pin with LLB_0 also being set to "High" configures Channel 0 of the XRT73L02 XRT73L02 to operate in the Digital Local Loop-back Mode. NOTE: This input pin is ignored and should be connected to GND if the XRT73L02 XRT73L02 is operating in the HOST Mode. 26 AVDD_0 * 27 RRing_0 I Receive Analog VDD - Channel 0: Receive Ring Input - Channel 0: This input pin along with RTIP_0 is used to receive the bipolar line signal from the Remote DS3/E3 Terminal. 28 RTIP_0 I Receive TIP Input - Channel 0: This input pin along with RRing_0 is used to receive the bipolar line signal from the Remote DS3/E3/STS-1 Terminal. 29 AGND_0 * 30 REQEN_0 I Receive Analog GND - Channel 0 Receive Equalization Enable Input - Channel 0: Setting this input pin "High" enables the Internal Receive Equalizer of Channel 0. Setting this pin "Low" disables the Internal Receive Equalizer. The guidelines for enabling and disabling the Receive Equalizer are described in Section 3.2. NOTE: This input pin is ignored and should be connected to GND if the XRT73L02 XRT73L02 is operating in the HOST Mode. 31 REQEN_1 I Receive Equalization Enable Input - Channel 1: Setting this input pin "High" enables the Internal Receive Equalizer of Channel 1. Setting this pin "Low" disables the Internal Receive Equalizer. The guidelines for enabling and disabling the Receive Equalizer are described in Section 3.2. NOTE: This input pin is ignored and should be connected to GND if the XRT73L02 XRT73L02 is operating in the HOST Mode. 32 AGND_1 * 33 RTIP_1 I Receive Analog GND - Channel 1 Receive TIP Input - Channel 1: This input pin along with RRing_1 is used to receive the bipolar line signal from the Remote DS3/E3/STS-1 Terminal. 7 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 PIN DESCRIPTION PIN # SIGNAL NAME TYPE 34 RRing_1 I DESCRIPTION Receive Ring Input - Channel 1: This input pin along with RTIP_1 is used to receive the bipolar line signal from the Remote DS3/E3 Terminal. 35 AVDD_1 * 36 RLB_1 I Receive Analog VDD - Channel 1 Remote Loop-back - Channel 1: This input pin along with LLB_1 dictates the Loop-Back mode in which Channel 1 in the XRT73L02 XRT73L02 is operating. A "High" on this pin with LLB_1 being set to "Low" configures Channel 1 of the XRT73L02 XRT73L02 to operate in the Remote Loop-back Mode. A "High" on this pin with LLB_1 also being set to "High" configures Channel 1 of the XRT73L02 XRT73L02 to operate in the Digital Local Loop-back Mode. NOTE: This input pin is ignored and should be connected to GND if the XRT73L02 XRT73L02 is operating in the HOST Mode. 37 LLB_1 I Local Loop-back - Channel 1: This input pin along with RLB_1 dictates the Loop-Back mode in which Channel 1 in the XRT73L02 XRT73L02 is operating. A "High" on this pin with RLB_1 set to "Low" configures Channel 1 of the XRT73L02 XRT73L02 to operate in the Analog Local Loop-back Mode. A "High" on this pin with RLB_1 set to "High" configures Channel 1 of the XRT73L02 XRT73L02 to operate in the Digital Local Loop-back Mode. NOTE: This input pin is ignored and should be connected to GND if the XRT73L02 XRT73L02 is operating in the HOST Mode. 38 LOSTHR_1 I Loss of Signal Threshold Control - Channel 1: The voltage forced on this pin controls the input loss of signal threshold for Channel 1. Forcing the LOSTHR_1 pin to GND or VDD provides two settings. This pin must be set to the desired level upon power up and should not be changed during operation. NOTE: This pin is only applicable during DS3 or STS-1 operations. 39 E3_Ch_1 I E3 Select Input - Channel 1: A "High" on this pin configures Channel 1 of the XRT73L02 XRT73L02 to operate in the E3 Mode. A "Low" on this pin configures Channel 1 of the XRT73L02 XRT73L02 to check the state of the STS-1/DS3_Ch_1 input pin NOTE: This input pin is ignored and should be connected to GND if the XRT73L02 XRT73L02 is operating in the HOST Mode. 40 SR/DR I Receive Output Single-Rail/Dual-Rail Select: Setting this pin "High" configures the Receive Sections of all Channels to output data in a Single-Rail Mode to the Terminal Equipment. Setting this pin "Low" configures the Receive Section of all Channels to output data in a Dual-Rail Mode to the Terminal Equipment. 41 STS-1/DS3_Ch_1 I STS-1/DS3 Select Input - Channel 1: Set this pin to "High" for STS-1 and "Low" for DS3 Operation. The XRT73L02 XRT73L02 ignores this pin if the E3_Ch_1 pin is set to "1". This input pin is ignored if the XRT73L02 XRT73L02 is operating in the HOST Mode. If the XRT73L02 XRT73L02 is operating in the HOST Mode, the pin should be tied to GND. 8 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 PIN DESCRIPTION PIN # SIGNAL NAME TYPE 42 REGR/ (RxClkNV) I DESCRIPTION Register Reset Input pin (Invert RxClk_(n) Output - Select): The function of this pin depends upon whether the XRT73L02 XRT73L02 is operating in the HOST Mode or in the Hardware Mode. NOTE: This pin is internally pulled "High". In the HOST-Mode - Register Reset Input pin: Setting this input pin "Low" causes the XRT73L02 XRT73L02 to reset the contents of the Command Registers to their default settings and default operating configuration. In the Hardware Mode - Invert RxClk Output Select: Setting this input pin "High" configures the Receive Section of all Channels in the XRT73L02 XRT73L02 to invert their RxClk_(n) clock output signals and configures Channel (n) to output the recovered data via the RPOS_(n) and RNEG_(n) output pins on the falling edge of RxClk_(n). Setting this pin "Low" configures Channel (n) to output the recovered data via the RPOS_(n) and RNEG_(n) output pins on the rising edge of RxClk_(n). 43 GND * ExClk Reference GND 44 VDD * ExClk Reference VDD 45 EXClk_1 I External Reference Clock Input - Channel 1: Apply a 34.368 MHz clock signal for E3 applications, a 44.736 MHz clock signal for DS3 applications or a 51.84 MHz clock signal for SONET STS-1 applications. The Clock Recovery PLL in Channel 1 uses this signal as a Reference Signal for Declaring and Clearing the Receive Loss of Lock Alarm. NOTES: 1. It is permissible to use the same clock which is also driving the TxClk input pin. 2. It is permissible to operate the two Channels at different data rates 46 RLOL_1 O Receive Loss of Lock Output Indicator - Channel 1: This output pin toggles "High" if Channel 1 of the XRT73L02 XRT73L02 has detected a Loss of Lock Condition. Channel 1 declares an LOL (Loss of Lock) Condition if the recovered clock frequency deviates from the Reference Clock frequency (available at the EXClk_(n) input pin) by more than 0.5%. 47 LCV_1 O Line Code Violation Indicator - Channel 1: Whenever the Receive Section of Channel 1 detects a Line Code Violation, it pulses this output pin "High". This output pin remains "Low" at all other times. NOTE: The XRT73L02 XRT73L02 outputs an NRZ pulse via this output pin. It is advisable to sample this output pin via the RxClk_1 clock output signal. 48 RLOS_1 O Receive Loss of Signal Output Indicator - Channel 1: This output pin toggles "High" if Channel 1 in the XRT73L02 XRT73L02 has detected a Loss of Signal Condition in the incoming line signal. The criteria the XRT73L02 XRT73L02 uses to declare an LOS Condition depends upon whether it is operating in the E3 or STS-1/DS3 Mode. 49 DGND_1 * Receive Digital Ground - Channel 1 9 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 PIN DESCRIPTION PIN # SIGNAL NAME TYPE 50 RPOS_1 O DESCRIPTION Receive Positive Data Output - Channel 1: This output pin pulses "High" whenever Channel 1 of the XRT73L02 XRT73L02 has received a Positive Polarity pulse in the incoming line signal at the RTIP_1/ RRing_1 inputs. NOTE: If the Channel 1 B3ZS/HDB3 Decoder is enabled, then the zero suppression patterns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V") is not reflected at this output. 51 RNEG_1 O Receive Negative Data Output - Channel 1: This output pin pulses "High" whenever Channel 1 of the XRT73L02 XRT73L02 has received a Negative Polarity pulse in the incoming line signal at the RTIP_1/ RRing_1 inputs. NOTE: If the Channel 1 B3ZS/HDB3 Decoder is enabled, then the zero suppression patterns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V") is not reflected at this output. 52 RxClk_1 O Receive Clock Output pin - Channel 1: This output pin is the Recovered Clock signal from the incoming line signal for Channel 1. The receive section of Channel 1 outputs data via the RPOS_1 and RNEG_1 output pins on the rising edge of this clock signal. NOTE: The Receive Section of Channel 1 is configured to update the data on the RPOS_1 and RNEG_1 output pins on the falling edge of RxClk_1 by doing one of the following: a. Operating in the Hardware Mode Pull the RxClkINV pin to "High". b. Operating in the HOST Mode Write a "1" into the RxClkINV bit-field of the Command Register. 53 LOSMUTEN I MUTE-upon-LOS Enable Input (Hardware Mode): This input pin is used to configure the XRT73L02 XRT73L02 while it is operating in the Hardware Mode to MUTE the recovered data via the RPOS_(n), RNEG_(n) output pins whenever one of the Channels declares an LOS condition. Setting this input pin "High" configures all Channels to automatically pull the RPOS_(n) and RNEG_(n) output pins to GND whenever it is declaring an LOS condition, MUTing the data being output to the Terminal Equipment. Setting this input pin "Low" configures all Channels to NOT automatically MUTE the recovered data whenever an LOS condition is declared. NOTES: 1. This input pin is ignored and should be connected to GND if the XRT73L02 XRT73L02 is operating in the HOST Mode. 2. This pin is internally pulled "High". 54 DVDD_1 * Receive Digital VDD - Channel 1 55 AGND_1 * Analog Ground (Substrate Connection) - Channel 1 56 DGND_1 * Transmit Digital GND - Channel 1 57 DMO_1 O Drive Monitor Output - Channel 1: If no transmitted AMI signal is present on MTIP_1 and MRing_1 input pins for 128±32 TxClk periods, then DMO_1 toggles and remains "High" until the next AMI signal is detected. 10 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 PIN DESCRIPTION PIN # SIGNAL NAME TYPE DESCRIPTION 58 DVDD_1 * Transmit Digital VDD - Channel 1 59 TAOS_1 I Transmit All Ones Select - Channel 1: A "High" on this pin causes the Transmit Section of Channel 1 to generate and transmit a continuous AMI all "1's" pattern onto the line. The frequency of this "1's" pattern is determined by TxClk_1. NOTES: 1. This input pin is ignored if the XRT73L02 XRT73L02 is operating in the HOST Mode. 2. If the XRT73L02 XRT73L02 is going to be operating in the HOST Mode, this pin should be tied to GND. 60 TxLEV_1 I Transmit Line Build-Out Enable/Disable Select - Channel 1: This input pin is used to enable or disable the Transmit Line Build-Out circuit of Channel 1. Setting this pin to "High" disables the Line Build-Out circuit of Channel 1. In this mode, Channel 1 outputs partially-shaped pulses onto the line via the TTIP_1 and TRing_1 output pins. Setting this pin to "Low" enables the Line Build-Out circuit of Channel 1. In this mode, Channel 1 outputs shaped pulses onto the line via the TTIP_1 and TRing_1 output pins. To comply with the Isolated DSX-3/STSX-1 Pulse Template Requirements per Bellcore GR-499-CORE GR-499-CORE or Bellcore GR-253-CORE GR-253-CORE: 1. Set this input pin to "1" if the cable length between the Cross-Connect and the transmit output of Channel 1 is greater than 225 feet. 2. Set this input pin to "0" if the cable length between the Cross-Connect and the transmit output of Channel 1 is less than 225 feet. This pin is active only if the following two conditions are true: a. The XRT73L02 XRT73L02 is configured to operate in either the DS3 or SONET STS-1 Modes. b. The XRT73L02 XRT73L02 is configured to operate in the Hardware Mode. NOTE: If the XRT73L02 XRT73L02 is going to be operating in the HOST Mode, this pin should be tied to GND. 61 TxOFF_1 I Transmitter OFF Input - Channel 1: Setting this input pin "High" configures the XRT73L02 XRT73L02 to turn off the Transmit Section of Channel 1. In this mode, the TTIP_1 and TRing_1 outputs is tristated. NOTES: 1. This input pin controls the TTIP_1 and TRing_1 outputs even when the XRT73L02 XRT73L02 is operating in the HOST Mode. 2. For HOST Mode Operation, tie this pin to GND if the Transmitter is intended to be turned off via the Microprocessor Serial Interface. 11 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 PIN DESCRIPTION PIN # SIGNAL NAME TYPE 62 TxClk_1 I DESCRIPTION Transmit Clock Input for TPData and TNData - Channel 1: This input pin must be driven at 34.368 MHz for E3 applications, 44.736 MHz for DS3 applications or 51.84 MHz for SONET STS-1 applications. The XRT73L02 XRT73L02 uses this signal to sample the TPData_1 and TNData_1 input pins. By default, the XRT73L02 XRT73L02 is configured to sample these two pins on the falling edge of this signal. If operating in the HOST Mode, the XRT73L02 XRT73L02 can be configured to sample the TPData_1 and TNData_1 input pins on either the rising or falling edge of TxClk_1. 63 TPData_1 I Transmit Positive Data Input - Channel 1: The XRT73L02 XRT73L02 samples this pin on the falling edge of TxClk_1. If it samples a "1", then it generates and transmits a positive polarity pulse to the line. NOTES: 1. The data should be applied to this input pin if the Transmit Section is configured to accept Single-Rail data from the Terminal Equipment. 2. If operating in the HOST Mode, the XRT73L02 XRT73L02 can be configured to sample the TPData_1 pin on either the rising or falling edge of TxClk_1. 64 TNData_1 I Transmit Negative Data Input - Channel 1: The XRT73L02 XRT73L02 samples this pin on the falling edge of TxClk_1. If it samples a "1", then it generates and transmits a negative polarity pulse to the line. NOTES: 1. This input pin is ignored and tied to GND if the Transmit Section is configured to accept Single-Rail data from the Terminal Equipment. 2. If operating in the HOST Mode, the XRT73L02 XRT73L02 can be configured to sample the TNData_1 pin on either the rising or falling edge of TxClk_1. 65 MTIP_1 I Monitor Tip Input - Channel 1: The bipolar line output signal from TTIP_1 is connected to this pin via a 270ohm resistor to check for line driver failure. This pin is internally pulled "High". 66 MRing_1 I Monitor Ring Input - Channel 1: The bipolar line output signal from TRing_1 is connected to this pin via a 270ohm resistor to check for line driver failure. This pin is internally pulled "High". 67 AVDD_1 * 68 TTIP_1 O Transmit Analog VDD - Channel 1: Transmit TTIP Output - Channel 1: The XRT73L02 XRT73L02 uses this pin with TRing_1 to transmit a bipolar line signal via a 1:1 transformer. 69 TRing_1 O Transmit Ring Output - Channel 1: The XRT73L02 XRT73L02 uses this pin with TTIP_1 to transmit a bipolar line signal via a 1:1 transformer. 70 AGND_1 * Transmit Analog GND - Channel 1 71 AGND_0 * Transmit Analog GND - Channel 0 72 TRing_0 O Transmit Ring Output - Channel 0: The XRT73L02 XRT73L02 uses this pin with TTIP_0 to transmit a bipolar line signal via a 1:1 transformer. 12 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 PIN DESCRIPTION PIN # SIGNAL NAME TYPE 73 TTIP_0 O DESCRIPTION Transmit TTIP Output - Channel 0: The XRT73L02 XRT73L02 uses this pin with TRing_0 to transmit a bipolar line signal via a 1:1 transformer. 74 AVDD_0 * 75 MRing_0 I Transmit Analog VDD - Channel 0 Monitor Ring Input - Channel 0: The bipolar line output signal from TRing_0 is connected to this pin via a 270ohm resistor to check for line driver failure. This pin is internally pulled "High". 76 MTIP_0 I Monitor Tip Input - Channel 0: The bipolar line output signal from TTIP_0 is connected to this pin via a 270ohm resistor to check for line driver failure. This pin is internally pulled "High". 77 TNData_0 I Transmit Negative Data Input - Channel 0: The XRT73L02 XRT73L02 samples this pin on the falling edge of TxClk_0. If it samples a "1", then it generates and transmits a negative polarity pulse to the line. NOTES: 1. This input pin is ignored and tied to GND if the Transmit Section is configured to accept Single-Rail data from the Terminal Equipment. 2. If operating in the HOST Mode, it can be configured to sample the TNData_0 pin on either the rising or falling edge of TxClk_0. 78 TPData_0 I Transmit Positive Data Input - Channel 0: The XRT73L02 XRT73L02 samples this pin on the falling edge of TxClk_0. If it samples a "1", then it generates and transmits a positive polarity pulse to the line. NOTES: 1. The data should be applied to this input pin if the Transmit Section is configured to accept Single-Rail data from the Terminal Equipment. 2. If the XRT73L02 XRT73L02 is operating in the HOST Mode it can be configured to sample the TPData_0 pin on either the rising or falling edge of TxClk_0. 79 TxClk_0 I Transmit Clock Input for TPData and TNData - Channel 0: This input pin must be driven at 34.368 MHz for E3 applications, 44.736 MHz for DS3 applications or 51.84 MHz for SONET STS-1 applications. The XRT73L02 XRT73L02 uses this signal to sample the TPData_0 and TNData_0 input pins. By default, the XRT73L02 XRT73L02 is configured to sample these two pins on the falling edge of this signal. If operating in the HOST Mode, the XRT73L02 XRT73L02 can be configured to sample the TPData_0 and TNData_0 input pins on either the rising or falling edge of TxClk_0. 80 TxOFF_0 I Transmitter OFF Input - Channel 0: Setting this input pin "High" configures the XRT73L02 XRT73L02 to turn off the Transmit Section of Channel 0. In this mode, the TTIP_0 and TRing_0 outputs is tristated. NOTES: 1. This input pin controls the TTIP_0 and TRing_0 outputs even when the XRT73L02 XRT73L02 is operating in the HOST Mode. 2. For HOST Mode Operation, tie this pin to GND if the Transmitter is intended to be turned off via the Microprocessor Serial Interface. 13 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Storage Temperature - 65°C to + 150°C Operating Temperature - 40°C to + 85°C Supply Voltage Range -0.5V to +6.0V Theta-JA 23° C/W Theta-JC 5.32° C/W ELECTRICAL CHARACTERISTICS (TA = 25°C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED) SYMBOL PARAMETER MIN. TYP. MAX. UNITS DC Electrical Characteristics VDDD DC Supply Voltage (Digital) 3.135 3.3 3.465 V VDDA DC Supply Voltage (Analog) 3.135 3.3 3.465 V TBD TBD mA mA 0.8 V 2.0 5.0 V 0.4 V ICC Supply Current (Measured while Transmitting and Receiving all "1's" ) DS3 Mode STS-1 Mode VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage, IOUT = -4.0mA 0 VOH Output High Voltage, IOUT = 4.0mA 2.8 IL Input Leakage Current* V ±10 NOTE: * Not applicable to pins with pull-down resistors. 14 µA áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 ELECTRICAL CHARACTERISTICS (CONTINUED) (TA = 25°C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED) AC ELECTRICAL CHARACTERISTICS (SEE IGURE 1) TERMINAL SIDE TIMING PARAMETERS (SEE IGURE 2 AND IGURE 3) SYMBOL PARAMETER MIN. TYP. MAX. UNITS TxClk_(n) Clock Duty Cycle (DS3/STS-1) 30 50 70 % TxClk_(n) Clock Duty Cycle (E3) 30 50 70 % TxClk_(n) Frequency (SONET STS-1) 51.84 MHz TxClk_(n) Frequency (DS3) 44.736 MHz TxClk_(n) Frequency (E3) 34.368 MHz tRTX TxClk_(n) Clock Rise Time (10% to 90%) 3.0 5.0 ns tFTX TxClk_(n) Clock Fall Time (90% to 10%) 3.0 5.0 ns tTSU TPData/TNData to TxClk_(n) Falling Set up time 3.0 1.5 ns tTHO TPData/TNData to TxClk_(n) Falling Hold time 3.0 1.5 ns tLCVO RxClk_(n) to rising edge of LCV_(n) output delay 2.5 ns tTDY TTIP_(n)/TRing_(n) to TxClk_(n) Rising Propagation Delay time 8.0 ns RxClk_(n), RxClk_(n)Clock Duty Cycle 50 % RxClk_(n), RxClk_(n) Frequency (SONET STS-1) 51.84 MHz RxClk_(n), RxClk_(n) Frequency (DS3) 44.736 MHz RxClk_(n), RxClk_(n) Frequency (E3) 34.368 MHz tCO RxClk_(n) to RPOS_(n)/RNEG_(n) Delay Time 2.5 ns tRRX RxClk_(n), RxClk_(n) Clock Rise Time (10% to 90%) 1.5 ns tFRX RxClk_(n), RxClk_(n) Clock Fall Time (10% to 90%) 1.5 ns CI Input Capacitance 10 pF CL Load Capacitance 10 pF 15 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 FIGURE 1. TRANSMIT PULSE AMPLITUDE TEST CIRCUIT FOR E3, DS3 AND STS-1 RATES (TYPICAL CHANNEL SHOWN) C h a n n e l (n ) R1 TTIP _(n) TxP O S _(n) TxN E G _(n) TxC lk_(n) T1 TN E G _(n) TxLineC lk_(n) 31.6 TP O S _(n) R3 75 1:1 R2 TR ing_(n) 31.6 FIGURE 2. TIMING DIAGRAM OF THE TRANSMIT TERMINAL INPUT INTERFACE tR T X tF T X TClk tT S U tT H O TPDATA or TNDATA TTIP or TRING tTDY FIGURE 3. TIMING DIAGRAM OF THE RECEIVE TERMINAL OUTPUT INTERFACE tR R X t FRX RClk t LCVO LCV tC O RPOS or RNEG 16 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 ELECTRICAL CHARACTERISTICS (CONTINUED), (TA = 25°C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED) LINE SIDE PARAMETERS E3 APPLICATION SYMBOL PARAMETER MIN. TYP. MAX UNITS Transmit Output Pulse Amplitude (Measured at Secondary Output of Transformer) 0.9 1.0 1.1 Vpk Transmit Output Pulse Amplitude Ratio 0.95 1.00 1.05 Transmit Output Pulse Width 12.5 14.55 16.5 Transmit Output Pulse Width Ratio 0.95 1.00 1.05 0.02 0.05 TRANSMIT CHARACTERISTICS (SEE IGURE 1) Transmit Output Jitter with jitter-free input @ TxClk_(n) ns UIpp Receive Line Characteristics Receive Sensitivity (Length of cable) 1200 Interference Margin -20 feet -15 dB Signal Level to Declare Loss of Signal -35 dB Signal Level to Clear Loss of Signal -15 dB Occurrence of LOS to LOS Declaration Time 10 255 UI Termination of LOS to LOS Clearance Time 10 255 UI Intrinsic Jitter (all "1's" Pattern)(1) 0.01 UI Intrinsic Jitter ("100" Pattern) 0.03 UI Jitter Tolerance @ Jitter Frequency = 100Hz 64 UI Jitter Tolerance @ Jitter Frequency = 1kHz 30 UI Jitter Tolerance @ Jitter Frequency = 10kHz 4 UI Jitter Tolerance @ Jitter Frequency = 800kHz 0.15 UI ELECTRICAL CHARACTERISTICS (CONTINUED), (TA = 25°C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED) LINE SIDE PARAMETERS SONET STS-1 APPLICATION TRANSMIT CHARACTERISTICS (SEE IGURE 1) SYMBOL PARAMETER MIN. TYP. MAX UNITS Transmit Output Pulse Amplitude (Measured with TxLEV=0) 0.68 0.75 0.85 Vpk Transmit Output Pulse Amplitude (Measured with TxLEV=1) 0.93 0.98 1.08 Vpk Transmit Output Pulse Width 8.6 9.65 10.6 ns Transmit Output Pulse Amplitude Ratio 0.9 1.0 1.1 0.02 0.05 Transmit Output Jitter with jitter-free input @ TxClk_(n) Receive Line Characteristics 17 UI áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 ELECTRICAL CHARACTERISTICS (CONTINUED), (TA = 25°C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED) LINE SIDE PARAMETERS SONET STS-1 APPLICATION TRANSMIT CHARACTERISTICS (SEE IGURE 1) SYMBOL PARAMETER MIN. Receive Sensitivity (Length of cable) TYP. MAX UNITS 1000 feet Signal Level to Declare Loss of Signal (LOSTHR = 0, REQ_IN = 1) 90 mV Signal Level to Clear Loss of Signal (LOSTHR = 0, REQ_IN = 1) 240 mV Signal Level to Declare Loss of Signal (LOSTHR = 1, REQ_IN = 1) 35 mV Signal Level to Clear Loss of Signal (LOSTHR = 1, REQ_IN = 1) 75 mV Signal Level to Declare Loss of Signal (LOSTHR = 0, REQ_IN = 0) 70 mV Signal Level to Clear Loss of Signal (LOSTHR = 0, REQ_IN = 0) 190 mV Signal Level to Declare Loss of Signal (LOSTHR = 1, REQ_IN = 0) 35 Signal Level to Clear Loss of Signal (LOSTHR = 1, REQ_IN = 0) 65 mV Intrinsic Jitter (all "1's" Pattern)(2) 0.03 UI Intrinsic Jitter ( "100" Pattern) 0.03 UI 90 mV Jitter Tolerance @ Jitter Frequency = 100Hz 64 UI Jitter Tolerance @ Jitter Frequency = 1kHz 64 UI Jitter Tolerance @ Jitter Frequency = 10kHz 5 UI Jitter Tolerance @ Jitter Frequency = 800kHz 0.4 UI (1) Measured with Equalizer enabled, 12db Cable attenuation, VDD = 3.3V and TA = 25°C (2) Measured at nominal STSX-1 level with equalizer enabled, VDD = 3.3V and TA = 25°C ELECTRICAL CHARACTERISTICS (CONTINUED), (TA = 250C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED) LINE SIDE PARAMETERS DS3 APPLICATION SYMBOL PARAMETER MIN. TYP. MAX UNITS Transmit Output Pulse Amplitude (Measured at 0 feet, TxLEV=0) 0.68 0.75 0.85 Vpk Transmit Output Pulse Amplitude (Measured at 0 feet, TxLEV=1) 0.9 1.0 1.1 Vpk 10.10 11.18 12.28 ns 0.9 1.0 1.1 0.02 0.05 TRANSMIT CHARACTERISTICS (SEE IGURE 1) Transmit Output Pulse Width Transmit Output Pulse Amplitude Ratio Transmit Output Jitter with jitter-free input @ TxClk_(n) Receive Line Characteristics 18 UI áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 ELECTRICAL CHARACTERISTICS (CONTINUED), (TA = 250C, VDD = 3.3V + 5%, UNLESS OTHERWISE SPECIFIED) LINE SIDE PARAMETERS DS3 APPLICATION SYMBOL PARAMETER MIN. TYP. MAX UNITS Receive Sensitivity (Length of Cable) 1000 feet Receive Intrinsic Jitter (all "1's" Pattern) 0.01 UI Receive Intrinsic Jitter (Using PRBS 223-1 Pattern) 0.02 UI Signal Level to Declare Loss of Signal (LOSTHR = 0, REQ_IN = 1) 70 mV Signal Level to Clear Loss of Signal (LOSTHR = 0, REQ_IN = 1) 200 mV Signal Level to Declare Loss of Signal (LOSTHR = 1, REQ_IN = 1) 35 mV Signal Level to Clear Loss of Signal (LOSTHR = 1, REQ_IN = 1) 80 mV Signal Level to Declare Loss of Signal (LOSTHR = 0, REQ_IN = 0) 50 mV 130 mV Signal Level to Declare Loss of Signal (LOSTHR = 1, REQ_IN = 0) 25 mV Signal Level to Clear Loss of Signal (LOSTHR = 1, REQ_IN = 0) 55 mV Intrinsic Jitter (all "1's" Pattern) 0.01 UI Intrinsic Jitter ("100" Pattern)(1) 0.02 UI Signal Level to Clear Loss of Signal (LOSTHR = 0, REQ_IN = 0) 155 Jitter Tolerance @ Jitter Frequency = 100Hz 64 UI Jitter Tolerance @ Jitter Frequency = 1kHz 64 UI Jitter Tolerance @ Jitter Frequency = 10kHz 5 UI Jitter Tolerance @ Jitter Frequency = 800kHz 0.4 UI (1) Measured at nominal DSX3 level, Equalizer enabled, VDD = 3.3V, TA = 25°C 19 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 ELECTRICAL CHARACTERISTICS (CONTINUED), (TA = 25°C, VDD = 3.3 + 5%, UNLESS OTHERWISE SPECIFIED) MICROPROCESSOR SERIAL INTERFACE TIMING (SEE IGURE 5) SYMBOL PARAMETER MIN. TYP. MAX UNITS t21 CS Low to Rising Edge of SClk Setup Time 5 ns t22 CS High to Rising Edge of SClk Hold Time 5 ns t23 SDI to Rising Edge of SClk Setup Time 5 ns t24 SDI to Rising Edge of SClk Hold Time 5 ns t25 SClk "Low" Time 65 80 ns t26 SClk "High" Time 65 80 ns t27 SClk Period 160 ns t28 CS Low to Rising Edge of SClk Hold Time 5 ns t29 CS "Inactive" Time 160 ns t30 Falling Edge of SClk to SDO Valid Time 80 ns t31 Falling Edge of SClk to SDO Invalid Time 65 ns t32 Falling Edge of SClk, or rising edge of CS to High Z t33 Rise/Fall time of SDO Output 100 ns 20 ns FIGURE 4. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE CS SClk 1 SDI R/W 2 A0 3 A1 4 A2 5 A3 6 0 7 0 8 A6 9 10 11 12 13 14 15 16 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 0 0 0 High Z High Z SDO 3. R/W = "0" for "Write" Operations NOTES: 1. A4 and A5 are always "0". 4. A shaded pulse, denotes a "don't care" value. 2. R/W = "1" for "Read" Operations 20 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 FIGURE 5. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE t29 t21 CS t27 t22 t25 SCLK t26 t24 t23 SDI t28 A0 R/W A1 CS SCLK t31 t30 SDO SDI Hi-Z D0 t33 t32 D2 D1 Hi-Z 21 D7 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 a. Operating in the Hardware Mode SYSTEM DESCRIPTION The XRT73L02 XRT73L02 can be configured to operate in the Hardware Mode by tying the HOST/(HW) input pin to GND. A functional block diagram of the XRT73L02 XRT73L02 E3/DS3/ STS-1 Transceiver IC is presented in Figure 6. The XRT73L02 XRT73L02 contains three independent transmitter and receiver sections and a common microprocessor interface section. When the XRT73L02 XRT73L02 is operating in the Hardware Mode, the following is true: 1. The Microprocessor Serial Interface block is disabled. THE TRANSMIT SECTION - CHANNELS 0 AND 1 The Transmit Section of each Channel accepts TTL/ CMOS level signals from the Terminal Equipment in either a Single-Rail or Dual-Rail format. The Transmit Section takes this data and does the following: 2. The XRT73L02 XRT73L02 is configured via input pin settings. Each of the pins associated with the Microprocessor Serial Interface takes on their alternative role as defined in Table 1. · Encode this data into the B3ZS format if the DS3 or SONET STS-1 Modes have been selected, or into the HDB3 format if the E3 Mode has been selected. TABLE 1: ROLE OF MICROPROCESSOR SERIAL INTERFACE PINS WHEN THE XRT73L02 XRT73L02 IS OPERATING IN THE HARDWARE MODE · Convert the CMOS level B3ZS or HDB3 encoded data into pulses with shapes that are compliant with the various industry standard pulse template requirements. FUNCTION WHILE IN PIN # 17 SClk/(RxOFF_1) RxOFF_1 SDI/(RxOFF_0) RxOFF_0 20 SDO/(E3_Ch_0) E3_Ch_0 42 THE RECEIVE SECTION - CHANNELS 0 AND 1 ENDECDIS 19 NOTE: The Transmit Section drives a "1" (or a Mark) onto the line by driving either a positive or negative polarity pulse across the 1:1 Transformer in a given bit period. The Transmit Section drives a "0" (or a Space) onto the line by driving no pulse onto the line. CS/(ENDECDIS) 18 · Drive these pulses onto the line via the TTIP_(n) and TRing_(n) output pins across a 1:1 Transformer. PIN NAME REGR/(RxClkINV) RxClkINV HARDWARE MODE When the XRT73L02 XRT73L02 is operating in the Hardware Mode, all of the remaining input pins become active. The Receive Section of each Channel receives a bipolar signal from the line via the RTIP and RRing signals across a 1:1 Transformer or a 0.01µF Capacitor. The Receive Section will do the following: b. Operating in the HOST Mode The XRT73L02 XRT73L02 can be configured to operate in the HOST Mode by tying the HOST/(HW) input pin to VDD. · Adjust the signal level through an AGC circuit. · Optionally equalize this signal for cable loss. When the XRT73L02 XRT73L02 is operating in the HOST Mode, the following is true: · Route the sliced data to the HDB3/B3ZS Decoder, during which the original data content as transmitted by the Remote Terminal Equipment is restored to its original content. 1. The Microprocessor Serial Interface block is enabled. Writing the appropriate data into the on-chip Command Registers makes many configuration selections. · The recovered clock and data outputs to the Local Terminal Equipment in the form of CMOS level signals via the RPOS_(n), RNEG_(n) and RxClk_(n) output pins. 2. All of the following input pins are disabled and should be connected to GND. · · · · · · · THE MICROPROCESSOR SERIAL INTERFACE The XRT73L02 XRT73L02 contains two identical channels. The Microprocessor Interface Inputs are common to both channels. The descriptions that follow refer to Channel (n) where (n) represents Channel 0 or Channel 1. The XRT73L02 XRT73L02 can be configured to operate in either the Hardware Mode or the HOST Mode. 22 Pins 1, 60 - TxLEV_(n) Pins 2, 59 - TAOS_(n) Pins 30, 31 - REQEN_(n) Pins 25, 36 - RLB_(n) Pins 24, 37 - LLB_(n) Pin 39 - E3_Ch_(n) Pins 21, 41 - STS1/DS3_Ch_(n) áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 designed for redundancy to quickly switch out a defective line card and switch-in the back-up line card. In HOST Mode Operation, the TxOFF_(n) input pins can still be used to turn on or turn off the Transmit Output Drivers in Channels 0 and 1, respectively. The intent behind this feature is to permit a system FIGURE 6. FUNCTIONAL BLOCK DIAGRAM OF THE XRT73L02 XRT73L02 E3_Ch_(n) RTIP_(n) RRing_(n) STS-1/DS3_Ch_(n) AGC/ Equalizer Host/(HW) RLOL_(n) EXClk_(n) RxClkINV Clock Recovery Slicer Peak Detector REQEN_(n) RxOFF Invert HDB3/ B3ZS Decoder Data Recovery LOS Detector LOSTHR_(n) RxClk_(n) RPOS_(n) SClk CS LCV_(n) ENDECDIS SDI SDO RNEG_(n) RLOS_(n) Serial Processor Interface LLB_(n) Loop MUX RLB_(n) REGR TAOS_(n) TTIP_(n) Pulse Shaping HDB3/ B3ZS Encoder MRing_(n) Device Monitor TNData_(n) Duty Cycle Adjust TRing_(n) MTIP_(n) TPData_(n) Transmit Logic TxClk_(n) TxLEV_(n) Tx Control TxOFF_(n) Channel 0 DMO_(n) Channel 1 Notes: 1. (n) = 0 or 1 for the respective Channel 2. Serial Processor Interface input pins are shared by both Channels in HOST Mode and are redefined in Hardware Mode. 1.1 CONFIGURING CHANNEL (N) 1.0 SELECTING THE DATA RATE Each channel in the XRT73L02 XRT73L02 can be configured to support the E3 (34.368 Mbps), DS3 (44.736 Mbps) or SONET STS-1 (51.84 Mbps) rates and to operate in a mode/data rate that is independent of the other channel. Refer to Table 2 to determine the appropriate Address for each Command Register of each channel in the XRT73L02 XRT73L02. The Command Register description refers to CR(m)-(n), where (m) = 0 to 7 and (n) refers to a particular channel of the XRT73L02 XRT73L02. Two methods are available to select the data rate for each channel of the XRT73L02 XRT73L02. 23 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 TABLE 2: ADDRESSES AND BIT FORMATS OF XRT73L02 XRT73L02 COMMAND REGISTERS REGISTER BIT-FORMAT ADDRESS COMMAND REGISTER TYPE D4 D3 D2 D1 D0 CHANNEL0 0x00 CR0-0 RO RLOL_0 RLOS_0 ALOS_0 DLOS_0 DMO_0 0x01 CR1-0 R/W TxOFF_0 TAOS_0 TxClkINV_0 TxLEV_0 TxBIN_0 0x02 CR2-0 R/W Reserved ENDECDIS_0 ALOSDIS_0 DLOSDIS_0 REQEN_0 0x03 CR3-0 R/W SR/(DR)_0 LOSMUT_0 RxOFF_0 RxClk_0INV Reserved 0x04 CR4-0 R/W Reserved STS-1/DS3_Ch_0 E3_Ch_0 LLB_0 RLB_0 0x05 CR5-0 R/W Reserved Reserved Reserved Reserved Reserved 0x06 CR6-0 R/W Reserved Reserved Reserved Reserved Reserved 0x07 CR7-0 R/W Reserved Reserved Reserved Reserved Reserved CHANNEL1 0x08 CR0-1 RO RLOL_1 RLOS_1 ALOS_1 DLOS_1 DMO_1 0x09 CR1-1 R/W TxOFF_1 TAOS_1 TxClkINV_1 TxLEV_1 TxBIN_1 0x0A CR2-1 R/W Reserved ENDECDIS_1 ALOSDIS_1 DLOSDIS_1 REQEN_1 0x0B CR3-1 R/W SR/(DR)_1 LOSMUT_1 RxOFF_1 RxClk_1INV Reserved 0x0C CR4-1 R/W Reserved STS-1/DS3_Ch_1 E3_Ch_1 LLB_1 RLB_1 0x0D CR5-1 R/W Reserved Reserved Reserved Reserved Reserved 0x0E CR6-1 R/W Reserved Reserved Reserved Reserved Reserved 0x0F CR7-1 R/W Reserved Reserved Reserved Reserved Reserved Address: The default value for each of the bit-fields in these registers is "0". The register addresses presented in the Hexadecimal format. a. Operating in the Hardware Mode Type: To configure individual Channel Data Rate, set the E3_Ch_(n) and the STS-1/DS3_Ch_(n) input pins (where n = 0 or 1) to the appropriate logic states referenced in Table 3. The Command Registers are either Read-Only (RO) or Read/Write (R/W) type of registers. TABLE 3: SELECTING THE DATA RATE FOR CHANNEL (N) OF THE XRT73L02 XRT73L02, VIA THE E3_CH_(N) AND STS-1/ DS3_CH_(N) INPUT PINS (HARDWARE MODE) DATA RATE STATE OF E3_CH_(N) PIN (PIN 20 OR 39) STATE OF STS-1/DS3_CH_(N) PIN (PIN 21 OR 41) MODE OF B3ZS/HDB3 ENCODER/ DECODER BLOCKS E3 (34.368 Mbps) 1 X (Don't Care) HDB3 DS3 (44.736 Mbps) 0 0 B3ZS 24 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 TABLE 3: SELECTING THE DATA RATE FOR CHANNEL (N) OF THE XRT73L02 XRT73L02, VIA THE E3_CH_(N) AND STS-1/ DS3_CH_(N) INPUT PINS (HARDWARE MODE) DATA RATE STATE OF E3_CH_(N) PIN (PIN 20 OR 39) STATE OF STS-1/DS3_CH_(N) PIN (PIN 21 OR 41) MODE OF B3ZS/HDB3 ENCODER/ DECODER BLOCKS STS-1 (51.84 Mbps) 0 1 B3ZS · Establishes the LOS Declaration/Clearance Criteria for Channel (n) (Section 3.5). b. Operating in the HOST Mode. To configure the Data Rate of a Channel, write the appropriate values into the STS-1/DS3_Ch_(n) and E3_Ch_(n) bit-fields in Command Register CR4-(n). 2.0 THE TRANSMIT SECTION Figure 6 shows the Transmit Section in each Channel of the XRT73L02 XRT73L02 consists of the following blocks: NOTE: Reference Table 2 for the correct address of each channel. · Transmit Logic Block · TxClk_(n) Duty Cycle Adjust Block · HDB3/(B3ZS) Encoder · Pulse Shaping Block The purpose of the Transmit Section in each Channel of the XRT73L02 XRT73L02 is to take TTL/CMOS level data from the Terminal Equipment and encode it into a format that can: COMMAND REGISTER CR4-(N) D4 X D3 D2 D1 D0 STS-1/(DS3)_(n) E3_Ch_(n) LLB_(n) RLB_(n) X X X X Xs Table 4 relates the values of these two bit-fields to the selected data rates. 1. be efficiently transmitted over coaxial cable at E3, DS3 or STS-1 data rates, TABLE 4: SELECTING THE DATA RATE FOR CHANNEL (N) OF THE XRT73L02 XRT73L02 VIA THE STS-1/DS3_CH_(N) AND THE E3_CH_(N) BIT-FIELDS IN THE APPROPRIATE COMMAND REGISTER (HOST MODE) SELECTED DATA RATE STS-1/ DS3_CH_(N) (D3) E3_CH_(N) (D2) E3 X (Don't Care) 1 DS3 0 0 STS-1 1 2. be reliably received by the Remote Terminal Equipment at the other end of the E3, DS3 or STS-1 data link, and 0 3. comply with the applicable pulse template requirements. The circuitry that the Transmit Section in each Channel of the XRT73L02 XRT73L02 takes to accomplish this goal is discussed below. 2.1 THE TRANSMIT LOGIC BLOCK The purpose of the Transmit Logic Block is to accept either Dual-Rail or Single-Rail (binary data stream) TTL/CMOS level data and timing information from the Terminal Equipment. Making these selections does the following: · Configure the VCO Center Frequency of Channel (n) of the Clock Recovery Phase-Locked Loop to match the selected data rate. 2.1.1 Accepting Dual-Rail Data from the Terminal Equipment · If the DS3 or STS-1 data rates are selected, it configures the B3ZS/(HDB3) Encoder and Decoder blocks to support B3ZS Encoding/Decoding. Whenever the XRT73L02 XRT73L02 accepts Dual-Rail data from the Terminal Equipment, it does so via the following input signals: · If the E3 data rate is selected, it configures the B3ZS/(HDB3) Encoder and Decoder blocks to support HDB3 Encoding/Decoding. · TPData_(n) · TNData_(n) · TxClk_(n) Figure 7 illustrates the typical interface for the transmission of data in a Dual-Rail Format between the Terminal Equipment and the Transmit Section of the XRT73L02 XRT73L02. · Configure the on-chip Pulse-Shaping circuitry to generate Transmit Output pulses of the appropriate shape and width to meet the applicable pulse template requirement. 25 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 FIGURE 7. THE TYPICAL INTERFACE FOR DATA TRANSMISSION IN DUAL-RAIL FORMAT FROM THE TRANSMITTING TERMINAL EQUIPMENT TO THE TRANSMIT SECTION OF A CHANNEL OF THE XRT73L02 XRT73L02 TxPOS Terminal Equipment (E3/DS3 or STS-1 Framer) TPData TxNEG TNData TxLineClk TxClk Transmit Logic Block Exar E3/DS3/STS-1 LIU The manner that the LIU handles Dual-Rail data is described below and illustrated in Figure 8. The Transmit Section of a Channel typically samples the data on the TPData and TNData input pins on the falling edge of TxClk_(n). FIGURE 8. HOW THE XRT73L02 XRT73L02 SAMPLES THE DATA ON THE TPDATA AND TNDATA INPUT PINS Data 1 1 0 TPData TNData TxClk Write a "1" into the TxBin_(n) (TRANSMIT BINary) bit-field of Command Register CR1-(n) shown below. TxClk_(n) is the clock signal that is of the selected data rate frequency for E3 = 34.368 MHz, DS3 = 44.736 MHz and STS-1 = 51.84 MHz. If the Transmit Section samples a "1" on the TPData input pin, the Transmit Section of the XRT73L02 XRT73L02 generates a positive polarity pulse via the TTIP_(n) and TRing_(n) output pins across a 1:1 transformer. If the Transmit Section samples a "1" on the TNData input pin, then the Transmit Section ultimately generates a negative polarity pulse via the TTIP_(n) and TRing_(n) output pins across a 1:1 transformer. NOTE: Please refer to Table 2 for the Address of the individual Channel (n). COMMAND REGISTER CR1-(N) D4 D3 D2 D1 D0 TxOFF_(n) TAOS_(n) TxClkINV_(n) TxLEV_(n) TxBin_(n) X 2.1.2 Configure Channel (n) to accept SingleRail Data from the Terminal Equipment X X X 1 The Transmit Section of each channel samples this input pin on the falling edge of the TxClk_(n) clock signal and encodes this data into the appropriate bipolar line signal across the TTIP_(n) and TRing_(n) output pins. To transmit data in a Single-Rail data from the Terminal Equipment, configure the XRT73L02 XRT73L02 in the HOST Mode. NOTES: 26 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 1. In this mode the Transmit Logic Block ignores the TNData input pin. Figure 9 illustrates the behavior of the TPData and TxClk_(n) signals when the Transmit Logic Block has been configured to accept Single-Rail data from the Terminal Equipment. 2. If the Transmit Section of a given channel is configured to accept Single-Rail data from the Terminal Equipment, the B3ZS/HDB3 Encoder must be enabled. FIGURE 9. THE BEHAVIOR OF THE TPDATA AND TXCLK INPUT SIGNALS WHILE THE TRANSMIT LOGIC BLOCK IS ACCEPTING SINGLE-RAIL DATA FROM THE TERMINAL EQUIPMENT Data 1 1 0 TPData TxClk 2.3.1 2.2 THE TRANSMIT CLOCK DUTY CYCLE ADJUST CIRCUITRY B3ZS Encoding If the XRT73L02 XRT73L02 has been configured to operate in the DS3 or SONET STS-1 Modes, the HDB3/B3ZS Encoder blocks operate in the B3ZS Mode. When the Encoder is operating in this mode it parses through and searches the Transmit Binary Data Stream from the Transmit Logic Block for the occurrence of three (3) consecutive zeros (e.g., "000"). If the B3ZS Encoder finds an occurrence of three consecutive zeros, then it substitutes these three "0's" with either a "00V" or a "B0V" pattern. The on-chip Pulse-Shaping circuitry in the Transmit Section of each Channel of the XRT73L02 XRT73L02 generates pulses of the appropriate shapes and width to meet the applicable pulse template requirements. The widths of these output pulses are defined by the width of the half-period pulses in the TxClk_(n) signal. However, if the widths of the pulses in the TxClk_(n) clock signal are allowed to vary significantly, this could jeopardize the chip's ability to generate Transmit Output pulses of the appropriate width, thereby not meeting the Pulse Template requirement specification. Consequently, the chip's ability to generate compliant pulses could depend upon the duty cycle of the clock signal applied to the TxClk_(n) input pin. "B" represents a Bipolar pulse that is compliant with the Alternating Polarity requirements of the AMI (Alternate Mark Inversion) line code. "V" represents a Bipolar Violation (e.g., a Bipolar pulse that violates the Alternating Polarity requirements of the AMI line code). The Transmit Clock Duty Cycle Adjust Circuitry accepts clock pulses via the TxClk_(n) input pin at duty cycles ranging from 30% to 70% and converts them to a 50% duty cycle. The B3ZS Encoder decides whether to substitute with either the "00V" or the "B0V" pattern in order to insure that an odd number of Bipolar pulses exist between any two consecutive violation pulses. 2.3 THE HDB3/B3ZS ENCODER BLOCK Figure 10 illustrates the B3ZS Encoder at work with two separate strings of three or more consecutive zeros. The purpose of the HDB3/B3ZS Encoder Block is to aid in the Clock Recovery process at the Remote Terminal Equipment by ensuring an upper limit on the number of consecutive zeros that can exist in the line signal. 27 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 FIGURE 10. AN EXAMPLE OF B3ZS ENCODING Data 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1 TPData TNData TxClk 0 0 V Line Signal B 2.3.2 HDB3 Encoding 0 V "0's" with either a "000V" or a "B00V" pattern. The HDB3 Encoder decides whether to substitute with either the "000V" or the "B00V" pattern in order to insure that an odd number of Bipolar pulses exist between any two consecutive violation pulses. If the XRT73L02 XRT73L02 has been configured to operate in the E3 Mode, the HDB3/B3ZS Encoder blocks operate in the HDB3 Mode. When the Encoder is operating in this mode it parses through and searches the Transmit Data Stream from the Transmit Logic Block for the occurrence of four (4) consecutive zeros ("0000"). If the HDB3 Encoder finds an occurrence of four consecutive zeros then it substitutes these four Figure 11 illustrates the HDB3 Encoder at work with two separate strings of four or more consecutive zeros. FIGURE 11. AN EXAMPLE OF HDB3 ENCODING Data 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 TPData TNData TxClk 0 0 0 V Line Signal B 2.3.3 0 0 V NOTE: By executing this step the HDB3/B3ZS Encoder and Decoder blocks in all channels of the XRT73L02 XRT73L02 are globally disabled. Disabling the HDB3/B3ZS Encoder The XRT73L02 XRT73L02 HDB3/B3ZS Encoder can be disabled by two methods. b. Operating in the HOST Mode. a. Operating in the Hardware Mode. When the XRT73L02 XRT73L02 is operating in the HOST Mode the HDB3/B3ZS Encoders in each channel can be individually enabled or disabled. Disable the HDB3/B3ZS Encoder block in Channel (n) by The HBD3/B3ZS Encoder blocks of all channels are disabled by setting the ENDECDIS (Encoder/ Decoder Disable) input pin to "0". 28 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 setting the ENDECDIS_(n) bit-field in Command Register (CR2-(n), to "1". COMMAND REGISTER CR2-(N) D4 D3 D2 D1 D0 Reserved ENDECDIS_(n) ALOSDIS_(n) DLOSDIS_(n) REQEN_(n) X 1 X X X following pulse template requirements when measured at the Digital Cross Connect System. Each of these Bellcore specifications state that the cable length between the Transmit Output and the Digital Cross Connect system can range anywhere from 0 to 450 feet. If either of these two methods is used to disable the HDB3/B3ZS Encoder, the LIU transmits the data as received via the TPData and TNData input pins. 2.4 THE TRANSMIT PULSE SHAPING CIRCUITRY The Transmit Pulse Shaper Circuitry consists of a Transmit Line Build-Out circuit which can be enabled or disabled by setting the TxLEV_(n) input pin or TxLEV_(n) bit-field to "High" or "Low". The purpose of the Transmit Line Build-Out circuit is to permit configuration of each channel in the XRT73L02 XRT73L02 to transmit an output pulse which is compliant to either of the The Isolated DSX-3 Pulse Template Requirement per Bellcore GR-499-CORE GR-499-CORE is illustrated in Figure 12 and the Isolated STSX-1 Pulse Template Requirement per Bellcore GR-253-CORE GR-253-CORE is illustrated in Figure 13. FIGURE 12. THE BELLCORE GR-499-CORE GR-499-CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR DS3 APPLICATIONS D S 3 P u ls e T e m p la te 1.2 1 0.6 Lower Curve Upper Curve 0.4 0.2 0 2 3 4 1. 9 1. 8 0. 1. 7 0. 1 6 0. 29 1 5 0. Tim e , in UI 1. 4 0. 3 0. 0. 2 0. 0 1 0. .2 .3 .4 .5 .6 .7 .8 .1 -0 -0 -0 -0 -0 -0 -0 -0 -0 .9 -0.2 -1 N o rm a l iz e d Am p l itu d e 0.8 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 . FIGURE 13. THE BELLCORE GR-253-CORE GR-253-CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS ST S-1 Pulse T em p late 1.2 1 Norm a lize d Am plitude 0.8 0.6 Lower Curve Upper Curve 0.4 0.2 0 2 3 4 1. 1. 9 1. 8 0. 1 7 0. 1 6 0. 1. 5 4 0. 0. 3 0. 0. 2 0. 0 1 0. .2 .3 .4 .1 -0 -0 -0 .5 -0 .7 .8 .6 -0 -0 -0 -0 -1 -0 .9 -0.2 Tim e , in UI 2.4.1 cuit Enabling the Transmit Line Build-Out Cir- Enable the Transmit Line Build-Out circuit for each channel in the XRT73L02 XRT73L02 by doing the following: a. Operating in the Hardware Mode If the Transmit Line Build-Out Circuit is enabled, the Transmit Section of Channel (n) of the XRT73L02 XRT73L02 outputs shaped pulses onto the line via the TTIP_(n) and TRing_(n) output pins. Set the TxLEV_(n) input pin to "Low" b. Operating in the HOST Mode Set the TxLEV_(n) bit-field to "0". COMMAND REGISTER CR1-(N) D4 D3 D2 D1 D0 TxOFF_(n) TAOS_(n) TxClkINV_(n) TxLEV_(n) TxBIN_(n) 0 X X 0 X 2.4.2 cuit a. Operating in the Hardware Mode Disabling the Transmit Line Build-Out Cir- Set the TxLEV_(n) input pin to "High". If the Transmit Line Build-Out circuit is disabled, the XRT73L02 XRT73L02 outputs partially-shaped pulses onto the line via the TTIP_(n) and TRing_(n) output pins. b. Operating in the HOST Mode Set the TxLEV_(n) bit-field to "1" as illustrated below. To disable the Transmit Line Build-Out circuit, do the following: 30 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 COMMAND REGISTER CR1-(N) D4 D3 D2 D1 D0 TxOFF_(n) TAOS_(n) TxClkINV_(n) TxLEV_(n) TxBin_(n) 0 X X 1 X the TTIP_(n) and TRing_(n) output pins. The cable loss that these pulses experience over long cable lengths (e.g., greater than 225 feet) causes these pulses to be properly shaped and comply with the appropriate pulse template requirement. 2.4.3 Design Guideline for Setting the Transmit Line Build-Out Circuit The TxLEV_(n) input pins or bit-fields should be set based upon the overall cable length between the Transmitting Terminal and the Digital Cross Connect system where the pulse template measurements are made. 2.4.4 The Transmit Line Build-Out Circuit and E3 Applications The ITU-T G.703 Pulse Template Requirements for E3 states that the E3 transmit output pulse should be measured at the Secondary Side of the Transmit Output Transformer for Pulse Template compliance. In other words, there is no Digital Cross Connect System pulse template requirement for E3. Consequently, the Transmit Line Build-Out circuit in a given Channel in the XRT73L02 XRT73L02 is disabled whenever that channel has been configured to operate in the E3 Mode. If the cable length between the Transmitting Terminal and the DSX-3 or STSX-1 is less than 225 feet, enable the Transmit Line Build-Out circuit by setting the TxLEV_(n) input pin or bit-field to "0". NOTE: In this case, the configured channel outputs shaped (e.g., not square-wave) pulses onto the line via its TTIP_(n) and TRing_(n) output pins. The shape of this output pulse is such that it complies with the pulse template requirements even when subjected to cable loss ranging from 0 to 225 feet. 2.5 INTERFACING THE TRANSMIT SECTIONS OF THE XRT73L02 XRT73L02 TO THE LINE If the cable length between the Transmitting Terminal and the DSX-3 or STSX-1 is greater than 225 feet, disable the Transmit Line Build-Out circuit by setting the TxLEV_(n) input pin or bit-field to "1". The E3, DS3 and SONET STS-1 specification documents all state that line signals transmitted over coaxial cable are to be terminated with 75 Ohm resistor. Interface the Transmit Section of the XRT73L02 XRT73L02 in the manner illustrated in Figure 14 to accomplish this. NOTE: In this case, the configured channel in the XRT73L02 XRT73L02 outputs partially-shaped pulses onto the line via FIGURE 14. RECOMMENDED SCHEMATIC FOR INTERFACING THE TRANSMIT SECTION OF THE XRT73L02 XRT73L02 TO THE LINE TTIP_(n) Channel (n) TxPOS_(n) TxNEG_(n) TxLineClk_(n) R1 31.6 J1 BNC TPData_(n) TNData_(n) TxClk_(n) 1:1 R2 31.6 TRing_(n) Only One Channel Shown 31 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 Asia Transformer Recommendations PARAMETER VALUE Turns Ratio 1:1 Primary Inductance 4µH Isolation Voltage 1500Vrms Leakage Inductance 150 Kampong Ampat #07-01/02 KA Centre Singapore 368324 Tel: 65-287-8998 FAX: 65-280-0080 0.06µH PART # INSULATION 3000V 1500V Small Thru-Hole PE-65967 PE-65967 1500V Small SMT T3001 T3001 1500V · AGC/Equalizer · Peak Detector · Slicer · Clock Recovery PLL · Data Recovery · HDB3/B3ZS Decoder The purpose of each Receive Section of the XRT73L02 XRT73L02 is to take an incoming attenuated/distorted bipolar signal from the line and encode it back into the TTL/CMOS format where it can be received and processed by the Terminal Equipment. Large Thru-Hole PE-65966 PE-65966 Figure 6 indicates that the Receive Section in the XRT73L02 XRT73L02 consists of the following blocks: PACKAGE TYPE PE-68629 PE-68629 3.0 THE RECEIVE SECTION Small SMT TRANSFORMER VENDOR INFORMATION Pulse Corporate Office 3.1 INTERFACING THE RECEIVE SECTIONS OF THE XRT73L02 XRT73L02 TO THE LINE 12220 World Trade Drive San Diego, CA 92128 Tel: (619)-674-8100 FAX: (619)-674-8262 Europe The design of the Receive Circuitry in the XRT73L02 XRT73L02 allows for transformer-coupling or capacitive-coupling of the Receive Section to the line. As mentioned earlier, the specification documents for E3, DS3 and STS-1 all specify 75 Ohm termination loads when transmitting over coaxial cable. The recommended method of Transformer-Coupling the Receive Section of the XRT73L02 XRT73L02 to the line is shown in Figure 15 and the Capacitive-Coupling method is shown in Figure 16. 1 & 2 Huxley Road The Surrey Research Park Guildford, Surrey GU2 5RE United Kingdom Tel: 44-1483-401700 FAX: 44-1483-401701 32 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 FIGURE 15. RECOMMENDED SCHEMATIC FOR TRANSFORMER-COUPLING THE RECEIVE SECTION OF THE XRT73L02 XRT73L02 TO THE LINE RTIP_(n) Channel (n) RxPOS_(n) RxNEG_(n) RxClk_(n) R1 37.5 RPOS_(n) RNEG_(n) RxClk_(n) T1 J1 BNC C1 0.01uf R2 37.5 1:1 RRing_(n) Only One Channel Shown FIGURE 16. RECOMMENDED SCHEMATIC FOR CAPACITIVE-COUPLING THE RECEIVE SECTION OF THE XRT73L02 XRT73L02 TO THE LINE J1 BNC C1 0.01uf RTIP_(n) R1 75 Channel (n) RxPOS_(n) RxNEG_(n) RxClk_(n) RPOS_(n) RNEG_(n) RxClk_(n) C2 0.01uf RRing_(n) Only One Channel Shown 33 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 3.2 THE RECEIVE EQUALIZER BLOCK Equalizer attempts to restore the shape of the line signal so that the transmitted data and clock can be recovered reliably. The purpose of this block is to equalize the incoming distorted signal due to cable loss. The Receive FIGURE 17. THE TYPICAL APPLICATION FOR THE SYSTEM INSTALLER Digital Cross-Connect System Transmitting Terminal 0 to 450 feet of Cable Pulses that are compliant to the Isolated DSX-3 or STSX-1 Pulse Template Requirement DSX-3 or STSX-1 0 to 450 feet of Cable Receiving Terminal · Design Considerations for DS3 and STS-1 Applications a. The length of cable between the Transmitting Terminal and the Digital Cross-Connect system can range between 0 and 450 feet. When installing equipment into environments depicted in Figure 17, we recommend that the Receive Equalizer be enabled by setting the REQEN_(n) input pin for Channel (n) or the respective bit-fields to "1". The only time that the Receive Equalizer should be disabled is when an off-chip equalizer is in the Receive path between the Digital Cross-Connect system and the RTIP/RRing input pins, or in applications where the Receiver is monitoring the transmit output signal directly. b. The length of cable between the Digital Cross-Connect system and the Receive Terminal can range between 0 and 450 feet. Consequently, the overall cable length between the Transmitting Terminal and the Receiving Terminal can range between very short cable length (e.g., near 0 feet) up to 900 feet. If during System Installation the overall cable length is known, to optimize the performance of the XRT73L02 XRT73L02 in terms of receive jitter performance, etc., enable or disable the Receive Equalizer based upon the following recommendations: · Design Considerations for E3 Applications or if the Overall Cable Length is known Figure 17 indicates the following: The Receive Equalizer should be turned ON if the Receive Section of a given channel is going to re- 34 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 mitting terminal to the receiving terminal. However, the Receive Equalizer was not designed to counter flat loss where all of the Fourier frequency components within the line signal are subject to the same amount of attenuation. Flat loss is handled by the AGC block. ceive a line signal with an overall cable length of 300 feet or greater. Conversely, turn OFF the Receive Equalizer if the Receive Section of a given channel is going to receive a line signal with an overall cable length of less than 300 feet. NOTES: Disable the Receive Equalizer block by doing either of the following: 1. If the Receive Equalizer block is turned ON when it is receiving a line signal over short cable length the received line signal may be over-equalized, which could degrade performance by increasing the amount of jitter that exists in the recovered data and clock signals or by creating bit-errors. a. Operating in the Hardware Mode Set the REQEN_(n) input pin "Low". b. Operating in the HOST Mode Write a "0" to the REQEN_(n) bit-field in Command Register CR2. 2. The Receive Equalizer has been designed to counter the frequency-dependent cable loss that a line signal experiences as it travels from the trans- COMMAND REGISTER CR2_(N) D4 D3 D2 D1 D0 RESERVED ENDECDIS_(n) ALOSDIS_(n) DLOSDIS_(n) REQEN_(n) X X X X 0 b. Output a clock signal via the RxClk_(n) output pin which is derived from the signal applied to the EXClk_(n) input pin. 3.3 PEAK DETECTOR AND SLICER After the incoming line signal has passed through the Receive Equalizer block, it is routed to the Slicer block. The Slicer block quantifies a given bit-period (or symbol) within the incoming line signal as either a "1" or a "0". 3.4.2 If the frequency difference between the line signal and that applied via the ExClk input pin is less than 0.5%, the channel operates in the Data/Clock Recovery mode. In this mode, the Clock Recovery PLL locks onto the line signal via the RTIP and RRing input pins. 3.4 CLOCK RECOVERY PLL The purpose of the Clock Recovery PLL is to track the incoming Dual-Rail data stream and to derive and generate a recovered clock signal. 3.5 THE HDB3/B3ZS DECODER It is important to note that the Clock Recovery PLL requires a line rate clock signal at the ExClk input pin. The Remote Transmitting Terminal typically encodes the line signal into some sort of Zero Suppression Line Code (e.g., HDB3 for E3 and B3ZS for DS3 and STS-1). The purpose of this encoding activity was to aid in the Clock Recovery process of this data from the Near-End Receiving Terminal. However, once the data has made it across the E3, DS3 or STS-1 Transport Medium and has been recovered by the Clock Recovery PLL, it is now necessary to restore the original content of the data. The purpose of the HDB3/ B3ZS Decoding block is to restore the data transmitted over the E3, DS3 or STS-1 line to its original content prior to Zero Suppression Coding. The Clock Recovery PLL operates in one of two modes: · The Training Mode · The Data/Clock Recovery Mode 3.4.1 The Data/Clock Recovery Mode The Training Mode If a given channel in the XRT73L02 XRT73L02 is not receiving a line signal via the RTIP and RRing input pins, or if the frequency difference between the line signal and that applied via the ExClk input pin exceeds 0.5%, the channel operates in the Training Mode. When the channel is operating in the Training Mode, it does the following: 3.5.1 B3ZS Decoding DS3/STS-1 Applications If the XRT73L02 XRT73L02 is configured to operate in the DS3 or STS-1 Modes, then the HDB3/B3ZS Decoding Blocks perform B3ZS Decoding. When the Decoders are operating in this mode, each of the Decoders parses through its respective incoming Dual-Rail data a. Declare a Loss of Lock indication by toggling its respective RLOL_(n) output pin "High". 35 áç XRT73L02 XRT73L02 2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT PRELIMINARY REV. P1.1.2 tive "0's" in the incoming line signal, the B3ZS Decoder flags this event as a Line Code Violation by pulsing the LCV output pin "High". and checks for the occurrence of either a "00V" or a "B0V" pattern. If the B3ZS Decoder detects this particular pattern, it substitutes these bits with a "000" pattern. Figure 18 illustrates the B3ZS Decoder at work with two separate Zero Suppression patterns in the incomin