XQR4000XL -XQR4013XL -XQR4036XL -XQR4062XL CB228 43E-8 54E-8 50E-7 78E-6 78E-4

Radiation Hardened FPGAs The XQR4000XL Family u 3 Device Sizes -XQR4013XL (10K to 30K system gates) -XQR4036XL (20K to 65K system

High Reliability Products Radiation Hardened FPGAs The XQR4000XL XQR4000XL Family u 3 Device Sizes -XQR4013XL -XQR4013XL (10K to 30K system gates) -XQR4036XL -XQR4036XL (20K to 65K system gates) -XQR4062XL -XQR4062XL (40K to 130K system gates) u Packages -Ceramic QFP - CB228 CB228 -PQFP, BGA under consideration u Temperature Range -55oC to +125oC Speed Grade -3 over Military Temperature Range -~ -1 over Commercial Temperature Range XQR4000XL XQR4000XL Radiation Specifications · Total Ionizing Dose 60K Rads · Latch-up Immune LETth >100 MeV*cm2/mg @ +125oC 0.35m (drawn) epitaxial CMOS process · Soft Upset Rate (upsets/bit-day) 2.43E-8 43E-8 (Galactic p+)1 9.54E-8 54E-8 (Galactic Heavy Ion) 1 Note1: For Low Earth Orbit (LEO), 680 km, 98°inclination, 100 mils Al shielding IC Process w0.35µ epitaxial CMOS process l l l l Thin, high quality gate oxide Highly doped field oxide Field implant in SRAM area 7µ epi substrate wManufactured on QML Line wQA Lot Monitor to insure Radiation Specifications Xilinx/Lockheed Test May 1998 wXQR4036XL devices l l l l 0.35m (drawn) CMOS Thin, high quality gate oxide Highly doped field oxide 0.7m epi substrate wTotal Dose: 60,000 Rads wHeavy-ion tests l LETs up to 120 MeV-cm2/mg. wNot a single case of latch-up @ 125 oC Calculated Upset Rates for LEO Galactic H.I. (ups/bit-day) 9.54E-8 54E-8 Galactic p+ (ups/bit-day) 2.43E-8 43E-8 Trapped p+ (ups/bit-day) 2.50E-7 50E-7 90% w/c p+ (ups/bit) 2.78E-6 78E-6 ALSF p+ (ups/bit) 1.78E-4 78E-4 90% w/c H.I. (ups/bit) 1.46E-6 46E-6 ALSF H.I. (ups/bit) 1.44E-6 44E-6 Notes 1. Low Earth Orbit (LEO), 680 km, 98°inclination, 100 mil Al shielding 2. Heavy ion testing was performed on Xilinx XQR devices at Brookhaven National Laboratories. This data was used to calculate upsets from the galactic cosmic and solar flare environments 3. Space Radiation 2.5 and CHIME models were used for the galactic and solar flare conditions. 4. Space Radiation 2.5 was used for the trapped radiation and proton contribution from the flares. Calculated Upset Rates for GEO Galactic Galactic H.I. p+ (ups/bit-day) (ups/bit-day) 2.34E-7 34E-7 5.62E-8 62E-8 Trapped p+ (ups/bit-day) - 90% w/c p+ (ups/bit) 3.90E-6 90E-6 ALSF p+ (ups/bit) 2.49E-4 49E-4 90% w/c H.I. (ups/bit) 7.20E-6 20E-6 ALSF H.I. (ups/bit) 6.98E-6 98E-6 Notes 1. Geostationary Earth Orbit (GEO), 35,000 km, 0°inclination, 100 mil Al shielding 2. Heavy ion testing was performed on Xilinx XQR devices at Brookhaven National Laboratories. This data was used to calculate upsets from the galactic cosmic and solar flare environments 3. Space Radiation 2.5 and CHIME models were used for the galactic and solar flare conditions. 4. Space Radiation 2.5 was used for the proton contribution from the flares. Ericsson/SAAB test January 1998 wXC4010 and XC4010XL XC4010XL l l Neutron single-event-upset tests at up to 100 MeV Not a single case of latch-up wConclusion l l SEU cross sections of 1.3 to 4.4 10-15 cm2/bit an order of magnitude below the lower limit reported for SRAMs wMTBF for avionics applications (at 10 km altitude,60o N) l l 1,300,000 flight hours for the XC4010E XC4010E 275,000 hours for the XC4010XL XC4010XL Ericsson Saab Avionics Conclusion "SRAM-based FPGAs (Xilinx XC4000 XC4000 series) show a low susceptibility to single event upsets caused by high energy neutrons . . these SRAM - based we conclude that FPGAs can be used without limitation in the atmospheric radiation environment, contrary to large SRAM memories where precaution in the use is necessary because of neutron-induced SEU." FPGA Configuration Memory wDistributed Dual Port Memory l configuration/readback port l control "port" wFPGA Functionality Defined by the State of the Memory l all bits "read" continuously wMemory Loaded on Power-Up l can load itself l can be loaded by another FPGA Configuration Memory (cont.) wMemory Can Be Re-Loaded l at any time l any number of times wMemory Can Be Read Back l during circuit operation l includes the "state" of the circuit Inherently-Robust Latch Design Cross-coupled inverters plus write (read) transistor u Common power and ground contacts u Stability is equivalent to 6-transistor SRAM cell u -active pull-up and pull-down -each ~5 kilohm on-resistance u Typical 4-transistor SRAM cell uses polysilicon pull-ups -six orders of magnitude weaker -5 gigohms vs. 5 kilohms All Latches are Sensitive to Single-Event Upsets wXilinx FPGAs store logic and routing in latches wAntifuse-based FPGAs use fewer latches l only for user data, not for logic and interconnect wAll latches require some kind of error correction Xilinx FPGAs offer a unique, efficient way to correct SEUs Rad-Hard Configuration Memories E2PROM · Northrop Grumman (formerly Westinghouse, Baltimore) · W28C64 W28C64 - 64K (8K x 8) · W28C256 W28C256 - 256K (32K x 8) · SEU LETth -60 MeV-cm2/mg (read cycle) -35 MeV-cm2/mg (write cycle) SRAM · Honeywell · HLX6228 HLX6228 - 1M (128K x 8) ·