NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: XPS IIC Bus Interface (v2.01a) DS606 DS606 December 2, 2009 Product Specification Introduction , , software (register) interface and parameterization options for the XPS IIC module. It provides a low speed, two wire, serial bus interface to a large number of popular devices. XPS IIC supports all , 1 XPS IIC Bus Interface (v2.01a) Functional Description Figure 1 illustrates the top-level block diagram for the XPS IIC Bus Interface module. X-Ref Target - Figure 1 PLB Interrupt Control ... | Original |
35 pages, |
DS516 PLBV46 PPC440 XC6VLX75T XC3SD1800A-FG676 microblaze block architecture XPS IIC XC6SLX16-CSG324 DS606 DS606 abstract |
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| Abstract: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IIC Diagnostics , . . . IIC Diagnostics Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IIC Diagnostics . . . . . . . , . . . . . . . . . . . . . IIC Diagnostics Menu . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . IIC Programming for the camera PCORE . . . . . . . . . . . . . ... | Original |
78 pages, |
schematic diagram video to vga DVD read writer circuit diagram vga camera module usb lcd 16x2 instruction set xilinx ch7301 circuit diagram of video wall microblaze command words lcd display 16x2 image sensor micron MT9V022 note 9V022 UG456 UG456 abstract |
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| Abstract: /documentation/ip_documentation/mpmc.pdf XPS Multi-CHannel External Memory Controller (XPS MCH EMC) DS575 DS575 / xps_mch_emc.pdf XPS LocalLink TEMAC DS537 DS537 XPS LocalLink FIFO DS568 DS568 Documentation · PLB v4.6 IP XPS IIC Bus Interface DS606 DS606 XPS ... | Original |
64 pages, |
microblaze locallink ML501 ML505 MT4HTF3264HY IDELAY DS643 ds573 XAPP1026 Xilinx Ethernet development ChipScope xilinx platform cable usb xilinx USB cable MT4HTF3264HY-53e ug086 ML501 abstract |
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| Abstract: 0x83600000 0x8360FFFF XPS GPIO LEDs_8Bit 0x81400000 0x8140FFFF XPS IIC IIC_Bus , block diagram of the reference system. X-Ref Target - Figure 1 XPS_LL TEMAC XPS_ SYSACE XPS_ INTC XPS_UART 16550 XPS GPIO PPC405 PPC405 XPS CENTRAL DMA XPS BRAM PLBv46 PCI XPS IIC MPMC X1001 X1001_01_010708 Figure 1: ML410 ML410 PLBv46 PCI Reference System Block Diagram The , , IIC, and GPIO. The modules are shown in Figure 1. The PCI Arbiter core is included in the FPGA. The ... | Original |
25 pages, |
104C PPC405 ALI chipset ML410 M1535D XAPP1001 xapp1001.zip datasheet ALi M1535D XC4VFX60 XC4VFX60 VIRTEX4 DEVELOPMENT BOARD ML555 Virtex4 uart datasheet Virtex4 XC4VFX60 ALi M1535D ML410 abstract |
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| Abstract: · XPS GPIO · XPS IIC Controller · XPS SYSACE Compact Flash Controller · MPMC , MPMC System ACE XPS IIC XPS IIC DDR2 Figure 4-1: Base Platform Block Diagram , demos in vsk_top.c: // Initialize the IIC cores vsk_iic_init(); // Initialize the Power Regulator to , handled by way of IIC PCOREs connected to the MicroBlaze. Note: Because the devices VSK I/O libraries , library for this PCORE uses IIC commands to configure these devices and associated logic. The primary ... | Original |
36 pages, |
ug514 576P50 AD9984 AD9984A ADV7180 CH7301 CH7301C DS610 MT9V022 SDTV TFP403 0x84400000 MT9V022 i2c microblaze UG514 UG514 UG514 abstract |
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| Abstract: :// н XPS Multi-CHannel External Memory Controller (XPS MCH EMC) н DS575 DS575 / xps_mch_emc.pdf н XPS LocalLink TEMAC н DS537 DS537 / xps_ll_temac.pdf Documentation PLB v4.6 IP н XPS LocalLink FIFO н DS568 DS568 / xps_ll_fifo.pdf н XPS IIC Bus Interface н DS606 DS606 http://www.xilinx.com/support ... | Original |
74 pages, |
MT4HTF3264HY UG193 UG196 application TEMAC ug198 ML506 DS444 ML50x DS614 UG086 XAPP1026 aspi-024-aspi-s402 VIRTEX-5 DDR2 controller VIRTEX-5 DDR2 xilinx mig user interface design ML505/506/507 ML505/506/507 abstract |
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| Abstract: :// XPS Multi-CHannel External Memory Controller (XPS MCH EMC) DS575 DS575 / xps_mch_emc.pdf XPS LocalLink TEMAC DS537 DS537 / xps_ll_temac.pdf Documentation PLB v4.6 IP XPS LocalLink FIFO DS568 DS568 / xps_ll_fifo.pdf XPS IIC Bus Interface DS606 DS606 http://www.xilinx.com/support ... | Original |
77 pages, |
UG086 UG196 UG198 DS583 MT9HTF6472Y-667 Virtex-5-datasheet virtex5 gtp WD2RE512X809 ds573 xilinx mig user interface design XILINX PCIE ML510 microblaze locallink VIRTEX-5 DDR2 ML510 abstract |
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| Abstract: SysACE_CompactFlash 0x83600000 0x8360FFFF XPS IIC IIC_Bus 0x81600000 0x8160FFFF Configuration of , system. X-Ref Target - Figure 1 XPS INTC MicroBlazeTM Processor XPS UARTLITE XPS BRAM CNTR PLBv46 XPS GPIO XPS CENTRAL DMA PLBv46 PCI MPMC X999_01_010308 Figure 1 , memory and UART, XPS Central DMA, MDM, GPIO, and an interrupt controller. The PCI Arbiter core is , Address LMB_BRAM_IF_CNTLR DLMB_CNTLR/ILMB_CN TLR 0x00000000 0x00001FFF XPS UartLite ... | Original |
19 pages, |
vhdl code for bram XC4VFX60 XAPP999 XAPP1001 ML410 pcie microblaze tcl script ModelSim ISE Virtex-5 LX50T XPS IIC Virtex 5 LX50T IPIF ML555 PLBv46 ML555 abstract |
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| Abstract: SysACE_CompactFlash 0x83600000 0x8360FFFF XPS IIC IIC_Bus 0x81600000 0x8160FFFF Avnet Spartan-3 , Specifics Figure 3 is a block diagram of the reference system. X-Ref Target - Figure 3 XPS INTC MicroBlazeTM Processor XPS UARTLITE XPS BRAM CNTR PLB XPS CENTRAL DMA PLBv46 PCI SRAM , BRAM memory, UART, MDM, XPS Central DMA, and interrupt controller. The PCI Arbiter core is included in , Base Address High Address LMB_BRAM DLMB_CNTLR/ILMB_CNTLR 0x00000000 0x00001FFF XPS ... | Original |
18 pages, |
0x83E0FFFF ML410 UART-16550 XAPP1001 XAPP1038 XC3S1000 XC3S1500 XC3S400 XCF04S xilinx jtag cable xc3s400 XC3S1500 SPARTAN-3 BOARD SPARTAN-3 XC3S400 pin SPARTAN-3 XC3S400 PLBv46 datasheet abstract |
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| Abstract: 0x8140FFFF XPS SysAce SysACE_CompactFlash 0x83600000 0x8360FFFF XPS IIC IIC_Bus , X-Ref Target - Figure 3 XPS INTC MicroBlazeTM Processor XPS UARTLITE XPS BRAM CNTR PLB XPS CENTRAL DMA PLBv46 PCI X1057 X1057_03_012408 Figure 3: RaggedStone1 Spartan-3 PLBv46 PCI , , XPS Central DMA, and interrupt controller. The PCI Arbiter core is included in the FPGA. , Address Map Peripheral Instance Base Address High Address XPS UART Lite RS232 RS232_Uart_1 ... | Original |
18 pages, |
XILINX SPARTAN XC3S1500 XC3S400 XC3S1500 XC3S1000 XAPP1057 ML410 AT49BV040A XPS IIC datasheet abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| the project files, for example from a xygwin shell: $ xps -nw system_linux.xmp XPS% run init either with the Base System Builder in XPS or all by hand you most likely will change the base addresses -Boot: $ xps -nw system_uboot.xmp XPS% run libs If all goes well the new configuration has been copied . 4. IIC Support - 1. The IIC commands are supported. 2. To enable this _PERSISTENT_0_IIC_0_BASEADDR can be used by U-Boot as part of its environemnt variables. 2. The MAC address www.datasheetarchive.com/download/49104857-995987ZC/xapp542.zip (README.ml300) |
Xilinx | 11/11/2004 | 9180.01 Kb | ZIP | xapp542.zip |
| _XIIC_NUM_INSTANCES 1 #define XPAR_OPB_IIC_0_BASEADDR 0xA8000000 #define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF #define XPAR_OPB_IIC_0_DEVICE_ID 0 #define XPAR_OPB_IIC_0_TEN_BIT_ADR 0 /*/ #define XPAR_XPS2_NUM_INSTANCES 2 #define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0 #define XPAR_OPB_PS2_DUAL _IRPT_INTR 1 #define 2 #define 3 #define 4 #define XPAR_DCR_INTC_0_OPB_SYSACE_0_SYSACE www.datasheetarchive.com/download/49104857-995987ZC/xapp542.zip (xparameters.h) |
Xilinx | 11/11/2004 | 9180.01 Kb | ZIP | xapp542.zip |
| _VEC_ID 11 /* Interrupt source for vector */ #define XPAR_INTC_0_IIC_0_VEC_ID 12 */ /* * * IIC defines. * DeviceID starts at 90 */ #define XPAR_XIIC_NUM_INSTANCES 2 /* Number of instances */ #define XPAR_IIC_0_DEVICE_ID 90 /* Device ID for instance */ #define XPAR_IIC_0_BASEADDR 0xA8000000 /* Device base address */ #define XPAR_IIC_0_TEN_BIT_ADR XTRUE /* Supports 10 bit addresses */ #define XPAR_IIC_1_DEVICE_ID 91 /* Device ID for instance www.datasheetarchive.com/download/49318403-996020ZC/xapp663.zip (xparameters.h) |
Xilinx | 23/08/2004 | 21918.22 Kb | ZIP | xapp663.zip |
| _VEC_ID 11 /* Interrupt source for vector */ #define XPAR_INTC_0_IIC_0_VEC_ID 12 */ /* * * IIC defines. * DeviceID starts at 90 */ #define XPAR_XIIC_NUM_INSTANCES 2 /* Number of instances */ #define XPAR_IIC_0_DEVICE_ID 90 /* Device ID for instance */ #define XPAR_IIC_0_BASEADDR 0xA8000000 /* Device base address */ #define XPAR_IIC_0_TEN_BIT_ADR XTRUE /* Supports 10 bit addresses */ #define XPAR_IIC_1_DEVICE_ID 91 /* Device ID for instance www.datasheetarchive.com/download/49318403-996020ZC/xapp663.zip (xparameters.h) |
Xilinx | 23/08/2004 | 21918.22 Kb | ZIP | xapp663.zip |
| XPAR_INTC_0_SPI_0_VEC_ID 11 /* Interrupt source for vector */ #define XPAR_INTC_0_IIC_0 */ /* * * IIC defines. * DeviceID starts at 90 */ #define XPAR_XIIC_NUM_INSTANCES 2 /* Number of instances */ #define XPAR_IIC_0_DEVICE_ID 90 /* Device ID for instance */ #define XPAR_IIC_0_BASEADDR 0xA8000000 /* Device base address */ #define XPAR_IIC_0_TEN_BIT_ADR XTRUE /* Supports 10 bit addresses */ #define XPAR_IIC_1_DEVICE_ID 91 /* Device ID for instance www.datasheetarchive.com/download/70640313-996021ZC/xapp669.zip (xparameters.h) |
Xilinx | 11/11/2004 | 301.07 Kb | ZIP | xapp669.zip |
| XPAR_INTC_0_SPI_0_VEC_ID 11 /* Interrupt source for vector */ #define XPAR_INTC_0_IIC_0 */ /* * * IIC defines. * DeviceID starts at 90 */ #define XPAR_XIIC_NUM_INSTANCES 2 /* Number of instances */ #define XPAR_IIC_0_DEVICE_ID 90 /* Device ID for instance */ #define XPAR_IIC_0_BASEADDR 0xA8000000 /* Device base address */ #define XPAR_IIC_0_TEN_BIT_ADR XTRUE /* Supports 10 bit addresses */ #define XPAR_IIC_1_DEVICE_ID 91 /* Device ID for instance www.datasheetarchive.com/download/70640313-996021ZC/xapp669.zip (xparameters.h) |
Xilinx | 11/11/2004 | 301.07 Kb | ZIP | xapp669.zip |
| _VEC_ID 11 /* Interrupt source for vector */ #define XPAR_INTC_0_IIC_0_VEC_ID 12 */ /* * * IIC defines. * DeviceID starts at 90 */ #define XPAR_XIIC_NUM_INSTANCES 2 /* Number of instances */ #define XPAR_IIC_0_DEVICE_ID 90 /* Device ID for instance */ #define XPAR_IIC_0_BASEADDR 0xA8000000 /* Device base address */ #define XPAR_IIC_0_TEN_BIT_ADR XTRUE /* Supports 10 bit addresses */ #define XPAR_IIC_1_DEVICE_ID 91 /* Device ID for instance www.datasheetarchive.com/download/40314210-995985ZC/xapp529_6_2.zip (xparameters.h) |
Xilinx | 26/03/2004 | 189.07 Kb | ZIP | xapp529_6_2.zip |
| XPAR_INTC_0_SPI_0_VEC_ID 11 /* Interrupt source for vector */ #define XPAR_INTC_0_IIC_0 */ /* * * IIC defines. * DeviceID starts at 90 */ #define XPAR_XIIC_NUM_INSTANCES 2 /* Number of instances */ #define XPAR_IIC_0_DEVICE_ID 90 /* Device ID for instance */ #define XPAR_IIC_0_BASEADDR 0xA8000000 /* Device base address */ #define XPAR_IIC_0_TEN_BIT_ADR XTRUE /* Supports 10 bit addresses */ #define XPAR_IIC_1_DEVICE_ID 91 /* Device ID for instance www.datasheetarchive.com/download/96886414-995984ZC/xapp529_6_1.zip (xparameters.h) |
Xilinx | 26/03/2004 | 97.7 Kb | ZIP | xapp529_6_1.zip |
| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.8 The IIC Bus Module .5.3.3 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 4 IIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.4.2 IIC Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.4.3 IIC Receive Transmit Buffer -23 4.8.1 Interfaces of the IIC Module www.datasheetarchive.com/files/infineon/mc_data/dave/products/xc167ci_v24.dip!/xc167ci/documents/xc167ci_pum_peripheral_v1.1_2002_12.pdf |
Infineon | 25/11/2003 | 10493 Kb | DIP | xc167ci_v24.dip |
| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.8 The IIC Bus Module .5.3.3 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 4 IIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.4.2 IIC Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.4.3 IIC Receive Transmit Buffer -23 4.8.1 Interfaces of the IIC Module www.datasheetarchive.com/files/infineon/mc_data/dave/products/xc167ci_v21.dip!/xc167ci/documents/xc167ci_pum_peripheral_v1.1_2002_12.pdf |
Infineon | 09/02/2004 | 10517.79 Kb | DIP | xc167ci_v21.dip |