XIO2000A SCPS155 M66EN - Datasheet Archive

 

Translation Bridge Data Manual Literature Number: SCPS155 January 12 2006 Printed on Recycled Paper IMPORTANT NOTICE Texas

 

XIO2000A XIO2000A PCI Express to PCI Bus Translation Bridge Data Manual Literature Number: SCPS155 SCPS155 January 12 2006 Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2005, Texas Instruments Incorporated Contents Section 1 2 3 Page XIO2000A XIO2000A Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Document Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Document History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Feature/Protocol Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Power-Up/-Down Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Bridge Reset Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 PCI Express Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 External Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Beacon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 Wake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4 Initial Flow Control Credits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.5 PCI Express Message Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Clamping Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 PCI Bus Clock Run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4 PCI Bus External Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.5 MSI Messages Generated from the Serial IRQ Interface . . . . . . . . . . . . . . . . . . . . . . 3.4.6 PCI Bus Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Quality of Service and Isochronous Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 PCI Port Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 PCI Isochronous Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.3 PCI Express Extended VC With VC Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.4 128-Phase, WRR PCI Port Arbitration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Configuration Register Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 PCI Interrupt Conversion to PCI Express Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 PME Conversion to PCI Express Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 PCI Express To PCI Bus Lock Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 Two-Wire Serial-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.1 Serial-Bus Interface Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.2 Serial-Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.3 Serial-Bus EEPROM Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.4 Accessing Serial-Bus Devices Through Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 Advanced Error Reporting Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.12 Data Error Forwarding Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13 General-Purpose I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14 Set Slot Power Limit Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15 PCI Express and PCI Bus Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . January 12 2006 SCPS155 SCPS155 1 2 2 2 2 3 3 3 4 8 15 15 15 16 17 18 18 19 19 19 19 20 20 20 21 21 22 23 23 24 25 26 27 28 29 30 31 32 33 33 35 37 37 37 38 38 38 iii Contents Section 4 iv Page Classic PCI Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 Class Code and Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 Primary Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10 Device Control Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11 Primary Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.12 Secondary Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13 Subordinate Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.14 Secondary Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.15 I/O Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16 I/O Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17 Secondary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.18 Memory Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.19 Memory Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.20 Prefetchable Memory Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.21 Prefetchable Memory Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.22 Prefetchable Base Upper 32-Bit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.23 Prefetchable Limit Upper 32-Bit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.24 I/O Base Upper 16-Bit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.25 I/O Limit Upper 16-Bit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.26 Capabilities Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.27 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.28 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.29 Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.30 Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.31 Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.32 Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.33 Power Management Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.34 Power Management Bridge Support Extension Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.35 Power Management Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.36 MSI Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.37 Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.38 MSI Message Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.39 MSI Message Lower Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.40 MSI Message Upper Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.41 MSI Message Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.42 Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.43 Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.44 Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.45 Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.46 PCI Express Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.47 Next Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCPS155 SCPS155 40 41 41 42 43 44 44 44 44 45 45 45 46 46 46 46 47 48 49 49 49 50 50 50 51 51 51 52 52 52 54 54 55 56 56 57 57 57 58 58 59 59 59 60 60 60 60 61 January 12 2006 Section 5 Page 4.48 PCI Express Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.49 Device Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.50 Device Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.51 Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.52 Link Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.53 Link Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.54 Link Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.55 Serial-Bus Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.56 Serial-Bus Word Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.57 Serial-Bus Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.58 Serial-Bus Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.59 GPIO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.60 GPIO Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.61 Control and Diagnostic Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.62 Control and Diagnostic Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.63 Control and Diagnostic Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.64 Subsystem Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.65 General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.66 Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.67 Clock Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.68 Clock Run Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.69 Arbiter Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.70 Arbiter Request Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.71 Arbiter Time-Out Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.72 Serial IRQ Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.73 Serial IRQ Edge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.74 Serial IRQ Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express Extended Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Advanced Error Reporting Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Next Capability Offset/Capability Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Uncorrectable Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Uncorrectable Error Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Uncorrectable Error Severity Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Correctable Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 Correctable Error Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 Advanced Error Capabilities and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9 Header Log Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10 Secondary Uncorrectable Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11 Secondary Uncorrectable Error Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.12 Secondary Uncorrectable Error Severity Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.13 Secondary Error Capabilities and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.14 Secondary Header Log Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.15 Virtual Channel Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.16 Next Capability Offset/Capability Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.17 Port VC Capability Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.18 Port VC Capability Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.19 Port VC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.20 Port VC Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . January 12 2006 SCPS155 SCPS155 61 62 63 64 65 66 67 67 67 68 69 70 71 72 73 74 74 75 77 78 79 80 81 82 83 84 85 87 88 88 89 90 91 92 93 94 94 95 96 97 98 99 99 100 100 101 102 102 v Contents Section 6 7 vi Page 5.21 VC Resource Capability Register (VC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.22 VC Resource Control Register (VC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.23 VC Resource Status Register (VC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.24 VC Resource Capability Register (VC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.25 VC Resource Control Register (VC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.26 VC Resource Status Register (VC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.27 VC Arbitration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.28 Port Arbitration Table (VC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory-Mapped TI Proprietary Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Device Control Map ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Upstream Isochrony Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Upstream Isochrony Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 Upstream Isochronous Window 0 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 Upstream Isochronous Window 0 Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7 Upstream Isochronous Window 0 Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8 Upstream Isochronous Window 1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9 Upstream Isochronous Window 1 Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10 Upstream Isochronous Window 1 Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11 Upstream Isochronous Window 2 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12 Upstream Isochronous Window 2 Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13 Upstream Isochronous Window 2 Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14 Upstream Isochronous Window 3 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.15 Upstream Isochronous Window 3 Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.16 Upstream Isochronous Window 3 Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17 GPIO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18 GPIO Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.19 Serial-Bus Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.20 Serial-Bus Word Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.21 Serial-Bus Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.22 Serial-Bus Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.23 Serial IRQ Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.24 Serial IRQ Edge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.25 Serial IRQ Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Absolute Maximum Ratings Over Operating Temperature Ranges . . . . . . . . . . . . . . . . . . . . . . . 7.2 Recommended Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 PCI Express Differential Transmitter Output Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 PCI Express Differential Receiver Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 PCI Express Differential Reference Clock Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 Electrical Characteristics Over Recommended Operating Conditions (PCI Bus) . . . . . . . . . . . 7.7 Electrical Characteristics Over Recommended Operating Conditions (3.3-V I/O) . . . . . . . . . . . 7.8 PCI Clock Timing Requirements Over Recommended Operating Conditions . . . . . . . . . . . . . . 7.9 PCI Bus Timing Requirements Over Recommended Operating Conditions . . . . . . . . . . . . . . . . 7.10 PCI Bus Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.11 PCI Bus Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCPS155 SCPS155 103 104 105 105 106 107 107 108 109 109 110 110 111 112 112 112 113 113 113 114 114 114 115 115 115 116 117 117 118 118 119 120 121 122 124 124 124 125 127 129 130 130 131 131 132 133 January 12 2006 Section 8 9 Page Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . January 12 2006 SCPS155 SCPS155 134 135 vii Figures List of Figures Figure 2-1 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 7-1 7-2 7-3 7-4 viii Page XIO2000A XIO2000A GZZ/ZZZ MicroStar BGATM Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . XIO2000A XIO2000A Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-State Bidirectional Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Type 0 Configuration Transaction Address Phase Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Type 1 Configuration Transaction Address Phase Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express Assert_INTx Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express Deassert_INTx Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express PME Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Starting A Locked Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuing A Locked Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Terminating A Locked Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial EEPROM Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial-Bus Start/Stop Conditions and Bit Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial-Bus Protocol Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial-Bus Protocol-Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial-Bus Protocol-Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial-Bus Protocol-Multibyte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load Circuit And Voltage Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLK Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PRST Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shared Signals Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCPS155 SCPS155 4 15 16 17 20 28 28 29 30 30 30 31 32 32 33 34 34 34 35 35 132 133 133 133 January 12 2006 List of Tables Table 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 Page XIO2000A XIO2000A GZZ/ZZZ Terminals Sorted Alphanumerically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XIO2000A XIO2000A Signal Names Sorted Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Combined Power Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI System Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Miscellaneous Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bridge Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initial Flow Control Credit Advertisements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Messages Supported by the Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Interrupt to MSI Message Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Classic PCI Arbiter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Number to PCI Bus Device Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128-Phase, WRR Time-Based Arbiter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Isochronous Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware-Fixed, Round-Robin Arbiter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-phase, WRR Arbiter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Type 0 Configuration Transaction IDSEL Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Mapping In The Code Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Register Loading Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers Used To Program Serial-Bus Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocking In Low Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Classic PCI Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class Code and Revision ID Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Control Base Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Base Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Limit Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Secondary Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Base Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Limit Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Prefetchable Memory Base Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Prefetchable Memory Limit Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Prefetchable Base Upper 32-Bit Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Prefetchable Limit Upper 32-Bit Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Base Upper 16-Bit Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Limit Upper 16-Bit Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bridge Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Capabilities Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Control/Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management Bridge Support Extension Register Description . . . . . . . . . . . . . . . . . . . . . . . . MSI Message Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSI Message Lower Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . January 12 2006 SCPS155 SCPS155 5 7 9 9 9 10 10 11 12 13 18 19 20 22 24 24 25 25 26 27 29 30 36 37 39 40 42 43 44 45 46 47 48 49 49 49 50 50 50 51 51 52 55 56 56 58 58 ix Tables Table 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 4-34 4-35 4-36 4-37 4-38 4-39 4-40 4-41 4-42 4-43 4-44 4-45 4-46 4-47 4-48 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 5-22 x Page MSI Message Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express Capabilities Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Capabilities Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Link Capabilities Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Link Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Link Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial-Bus Slave Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial-Bus Control and Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control and Diagnostic Register 0 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control and Diagnostic Register 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control and Diagnostic Register 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Subsystem Access Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Run Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arbiter Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arbiter Request Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arbiter Time-Out Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial IRQ Mode Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial IRQ Edge Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial IRQ Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Express Extended Configuration Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Uncorrectable Error Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Uncorrectable Error Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Uncorrectable Error Severity Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Correctable Error Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Correctable Error Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Advanced Error Capabilities and Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Secondary Uncorrectable Error Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Secondary Uncorrectable Error Mask Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Secondary Uncorrectable Error Severity Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Secondary Error Capabilities and Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Secondary Header Log Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port VC Capability Register 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port VC Capability Register 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port VC Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port VC Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VC Resource Capability Register (VC0) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VC Resource Control Register (VC0) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VC Resource Status Register (VC0) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VC Resource Capability Register (VC1) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VC Resource Control Register (VC1) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VC Resource Status Register (VC1) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SCPS155 SCPS155 59 61 62 63 64 65 66 67 68 69 70 71 72 73 74 74 75 77 78 79 80 81 82 83 84 85 87 89 90 91 92 93 94 95 96 97 98 99 100 101 102 102 103 104 105 105 106 107 January 12 2006 Table 5-23 5-24 5-25 5-26 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 Page VC Arbitration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VC Arbitration Table Entry Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Arbitration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port Arbitration Table Entry Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Control Memory Window Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Upstream Isochronous Capabilities Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Upstream Isochrony Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Upstream Isochronous Window 0 Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Upstream Isochronous Window 1 Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Upstream Isochronous Window 2 Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Upstream Isochronous Window 3 Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Data Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial-Bus Slave Address Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial-Bus Control and Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial IRQ Mode Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial IRQ Edge Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial IRQ Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . January 12 2006 SCPS155 SCPS155 107 107 108 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 xi Tables (This page has been left blank intentionally.) xii SCPS155 SCPS155 January 12 2006 Features 1 XIO2000A XIO2000A Features D Full x1 PCI Express Throughput D Fully Compliant with PCI Express to D D D D D D D D D D D D PCI/PCI-X Bridge Specification, Revision 1.0 Fully Compliant with PCI Express Base Specification, Revision 1.0a Fully Compliant with PCI Local Bus Specification, Revision 2.3 Extended Virtual Channel (VC) Support Includes a Second VC for Quality-of-Service and Isochronous Applications PCI Express Advanced Error Reporting Capability Including ECRC Support Support for D1, D2, D3hot, and D3cold Active State Link Power Management Saves Power When Packet Activity on the PCI Express Link is Idle, Using Both L0s and L1 States Wake Event and Beacon Support Error Forwarding Including PCI Express Data Poisoning and PCI Bus Parity Errors Utilizes 100-MHz Differential PCI Express Common Reference Clock or 125-MHz Single-Ended, Reference Clock Robust Pipeline Architecture To Minimize Transaction Latency Full PCI Local Bus 66-MHz/32-Bit Throughput Support for Six Subordinate PCI Bus Masters with Internal Configurable, 2-Level Prioritization Scheme D Advanced VC Arbitration Options Include D D D D D D D D D D D D VC1 Strict Priority, Hardware-Fixed Round-Robin, and 32-Phase, Weighted Round-Robin Advanced PCI Bus Port Arbitration Options Include 128-phase, Weighted Round-Robin Time-Based and 128-phase, Weighted Round-Robin Aggressive Time-Based Advanced PCI Isochronous Windows for Memory Space Mapping to a Specified Traffic Class Advanced PCI Express Message Signaled Interrupt Generation for Serial IRQ Interrupts from CardBus Applications External PCI Bus Arbiter Option PCI Bus LOCK Support Clock Run and Power Override Support Six Buffered PCI Clock Outputs (33 MHz or 66 MHz) PCI Bus Interface 3.3-V and 5.0-V (33 MHz only at 5.0 V) Tolerance Options Integrated AUX Power Switch Drains VAUX Power Only When Main Power Is Off Eight 3.3-V, Multifunction, General-Purpose I/O Terminals Memory-Mapped EEPROM Serial-Bus Controller Supporting PCI Express Power Budget/Limit Extensions for Add-In Cards Compact Footprint, 201-Ball, GZZ MicroStarTM BGA or Lead-Free 201-Ball, ZZZ MicroStarTM BGA Table 1-1. Figure 1-1. MicroStar BGA is a trademark of Texas Instruments. Other trademarks are the property of their respective owners. January 12 2006 SCPS155 SCPS155 1 Introduction 2 Introduction The Texas Instruments XIO2000A XIO2000A is a PCI Express to PCI local bus translation bridge that provides full PCI Express and PCI local bus functionality and performance. 2.1 Description The XIO2000A XIO2000A is a single-function PCI Express to PCI translation bridge that is fully compliant to the PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. For downstream traffic, the bridge simultaneously supports up to eight posted and four nonposted transactions for each enabled virtual channel (VC). For upstream traffic, up to six posted and four nonposted transactions are simultaneously supported for each VC. The PCI Express interface is fully compliant to the PCI Express Base Specification, Revision 1.0a. The PCI Express interface supports a x1 link operating at full 250 MB/s packet throughput in each direction simultaneously. Two independent VCs are supported. The second VC is optimized for isochronous traffic types and quality-of-service (QoS) applications. Also, the bridge supports the advanced error reporting capability including extended CRC (ECRC) as defined in the PCI Express Base Specification. Supplemental firmware or software is required to fully utilize both of these features. Robust pipeline architecture is implemented to minimize system latency across the bridge. If parity errors are detected, then packet poisoning is supported for both upstream and downstream operations. The PCI local bus is fully compliant with the PCI Local Bus Specification (Revision 2.3) and associated programming model. Also, the bridge supports the standard PCI-to-PCI bridge programming model. The PCI bus interface is 32-bit and can operate at either 33 MHz or 66 MHz. Also, the PCI interface provides fair arbitration and buffered clock outputs for up to 6 subordinate devices. The bridge has advanced VC arbitration and PCI port arbitration features for upstream traffic. When these arbitration features are fully utilized, bridge throughput performance may be tuned for a variety of complex applications. Power management (PM) features include active state link PM, PME mechanisms, the beacon and wake protocols, and all conventional PCI D-states. If the active state link PM is enabled, then the link automatically saves power when idle using the L0s and L1 states. PM active state NAK, PM PME, and PME-to-ACK messages are supported. Standard PCI bus power management features provide several low power modes, which enable the host system to further reduce power consumption. The bridge has additional capabilities including, but not limited to, serial IRQ with MSI messages, serial EEPROM, power override, clock run, and PCI bus LOCK. Also, eight general-purpose inputs and outputs (GPIOs) are provided for further system control and customization. 2.2 Related Documents · · · · · · · · · 2.3 Trademarks · · · 2 PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0 PCI Express Base Specification, Revision 1.0a PCI Express Card Electromechanical Specification, Revision 1.0a PCI Local Bus Specification, Revision 2.3 PCI-to-PCI Bridge Architecture Specification, Revision 1.2 PCI Bus Power Management Interface Specification, Revision 1.1 or 1.2 PCI Mobile Design Guide, Revision 1.1 Serialized IRQ Support for PCI Systems, Revision 6.0 PCI Express Jitter and BER White Paper PCI Express is a trademark of PCI-SIG TI and MicroStar BGA are trademarks of Texas Instruments Other trademarks are the property of their respective owners SCPS155 SCPS155 January 12 2006 Introduction 2.4 Document Conventions Throughout this data manual, several conventions are used to convey information. These conventions are listed below: 1. To identify a binary number or field, a lower case b follows the numbers. For example: 000b is a 3-bit binary field. 2. To identify a hexadecimal number or field, a lower case h follows the numbers. For example: 8AFh is a 12-bit hexadecimal field. 3. All other numbers that appear in this document that do not have either a b or h following the number are assumed to be decimal format. 4. If the signal or terminal name has a bar above the name (for example, GRST), then this indicates the logical NOT function. When asserted, this signal is a logic low, 0, or 0b. 5. Differential signal names end with P, N, +, or - designators. The P or + designators signify the positive signal associated with the differential pair. The N or - designators signify the negative signal associated with the differential pair. 6. RSVD indicates that the referenced item is reserved. 7. The power and ground signals in Figure 2-1 are not subscripted to aid in readability. 8. In Sections 4 through 6, the configuration space for the bridge is defined. For each register bit, the software access method is identified in an access column. The legend for this access column includes the following entries: r ­ read access by software u ­ updates by the bridge internal hardware w ­ write access by software c ­ clear an asserted status bit with a write-back of 1b by software 2.5 Document History REVISION DATE REVISION NUMBER REVISION COMMENTS 05/2004 - Product preview 08/2005 A Initial release 2.6 Ordering Information ORDERING NUMBER NAME VOLTAGE PACKAGE XIO2000A XIO2000A PCI-Express to PCI Bridge 3.3-V, 5.0-V tolerant PCI bus I/Os with 3.3-V and 1.5-V power terminals 201-terminal GZZ MicroStar PBGA XIO2000A XIO2000A PCI-Express to PCI Bridge 3.3-V, 5.0-V tolerant PCI bus I/Os with 3.3-V and 1.5-V power terminals 201-terminal ZZZ (Lead-Free) MicroStar PBGA January 12 2006 SCPS155 SCPS155 3 Introduction 2.7 Terminal Assignments The XIO2000A XIO2000A is packaged in a 201-ball GZZ/ZZZ MicroStarTM BGA. Figure 2-1 is a terminal diagram of the GZZ/ZZZ package and Table 2-1 lists the terminals sorted alphanumerically. Table 2-2 lists the terminals in alphanumerical order. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GPIO3 GPIO6 GPIO7 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD VDD_33 RSVD RSVD RSVD RSVD VSS VSS VSS VSS VDD_33 VSS VDD_33 VDD_33 VDD_33 17 GPIO1 // U INTC PRST LOCK PWR_ OVRD GPIO5 // GPIO0 // T INTB R M66EN M66EN P AD30 AD31 CLK N AD28 AD29 M AD26 AD27 L AD23 INTD SERIRQ GPIO2 RSVD SDA CLKRUN GPIO4 // INTA VSS VDD_33 VSS RSVD VSS VDD_15 RSVD RSVD VSS RSVD RSVD GRST VDD_33 PME WAKE SCL VDD_15 VDD_15 _COMB VDD_33 REF0_ AD24 AD25 VSS VSS VSS VSS _COMB VSS REF1_ PCIE C/BE[3] PCIE VSSA IO VDD_33 VCCP H C/BE[2] G FRAME F DEVSEL E SERR PAR C/BE[1] AD15 VSS C AD14 B AD12 VDDA_ 15 VDD_33 D _COMB 15 J VDD_33 33 VDDA_ AD20 VDDA_ _AUX K AD21 AD19 AD22 AD18 VSS VSS VDD_15 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSA PERST TXN TXP VSSA VSS VDD_ AD17 AD16 VDD_33 VSS VSS VSS VSS VSS VSSA 15 VDDA_ IRDY TRDY VSS VSS VSS VSS VSS VSS VSSA 15 VDDA_ STOP PERR VSSA VSSA 15 VSSA RXN RXP RSVD RSVD VDDA_ AD3 VSS VDD_15 VDD_33 VSS 33 CLK AD13 AD8 VSS VDD_33 AD2 REF REQ2 GNT3 GNT4 VDD_33 CLK C/BE[0] AD7 AD5 AD1 CLK OUT1 AD10 OUT2 GNT1 GNT2 REQ0 CLK REQ4 CLK AD11 1 2 AD9 3 VCCP 4 AD6 5 AD4 6 AD0 7 GNT0 8 9 10 CLKRUN _EN REQ5 CLK OUT4 OUT5 11 12 13 VSSA CLK OUT3 A CLK+ VSS OUT6 REQ3 REF CLK- REQ1 OUT0 EXT_ REFCLK ARB_EN _SEL 15 16 GNT5 14 17 Figure 2-1. XIO2000A XIO2000A GZZ/ZZZ MicroStar BGA Package (Bottom View) 4 SCPS155 SCPS155 January 12 2006 Introduction Table 2-1. XIO2000A XIO2000A GZZ/ZZZ Terminals Sorted Alphanumerically BGA BALL # SIGNAL NAME BGA BALL # SIGNAL NAME BGA BALL # SIGNAL NAME A02 AD11 C17 REFCLK+ H10 VSS VSS A03 AD9 D01 C/BE[1] H11 A04 VCCP AD6 D02 AD15 H14 A05 D03 H15 VDD_15 VSSA A06 AD4 D07 VSS AD3 H16 TXN A07 AD0 D08 H17 TXP A08 GNT0 D09 VSS VDD_15 J01 A09 GNT1 D10 J02 VCCP AD19 A10 GNT2 D11 VDD_33 VSS J03 AD18 VDD_15 VSS A11 CLKOUT3 D15 CLKOUT4 D16 VDDA_33 RSVD J04 A12 A13 CLKOUT5 D17 RSVD J08 A14 GNT5 E01 SERR J09 A15 EXT_ARB_EN E02 PAR J10 A16 REFCLK_SEL E03 J11 B01 AD12 E15 VDD_33 VSSA J14 B03 AD10 E16 RXN J15 B04 C/BE[0] E17 RXP J16 B05 AD7 F01 DEVSEL J17 VSSA PERST B06 AD5 F02 STOP K01 AD20 B07 AD1 F03 PERR K02 AD21 B08 REQ0 F15 K03 AD22 B09 CLKOUT1 F16 VSSA VSSA K04 B10 CLKOUT2 F17 K07 VSS VSS B11 REQ3 G01 VDDA_15 FRAME B12 REQ4 G02 IRDY K09 B13 REQ5 G03 TRDY K10 B14 CLKOUT6 G04 B15 CLKRUN_EN G07 VSS VSS K14 B17 VSSA AD14 G08 C01 C02 AD13 G10 C04 AD8 G11 C05 G14 C06 VSS VDD_33 C07 AD2 G16 C08 CLKOUT0 C09 REQ1 C10 C11 J07 K08 K11 VSS VSS VSS VSS VDDA_15 VDDA_15 VSS VSS VSS VSS VDD_33_AUX VDDA_33 VSS VSS K15 VSS VSS K17 VDD_33_COMB VSS L01 AD23 VSSA VDDA_15 L02 C/BE[3] L03 AD24 L04 AD25 G17 VSSA VSS L07 H01 C/BE[2] L08 VSS VSS REQ2 H02 AD17 L09 GNT3 H03 AD16 L10 C12 GNT4 H04 L11 C13 H07 C14 VDD_33 VSS VDD_33 VSS C16 REFCLK- H09 January 12 2006 G09 G15 H08 VSS VSS K16 L14 L15 L16 VSS VSS VSS VDD_33_COMBIO VSSA REF0_PCIE SCPS155 SCPS155 5 Introduction Table 2-1. XIO2000A XIO2000A GZZ/ZZZ Terminals Sorted Alphanumerically (Continued) BGA BALL # SIGNAL NAME BGA BALL # SIGNAL NAME BGA BALL # SIGNAL NAME L17 REF1_PCIE P17 RSVD T09 RSVD M01 AD26 R01 M66EN M66EN T10 RSVD M02 AD27 R02 INTA T11 RSVD M03 R04 VSS VDD_33 T12 RSVD M15 VDD_33 PME T13 M16 WAKE R06 T14 M17 R07 T15 RSVD N01 VDD_15_COMB AD28 VSS GPIO4 // SCL VDD_33 RSVD R08 RSVD T17 RSVD N02 AD29 R09 RSVD U02 INTC N03 R10 VSS VSS U03 PRST N15 VSS RSVD U04 LOCK N16 RSVD R12 U05 GPIO1 // PWR_OVRD N17 GRST R13 VSS VSS U06 GPIO3 P01 AD30 R14 U07 GPIO6 P02 AD31 R16 VDD_33 RSVD U08 GPIO7 P03 CLK R17 RSVD VDD_15 VSS T01 VSS INTB U09 P07 U10 RSVD T03 INTD U11 RSVD VDD_33 VDD_33 T04 SERIRQ U12 RSVD T05 GPIO0 // CLKRUN U13 RSVD VDD_33 VDD_15 T06 GPIO2 U14 RSVD P15 T07 GPIO5 // SDA U15 RSVD P16 RSVD T08 RSVD U16 RSVD P08 P09 P10 P11 6 SCPS155 SCPS155 R05 R11 January 12 2006 Introduction Table 2-2. XIO2000A XIO2000A Signal Names Sorted Alphabetically SIGNAL NAME BGA BALL # SIGNAL NAME BGA BALL # SIGNAL NAME BGA BALL # AD0 A07 CLKRUN_EN B15 RSVD N15 AD1 B07 DEVSEL F01 RSVD N16 AD2 C07 EXT_ARB_EN A15 RSVD P16 AD3 D07 FRAME G01 RSVD P17 AD4 A06 GNT0 A08 RSVD R08 AD5 B06 GNT1 A09 RSVD R09 AD6 A05 GNT2 A10 RSVD R16 AD7 B05 GNT3 C11 RSVD T08 AD8 C04 GNT4 C12 RSVD T09 AD9 A03 GNT5 A14 RSVD T10 AD10 B03 GPIO0 // CLKRUN T05 RSVD T11 AD11 A02 GPIO1 // PWR_OVRD U05 RSVD T12 AD12 B01 GPIO2 T06 RSVD T14 AD13 C02 GPIO3 U06 RSVD T15 AD14 C01 GPIO4 // SCL R07 RSVD T17 AD15 D02 GPIO5 // SDA T07 RSVD U09 AD16 H03 GPIO6 U07 RSVD U10 AD17 H02 GPIO7 U08 RSVD U11 AD18 J03 GRST N17 RSVD U12 AD19 J02 INTA R02 RSVD U13 AD20 K01 INTB T01 RSVD U14 AD21 K02 INTC U02 RSVD U15 AD22 K03 INTD T03 RSVD U16 AD23 L01 IRDY G02 RXN E16 AD24 L03 LOCK U04 RXP E17 AD25 L04 M66EN M66EN R01 SERIRQ T04 AD26 M01 PAR E02 SERR E01 AD27 M02 PERR F03 STOP F02 AD28 N01 PERST J17 TRDY G03 AD29 N02 PME M15 TXN H16 AD30 P01 PRST U03 TXP H17 AD31 P02 REF0_PCIE L16 B04 REF1_PCIE L17 VCCP VCCP A04 C/BE[0] C/BE[1] D01 REFCLK- C16 H01 REFCLK_SEL A16 VDD_15 VDD_15 D09 C/BE[2] C/BE[3] L02 REFCLK+ C17 J04 CLK P03 REQ0 B08 VDD_15 VDD_15 CLKOUT0 C08 REQ1 C09 CLKOUT1 B09 REQ2 C10 CLKOUT2 B10 REQ3 B11 CLKOUT3 A11 REQ4 B12 CLKOUT4 A12 REQ5 B13 CLKOUT5 A13 RSVD CLKOUT6 B14 RSVD January 12 2006 VDD_15 VDD_15_COMB J01 H14 P07 P15 M17 VDD_33 VDD_33 C06 D10 D16 VDD_33 VDD_33 D17 VDD_33 H04 C13 E03 SCPS155 SCPS155 7 Introduction Table 2-2. XIO2000A XIO2000A Signal Names Sorted Alphabetically (Continued) SIGNAL NAME BGA BALL # VDD_33 VDD_33 M03 VDD_33 VDD_33 P10 VDD_33 VDD_33 R05 VDD_33 VDD_33_AUX T13 P09 P11 R14 VDD_33_COMB VDD_33_COMBIO VDDA_15 VDDA_15 K14 K16 L14 F17 G15 VDDA_15 VDDA_15 J14 VDDA_33 VDDA_33 D15 VSS VSS C05 VSS VSS D03 VSS VSS D11 VSS 2.8 J15 K15 SIGNAL NAME BGA BALL # VSS VSS G08 VSS VSS G10 VSS VSS G17 VSS VSS H08 VSS VSS H10 VSS VSS J07 VSS VSS J09 VSS VSS G09 G11 H07 H09 H11 J08 J10 J11 K04 VSS VSS K07 VSS VSS K09 K11 G04 VSS VSS G07 VSS C14 D08 K08 K10 SIGNAL NAME BGA BALL # VSS VSS L08 VSS VSS L10 VSS VSS N03 VSS VSS R04 VSS VSS R10 VSS VSS R12 VSS VSSA R17 VSSA VSSA E15 VSSA VSSA F16 VSSA VSSA L09 L11 P08 R06 R11 R13 B17 F15 G14 G16 H15 K17 VSSA VSSA L15 J16 L07 WAKE M16 Terminal Descriptions Table 2-3 through Table 2-10 give a description of the terminals. These terminals are grouped in tables by functionality. Each table includes the terminal name, terminal number, I/O type, and terminal description. The following list describes the different input/output cell types that appear in the terminal description tables: · · · · · · · · 8 HS DIFF IN = High speed differential input. HS DIFF OUT = High speed differential output. PCI BUS = PCI bus 3-state bidirectional buffer with 3.3-V or 5.0-V clamp rail. LV CMOS = 3.3-V low voltage CMOS input or output with 3.3-V clamp rail. BIAS = Input/output terminals that generate a bias voltage to determine a driver's operating current. Feed through = these terminals connect directly to macros within the part and not through an input or output cell. PWR = Power terminal GND = Ground terminal SCPS155 SCPS155 January 12 2006 Introduction Table 2-3. Power Supply Terminals BALL I/O TYPE EXTERNAL PARTS A04, J01 PWR Bypass capacitors 5.0-V or 3.3-V PCI bus clamp voltage to set maximum I/O voltage tolerance of the secondary PCI bus signals VDD_15 D09, H14, J04, P07, P15 PWR Bypass capacitors 1.5-V digital core power terminals VDDA_15 F17, J14, J15, G15 PWR Pi filter VDD_33 C06, C13, D10, E03, H04, M03, P09, P10, P11, R05, R14, T13 PWR Bypass capacitors K14 PWR Bypass capacitors D15, K15 PWR Pi filter SIGNAL VCCP VDD_33_AUX VDDA_33 DESCRIPTION 1.5-V analog power terminal 3.3-V digital I/O power terminals 3.3-V auxiliary power terminal Note: This terminal is connected to VSS through a pulldown resistor if no auxiliary supply is present. 3.3-V analog power terminal Table 2-4. Ground Terminals BALL I/O TYPE VSS C05, C14, D03, D08, D11, G04, G17, K04, K17, N03, P08, R04, R06, R10, R11, R12, R13, R17 GND Digital ground terminals VSS G07, G08, G09, G10, G11, H07, H08, H09, H10, H11, J07, J08, J09, J10, J11, K07, K08, K09, K10, K11, L07, L08, L09, L10, L11 GND Ground terminals for thermally-enhanced package B17, E15, F15, F16, G14, G16, H15, J16, L15 GND Analog ground terminal SIGNAL VSSA DESCRIPTION Table 2-5. Combined Power Outputs SIGNAL VDD_15_COMB VDD_33_COMB VDD_33_COMBIO BALL I/O TYPE EXTERNAL PARTS M17 Feed through Bypass capacitors Feed through Bypass capacitors Feed through Bypass capacitors K16 L14 DESCRIPTION Internally-combined 1.5-V main and VAUX power output for external bypass capacitor filtering. Supplies all internal 1.5-V circuitry powered by VAUX. Caution: Do not use this terminal to supply external power to other devices. Internally-combined 3.3-V main and VAUX power output for external bypass capacitor filtering. Supplies all internal 3.3-V circuitry powered by VAUX. Caution: Do not use this terminal to supply external power to other devices. Internally-combined 3.3-V main and VAUX power output for external bypass capacitor filtering. Supplies all internal 3.3-V input/output circuitry powered by VAUX. Caution: Do not use this terminal to supply external power to other devices. January 12 2006 SCPS155 SCPS155 9 Introduction Table 2-6. PCI Express Terminals SIGNAL PERST BALL I/O TYPE CELL TYPE CLAMP RAIL EXTERNAL PARTS J17 I LV CMOS VDD_33_ COMBIO - DESCRIPTION PCI Express reset input. The PERST signal identifies when the system power is stable and generates an internal power on reset. Note: The PERST input buffer has hysteresis. REF0_PCIE REF1_PCIE L16 L17 I/O BIAS - External resistor External reference resistor + and - terminals for setting TX driver current. An external resistor is connected between terminals L16 and L17. RXP RXN E17 E16 DI HS DIFF IN VSS - High-speed receive pair. RXP and RXN comprise the differential receive pair for the single PCI Express lane supported. TXP TXN H17 H16 DO HS DIFF OUT VDD_15 Series capacitors High-speed transmit pair. TXP and TXN comprise the differential transmit pair for the single PCI Express lane supported. WAKE M16 O LV CMOS VDD_33_ COMBIO - Wake is an active low signal that is driven low to reactivate the PCI Express link hierarchy's main power rails and reference clocks. Note: Since WAKE is an open-drain output buffer, a system side pullup resistor is required. Table 2-7. Clock Terminals SIGNAL BALL I/O TYPE CELL TYPE CLAMP RAIL EXTERNAL PARTS VDD_33 Pullup or pulldown resistor VDD_33 - Reference clock. REFCLK+ and REFCLK- comprise the differential input pair for the 100-MHz system reference clock. For a single-ended, 125-MHz system reference clock, use the REFCLK+ input. Reference clock. REFCLK+ and REFCLK- comprise the differential input pair for the 100-MHz system reference clock. For a single-ended, 125-MHz system reference clock, attach a capacitor from REFCLK- to VSS. DESCRIPTION Reference clock select. This terminal selects the reference clock input. REFCLK_SEL A16 I LV CMOS REFCLK+ C17 DI HS DIFF IN VDD_33 Capacitor to VSS for single-ended mode VCCP - PCI clock input. This is the clock input to the PCI bus core. - PCI clock outputs. These clock outputs are used to clock the PCI bus. If the bridge PCI bus clock outputs are used, then CLKOUT6 must be connected to the CLK input. REFCLK- C16 DI HS DIFF IN CLK P03 I PCI Bus CLKOUT0 CLKOUT1 CLKOUT2 CLKOUT3 CLKOUT4 CLKOUT5 CLKOUT6 C08 B09 B10 A11 A12 A13 B14 O PCI Bus 10 SCPS155 SCPS155 VCCP 0 = 100-MHz differential common reference clock used. 1 = 125-MHz single-ended, reference clock used. January 12 2006 Introduction Table 2-8. PCI System Terminals BALL I/O TYPE CELL TYPE CLAMP RAIL EXTERNAL PARTS AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 P02 P01 N02 N01 M02 M01 L04 L03 L01 K03 K02 K01 J02 J03 H02 H03 D02 C01 C02 B01 A02 B03 A03 C04 B05 A05 B06 A06 D07 C07 B07 A07 I/O PCI Bus VCCP - PCI address data lines C/BE[3] C/BE[2] C/BE[1] C/BE[0] L02 H01 D01 B04 I/O PCI Bus VCCP - PCI command byte enables DEVSEL F01 I/O PCI Bus VCCP Pullup resistor per PCI spec PCI device select FRAME G01 I/O PCI Bus VCCP Pullup resistor per PCI spec PCI frame GNT5 GNT4 GNT3 GNT2 GNT1 GNT0 A14 C12 C11 A10 A09 A08 O PCI Bus VCCP - INTA INTB INTC INTD R02 T01 U02 T03 I PCI Bus VCCP Pullup resistor per PCI spec PCI interrupts A-D. These signals are interrupt inputs to the bridge on the secondary PCI bus. IRDY G02 I/O PCI Bus VCCP Pullup resistor per PCI spec PCI initiator ready SIGNAL January 12 2006 DESCRIPTION PCI grant outputs. These signals are used for arbitration when the PCI bus is the secondary bus and an external arbiter is not used. GNT0 is used as the REQ for the bridge when an external arbiter is used. SCPS155 SCPS155 11 Introduction Table 2-8. PCI System Terminals (Continued) BALL I/O TYPE CELL TYPE CLAMP RAIL EXTERNAL PARTS PAR E02 I/O PCI Bus VCCP - PCI bus parity PERR F03 I/O PCI Bus VCCP Pullup resistor per PCI spec PCI parity error PME M15 I LV CMOS VDD_33_ COMBIO Pullup resistor per PCI spec Note: The PME input buffer has hysteresis. VCCP If unused, a weak pullup resistor per PCI spec PCI request inputs. These signals are used for arbitration on the secondary PCI bus when an external arbiter is not used. REQ0 is used as the GNT for the bridge when an external arbiter is used. SIGNAL DESCRIPTION PCI power management event. This terminal may be used to detect PME events from a PCI device on the secondary bus. REQ5 REQ4 REQ3 REQ2 REQ1 REQ0 B13 B12 B11 C10 C09 B08 I PCI Bus PRST U03 O PCI Bus VCCP - SERR E01 I/O PCI Bus VCCP Pullup resistor per PCI spec PCI system error STOP F02 I/O PCI Bus VCCP Pullup resistor per PCI spec PCI stop TRDY G03 I/O PCI Bus VCCP Pullup resistor per PCI spec PCI target ready PCI reset. This terminal is an output to the secondary PCI bus. Table 2-9. Reserved Terminals BALL I/O TYPE RSVD N15, N16, P16, R08, T08, T10, T11, T12, T14, T15, T17, U09, U11, U12, U13, U14, U15, U16 O Reserved, do not connect to external signals. RSVD R16 I Must be connected to VDD_33. RSVD D16, D17, P17, R09, T09, U10 I Must be connected to VSS. SIGNAL 12 SCPS155 SCPS155 DESCRIPTION January 12 2006 Introduction Table 2-10. Miscellaneous Terminals SIGNAL BALL I/O TYPE CELL TYPE CLAMP RAIL EXTERNAL PARTS VDD_33 Optional pullup resistor DESCRIPTION Clock run enable CLKRUN_EN B15 I LV CMOS 0 = Clock run support disabled 1 = Clock run support enabled Note: The CLKRUN_EN input buffer has an internal active pulldown. External arbiter enable EXT_ARB_EN A15 I LV CMOS VDD_33 Optional pullup resistor 0 = Internal arbiter enabled 1 = External arbiter enabled Note: The EXT_ARB_EN input buffer has an internal active pulldown. GPIO0 // CLKRUN T05 I/O LV CMOS VDD_33 Optional pullup resistor General-purpose I/O 0/clock run. This terminal functions as a GPIO controlled by bit 0 (GPIO0_DIR) in the GPIO control register (see Section 4.59) or the clock run terminal. This terminal is used as clock run input when the bridge is placed in clock run mode. Note: In clock run mode, an external pullup resistor is required to prevent the CLKRUN signal from floating. Note: This terminal has an internal active pullup resistor. GPIO1 // PWR_OVRD U05 I/O LV CMOS VDD_33 - General-purpose I/O 1/power override. This terminal functions as a GPIO controlled by bit 1 (GPIO1_DIR) in the GPIO control register (see Section 4.59) or the power override output terminal. GPIO1 becomes PWR_OVRD when bits 22:20 (POWER_OVRD) in the general control register are set to 001b or 011b (see Section 4.65). Note: This terminal has an internal active pullup resistor. General-purpose I/O 2. This terminal functions as a GPIO controlled by bit 2 (GPIO2_DIR) in the GPIO control register (see Section 4.59). GPIO2 T06 I/O LV CMOS VDD_33 - Note: When PERST is deasserted, this terminal must be a 1b to enable the PCI Express 1.0a compatibility mode. Note: This terminal has an internal active pullup resistor. GPIO3 GPIO4 // SCL U06 R07 I/O I/O LV CMOS LV CMOS VDD_33 - General-purpose I/O 3. This terminal functions as a GPIO controlled by bit 3 (GPIO3_DIR) in the GPIO control register (see Section 4.59). Note: This terminal has an internal active pullup resistor. VDD_33 Optional pullup resistor GPIO4 or serial-bus clock. This terminal functions as serial-bus clock if a pullup resistor is detected on SDA. If a pulldown resistor is detected on SDA, this terminal functions as GPIO4. Note: In serial-bus mode, an external pullup resistor is required to prevent the SCL signal from floating. Note: This terminal has an internal active pullup resistor. GPIO5 // SDA GPIO6 GPIO7 January 12 2006 T07 U07 U08 I/O I/O I/O LV CMOS VDD_33 LV CMOS VDD_33 LV CMOS VDD_33 Pullup or Pulldown resistor - GPIO5 or serial-bus data. This terminal functions as serial-bus data if a pullup resistor is detected on SDA. If a pulldown resistor is detected on SDA, this terminal functions as GPIO5. Note: In serial-bus mode, an external pullup resistor is required to prevent the SDA signal from floating. General-purpose I/O 6. This terminal functions as a GPIO controlled by bit 6 (GPIO6_DIR) in the GPIO control register (see Section 4.59). Note: This terminal has an internal active pullup resistor. - General-purpose I/O 7. This terminal functions as a GPIO controlled by bit 7 (GPIO7_DIR) in the GPIO control register (see Section 4.59). Note: This terminal has an internal active pullup resistor. SCPS155 SCPS155 13 Introduction Table 2-10. Miscellaneous Terminals (Continued) SIGNAL GRST BALL N17 LOCK U04 I/O TYPE CELL TYPE CLAMP RAIL EXTERNAL PARTS I LV CMOS VDD_33_ COMBIO - I/O PCI Bus VCCP Pullup resistor per PCI spec VCCP Pullup resistor per PCI spec DESCRIPTION Global reset input. Asynchronously resets all logic in device, including sticky bits and power management state machines. Note: The GRST input buffer has both hysteresis and an internal active pullup. This terminal functions as PCI LOCK when bit 12 (LOCK_EN) is set in the general control register (see Section 4.65). Note: In lock mode, an external pullup resistor is required to prevent the LOCK signal from floating. 66-MHz mode enable M66EN M66EN SERIRQ 14 R01 T04 SCPS155 SCPS155 I I/O PCI Bus PCI Bus VCCP Pullup or pulldown resistor 0 = Secondary PCI bus and clock outputs operate at 33 MHz 1 = Secondary PCI bus and clock outputs operate at 66 MHz Note: If the PCI bus clock is always 33 MHz, then this terminal is connected to VSS. Serial IRQ interface. This terminal functions as a serial IRQ interface if a pullup is detected when PERST is deasserted. If a pulldown is detected, then the serial IRQ interface is disabled. January 12 2006 Feature/Protocol Descriptions 3 Feature/Protocol Descriptions This chapter provides a high-level overview of all significant device features. Figure 3-1 shows a simplified block diagram of the basic architecture of the PCI-Express to PCI Bridge. The top of the diagram is the PCI Express interface and the PCI bus interface is located at the bottom of the diagram. PCI Express Transmitter PCI Express Receiver Power Mgmt GPIO Configuration and Memory Register Clock Generator Reset Controller Serial EEPROM Serial IRQ PCI Bus Interface Figure 3-1. XIO2000A XIO2000A Block Diagram 3.1 Power-Up/-Down Sequencing The bridge contains both 1.5-V and 3.3-V power terminals. In addition, a VAUX supply exists to support the D3cold state. The clamping voltage (VCCP) can be either 3.3-V or 5.0-V, depending on the PCI bus interface requirements. The following power-up and power-down sequences describe how power is applied to these terminals. In addition, the bridge has three resets: PERST, GRST, and an internal power-on reset. These resets are fully described in Section 3.2. The following power-up and power-down sequences describe how PERST is applied to the bridge. The application of the PCI Express reference clock (REFCLK) is important to the power-up/-down sequence and is included in the following power-up and power-down descriptions. 3.1.1 Power-Up Sequence 1. Assert PERST to the device. 2. Apply 1.5-V and 3.3-V voltages. 3. Apply VCCP clamp voltage. 4. Apply a stable PCI Express reference clock. 5. To meet PCI Express specification requirements, PERST cannot be deasserted until the following two delay requirements are satisfied: - Wait a minimum of 100 µs after applying a stable PCI Express reference clock. The 100-µs limit satisfies the requirement for stable device clocks by the deassertion of PERST. - Wait a minimum of 100 ms after applying power. The 100-ms limit satisfies the requirement for stable power by the deassertion of PERST. January 12 2006 SCPS155 SCPS155 15 Feature/Protocol Descriptions See the power-up sequencing diagram in Figure 3-2. VDD_15 and VDDA_15 VDD_33 and VDDA_33 VCCP REFCLK PERST 100 µs 100 ms Figure 3-2. Power-Up Sequence 3.1.2 Power-Down Sequence 1. Assert PERST to the device. 2. Remove the reference clock. 3. Remove VCCP clamp voltage. 4. Remove 3.3-V and 1.5-V voltages. Please see the power-down sequencing diagram in Figure 3-3. If the VDD_33_AUX terminal is to remain powered after a system shutdown, then the bridge power-down sequence is exactly the same as shown in Figure 3-3. 16 SCPS155 SCPS155 January 12 2006 Feature/Protocol Descriptions VDD_15 and VDDA_15 VDD_33 and VDDA_33 VCCP REFCLK PERST Figure 3-3. Power-Down Sequence 3.2 Bridge Reset Features There are five bridge reset options that include internally-generated power-on reset, resets generated by asserting input terminals, and software-initiated resets that are controlled by sending a PCI Express hot reset or setting a configuration register bit. Table 3-1 identifies these reset sources and describes how the bridge responds to each reset. January 12 2006 SCPS155 SCPS155 17 Feature/Protocol Descriptions Table 3-1. Bridge Reset Options RESET OPTION XIO2000A XIO2000A FEATURE Bridge internally-generated power-on reset During a power-on cycle, the bridge asserts an internal reset and monitors the VDD_15_COMB (M17) terminal. When this terminal reaches 90% of the nominal input voltage specification, power is considered stable. After stable power, the bridge monitors the PCI Express reference clock (REFCLK) and waits 10 µs after active clocks are detected. Then, internal power-on reset is deasserted. When the internal power-on reset is asserted, all control registers, state machines, sticky register bits, and power management state machines are initialized to their default state. When GRST is asserted low, an internal power-on reset occurs. This reset is asynchronous and functions during both normal power states and VAUX power states. When GRST is asserted low, all control registers, state machines, sticky register bits, and power management state machines are initialized to their default state. Global reset input GRST (N17) RESET RESPONSE In addition, the bridge asserts PCI bus reset (PRST). In addition, the bridge asserts PCI bus reset (PRST). When the rising edge of GRST occurs, the bridge samples the state of all static control inputs and latches the information internally. If an external serial EEPROM is detected, then a download cycle is initiated. Also, the process to configure and initialize the PCI Express link is started. The bridge starts link training within 80 ms after GRST is deasserted. PCI Express reset input PERST (J17) This bridge input terminal is used by an upstream PCI Express device to generate a PCI Express reset and to signal a system power good condition. When PERST is asserted low, the bridge generates an internal PCI Express reset as defined in the PCI Express specification. When PERST transitions from low to high, a system power good condition is assumed by the bridge. Note: The system must assert PERST before power is removed, before REFCLK is removed, or before REFCLK becomes unstable. PCI Express training control hot reset The bridge responds to a training control hot reset received on the PCI Express interface. After a training control hot reset, the PCI Express interface enters the DL_DOWN state. When PERST is asserted low, all control register bits that are not sticky are reset. Within the configuration register maps, the sticky bits are indicated by the k symbol. Also, all state machines that are not associated with sticky functionality or VAUX power management are reset. In addition, the bridge asserts PCI bus reset (PRST). When the rising edge of PERST occurs, the bridge samples the state of all static control inputs and latches the information internally. If an external serial EEPROM is detected, then a download cycle is initiated. Also, the process to configure and initialize the PCI Express link is started. The bridge starts link training within 80 ms after PERST is deasserted. In the DL_DOWN state, all remaining configuration register bits and state machines are reset. All remaining bits exclude sticky bits and EEPROM loadable bits. All remaining state machines exclude sticky functionality, EEPROM functionality, and VAUX power management. Within the configuration register maps, the sticky bits are indicated by the k symbol and the EEPROM loadable bits are indicated by the symbol. In addition, the bridge asserts PCI bus reset (PRST). PCI bus reset PRST (U03) 3.3 System software has the ability to assert and deassert the PRST terminal on the secondary PCI bus interface. This terminal is the PCI bus reset. When bit 6 (SRST) in the bridge control register at offset 3Eh (see Section 4.29) is asserted, the bridge asserts the PRST terminal. A 0 in the SRST bit deasserts the PRST terminal. PCI Express Interface 3.3.1 External Reference Clock The bridge requires either a differential, 100-MHz common clock reference or a single-ended, 125-MHz clock reference. The selected clock reference must meet all PCI Express Electrical Specification requirements for frequency tolerance, spread spectrum clocking, and signal electrical characteristics. 18 SCPS155 SCPS155 January 12 2006 Feature/Protocol Descriptions If the REFCLK_SEL (A16) input is connected to VSS, then a differential, 100-MHz common clock reference is expected by the bridge. If the A16 terminal is connected to VDD_33, then a single-ended, 125-MHz clock reference is expected by the bridge. When the single-ended, 125-MHz clock reference option is enabled, the single-ended clock signal is connected to the REFCLK+ (C17) terminal. The REFCLK- (C16) terminal is connected to one side of an external capacitor with the other side of the capacitor connected to VSS. When using a single-ended reference clock, care must be taken to ensure interoperability from a system jitter standpoint. The PCI Express Base Specification does not ensure interoperability when using a differential reference clock commonly used in PC applications along with a single-ended clock in a noncommon clock architecture. System jitter budgets will have to be verified to ensure interoperability. See the PCI Express Jitter and BER White Paper from the PCI-SIG. 3.3.2 Beacon The bridge supports the PCI Express in-band beacon feature. Beacon is driven on the upstream PCI Express link by the bridge to request the reapplication of main power when in the L2 link state. To enable the beacon feature, bit 10 (BEACON_ENABLE) in the general control register at offset D4h is asserted. See Section 4.65, General Control Register, for details. If the bridge is in the L2 link state and beacon is enabled, when a secondary PCI bus device asserts PME, then the bridge outputs the beacon signal on the upstream PCI Express link. The beacon signal frequency is approximately 500 kHz ± 50% with a differential peak-to-peak amplitude of 500 mV and no de-emphasis. Once the beacon is activated, the bridge continues to send the beacon signal until main power is restored as indicated by PERST going inactive. At this time, the beacon signal is deactivated. 3.3.3 Wake The bridge supports the PCI Express sideband WAKE feature. WAKE is an active low signal driven by the bridge to request the reapplication of main power when in the L2 link state. Since WAKE is an open-collector output, a system-side pullup resistor is required to prevent the signal from floating. When the bridge is in the L2 link state and PME is received from a device on the secondary PCI bus, the WAKE signal is asserted low as a wakeup mechanism. Once WAKE is asserted, the bridge drives the signal low until main power is restored as indicated by PERST going inactive. At this time, WAKE is deasserted. 3.3.4 Initial Flow Control Credits The bridge flow control credits are initialized using the rules defined in the PCI Express Base Specification. Table 3-2 identifies the initial flow control credit advertisement for the bridge. The initial advertisement is exactly the same when a second virtual channel (VC) is enabled. Table 3-2. Initial Flow Control Credit Advertisements CREDIT TYPE INITIAL ADVERTISEMENT Posted request headers (PH) 8 Posted request data (PD) 128 Nonposted header (NPH) 4 Nonposted data (NPD) 4 Completion header (CPLH) 0 (infinite) Completion data (CPLD) 0 (infinite) 3.3.5 PCI Express Message Transactions PCI Express messages are both initiated and received by the bridge. Table 3-3 outlines message support within the bridge. January 12 2006 SCPS155 SCPS155 19 Feature/Protocol Descriptions Table 3-3. Messages Supported by the Bridge MESSAGE SUPPORTED BRIDGE ACTION Assert_INTx Yes Transmitted upstream Deassert_INTx Yes Transmitted upstream PM_Active_State_Nak Yes Received and processed PM_PME Yes Transmitted upstream PME_Turn_Off Yes Received and processed PME_TO_Ack Yes Transmitted upstream ERR_COR Yes Transmitted upstream ERR_NONFATAL Yes Transmitted upstream ERR_FATAL Yes Transmitted upstream Unlock Yes Received and processed Set_Slot_Power_Limit Yes Received and processed Hot plug messages No Discarded Advanced switching messages No Discarded Vendor defined type 0 No Unsupported request Vendor defined type 1 No Discarded All supported message transactions are processed per the PCI Express Base Specification. 3.4 PCI Bus Interface 3.4.1 I/O Characteristics Figure 3-4 shows a 3-state bi-directional buffer that represents the I/O cell design for the PCI bus. Section 7.6, Electrical Characteristics over Recommended Operating Conditions, provides the electrical characteristics of the PCI bus I/O cell. NOTE: The PCI bus interface on the bridge meets the ac specifications of the PCI Local Bus Specification. Additionally, PCI bus terminals (input or I/O) must be held high or low to prevent them from floating. VCCP Tied for Open Drain OE Pad Figure 3-4. 3-State Bidirectional Buffer 3.4.2 Clamping Voltage In the bridge, the PCI bus I/O drivers are powered from the VDD_33 power rail. Plus, the I/O driver cell is tolerant to input signals with 5.0-V peak-to-peak amplitudes. For PCI bus interfaces operating at 66 MHz, all devices are required to output only 3.3-V peak-to-peak signal amplitudes. For PCI bus interfaces operating at 33-MHz, devices may output either 3.3-V or 5.0-V peak-to-peak signal amplitudes. The bridge accommodates both signal amplitudes. Each PCI bus I/O driver cell has a clamping diode connected to the VCCP voltage rail that protects the cell from excessive input voltage. If the PCI signaling is 3.3-V, then VCCP (A04, J01) is connected to a 3.3-V power supply. If the PCI signaling is 5.0 V, then VCCP (A04, J01) is connected to a 5.0-V power supply. 20 SCPS155 SCPS155 January 12 2006 Feature/Protocol Descriptions The PCI bus signals attached to the VCCP clamping voltage are identified in the following list: · In Table 2-7, Clock Terminals, the terminal names include CLK and CLKOUT6:0. · In Table 2-8, PCI System Terminals, all terminal names except for PME · In Table 2-10, Miscellaneous Terminals, the terminal names include SERIRQ, M66EN M66EN, and LOCK. 3.4.3 PCI Bus Clock Run The bridge supports the clock run protocol as specified in the PCI Mobile Design Guide. When the clock run protocol is enabled, the bridge assumes the role of the central resource master. To enable the clock run function, terminal B15 (CLKRUN_EN) is asserted high. Then, terminal T05 (GPIO0) is enabled as the CLKRUN signal. An external pullup resistor must be provided to prevent the CLKRUN signal from floating. To verify the operational status of the PCI bus clocks, bit 0 (SEC_CLK_STATUS) in the clock run status register at offset DAh (see Section 4.68) is read. Since the bridge has several unique features associated with the PCI bus interface, the system designer must consider the following interdependencies between these features and the CLKRUN feature: 1. If the system designer chooses to generate the PCI bus clock externally, then the CLKRUN mode of the bridge must be disabled. The central resource function within the bridge only operates as a CLKRUN master and does not support the CLKRUN slave mode. 2. If the central resource function has stopped the PCI bus clocks, then the bridge still detects INTx state changes and will generate and send PCI Express messages upstream. 3. If the serial IRQ interface is enabled and the central resource function has stopped the PCI bus clocks, then any PCI bus device that needs to report an IRQ interrupt asserts CLKRUN to start the bus clocks. 4. When a PCI bus device asserts CLKRUN, the central resource function turns on PCI bus clocks for a minimum of 512 cycles. 5. If the serial IRQ function detects an IRQ interrupt, then the central resource function keeps the PCI bus clocks running until the IRQ interrupt is cleared by software. 6. If the central resource function has stopped the PCI bus clocks and the bridge receives a downstream transaction that is forwarded to the PCI bus interface, then the bridge asserts CLKRUN to start the bus clocks. 7. The central resource function is reset by PCI bus reset (PRST) assuring that clocks are present during PCI bus resets. 3.4.4 PCI Bus External Arbiter The bridge supports an external arbiter for the PCI bus. Terminal A15 (EXT_ARB_EN), when asserted high, enables the use of an external arbiter. When an external arbiter is enabled, GNT0 is connected to the external arbiter as the REQ for the bridge. Likewise, REQ0 is connected to the external arbiter as the GNT for the bridge. All internal port arbitration features are disabled when an external arbiter is enabled. 128-phase, weighted round-robin (WRR) time-based arbitration, bus parking, arbiter time-out, tier select, and request masking modes have no effect if an external arbiter is enabled. January 12 2006 SCPS155 SCPS155 21 Feature/Protocol Descriptions 3.4.5 MSI Messages Generated from the Serial IRQ Interface When properly configured, the bridge converts PCI