XE1431 XE1413 CX72303 XE1431IO77TR XE1431-BASED LFBGA72 - Datasheet Archive

 

Bluetooth® SoC VREGA RC Oscillator VREGD] Power Management VDDBAT VREF Memory VREG_OFF Boot Loader Bluetooth Sequencer MOSI

 

XE1431 XE1431 Bluetooth® SoC VREGA RC Oscillator VREGD] Power Management VDDBAT VREF Memory VREG_OFF Boot Loader Bluetooth Sequencer MOSI CPU NSS[4:0] RADIO SPI ROM SCK radio inputs Interface radio outputs MISO VMIC_P VMIC_N NRESET CODEC PA[7:0] GPIO/UART PB[7:0] Bluetooth Interface PA_OUTN Bluetooth Interface PA_OUTP Bluetooth WAKEUP Controller clocks XE1431 XE1431 Ultra low power Bluetooth® SoC solution with Embedded Host CPU for data and voice applications GENERAL DESCRIPTION KEY PRODUCT FEATURES ® · The XE1431 XE1431 is a Bluetooth System-on-Chip based on the Semtech Bluetooth Sequencer, which includes a fully programmable 8-bit application microcontroller, a high speed UART, SPI interface, RC oscillator, power management unit, and an on-chip voice CODEC. The purpose of the XE1431 XE1431 is to offer a very high level of integration requiring a minimum of external components to build complete voice and data applications while maintaining design flexibility. · · · · · · · · · · · This product has been designed for ultra low power consumption and cheap solutions. By combining the XE1431 XE1431 with a low power 2.4 GHz radio device such as the Semtech XE1413 XE1413 or CX72303 CX72303, an ultra low power Bluetooth wireless headset consuming less than 23mW @2.2V (HV3) can be built. System On Chip for Voice and Data, including the Bluetooth baseband, an application host MCU and a 15-bit audio linear Codec Fully integrated Bluetooth protocol stack up to the HCI, compliant to revision 1.1 Embedded 8-bit host microcontroller On-chip preamplifier and power amplifier Supports Class 1, Class 2 and Class 3 radio modules Minimum of external components required Small form factor 20 programmable GPIO's High speed UART On chip power management unit and RC oscillator Operating voltage range 2.2 to 3.6V Ultra low power consumption, typically below 15 mA @ 2.2V for ACL link, DM1, 115 kbit/s. APPLICATIONS · · · · · · Bluetooth cellphone headset Handsfree kit VoRF Computer accessories Cable replacement Wireless games ORDERING INFORMATION Part Number XE1431IO77TR XE1431IO77TR LF Rev 3 April 2006 Description Bluetooth SoC for voice and data applications www.semtech.com 1 XE1431 XE1431 Bluetooth® SoC Table of Contents 1 Application Information ­ XE1431-based System Level Block Diagram . 5 2 2.1 3 XE1431 XE1431 Pinout . 6 Pin description. 6 Detailed Functional Description . 9 3.1 Block Diagram . 9 3.2 Host Processor system . 11 3.2.1 CoolRISC 816 CPU. 11 3.2.2 Program memory. 11 3.2.3 Data memory. 12 3.3 Power Management Unit. 12 3.3.1 Features . 12 3.3.2 Register map . 12 3.3.3 Modes of operation . 13 3.3.4 Block diagram. 14 3.3.5 Regulators specifications, external components . 15 3.3.6 Battery End-Of-Life (EOL). 15 3.4 Reset controller . 16 3.4.1 Features . 16 3.4.2 Register map . 16 3.4.3 Power-On-Reset / Brownout detector . 16 3.4.4 Bus Error . 17 3.4.5 Watchdog . 17 3.4.6 Analog reset specifications . 18 3.5 Clock Distribution Unit . 18 3.5.1 Features . 18 3.5.2 Register map . 18 3.5.3 RC oscillator . 19 3.5.4 SLOW_CLOCK_IN. 20 3.5.5 SYS_CLOCK_IN . 20 3.5.6 Clock source selection . 20 3.5.7 RegSysMisc description. 21 3.5.8 Prescalers . 22 3.5.9 Codec and Bluetooth Sequencer clocks . 27 3.6 Interrupt controller . 27 3.6.1 Features . 27 3.6.2 Register map . 27 3.6.3 Operation. 29 3.7 Event controller . 30 3.7.1 Features . 30 3.7.2 Register map . 30 3.7.3 Operation. 31 3.8 Digital input port PA[7:0]. 31 3.8.1 Features . 31 3.8.2 Register map . 31 3.8.3 Block diagram. 33 3.8.4 Debounce mode . 33 3.8.5 Pull-ups/Snap-to-rail. 33 3.8.6 Interrupt sources . 34 3.8.7 Event sources. 34 3.8.8 Clock sources. 34 3.8.9 Reset sources . 35 3.9 Digital input/output port PB[7:0] . 35 3.9.1 Features . 35 © Semtech 2006 www.semtech.com 2 XE1431 XE1431 Bluetooth® SoC 3.9.2 Register map . 35 3.9.3 Multiplexing PB with other peripherals. 36 3.9.4 Port B digital capabilities . 37 3.10 Counters/Timers. 38 3.10.1 Features . 38 3.10.2 Register map . 38 3.10.3 General Operation Overview. 40 3.10.4 Clock selection . 40 3.10.5 Mode selection . 41 3.10.6 Counter / Timer mode . 42 3.10.7 PWM mode. 43 3.10.8 Counter capture function. 44 3.11 Serial Peripheral Interface (SPI) . 45 3.11.1 Features . 45 3.11.2 Register map . 45 3.11.3 Operation. 46 3.11.4 Software hints. 48 3.11.5 Pins . 49 3.12 Application UART . 49 3.12.1 Features . 49 3.12.2 Registers map . 50 3.12.3 Block diagram. 51 3.12.4 Configuration . 52 3.12.5 Baud rates . 52 3.12.6 Transmission . 53 3.12.7 Reception . 54 3.12.8 Flow control . 55 3.12.9 Software hints. 56 3.13 Bluetooth Sequencer Interface. 56 3.13.1 Features . 56 3.13.2 Overview . 56 3.13.3 Link Controller Features. 58 3.13.4 Link Manager Features . 58 3.13.5 Standard Host Controller Interface (HCI) Commands . 58 3.13.6 Vendor Specific HCI Commands ­ "EasyBlueTM Commands". 61 3.13.7 Radio Interface . 62 3.13.8 HCI UART . 62 3.13.9 Bluetooth Sequencer clock source . 63 3.14 Audio CODEC . 63 3.14.1 Features . 63 3.14.2 Register map . 63 3.14.3 Block diagram. 66 3.14.4 CODEC clock source . 67 3.14.5 Specifications . 68 3.14.6 Microphone input. 69 3.14.7 Speaker output . 69 3.15 Debug Interface. 71 3.15.1 Description . 71 3.15.2 Register map . 71 3.15.3 Pins mapping. 72 3.15.4 Configuration . 73 3.15.5 Configuration Examples . 74 3.16 Development / Debug On Chip . 74 4 Electrical Specifications . 75 4.1 Absolute Maximum Ratings . 75 4.2 Recommended Operating Conditions . 75 4.3 Supply configuration, power consumption . 76 © Semtech 2006 www.semtech.com 3 XE1431 XE1431 Bluetooth® SoC 4.3.1 4.3.2 3V supply configuration, single 13 MHz crystal oscillator . 76 1.8V supply configuration, single 13 MHz crystal oscillator . 77 5 Application Schematics ­ Bluetooth Headset . 78 6 Packaging Information ­ 72-pin LFBGA . 80 7 Reference Documents . 81 8 Notice, Trademarks. 81 © Semtech 2006 www.semtech.com 4 XE1431 XE1431 Bluetooth® SoC 1 APPLICATION INFORMATION ­ XE1431-BASED XE1431-BASED SYSTEM LEVEL BLOCK DIAGRAM The Semtech XE1431 XE1431, a member of the EasyBlueTM family, is based on a unique Embedded-Host architecture which enables any data or voice application to be enhanced with ultra low power Bluetooth technology with low risk and a short development time. The core of the XE1431 XE1431 is the Semtech ROM-based Bluetooth sequencer combined with an embedded 8-bit RISC microcontroller and several standard peripherals such as GPIO, high speed UART, audio CODEC, and a power management unit. The Bluetooth sequencer executes the lower layers of the Bluetooth stack, while the microcontroller runs the application and the higher levels of the protocol. Since the sequencer and the microcontroller are independent, the effort for validation and qualification of the Bluetooth protocol is greatly decreased. A typical wireless headset block diagram using the XE1431 XE1431 is shown in Figure 1. The on-chip CODEC is connected with a microphone and a speaker. The Serial Peripheral Interface (SPI) directly interfaces to an external Flash memory. This memory stores the application and the upper layers of the Bluetooth protocol stack which are loaded at boot-up time, and then executed by the on-chip application processor. Fully programmable General Purpose Input/Output ports (GPIO) are available to interface push-buttons, LED's or other peripherals. The high speed UART supports hardware flow control and data rates up to 921 kbit/s. serial Flash SPI GPIO/UART CODEC Application Processor Bluetooth Sequencer GPIO XE1431 XE1431 Radio Interface XEMICS XE1413 XE1413 Bluetooth Radio Figure 1 - Bluetooth Headset Application The on-chip host processor runs the application software and the upper layer Bluetooth protocol stack software while the Bluetooth sequencer handles the low level of the protocol without intervention of the application processor. This architecture guarantees that the real time operations of the lower levels can not be influenced by the application. Qualified upper layer Bluetooth protocol software from various 3rd party suppliers can be supplied to run on the XE1431 XE1431. This system architecture definitely eases the software development and Bluetooth qualification processes and guarantees the highest flexibility. The Bluetooth qualification process for the final application is simplified by the fact that the XE1431 XE1431 uses a qualified Bluetooth ROM implementation. © Semtech 2006 www.semtech.com 5 XE1431 XE1431 Bluetooth® SoC 2 XE1431 XE1431 PINOUT Bottom view 10 9 8 7 6 5 4 3 2 1 index pin A1 A B C 7mm D E F G 0.5mm H J K 7mm Figure 2 - LFBGA72 LFBGA72, bottom view 2.1 PIN DESCRIPTION Pin Symbol Type/ capabilities Do not connect Reset Description Do not connect Test pin Voltage level - A1 TP0 A2 TP1 Do not connect Do not connect Test pin - A3 TP2 Connect to ground Connect to ground Test pin - A4 PB[1] DIOu DIu General purpose port B I/O VDDIO_DIG A5 PB[3] DIOu DIu General purpose port B I/O VDDIO_DIG A6 PB[5] / UA_RTS DIOu DIu General purpose port B I/O VDDIO_DIG UART RTS handshaking A7 PB[7] / UA_RX DIOu DIu General purpose port B I/O VDDIO_DIG UART receive signal A8 MOSI DIOu DO SPI master Out slave In VDDIO_DIG A9 MISO DIOu DIu SPI master In slave Out VDDIO_DIG A10 SCK DIOu DO SPI clock VDDIO_DIG B1 NRESET DIu DIu Master Reset VDD_M © Semtech 2006 www.semtech.com 6 XE1431 XE1431 Bluetooth® SoC Pin Symbol Reset Description VSS_DIG Type/ capabilities P P Digital core ground Voltage level - B2 B3 PB[0] DIOu DIu General purpose port B I/O VDDIO_DIG B4 PB[2] DIOu DIu General purpose port B I/O VDDIO_DIG B5 PB[4] / UA_CTS DIOu DIu General purpose port B I/O VDDIO_DIG UART CTS handshaking B6 PB[6] / UA_TX DIOu DIu General purpose port B I/O VDDIO_DIG UART transmit signal B7 VSSIO_DIG P P digital pads ground - B8 VDDIO_DIG P P digital pads supply voltage - B9 NSS[0] DIOu DIu First SPI slave select VDDIO_DIG B10 NSS[1] DIOu DIu Second SPI slave select VDDIO_DIG C1 VREG_OFF DO DO Internal regulators status VDDM C2 VDDBAT AI AI Sensor input for battery end-of-life detection - C9 NSS[2] DIOu DIu Third SPI slave select VDDIO_DIG C10 NSS[3] DIOu DIu Fourth SPI slave select VDDIO_DIG D1 VMIC_P AI AI Microphone positive input - D2 VDD_ANA P P Analog core supply voltage - D4 DBG[4] DIOk DIk Debug Interface HCI CTS VDDIO_DIG D7 DBG[7] DIOk DIk Debug Interface HCI TX VDDIO_DIG D9 PA[0] DIuk DIu General purpose port A input VDDIO_DIG D10 NSS[4] DIOu DIu Fifth SPI slave select VDDIO_DIG E1 VMIC_N AI AI Microphone negative input - E2 VREGA AO AO Analog regulated voltage - E5 DBG[5] DIOk DIk Debug Interface HCI RTS VDDIO_DIG E6 DBG[6] DIOk DIk Debug Interface HCI RX VDDIO_DIG E9 PA[2] DIuk DIu General purpose port A input VDDIO_DIG E10 PA[1] DIuk DIu General purpose port A input VDDIO_DIG F1 VREF AO AO Reference voltage output - F2 VDD_M P P Main supply voltage - F5 DBG[1] DIOk DIk Debug Interface PCM clock VDDIO_DIG F6 DBG[3] DIOk DIk Debug Interface PCM data in VDDIO_DIG F9 PA[4] DIuk DIu General purpose port A input VDDIO_DIG F10 PA[3] DIuk DIu General purpose port A input VDDIO_DIG G1 VSS_M P P Analog ground - G2 VREGD AO AO Digital regulated voltage - © Semtech 2006 www.semtech.com 7 XE1431 XE1431 Bluetooth® SoC Pin Symbol Reset Description DBG[0] Type/ capabilities DIOk G4 DIk Debug Interface PCM fsync G7 DBG[2] DIOk DIk Debug Interface PCM data out VDDIO_DIG G9 PA[6] DIuk DIu General purpose port A input VDDIO_DIG G10 PA[5] DIuk DIu General purpose port A input VDDIO_DIG H1 PA_OUTP AO AO Power amplifier positive output VDD_PA H2 VDD_PA P P Power amplifier supply voltage - H9 VDD_DIG P P Digital core supply voltage - H10 PA[7] DIuk DIu General purpose port A input VDDIO_DIG J1 PA_OUTN AO AO Power amplifier negative output VDD_PA J2 TP3 Do not connect Do not connect Test pin - J3 WAKEUP DId DId Chip wake up VDD_M J4 SPI_DATA_IN DIk DIk Radio SPI input VDDIO J5 VDDIO P P Radio pads supply voltage - J6 VSSIO P P Radio pads ground - J7 RX_EN DO DO Radio RX enable VDDIO J8 SYNC_DETECT DO DO Radio sync detect VDDIO J9 SYS_CLOCK_IN DI DI Master clock input VDDIO J10 DOC_SDIO DIOu DIu Monitor data I/O VDDIO_DIG K1 VSS_PA P P Power amplifier ground - K2 TP4 Do not connect Do not connect Test pin - K3 RX_DATA DIk DIk Radio RX data VDDIO K4 SLW_CLOCK_IN DIk DIk 32 kHz clock input VDDIO K5 TX_DATA DO DO Radio TX data VDDIO K6 TX_EN DO DO Radio TX enable VDDIO K7 SPI_DATA_OUT DO DO Radio SPI data out VDDIO K8 SPI_CLK_OUT DO DO Radio SPI serial clock VDDIO K9 SPI_EN_BAR DO DO Radio SPI select VDDIO K10 DOC_SCK DIu DIu Monitor clock VDDIO_DIG A : Analog I : Input u : Internal pull-up k : Internal keeper Voltage level VDDIO_DIG D : Digital O : Output d : Internal pull-down P : Power Table 1 ­ Pin description © Semtech 2006 www.semtech.com 8 XE1431 XE1431 Bluetooth® SoC 3 DETAILED FUNCTIONAL DESCRIPTION 3.1 BLOCK DIAGRAM Program Memory (ROM / RAM) RX_DATA SPI_DATA_IN CoolRISC 816 RISC CPU Data Memory Event Controller NRESET BT HCI UART Codec Reset Controller Bluetooth Sequencer TX_DATA RX_EN SYNC_DETECT TX_EN SPI_DATA_OUT SPI_CLK_OUT SPI_EN_BAR GPIO PB uart bus pcm bus VMIC_P, VMIC_N PA_OUTP, PA_OUTN PB[7 :0] Interrupt Controller Application UART Counter/ Timer GPI PA Clock Controller SPI PA[7 :0] SYS_CLOCK_IN SLW_CLOCK_IN RC Oscillator Power Management TP[4 :0] DOC_SCK, DOC_SDIO MISO, MOSI, SCK,NSS[4 :0] WAKEUP VDDBAT VREGA, VREGD VREF, VREG_OFF VDD_M, VDD_PA, VDD_DIG, VDDIO, VDD_ANA, VDDIO_DIG DoC VSS_M, VSS_PA, VSS_DIG, VSSIO, VSSIO_DIG DBG[7 :0] Figure 3 - XE1431 XE1431 block diagram © Semtech 2006 www.semtech.com 9 XE1431 XE1431 Bluetooth® SoC A high-level block diagram of the XE1431 XE1431 is shown in Figure 3. The CoolRISCTM 816 8-bit RISC processor is optimized for both computation power and energy consumption efficiency. Every instruction executes in one clock cycle. The system frequency can be selected between different possible clock signals ­ SLW_CLOCK_IN, which is typ. 32 kHz, SYS_CLOCK_IN, which is typ. 13 MHz, or the internal programmable RC oscillator fRC up to 14 MHz. The program memory consists first of 4k instructions in ROM for the boot code and the debug drivers, and then 40k instructions RAM dedicated to the application and the upper layers of the Bluetooth protocol stack. The data memory is 8 kbyte RAM. The interrupt and event controllers manage interrupts and events from peripherals and internal timers. The reset controller takes care of the power-on phase. The clock controller selects the processor and peripherals clocks between the internal RC oscillator or the two external clocks. GPIO's are split into two peripherals: a) the port A (PA) is an 8-bit wide input digital port with selectable pull-up and debouncer. It can also be programmed to generate interrupts and resets; and b) the port B (PB) is an 8-bit wide input/output digital port with selectable pull-up and open-drain capabilities. The SPI and UART interfaces implement serial communication protocols. The SPI can communicate with up to 5 peripherals, one of them being the serial non-volatile memory storing the application code. The UART has an 8-byte FIFO and supports hardware flow control. The integrated power management unit generates the regulated supply voltages for the XE1431 XE1431, thus reducing the number of external components. It also monitors the battery voltage to detect the end-of-life of the battery. The codec is compliant with the Bluetooth Audio specifications and integrates a built-in CVSD coder/decoder. The audio samples are transferred directly from the Bluetooth sequencer to the codec to reduce the processor load and power consumption. A DMA interface allows transferring of samples directly between the memory and codec. The Bluetooth sequencer is a complete dedicated Bluetooth co-processor. It implements the lower layers of the Bluetooth protocol stack from the radio interface up to the HCI. It runs independently from the processor and communicates with it through a dedicated internal UART link. This tremendously simplifies the debugging of the final product and the Bluetooth qualification since the application can not disturb the time-critical part of the Bluetooth stack. The Bluetooth sequencer supports all modes of operation (Active, Hold, Sniff, Park, Standby), all packet types, simultaneous operation with up to 7 ACL (data) links and one SCO (audio) link in a point-to-point, piconet, or scatternet network configuration. The debug-on-chip (DoC) peripheral interfaces the chip with the software debugger. © Semtech 2006 www.semtech.com 10 XE1431 XE1431 Bluetooth® SoC 3.2 HOST PROCESSOR SYSTEM 3.2.1 CoolRISC 816 CPU The CPU of the XE1431 XE1431 is a CoolRISC816, an 8-bit low power RISC core. The instruction set is made up of 35 generic instructions coded on 22 bits and always executed in one clock cycle, including conditional jumps and 8x8 multiplications, thus providing 1 MIPS/MHz. Instructions and data memory are separated (Harvard architecture). The 16 8-bit registers enable the use of a C compiler. The complete CPU hardware and software description is given in the document "CoolRISC 816, 8-bit Microprocesor Core, Hardware and Software Reference Manual", version 4.5 which can be found on the Semtech website http://www.semtech.com . F F 0xBFFF 0x3FFF DoC 0x3FF0 0x3FEF 0x2000 0h0FFF ROM 4k x 22 bit 0x0000 r2 r3 i0h i0l i1h i2l i3h i3l iph 0x2000 0x1FFF i1l i2h data bus r1 ipl Data memory RAM 8k x 8 bit r0 CPU internal registers RAM 40k x 22 bit instruction bus Instruction memory CPU Peripheral registers stat 0x0000 a Figure 4 - Memory organization 3.2.2 Program memory The instruction memory is composed of both ROM and RAM. The ROM size is 4096 x 22-bit and stores the boot code and the Debug-On-Chip (DoC) driver. The RAM size is 40k instructions and is completely available for the application except for the last 64 instructions between 0xBFB0 and 0xBFFF which are used by the Debug-on-Chip. The ROM is located from the address 0x0000 to the address 0x0FFF. The RAM is located in the 0x2000 to 0xBFFF range. Addresses 0x2000 to 0x2004 are jump and interrupt vectors. Address 0x2000 Usage start vector Comment Usually set to 0x2005. The code actually begins at 0x2005 0x2001 0x2002 0x2003 0x2004 Mid priority interrupt handler Low priority interrupt handler High priority interrupt handler RESERVED Table 2 ­ Jump and interrupt vectors address table © Semtech 2006 www.semtech.com 11 XE1431 XE1431 Bluetooth® SoC 3.2.3 Data memory The data memory space is made of 8 kbytes of RAM. The last 16 bytes between 0x3FF0 and 0x3FFF are reserved for the Debug-On-Chip (DoC) interface. The rest of the space from 0x2000 to 0x3FEF is available for the application. The peripheral registers are located in the page 0 of the data memory space. Block System registers (reset controller & clock controller) Port A registers Port B registers Application UART registers Debug-On-Chip registers (reserved) Event controller registers Interrupt controller registers Power management unit registers HCI UART (to/from Bluetooth Sequencer) registers Counter registers SPI registers Debug-on-Chip registers (reserved) Codec registers Data Memory Debug-on-Chip memory (reserved) Address range 0x0010 to 0x001F 0x0020 to 0x0027 0x0028 to 0x002D 0x0030 to 0x0037 0x0038 to 0x003B 0x003C to 0x003F 0x0040 to 0x0047 0x0048 to 0x004C 0x0050 to 0x0057 0x0058 to 0x005F 0x0068 to 0x006F 0x0080 to 0x009F 0x00E0 to 0x00FF 0x2000 to 0x3FEF 0x3FF0 to 0x3FFF Table 3 - Data memory and registers map 3.3 POWER MANAGEMENT UNIT 3.3.1 · · · · · · · Features Wide power supply range, VDD_M from 2.2 to 3.6V. High current (50 mA) integrated 1.8V regulator to supply the digital core of the XE1431 XE1431 and external chips, VREGD output. Integrated 1.8V analog regulator to supply analog blocks, VREGA output. Integrated temperature-compensated voltage reference. Battery end-of-life detection, VDDBAT input. Mode of operation controller to suppress the need for external power supply switch. Ultra low power consumption in OFF mode. 3.3.2 Register map Name RegPmgtVrega RegPmgtVregd RegPmgtEol Address (Hex) 0x0048 0x0049 0x004A Table 4 - Power management unit register mapping Pos 7:6 5 4 RegPmgtVrega DefaultVrega EnableVrega r/w r rw rw Reset 00 1 0 3:0 TuneVrega rw 0011 Function reserved force analog tuning to default values 1 = VREGA voltage regulator switched on 0 = VREGA voltage regulator switched off adjust VREGA value Table 5 - RegPmgtVrega register © Semtech 2006 www.semtech.com 12 XE1431 XE1431 Bluetooth® SoC Pos 7 6:5 4 RegPmgtVregd WakeUp VregdStatus r/w r r r Reset x 00 1 3:2 1 TuneVregd VregdLock rw w 00 1 0 - r 0 Function value of the wakeup pin reserved 1 = VREGD voltage regulator switched on 0 = VREGD voltage regulator switched off adjust VREGD value 1 = lock VREGD voltage regulator 0 = shut down VREGD voltage regulator reserved Table 6 - RegPmgtVregd register Pos 7 RegPmgtEol EolOk r/w r Reset x 6 5 EnableEol r rw 0 0 4:0 EolThreshold rw 00000 Function 0 = VDDBAT pin voltage < EolThreshold 1 = VDDBAT pin voltage EolThreshold reserved 1 = battery end-of-life switched on 0 = battery end-of-life switched off adjust battery end-of-life comparator threshold Table 7 - RegPmgtEol register 3.3.3 Modes of operation The power management unit's role is to generate regulated voltages for both internal and the external components such as the non-volatile serial memory and the radio chip. It includes a controller to switch on/off all voltage regulators when needed in order to reduce power consumption. Three modes of operation are defined (see Figure 6): · OFF mode: all internal power supplies are shut down. Power consumption is very low, typically a few microamps. · ON mode: all blocks except the CODEC are powered. The application is running and a Bluetooth connection may be active. The chip enters this state when the WAKEUP input is set high (see Figure 5), and leaves this mode under software control, when requested by the application. In the ON mode, the pin VREGD outputs 1.8V and the pin VREGA is floating. · AUDIO mode: all blocks are powered. It is entered upon request from the application. In the AUDIO mode, the pins VREGA and VREGD output 1.8V. WAKEUP twakeup Figure 5 - WAKEUP timing diagram Software control (ex. SCO link activated) WAKEUP pin OFF ON Software control (for ex. Timeout or button) AUDIO Software control (for ex. SCO link closed) Figure 6 - XE1431 XE1431 power management modes © Semtech 2006 www.semtech.com 13 XE1431 XE1431 Bluetooth® SoC 3.3.4 Block diagram VDD_M VREF VDD_M Iref vreg_dig VDD_M Vref Bandga VREGD VDD_M VDD_M VREG_OFF vreg_ana VDDBAT Eol VREGA VDD_M power_mngt controller VDD_M VDD_DIG VDDIO levelshifters VDD_ANA VDD_ANA VDD DIG VDD_DIG analog core digital core VDDIO padring VDD_DIG VDDIO_DIG VDD_PA Power Amplifier VDDIO_DIG padring Figure 7 - Power management unit block diagram The main power supply is VDD_M. It powers the power management unit and some I/O pads. The power management unit generates the VREGD and VREGA regulated voltages. VREGD is usually used to supply the digital core, through the VDD_DIG pin, and external components such as a serial non-volatile memory and the radio chip. VREGA is usually used to supply the internal analog blocks, through the pin VDD_ANA. It may also be used to power an external microphone. VDDIO is the power supply for the radio interface. If the radio chip is powered by VREGD, then VDDIO should be connected to VREGD as well. VDDIO_DIG is the power supply for most of the digital pads. Depending on the application, it may be connected to VREGD, VDD_M, or any other power supply which fulfills the specifications. © Semtech 2006 www.semtech.com 14 XE1431 XE1431 Bluetooth® SoC VDD_M should be decoupled with a capacitor CVDD_M for best performances. VREGD has to be connected to an external capacitor CVREGD to insure the stability and the performance of the voltage regulator. VREGA has to be connected to an external capacitor CVREGA to insure the stability and the performance of the voltage regulator. VREF is connected to an external capacitor CVREF. VDD_PA can be connected to VREGD. 3.3.5 Regulators specifications, external components Symbol VREGA VREGD IREGA IREGD Description Analog regulated output voltage Digital regulated output voltage Output current on VREGA Output current on VREGD Min 1.62 Typ. 1.8 Max 1.98 Unit V 1.62 1.8 1.98 V 10 50 mA mA Comments Recommended max. load Recommended max. load Table 8 - On-chip voltage regulators specifications Symbol CVREGD CVREGA CVREF CVDD_M Value 4.7 uF 1 uF 1 uF 1 uF Table 9 - Typical external components Capacitors should be added to decouple VDD_PA, VDD_DIG, VDD_ANA, VDDIO, and VDDIO_DIG, as a common practice. 3.3.6 Battery End-Of-Life (EOL) VDDBAT R 500 k V1 EolOk Ieol 0.7V Figure 8 - Battery end-of-life structure The battery end-of-life circuit structure is described in Figure 8. A voltage is created by drawing a constant current Ieol from the pin VDDBAT through the internal resistor R, and is compared with a voltage reference. The bit EolOk of the register RegPmgtEol is directly the output of the comparator. The EolOk is set to "1" whenever the voltage at VDDBAT is higher or equal to the threshold voltage VEOLThreshold. This threshold voltage of the comparator is given by the Equation 1. For cThe start up time of the end-of-life circuit is TEOLstart. The response time to a change on VDDBAT is TEOLres. 4 VEOLThreshold = VEOLref + VEOLstep 2 i EolThreshold [i ] i =0 Equation 1 - Threshold voltage of the EOL comparator © Semtech 2006 www.semtech.com 15 XE1431 XE1431 Bluetooth® SoC Symbol VEOLref VEOLstep EOLThresho ld TEOLstart TEOLres Parameter EOL reference voltage Threshold tuning step EOLthreshold offset setting Min 0.710 40 0x00 Typ 0.725 45 Max 0.740 50 0x14 Unit V mV 100 20 s s start-up time time response Comment @ VDD_M=3V, 20°C @ VDD_M=3V, 20°C Table 10 - End-of-life analog specifications 3.4 RESET CONTROLLER 3.4.1 · · · · Features Handles different reset sources: power-on-reset, NRESET pin, BusError, Watchdog, and port PA Power-on-reset/Brownout detector without external components Programmable watchdog timer Reset can be triggered by NRESET pin 3.4.2 Register map Name RegSysCtrl RegSysWd Address (Hex) 0x0010 0x0014 Table 11 - Reset controller registers Pos 7:6 5 RegSysCtrl EnableBusError r/w r rw Reset 00 0 4 EnableResetWD rw 0 3:0 - r 0000 Function reserved 1 = BusError reset is enabled 0 = BusError reset is disabled 1 = Watchdog reset is enabled 0 = Watchdog reset is disabled reserved Table 12 - RegSysCtrl register Pos 7:4 3:0 RegSysWd WDKey r/w r rw Reset 0000 0000 Function reserved Watchdog key Table 13 - RegSysWd register 3.4.3 Power-On-Reset / Brownout detector The power-on-reset monitors both VDD_M and VDD_DIG. Upon start-up, when both voltages reach a level sufficient to ensure correct circuit behavior, the internal reset signal is released. Then, if during operations the supply voltage drops below the specified threshold (see Table 14), the circuit goes into a reset mode. © Semtech 2006 www.semtech.com 16 XE1431 XE1431 Bluetooth® SoC VDD_M POR_VDD_M reset (general system reset) VDD_DIG NRESET pad resetfromportA POR_VDD_DIG buserrorreset watchdogreset Figure 9 ­ POR, NRESET, and reset circuitry The output of POR_VDD_M controls the pull resistor of the NRESET pad. If the NRESET pad is left unconnected (recommended) the POR_VDD_M is propagated into the system. Otherwise, the internal nreset_system signal may be activated by connecting the NRESET pad to the ground. The NRESET pad is active low. The POR_VDD_M insures that VDD_M is stable so that the power management unit can operate safely. The POR_VDD_DIG insures that VDD_DIG is correct so that the digital core can start. 3.4.4 Bus Error The address space is assigned as shown in the memory map in Table 3. If the bit EnableBusError is set in the register RegSysCtrl and an unused address is accessed by the processor, then a reset is generated. 3.4.5 Watchdog Once enabled by setting the bit EnableResetWD of the RegSysCtrl register, a counter will be started and a reset condition (watchdogreset, Figure 9) will be generated when the counter reaches its maximum value, unless the counter is cleared by software. The counter is 3-bit wide and is clocked by the ck2Hz output of the low prescaler. Its period is typically around 4 seconds but will depend on the clock controller configuration. The watchdog is cleared by writing consecutively the values 0x0a and 0x03 in the RegSysWd register. In assembler, the sequence will look like: move RegSysWd, #0x0a move RegSysWd, #0x03 Only writing 0x0a followed by 0x03 will clear the watchdog. If some other writing is done in and between, in RegSysWd, then the watchdog will not be cleared. The status of the watchdog may be checked by reading the register RegSysWd. The watchdog is a four bit counter with a range of 0 to 7. The reset is generated when the counter reaches the value 8. © Semtech 2006 www.semtech.com 17 XE1431 XE1431 Bluetooth® SoC 3.4.6 Analog reset specifications VDD_M / VDD_DIG VrstD VrstT reset trise tdrop ton Figure 10 ­ Power-On / Brownout reset conditions POR VDD_M supervision VDD_DIG supervision Symbol VrstT VrstD ton trise tdrop VrstT VrstD ton trise tdrop Description Start Voltage Drop Voltage Reset Time Rise Time Drop Time Start Voltage Drop Voltage Reset Time Rise Time Drop Time Min 0.8 0.8 10 0.8 0.8 10 Max 1.5 1.5 300 15 1.5 1.5 300 15 - Unit V V s s s V V s s s Table 14 - POR specifications 3.5 CLOCK DISTRIBUTION UNIT 3.5.1 · · · · 3.5.2 Features On-chip RC oscillator Three available clock sources: RC oscillator, SYS_CLOCK_IN pin, SLW_CLOCK_IN pin Two divider chains: high-prescaler (8 bits) and low-prescaler (15 bits). CPU clock disabled in halt mode. Register map Name RegSysClock RegSysMisc RegSysPre0 RegSysRcTrim1 RegSysRcTrim2 Address (Hex) 0x0012 0x0013 0x0015 0x001B 0x001C Table 15 ­ Clock distribution registers addresses © Semtech 2006 www.semtech.com 18 XE1431 XE1431 Bluetooth® SoC Pos 7 RegSysClock CpuSel r/w rw Reset 0 6 SysClockClk r 0 5 EnableSysClk rw 0 4 3 ColdSlwClock r r 0 1 2 ColdRC r 1 1 EnableSlwClock rw 0 0 EnableRC rw 1 Function 1 = CPU clock is either SYS_CLOCK_IN or SLW_CLOCK_IN 0 = CPU clock is ckRC 1 = SYS_CLOCK_IN clock detected 0 = SYS_CLOCK_IN clock not detected 1 = enable SYS_CLOCK_IN clock 0 = disable SYS_CLOCK_IN clock reserved 1 = SLW_CLOCK_IN in starting phase (32 768 cycles) 0 = SLW_CLOCK_IN starting phase finished 1 = ckRC in starting phase (8 cycles) 0 = ckRC starting phase finished 1 = enable SLW_CLOCK_IN 0 = disable SLW_CLOCK_IN 1 = enable ckRC 0 = disable ckRC Table 16 - RegSysClock register Pos 7:3 2 RegSysMisc DebFast r/w r rw Reset 00000 0 1 0 OutputCk32kHz OutputCkCpu rw rw 0 0 Function reserved 1 = select high frequency for debouncer (PA) clock 0 = select low frequency for debouncer (PA) clock output ck32kHz on pad PB[3] output CkCpu on pad pb[2] Table 17 - RegSysMisc register Pos 7:1 0 RegSysPre0 ResPre r/w r w Reset 0000000 0 Function reserved 1 = reset the low prescaler Table 18 - RegSysPre0 register Pos 7:5 4:2 1:0 RegSysRcTrim1 RCDivFactor RCCoarseMSB r/w r rw rw Reset 000 000 01 Function reserved Divide RC frequency by 2RcDivFactor RC coarse adjustment (MSB) Table 19 - RegSysTrim1 register Pos 7:6 5:4 1:0 RegSysRcTrim2 RCCoarseLSB RCFine r/w r rw rw Reset 00 00 0000 Function reserved RC coarse adjustment (LSB) RC fine adjustment Table 20 - RegSysTrim2 register 3.5.3 RC oscillator The RC oscillator is always turned on and selected for CPU and system operation after a power-on reset or a negative pulse on pad NRESET. It can be deselected after the SYS_CLOCK_IN or the SLW_CLOCK_IN has been started and selected as system clock. © Semtech 2006 www.semtech.com 19 XE1431 XE1431 Bluetooth® SoC The EnableRC bit in the register RegSysClock controls the signal from the RC oscillator. The user can disable the RC oscillator clock signal by resetting the bit EnableRC. The RC oscillator frequency is trimmed with the registers RegSysRcTrim1 and RegSysRcTrim2. The absolute value of the frequency for a given register content may change from chip to chip due to process tolerances. However, the modification of the frequency as a function of a modification of the register content is fairly precise. The RC oscillator output frequency, fRC, is obtained by the following trimming rule: f RC = fo 1 2 RCDivFactor (1 + ( RCCoarse - 8) CoarseStep + RCFine FineStep ) Equation 2 - RC oscillator clock frequency The Table 21 summarizes the characteristics of the oscillator. Symbol f0 FineStep CoarseStep Description Internal oscillator frequency Fine tuning step Coarse tuning step Min 5.5 - Typ 8.25 0.5 7 Max 11 Unit MHz % % Table 21 ­ RC oscillator specifications Important note: the system is not guaranteed to operate properly with a frequency fRC greater than 14 MHz. Setting the RC oscillator over this limit may produce unpredictable results. 3.5.4 SLOW_CLOCK_IN SLW_CLOCK_IN must be present and conform to the Bluetooth specifications if the Bluetooth sequencer deep-sleep mode is used. It is typically generated by the XE1413 XE1413 radio chip. Its frequency is 32'000 Hz or 32'768 Hz. 3.5.5 SYS_CLOCK_IN It is used by the Bluetooth sequencer and the Codec. Its frequency must be 13 MHz with a tolerance of ± 20 ppm. SYS_CLOCK_IN is typically generated by the XE1413 XE1413 radio chip. 3.5.6 Clock source selection Different clock sources can be selected independently for the application processor and the reset of the system. The clock of the Bluetooth sequencer is hard-coded and can not be chosen by the user. The RC clock is always selected after power-up or a negative pulse on the NRESET pin. The CPU clock selection is done with the register RegSysClock according to the Table 22. Switching from one clock source to another is glitch free. See also Figure 11, Figure 12, and Figure 13. © Semtech 2006 www.semtech.com 20 XE1431 XE1431 Bluetooth® SoC 0 RC 0 RC + SlwClock SysClock EnableSlwClock SlwClock Clock Targets CpuCk EnableRC Mode name EnableSysClock Clock Sources CpuSel = 0 CpuSel = 1 High prescaler clock input Low prescaler clock input 0 1 SLW_CLOCK_IN SLW_CLOCK_IN Off Off 1 0 ckRC high prescaler output ckRC high prescaler output 0 1 1 ckRC SLW_CLOCK_IN ckRC SLW_CLOCK_IN 1 X X SYS_CLOCK_IN high prescaler output SYS_CLOCK_IN high prescaler output Table 22 ­ XE1431 XE1431 Clock configuration Switching from one clock to one other and stopping the unused clock must be performed in three MOVE instructions to RegSysClock. First enable the new clock, then select the CPU clock, and finally stop the unused clock. Combining the different operations in one instruction may cause system malfunction. 3.5.7 RegSysMisc description The bit DebFast selects the debouncer clock between 256 Hz for DebFast = 0 and 8 kHz for DebFast = 1. The debouncer clock feeds the port PA input debouncer. The PA debouncer is described in paragraph 3.8.4 When OutputCk32kHz is 1, the ck32kHz clock is output of the port B PB[3]. The CPU clock is output on the port B PB[2] when the bit OutputCkCpu is 1. © Semtech 2006 www.semtech.com 21 XE1431 XE1431 Bluetooth® SoC 3.5.8 Prescalers The Figure 11 describes the overall structure of the prescaler. RC Oscillator SYS_CLOCK_IN ckRC 0 1 ckRCext High Prescaler EnableSysClock ckRCext/2 . ckRCext/256 SLW_CLOCK_IN (EnableSlwClock) AND (NOT(EnableSysClock) Low Prescaler ck32kHz RCDivFactor RCCoarse RCFine ck32kHz . ck1Hz 1 1 ckcpu 0 0 CpuSel (EnableRC) OR (EnableSysClock) Figure 11 - Prescaler Unit block diagram © Semtech 2006 www.semtech.com 22 XE1431 XE1431 Bluetooth® SoC 3.5.8.1 High Prescaler The high prescaler is made up of an 8-stage dividing chain. It can be driven with the RC oscillator clock or the SYS_CLOCK pin, depending on the EnableSysClock parameter. ÷2 ckRCext/2 ÷2 ckRCext/4 ÷2 ckRCext/8 ÷2 ckRCext/16 ÷2 ckRCext/32 ÷2 ckRCext/64 ÷2 ckRCext/128 ÷2 ckRCext ckRCext/256 Figure 12 - High prescaler block diagram The Table 23 summarizes which peripherals use the outputs of the high prescaler. Since each stage of the high prescaler divides the frequency by 2, the frequency of all the outputs of the high prescaler is proportional to the frequency of ckRCext. High prescaler output ckRCext ckRCext/2 ckRCext/4 ckRCext/8 ckRCext/16 ckRCext/32 ckRCext/64 ckRCext/128 Peripherals application UART, Bluetooth UART, SPI, counter/timer, port PA application UART, Bluetooth UART application UART, Bluetooth UART, SPI, counter/timer application UART, Bluetooth UART, SPI application UART, Bluetooth UART, SPI application UART, Bluetooth UART application UART, Bluetooth UART application UART, Bluetooth UART Table 23 - High prescaler outputs usage 3.5.8.2 Low prescaler The low prescaler can be driven from one of the high prescaler outputs ckRCext/2 to ckRCext/128 or directly with the SLW_CLOCK_OUT pin when the bit EnableSlwClock is set to 1 and bit EnableSysClock is reseted to 0. The bit ResPre in the register RegSysPre0 synchronously resets the low prescaler. The low prescaler is also automatically cleared when the bit EnableSlwClock is set to 1. The bit ColdSlwClock value is 1 to indicate that the SLW_CLOCK_IN is in its starting phase. It automatically enters this phase when the bit EnableSlwClock is set to 1. During this phase, SLW_CLOCK_IN is not available. It becomes available after 32'768 cycles, when the bit ColdSlwClock returns to 0. © Semtech 2006 www.semtech.com 23 XE1431 XE1431 Bluetooth® SoC (EnableSlwClock) AND (NOT(EnableSysClock) SLW_CLOCK_IN 1 0 Ck32kHz ÷2 Ck128Hz Ck16kHz ÷2 Ck64Hz ÷2 Ck8kHz ÷2 Ck32Hz ÷2 Ck4kHz ÷2 Ck16Hz ÷2 Ck2kHz ÷2 Ck8Hz ÷2 ckRCext/2 ckRCext/4 ckRCext/8 ckRCext/16 ckRCext/32 ckRCext/64 ckRCext/128 ÷2 Ck1kHz ÷2 Ck4Hz ÷2 Ck512Hz ÷2 Ck2Hz ÷2 Ck256Hz ÷2 Ck1Hz RCDivFactor RCCoarse RCFine Decoder Figure 13 - Low prescaler block diagram The high prescaler output may be used as the low prescaler input. A decoder is used to select from the high prescaler the frequency tap that is the closest to 32 kHz to operate the low prescaler when SLW_CLOCK_IN is not running. In this case, the RC oscillator frequency will also be valid for the low prescaler frequency outputs. The Table 24 shows how the RC trimming values in the RegSysRcTrim1 and RegSysRcTrim2 registers are decoded to select the input frequency from the high prescaler. The least significant bits of the RCFine word are ignored. In order to ensure the correct frequency selection for the low prescaler with an external clock, a proper value must be set in the RC trim registers. If the frequency is not set correctly, all timings derived from the low prescaler will be shifted accordingly (e.g. watchdog and interrupt frequencies). In the Table 24, ckRCext stands for either ckRC or SYS_CLOCK_IN. RCDivFactor & RCCoarseMSB & RCCoarseLSB & RCFine [0x0000]hex [0x0002]hex [0x0100]hex [0x0102]hex [0x010a]hex [0x0110]hex [0x0119]hex [0x0120]hex [0x0127]hex Selected high prescaler tap RCDivFactor & RCCoarseMSB & RCCoarseLSB & RCFine [0x04c8]hex [0x04d0]hex [0x04d6]hex [0x04e0]hex [0x04e5]hex [0x04f0]hex [0x04f3]hex [0x0500]hex [0x0502]hex ckRCext / 64 ckRCext / 128 ckRCext / 32 ckRCext / 64 ckRCext / 128 ckRCext / 64 ckRCext / 128 ckRCext / 64 ckRCext / 128 © Semtech 2006 Selected high prescaler tap ckRCext / 32 ckRCext / 16 ckRCext / 32 ckRCext / 16 ckRCext / 32 ckRCext / 16 ckRCext / 32 ckRCext / 2 ckRCext / 4 www.semtech.com 24 XE1431 XE1431 Bluetooth® SoC RCDivFactor & RCCoarseMSB & RCCoarseLSB & RCFine [0x0130]hex [0x0135]hex [0x0140]hex [0x0144]hex [0x0150]hex [0x0152]hex [0x0160]hex [0x0161]hex [0x0200]hex [0x0202]hex [0x020a]hex [0x0210]hex [0x0219]hex [0x0220]hex [0x0227]hex [0x0230]hex [0x0235]hex [0x0240]hex [0x0244]hex [0x0250]hex [0x0252]hex [0x0260]hex [0x0261]hex [0x028e]hex [0x0290]hex [0x029d]hex [0x02a0]hex [0x02ab]hex [0x02b0]hex [0x02b9]hex [0x02c0]hex [0x02c8]hex [0x02d0]hex [0x02d6]hex [0x02e0]hex [0x02e5]hex [0x02f0]hex [0x02f3]hex [0x0300]hex [0x0302]hex [0x030a]hex [0x0310]hex [0x0319]hex [0x0320]hex [0x0327]hex [0x0330]hex [0x0335]hex [0x0340]hex [0x0344]hex [0x0350]hex [0x0352]hex Selected high prescaler tap RCDivFactor & RCCoarseMSB & RCCoarseLSB & RCFine [0x050a]hex [0x0510]hex [0x0519]hex [0x0520]hex [0x0527]hex [0x0530]hex [0x0535]hex [0x0540]hex [0x0544]hex [0x0550]hex [0x0552]hex [0x0560]hex [0x0561]hex [0x058e]hex [0x0590]hex [0x059d]hex [0x05a0]hex [0x05ab]hex [0x05b0]hex [0x05b9]hex [0x05c0]hex [0x05c8]hex [0x05d0]hex [0x05d6]hex [0x05e0]hex [0x05e5]hex [0x05f0]hex [0x05f3]hex [0x0600]hex [0x0602]hex [0x060a]hex [0x0610]hex [0x0619]hex [0x0620]hex [0x0627]hex [0x0630]hex [0x0635]hex [0x0640]hex [0x0644]hex [0x0650]hex [0x0652]hex [0x0660]hex [0x0661]hex [0x068e]hex [0x0690]hex [0x069d]hex [0x06a0]hex [0x06ab]hex [0x06b0]hex [0x06b9]hex [0x06c0]hex ckRCext / 64 ckRCext / 128 ckRCext / 64 ckRCext / 128 ckRCext / 64 ckRCext / 128 ckRCext / 64 ckRCext / 128 ckRCext / 16 ckRCext / 32 ckRCext / 64 ckRCext / 32 ckRCext / 64 ckRCext / 32 ckRCext / 64 ckRCext / 32 ckRCext / 64 ckRCext / 32 ckRCext / 64 ckRCext / 32 ckRCext / 64 ckRCext / 32 ckRCext / 64 ckRCext / 128 ckRCext / 64 ckRCext / 128 ckRCext / 64 ckRCext / 128 ckRCext / 64 ckRCext / 128 ckRCext / 64 ckRCext / 128 ckRCext / 64 ckRCext / 128 ckRCext / 64 ckRCext / 128 ckRCext / 64 ckRCext / 128 ckRCext / 8 ckRCext / 16 ckRCext / 32 ckRCext / 16 ckRCext / 32 ckRCext / 16 ckRCext / 32 ckRCext / 16 ckRCext / 32 ckRCext / 16 ckRCext / 32 ckRCext / 16 ckRCext / 32 © Semtech 2006 Selected high prescaler tap ckRCext / 8 ckRCext / 4 ckRCext / 8 ckRCext / 4 ckRCext / 8 ckRCext / 4 ckRCext / 8 ckRCext / 4 ckRCext / 8 ckRCext / 4 ckRCext / 8 ckRCext / 4 ckRCext / 8 ckRCext / 16 ckRCext / 8 ckRCext / 16 ckRCext / 8 ckRCext / 16 ckRCext / 8 ckRCext / 16 ckRCext / 8 ckRCext / 16 ckRCext / 8 ckRCext / 16 ckRCext / 8 ckRCext / 16 ckRCext / 8 ckRCext / 16 ckRCext / 1 ckRCext / 2 ckRCext / 4 ckRCext / 2 ckRCext / 4 ckRCext / 2 ckRCext / 4 ckRCext / 2 ckRCext / 4 ckRCext / 2 ckRCext / 4 ckRCext / 2 ckRCext / 4 ckRCext / 2 ckRCext / 4 ckRCext / 8 ckRCext / 4 ckRCext / 8 ckRCext / 4 ckRCext / 8 ckRCext / 4 ckRCext / 8 ckRCext / 4 www.semtech.com 25 XE1431 XE1431 Bluetooth® SoC RCDivFactor & RCCoarseMSB & RCCoarseLSB & RCFine [0x0360]hex [0x0361]hex [0x038e]hex [0x0390]hex [0x039d]hex [0x03a0]hex [0x03ab]hex [0x03b0]hex [0x03b9]hex [0x03c0]hex [0x03c8]hex [0x03d0]hex [0x03d6]hex [0x03e0]hex [0x03e5]hex [0x03f0]hex [0x03f3]hex [0x0400]hex [0x0402]hex [0x040a]hex [0x0410]hex [0x0419]hex [0x0420]hex [0x0427]hex [0x0430]hex [0x0435]hex [0x0440]hex [0x0444]hex [0x0450]hex [0x0452]hex [0x0460]hex [0x0461]hex [0x048e]hex [0x0490]hex [0x049d]hex [0x04a0]hex [0x04ab]hex [0x04b0]hex [0x04b9]hex [0x04c0]hex Selected high prescaler tap RCDivFactor & RCCoarseMSB & RCCoarseLSB & RCFine [0x06c8]hex [0x06d0]hex [0x06d6]hex [0x06e0]hex [0x06e5]hex [0x06f0]hex [0x06f3]hex [0x0700]hex [0x0702]hex [0x070a]hex [0x0710]hex [0x0719]hex [0x0720]hex [0x0727]hex [0x0730]hex [0x0735]hex [0x0740]hex [0x0744]hex [0x0750]hex [0x0752]hex [0x0760]hex [0x0761]hex [0x078e]hex [0x0790]hex [0x079d]hex [0x07a0]hex [0x07ab]hex [0x07b0]hex [0x07b9]hex [0x07c0]hex [0x07c8]hex [0x07d0]hex [0x07d6]hex [0x07e0]hex [0x07e5]hex [0x07f0]hex [0x07f3]hex ckRCext / 16 ckRCext / 32 ckRCext / 64 ckRCext / 32 ckRCext / 64 ckRCext / 32 ckRCext / 64 ckRCext / 32 ckRCext / 64 ckRCext / 32 ckRCext / 64 ckRCext / 32 ckRCext / 64 ckRCext / 32 ckRCext / 64 ckRCext / 32 ckRCext / 64 ckRCext / 4 ckRCext / 8 ckRCext / 16 ckRCext / 8 ckRCext / 16 ckRCext / 8 ckRCext / 16 ckRCext / 8 ckRCext / 16 ckRCext / 8 ckRCext / 16 ckRCext / 8 ckRCext / 16 ckRCext / 8 ckRCext / 16 ckRCext / 32 ckRCext / 16 ckRCext / 32 ckRCext / 16 ckRCext / 32 ckRCext / 16 ckRCext / 32 ckRCext / 16 Selected high prescaler tap ckRCext / 8 ckRCext / 4 ckRCext / 8 ckRCext / 4 ckRCext / 8 ckRCext / 4 ckRCext / 8 ckRCext / 0 ckRCext / 1 ckRCext / 2 ckRCext / 1 ckRCext / 2 ckRCext / 1 ckRCext / 2 ckRCext / 1 ckRCext / 2 ckRCext / 1 ckRCext / 2 ckRCext / 1 ckRCext / 2 ckRCext / 1 ckRCext / 2 ckRCext / 4 ckRCext / 2 ckRCext / 4 ckRCext / 2 ckRCext / 4 ckRCext / 2 ckRCext / 4 ckRCext / 2 ckRCext / 4 ckRCext / 2 ckRCext / 4 ckRCext / 2 ckRCext / 4 ckRCext / 2 ckRCext / 4 Table 24 ­ ck32kHz frequency selector © Semtech 2006 www.semtech.com 26 XE1431 XE1431 Bluetooth® SoC The Table 25 summarizes which peripherals use the outputs of the low prescaler. The frequencies of all outputs of the low prescaler are directly proportional to the frequency of the clock source of the low prescaler. Low prescaler output ck32kHz ck2kHz ck1kHz ck128Hz ck2Hz ck1Hz Peripherals application UART, Bluetooth sequencer UART, counter/timer, port PA debouncer counter/timer counter/timer, port PA debouncer interrupt controller, event controller watchdog interrupt controller, event controller Table 25 - Low prescaler outputs usage 3.5.9 Codec and Bluetooth Sequencer clocks The codec can only use SYS_CLOCK_IN since it needs exactly a 13 MHz frequency to meet the Bluetooth audio specifications. The Bluetooth sequencer uses SYS_CLOCK_IN for normal operations and SLW_CLOCK_IN during the low power modes. RC Oscillator Application Processor SLW CLOCK IN Bluetooth Sequencer SYS_CLOCK_IN CODEC Figure 14 ­ Codec and Bluetooth Sequencer clocking sources In a typical application where the XE1431 XE1431 is used with its companion chip, the XE1413 XE1413 radio, SYS_CLOCK_IN and SLW_CLOCK_IN are generated by the XE1413 XE1413. 3.6 INTERRUPT CONTROLLER 3.6.1 · · Features Supports 24 sources of interrupt Three levels of priority . 3.6.2 Register map Name RegIrqHig RegIrqMid RegIrqLow RegIrqEnHig RegIrqEnMid RegIrqEnLow Address (Hex) 0x0040 0x0041 0x0042 0x0043 0x0044 0x0045 Table 26 - Interrupt controller register map © Semtech 2006 www.semtech.com 27 XE1431 XE1431 Bluetooth® SoC Pos 7 6 5 4 3 2 1 0 RegIrqHig 128Hz Spi CntA CntC Codec UartHTx UartHRx r/w r rc1 rc1 rc1 rc1 rc1 rc1 rc1 Reset 0 0 0 0 0 0 0 0 Function reserved interrupt from ck128Hz low prescaler output interrupt from SPI interrupt from counter A interrupt from counter C interrupt from Codec interrupt from Bluetooth Sequencer UART transmitter interrupt from Bluetooth Sequencer UART receiver Table 27 - RegIrqHigh register Pos 7 6 5 4 3 2 1 0 RegIrqMid UartTx UartRx Pa5 Pa4 1Hz WakeUp Pa1 Pa0 r/w rc1 rc1 rc1 rc1 rc1 rc1 rc1 rc1 Reset 0 0 0 0 0 0 0 0 Function interrupt from application UART transmitter interrupt from application UART receiver interrupt from port PA[5] interrupt from port PA[4] interrupt from ck1Hz low prescaler output interrupt from WAKEUP pin interrupt from port PA[1] interrupt from port PA[0] Table 28 - RegIrqMid register Pos 7 6 5 4 3 2 1 0 RegIrqLow Pa7 Pa6 CntB CntD Pa3 Pa2 UartHFlowControl UartFlowControl r/w rc1 rc1 rc1 rc1 rc1 rc1 rc1 rc1 Reset 0 0 0 0 0 0 0 0 Function interrupt from port PA[7] interrupt from port PA[6] interrupt from counter B interrupt from counter D interrupt from port PA[3] interrupt from port PA[2] interrupt from Bluetooth Sequencer UART flow control interrupt from application UART flow control Table 29 - RegIrqLow register Pos 7 6 5 4 3 2 1 RegIrqEnHig En128Hz EnSpi EnCntA EnCntC EnCodec EnUartHTx r/w r rw rw rw rw rw rw Reset 0 0 0 0 0 0 0 0 EnUartHRx rw 0 Function reserved enable interrupt from ck128Hz low prescaler output enable interrupt from SPI enable interrupt from counter A enable interrupt from counter C enable interrupt from Codec enable interrupt from Bluetooth Sequencer UART transmitter enable interrupt from Bluetooth Sequencer UART receiver Table 30 - RegIrqEnHig register © Semtech 2006 www.semtech.com 28 XE1431 XE1431 Bluetooth® SoC Pos 7 6 5 4 3 2 1 0 RegIrqEnMid EnUartTx EnUartRx EnPa5 EnPa4 En1Hz EnWakeUp EnPa1 EnPa0 r/w rc1 rc1 rc1 rc1 rc1 rc1 rc1 rc1 Reset 0 0 0 0 0 0 0 0 Function enable interrupt from application UART transmitter enable interrupt from application UART receiver enable interrupt from port PA[5] enable interrupt from port PA[4] enable interrupt from ck1Hz low prescaler output enable interrupt from WAKEUP pin enable interrupt from port PA[1] enable interrupt from port PA[0] Table 31 - RegIrqEnMid register Pos 7 6 5 4 3 2 1 RegIrqEnLow EnPa7 EnPa6 EnCntB EnCntD EnPa3 EnPa2 EnUartHFlowControl r/w rc1 rc1 rc1 rc1 rc1 rc1 rc1 Reset 0 0 0 0 0 0 0 0 EnUartFlowControl rc1 Function interrupt from port PA[7] interrupt from port PA[6] interrupt from counter B enable interrupt from counter D enable interrupt from port PA[3] enable interrupt from port PA[2] enable interrupt from Bluetooth Sequencer UART flow control enable interrupt from application UART flow control 0 Table 32 - RegIrqEnLow register Pos 7:0 RegIrqPriority IrqPriority r/w r Reset 11111111 Function Number of the highest priority interrupt set Table 33 - RegIrqPriority register Pos 7:3 2 RegIrqIrq HighIrqTriggered r/w r r Reset 00000 0 1 0 MidIrqTriggered LowIrqTriggered r r 0 0 Function reserved 1 = one or more high priority interrupt have been triggered 1 = one or more mid priority interrupt have been triggered 1 = one or more low priority interrupt have been triggered Table 34 ­ RegIrqIrq 3.6.3 Operation The XE1431 XE1431 supports 24 sources of interrupt, divided into 3 levels of priority: high (8 sources of interrupt), middle (8 sources of interrupt), and low (8 sources of interrupt). All sources of interrupt are sampled by the highest frequency available in the system. A CPU interrupt is generated and memorized when an interrupt source is triggered. The three levels of priority are directly mapped to those supported by the CoolRISC (IN0, IN1 and IN2; see the CoolRISC documentation for more information on the interrupt processing). RegIrqHig, RegIrqMid, and RegIrqLow are 8-bit registers containing flags for the interrupt sources. Those flags are set when the interrupt is enabled (i.e. if the corresponding bit in the registers RegIrqEnHig, RegIrqEnMid or RegIrqEnLow is set) and a rising edge is detected on the corresponding interrupt source. Once memorized, an interrupt flag can be cleared by writing a `1' in the corresponding bit of RegIrqHig, RegIrqMid or RegIrqLow. Writing a `0' does not modify the flag. To definitively clear the interrupt, one has to clear the CoolRISC interrupt in the CoolRISC status register in addition to cleaning the corresponding RegIrq register. All interrupts are automatically cleared after a reset. © Semtech 2006 www.semtech.com 29 XE1431 XE1431 Bluetooth® SoC Two registers are provided to facilitate the writing of interrupt service software. RegIrqPriority contains the number of the highest priority set (its value is 0xFF when no interrupt is memorized). RegIrqIrq indicates the priority level of the current interrupts. 3.7 EVENT CONTROLLER 3.7.1 · · Features Supports 8 sources of events Two levels of priority 3.7.2 Register map Name RegEvn RegEvnEn RegEvnPriority RegEvnEvn Address (Hex) 0x003C 0x003D 0x003E 0x003F Table 35 - Event controller registers Pos 7 6 5 4 3 2 1 0 RegEvn CntA CntC Pa1 CntB CntD 1Hz Pa0 r/w rc1 rc1 r rc1 rc1 rc1 rc1 rc1 Reset 0 0 0 0 0 0 0 0 Function event from counter A (high priority) event from counter C (high priority) reserved event from port PA[1] (high priority) event from counter B (low priority) event from counter D (low priority) event from ck1Hz low prescaler output event from port PA[0] Table 36 - RegEvn register Pos 7 6 5 4 3 2 1 0 RegEvnEn EnCntA EnCntC EnPa1 EnCntB EnCntD En1Hz EnPa0 r/w rw rw r rw rw rw rw rw Reset 0 0 1 0 0 0 0 0 Function enable event from counter A (high priority) enable event from counter C (high priority) reserved enable event from port PA[1] (high priority) enable event from counter B (low priority) enable event from counter D (low priority) enable event from ck1Hz low prescaler output enable event from port PA[0] Table 37 - RegEvnEn register Pos 7:0 RegEvnPriority EvnPriority r/w r Reset 00000000 Function number of the highest event triggered Table 38 - RegEvnPriority register © Semtech 2006 www.semtech.com 30 XE1431 XE1431 Bluetooth® SoC Pos 7:2 1 0 RegEvnEvn EvnHigh EvnLow r/w r r r Reset 000000 0 0 Function reserved 1 = one or more high priority event have been triggered 1 = one or more low priority event have been triggered Table 39 - RegEvnEvn register 3.7.3 Operation The XE1431 XE1431 supports 8 event sources, divided into 2 levels of priority. All sources of event are sampled by the highest frequency available in the system. A CPU event is generated and memorized when an event becomes source is triggered. The 8 sources of event are divided into 2 levels of priority: High (4 sources of event) and Low (4 sources of event). Those 2 levels of priority are directly mapped to those supported by the CoolRISC (EV0 and EV1; see CoolRISC documentation for more information on event processing). RegEvn is an 8-bit register containing flags for the sources of event. Those flags are set when the event is enabled (i.e. if the corresponding bit in the registers RegEvnEn is set) and a rising edge is detected on the corresponding event source. Once memorized, writing a `1' in the corresponding bit of RegEvn clears the event flag. Writing a `0' does not modify the flag. All events are automatically cleared after a reset. Two registers are provided to facilitate the writing of interrupt service software. RegEvnPriority contains the number of the highest event set (its value is 0xFF when no event is memorized). RegEvnEvn indicates the priority level of the current pending events. 3.8 DIGITAL INPUT PORT PA[7:0] 3.8.1 · · · · · · · Features Input port, 8-bit wide Each bit can be programmed individually for debounced or direct input, with pull-up or not Snap-to-rail option for each input Each bit can be configured as a source of interrupt on the rising or falling edge A system reset can be generated on an input pattern PA[0] and PA[1] can be configured to generate two events PA[0] to PA[3] can be used as clock inputs for the counters/timers/PWM 3.8.2 Register map Name RegPAIn RegPADebounce RegPAEdge RegPAPullup RegPARes0 RegPARes1 RegPACtrl RegPASnapToRail Address (Hex) 0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 0x0026 0x0027 Table 40 - PA registers Pos 7:0 RegPAIn PAIn r/w r Reset xxxxxxxx Function value of pads PA[7:0] Table 41 - RegPAIn register © Semtech 2006 www.semtech.com 31 XE1431 XE1431 Bluetooth® SoC Pos 7:0 RegPADebounce PADebounce r/w rw Reset 00000000 Function 1 = debouncer enabled (for each corresponding PA pad) 0 =debouncer disabled (for each corresponding PA pad) Table 42 - RegPADebounce register Pos 7:0 RegPAEdge PAEdge r/w rw Reset 00000000 Function 0 = positive edge (for each corresponding PA pad) 1 = negative edge (for each corresponding PA pad) Table 43 - RegPAEdge register Pos 7:0 RegPAPullup PAPullup r/w rw Pos 7:0 RegPARes0 PARes0 r/w rw Reset 11111111 Function 1 = pull-up enabled (for each corresponding PA pad) 0 = pull-up disabled (for each corresponding PA pad) Table 44 - RegPAPullup register Reset 00000000 Function for each corresponding PA pad: bit 0 of reset configuration (see 3.8.9) Table 45 - RegPARes0 register Pos 7:0 RegPARes1 PARes1 r/w rw Reset 00000000 Function for each corresponding PA pad: bit 1 of reset configuration (see 3.8.9) Table 46 - RegPARes1 register Pos 7:1 0 RegPACtrl DebounceSelect r/w rw rw Reset 0000000 0 Function reserved 1 = fast debounce clock selected 0 = slow debounce clock selected Table 47 - RegPACtrl register Pos 7:0 RegPASnapToRail SnapToRail r/w rw Reset 00000000 Function 1 = snap-to-rail mode enabled (for each corresp PA pad) 0 =snap-to-rail mode disabled (for each corresp PA pad) Table 48 - RegPASnapToRail register © Semtech 2006 www.semtech.com 32 XE1431 XE1431 Bluetooth® SoC 3.8.3 Block diagram The Figure 15 shows the block diagram of the port PA. Port A VDDIO_DIG 8 logic RegPASnapToRail 8 RegPAPullup 8 8 8x debounce RegPADebounce 0 RegPACtrl 8 8 1 1 0 DebFast (RegPACtrl(0) 1 8 events 8 8 1 interrupts 0 8x Vss RegPAIn RegPAEdge cntclocks Slow (1kHz) Fast (32kHz) RegPARes1 RegPARes0 11 10 01 0 resetfromporta 00 8x Figure 15 - Structure of PA[7:0] 3.8.4 Debounce mode Each bit of the port PA can be individually debounced by setting the corresponding bit in RegPADebounce. After reset, the debounce function is disabled. After enabling the debouncer, the change of the input value is accepted only if eight consecutive samples are identical. Selection of the clock is done by the bit DebounceSelect in register RegPACtrl. DebounceSelect 0 1 Debounce filter clock slow (ck1kHz low prescaler output) Fast (ck32kHz low prescaler output) Table 49 - Debouncer clock selection 3.8.5 Pull-ups/Snap-to-rail Different functions are possible depending on the value of the registers RegPAPullup and RegPASnapToRail. When the corresponding bit in RegPAPullup is cleared, the inputs are floating (pull-up and pull-down resistors are disconnected). When the corresponding bits are set in RegPAPullup is 1 and cleared in RegPASnapToRail , a pullup resistor is connected to the input pin. Alternatively, when the corresponding bits are cleared in RegPAPullup and set in RegPASnapToRail, the snap-to-rail function is active. The snap-to-rail function connects a pull-up or pull-down resistor to the input pin depending on the value last forced on the input pin. This function can be used for instance when the input port is connected to a tri-state bus. When the bus is floating, the pull-up or pull-down maintains the bus in the last low impedance state before it became floating until another low impedance output drives the bus. It also reduces the power consumption with respect to a classic pull-up since it selects the pull-up or pull-down resistor that matches the detected input state. © Semtech 2006 www.semtech.com 33 XE1431 XE1431 Bluetooth® SoC The state of input pin is summarized in the Table 50. RegPAPullup[i] 0 1 1 1 RegPASnapToRail[i] X 0 1 1 Last externally forced PA[i] value X X 0 1 PA[i] pull none (floating) pull-up pull-down pull-up Table 50 - PA pin state vs. RegPAPullup and RegPASnapToRail registers The port PA starts up with the pull-up resistor connected and the snap-to-rail function disabled. 3.8.6 Interrupt sources Every PA port input is an interrupt source which can be enabled on a rising or falling edge with the corresponding bit in RegPAEdge. After reset, the rising edge is selected for interrupt generation. The interrupt source can be debounced by setting register RegPADebounce. The interrupt signals are sampled on the fastest clock in the circuit. In order to guarantee that the interrupt is detected by the circuit, the minimal pulse length should be 1 cycle of this clock. Care must be taken when modifying RegPAEdge because this register performs an edge selection. The change of this register may result in a transition which may be interpreted as a valid interruption it the corresponding interrupt sources are not temporarily disabled in the interrupt controller. 3.8.7 Event sources Pins PA[0] and PA[1] are also available as events on the event controller. 3.8.8 Clock sources PA[0] to PA[3] input ports (debounced or not) are available as clock sources for the counter/timer/PWM peripherals. © Semtech 2006 www.semtech.com 34 XE1431 XE1431 Bluetooth® SoC 3.8.9 Reset sources The PA port can be configured to generate a system reset when a predetermined word is detected on PA[7:0]. The reset is built using a logical AND of the 8 PAReset[i] signals: resetfromportA = PAReset[7] AND PAReset[6] AND PAReset[5] AND . AND PAReset[0] PAReset[i] is itself a logical function of the corresponding pin PA[i]. One of four logical functions can be selected for each pin by writing into two registers RegPARes0 and RegPARes1 as shown in Table 51. PARes1[i] 0 0 1 1 PARes0[x] 0 1 0 1 PAReset[i] 0 PA[i] not PA[i] 1 Table 51 - PAReset generation A reset from port PA can be inhibited by placing a 0 on both PARes1[i] and PARes0[i] for at least 1 pin. Setting both RegPARes1[i] and RegPARes0[i] to 1, makes the reset independent of the value on the corresponding pin. Setting both registers to 0xff, will reset the circuit independently of the PA input value. This makes it possible to generate a software reset. Depending on the value of PA[0] to PA[7], the change of RegPARes0 and RegPARes1 can cause a reset. Therefore it is safe to always have one (RegPARes0[i], RegPARes1[i]) equal to 0x00 during the setting operations. 3.9 DIGITAL INPUT/OUTPUT PORT PB[7:0] 3.9.1 · · · · · · · · Features 8-bit wide input/output port Each bit can be configured as input or output Each bit can be configured as open-drain or push-pull A pull-up can be enabled on each bit In open-drain mode, the pull-up is not active when corresponding pad is set to zero Two internal freq. (ck32kHz and CkCpu) can be output on PB[2] and PB[3] Two PWM signals can be driven on pads PB[0] and PB[1] The UART interface uses PB[7:4] for UA_RX, UA_TX, UA_RTS and UA_CTS respectively 3.9.2 Register map Name RegPBOut RegPBIn RegPBDir RegPBOpen RegPBPullup Address (Hex) 0x0028 0x0029 0x002A 0x002B 0x002C Table 52 - port PB registers Pos 7:0 RegPBout PBOut r/w rw Reset 00000000 Function port output value Table 53 - RegPBOut register © Semtech 2006 www.semtech.com 35 XE1431 XE1431 Bluetooth® SoC Pos 7:0 RegPBIn PBIn r/w r Reset xxxxxxxx Function input value, read from pads PB[7:0] Table 54 - RegPBIn register Pos 7:0 RegPBDir PBDir r/w rw Reset 00000000 Function for each corresponding PB pad: 1 = pad is configured as digital output 0 = pad is configured as digital input Table 55 - RegPBDir register Pos 7:0 RegPBOpen PBOpen r/w rw Reset 00000000 Function for each corresponding PB pad: 1 = pad is configured as open drain 0 = pad is configured as push-pull Table 56 - RegPBOpen register Pos 7:0 RegPBPullup PBPullup r/w rw Reset 11111111 Function for each corresponding PB pad: 1 = pull-up enabled 0 = pull-up disabled Table 57 - RegPBPullup 3.9.3 Multiplexing PB with other peripherals Port PB acts as a GPIO port by default. This functionality can be overridden as other functions are enabled as shown in Table 58. Port PB number 7 6 5 4 3 2 1 0 Priority Medium UA_RX UA_TX UA_RTS UA_CTS ck32k CPU clock counter C (C+D) PWM1 counter A (A+B) PWM0 Low GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Table 58 - PB[7:0] usage When the counters are used to implement a PWM function (see 3.10), the PB[0] and PB[1] terminals are used as outputs (PB[0] is used if bit 0 in RegCntConfig1 is set to 1, PB[1] is used if bit 1 in RegCntConfig1 is set to 1) and the PWM generated values override the values written in RegPBout. However, RegPBDir[0] and RegPBDir[1] are not automatically overwritten and have to be set to 1. If bit 1 is set in RegSysMisc, the ck32kHz low prescaler output is output on PB[3]. This overrides the value contained in RegPBOut[3]. However, RegPBDir[3] must be set to 1. The frequency and duty cycle of the clock signal are given in Figure 16. © Semtech 2006 www.semtech.com 36 XE1431 XE1431 Bluetooth® SoC 1/fckRCext 1/fck32kHz Figure 16 - ck32k output clock timing Similarly, If bit 0 is set in RegSysMisc, the CPU clock is output on PB[2] as described on Figure 17. This overrides the value contained in RegPBOut[2]. However, RegPBDir[2] must be set to 1. 1/f1 1/f2 Figure 17 - CPU output clock timing The timing of the CPU clock depends on the selection of the bit CpuSel in the RegSysClock register and is given in Table 59. CpuSel 0 1 f1 fckRCext/4 fckRCext f2 fckRCext fck32kHz Table 59 - CPU clock on PB[2] timing 3.9.4 Port B digital capabilities The direction of each bit within PB[7:0] (input only or input/output) can be individually set using the RegPBDir register. If RegPBDir[i] = 1, both the input and output buffers are active on the corresponding pin. If RegPBDir[i] is 0, the corresponding PB pin is an input only and the output buffer is in high impedance. After reset PB is in input only mode; RegPBDir[i] is reset to 0. The input values of PB are available in RegPBIn (read only). Reading is always direct - there is no debounce function. In case of possible noise on input signals, a software debouncer with polling or an external hardware filter has to be realized. The input buffer is also active when the port is defined as output and allows reading back of the effective value on the pin. Data stored in RegPBOut are output at Port B if RegPBDir[x] is 1. The default value after reset is low (0). When a pin is in output mode (RegPBDir[i] is set), the output can be a conventional CMOS (Push-Pull) or an Nchannel Open-drain, driving the output low. By default, after reset the RegPBOpen is cleared (push-pull). If RegPBOpen[i] is set the internal P-channel transistor in the output buffer is electrically removed and the output can only be driven low with RegPBOut[i] cleared, or be high-impedance when RegPBOut[i] is set. The internal pull-up or an external pull-up resistor can be used to drive the pin high. Because the P-channel transistor actually exists (this is not a real Open-drain output) the pull-up range is limited to VDDIO_DIG + 0.2V (avoid forward bias of the P transistor / diode). An optional pull-up can be connected to every bit by configuring RegPBPullup. Input is pulled up when its corresponding bit in this register is set. Default status after reset is 1, which means with pull-up. To limit power consumption, pull-up resistors are only enabled when the associated pin is either a digital input or an N-channel opendrain output with the pad set (n-channel transistor disabled). In the other cases (push-pull output or open-drain output driven low), the pull up resistors are disabled independently from RegPBPullup. After power-on reset, the Port B is configured as an input port with pull-up activated. The input buffer is always active. This means that the PB input should be a valid digital value at all time. An unused pin should be configured as input pull-up or output. Violating this rule may lead to high power consumption. © Semtech 2006 www.semtech.com 37 XE1431 XE1431 Bluetooth® SoC 3.10 COUNTERS/TIMERS 3.10.1 · · · · · · · · · Features 4 x 8-bits timer/counter modules or 2 x 16-bits timers/counter modules, each with 4 possible clock sources Up/down counter modes Interrupt and event generation Capture function (internal or external source) Rising, falling or both edge of capture signal (except for ck32k, only rising edge) PA[3:0] can be used as clock inputs (debounced or direct, frequency divided by 2 or not) 2 x 8 bits PWM or 2 x 16 bits PWM PWM resolution of 8, 10, 12, 14 or 16 bits Complex mode combinations are possible 3.10.2 Register map Name RegCntA RegCntB RegCntC RegCntD RegCntCtrlCk RegCntConfig1 RegCntConfig2 RegCntOn Address (Hex) 0x0058 0x0059 0x005A 0x005B 0x005C 0x005D 0x005E 0x005F Table 60 - Counter Registers Pos 7:0 RegCntA CntA r/w rw Reset 00000000 Function counter A (1) Table 61 - RegCntA register Pos 7:0 RegCntB CntB r/w rw Reset 00000000 Function counter B (1) Table 62 - RegCntB registers Pos 7:0 RegCntC CntC r/w rw Reset 00000000 Function counter C (2) Table 63 - RegCntC register Pos 7:0 RegCntD CntD r/w rw Reset 00000000 Function counter D (2) Table 64 - RegCntD register Pos 7:6 5:4 3:2 1:0 RegCntCtrlCk CntDCkSel CntCCkSel CntBCkSel CntACkSel r/w rw rw rw rw Reset 00 00 00 00 Function counter D clock selection counter C clock selection counter B clock selection counter A clock selection Table 65 - RegCntCtrlCk register © Semtech 2006 www.semtech.com 38 XE1431 XE1431 Bluetooth® SoC Pos 7 RegCntConfig1 CntDDownUp r/w rw Reset 0 6 CntCDownUp rw 0 5 CntBDownUp rw 0 4 CntADownUp rw 0 3 CascadeCD rw 0 2 CascadeAB rw 0 1 CntPWM1 rw 0 0 CntPWM0 rw 0 Function 1 = counter D counting up 0 = counter D counting down 1 = counter C counting up 0 = counter C counting down 1 = counter B counting up 0 = counter B counting down 1 = counter A counting up 0 = counter A counting down 1 = cascade counters C and D 0 = do not cascade counters C and D 1 = cascade counter A and B 0 = do not cascade counters A and B 1 = counter C (or C + D) PWM enabled 0 = counter C (or C + D) PWM disabled 1 = counter A (or A + B) PWM enabled 0 = counter A (or A + B) PWM disabled Table 66 - RegCntConfig1 register Pos 7:6 5:4 3:2 1:0 RegCntConfig2 CapSel CaptFunc Pwm1Size Pwm0Size r/w rw rw rw rw Reset 00 00 00 00 Function capture source selection capture function selection PWM1 size selection PWM0 size selection Table 67 - RegCntConfig2 register Pos 7 Reset 0 CntCExtDiv rw 0 5 CntBExtDiv rw 0 4 CntAExtDiv rw 0 3 CntDEnable rw 0 2 CntCEnable rw 0 1 CntBEnable rw 0 0 (2) r/w rw 6 (1) RegCntOn CntDExtDiv CntAEnable rw 0 Function 1 = divide external clock PA[3] by 2 0 = do not divide 1 = divide external clock PA[2] by 2 0 = do not divide 1 = divide external clock PA[1] by 2 0 = do not divide 1 = divide external clock PA[0] by 2 0 = do not divide 1 = counter D enabled 0 = counter D disabled 1 = counter C enabled 0 = counter C disabled 1 = counter B enabled 0 = counter B disabled 1 = counter A enabled 0 = counter A disabled When writing to RegCntA or RegCntB, the processor writes the counter comparison values. When reading these locations, the processor reads back either the actual counter value or the last captured value if the capture mode is active. When writing RegCntC or RegCntD, the processor writes the counter comparison values. When reading these locations, the processor reads back the actual counter value. Table 68 - RegCntOn register © Semtech 2006 www.semtech.com 39 XE1431 XE1431 Bluetooth® SoC 3.10.3 General Operation Overview Counter A and Counter B are 8-bit counters which can be cascaded to form 16-bit counters. Counter C and Counter D have the same features. The counters can also be used to generate two PWM outputs on PB[0] and PB[1]. PWM signals can be generated with 8-, 10-, 12-, 14- or 16-bit precision. Counters A and B can be captured by events on an internal or an external signal. The capture can be performed on both 8-bit counters running individually on two different clock sources or on both cascaded counters to form a 16-bit counter. In any case, the same capture signal is used for both counters. When the counters A and B are not cascaded, they can be used in several configurations: A and B as counters, A and B as captured counters, A as PWM and B as counter, A as PWM and B as captured counter. When counters C and D are not cascaded, both can be used either as counters or counter C as PWM and counter D as counter. Counters are enabled by RegCntOn. When counters are cascaded, the bit CntBEnable controls the counter A + B, and CntDEnable controls the counter C + D. All counters have a corresponding 8-bit read/write register: RegCntA, RegCntB, RegCntC, and RegCntD. When read, these registers contain the counter value (or the captured counter value). When written, they modify the counter comparison values. It is possible to read any counter at any time, even when the counter is running. The value is guaranteed to be correct when the counter is running on an internal clock source. For correct acquisition of the counter value when running on an external clock source, use one of the three following methods: 1) 2) 3) For slow operating counters (typically at least 8 times slower than the CPU clock), over-sample the counter content and perform a majority operation on the consecutive read results to select the correct actual content of the counter. Stop the concerned counter, perform the read operation and restart the counter. While stopped, the counter content is frozen and the counter does not take into account the clock edges delivered on the external pin. Use the capture mechanism. When a value is written into the counter register while the counter is in counter mode, both the comparison value is updated and the counter value is modified. In upcount mode, the register value is reset to zero. In downcount mode, the comparison value is loaded into the counter. Due to the synchronization mechanism between the processor clock domain and the external clock source domain, this modification of the counter value can be postponed until the counter is enabled and receives its first valid clock edge. In PWM mode or in capture mode, the counter value is not modified by the write operation in the counter register. Changing to counter mode does not update the counter value (no reset in upcount, no load in downcount mode). 3.10.4 Clock selection The clock source for each counter can be individually selected by writing the appropriate value in the register RegCntCtrlCk. Table 69 gives the correspondence between the binary codes used for the configuration bits RegCntCtrlCk[1:0], RegCntCtrlCk[3:2], RegCntCtrlCk[5:4] or RegCntCtrlCk[7:6] and the clock source selected respectively for the counters A, B, C or D. RegCntCtrlCk[i:j] Clock source for 11 10 01 00 Counter A Counter B 128 Hz timer from clock controller ckRCext / 4 ckRCext PA[0] PA[1] Counter C Counter D ck1kHz low prescaler output ck32kHz low prescaler output PA[2] PA[3] Table 69 - Counter clock selection See chapter 0 for details about the different clock sources. Four external clocks may be provided to the counters through pins PA[3:0]. Optionally, the external clock sources can be debounced by configuring the port PA. Additionally, the external clocks may be divided by 2 by configuring RegCntOn[7:4]. © Semtech 2006 www.semtech.com 40 XE1431 XE1431 Bluetooth® SoC Switching between an internal and an external clock source can only be performed while the counter is stopped. Enabling or disabling the external clock frequency division can only happen when the counter using this clock is stopped, or when this counter is running on an internal clock source. 3.10.5 Mode selection Each counter can be configured in the following modes: Counter Capture PWM Captured PWM The counter mode is set by writing the registers RegCntConfig1 and RegCntConfig2. RegCntConfig1 [2] RegCntConfig1 [0] RegCntConfig2 [5:4] 0 0 00 1 0 00 0 1 00 1 1 00 0 0 1 0 0 1 1 1 1X or X1 1X or X1 1X or X1 1X or X1 Counter A mode Counter B mode Counter A IRQ source Counter B PB[0] Counter AB - PB[0] - Counter B PWM A - - PWM AB Capture A Capture B PB[0] Capture AB Capture AB PB[0] Capture A Capture B PWM A Capture AB Captured Captured PWM 8b counter 8b Downup: A Downup: B Captured 10 ­ 16b PWM (captured value on 16b) Downup: A PB[0] function Counter A Counter 8b Counter 8b Downup: A Downup: B Counter 16b AB Downup: A PWM 8b Counter 8b Downup: A Downup: B PWM 10 ­ 16b AB Downup A Captured Captured counter 8b counter 8b Downup: A Downup: B Captured counter 16b AB Downup: A Counter B IRQ source Capture AB PWM AB Table 70 ­ Counters A&B operation modes Switching between different modes must be done while the concerned counters are stopped. While switching capture mode on and off, unwanted interrupts can appear on the interrupt channels concerned by this mode change. The Table 71 shows the operation modes for counters C and D as a function of the mode control bits. RegCntConfig1 [3] [1] 0 0 1 0 0 1 1 1 Counter C Counter D mode mode Counter 8b Counter 8b Downup: C Downup: D Counter 16b CD Downup: C PWM 8b Counter 8b Downup: C Downup: D PWM 10 ­ 16b CD Downup: C Counter C IRQ source Counter C Counter D IRQ source Counter D PB[1] function PB(1) Counter CD - PB(1) - Counter D PWM C - - PWM CD Table 71 - Counters C&D: operation modes © Semtech 2006 www.semtech.com 41 XE1431 XE1431 Bluetooth® SoC 3.10.6 Counter / Timer mode The counters in counter / timer mode are used to generate interrupts after a predefined number of clock periods applied on the counter clock input have elapsed. Each counter can be set individually either in upcount mode by setting bit 4 to 7 in register RegCntConfig1 or in downcount mode by resetting these bit. Counters A and B can be cascaded to behave as a 16-bit counter by setting RegCntConfig1[2]. Counters C and D can be also cascaded by setting RegCntConfig1[3]. When cascaded, the up/down count modes of counters B and D are defined respectively by the up/down count modes set for the counters A and C. When in upcount mode, the counter will start incrementing from zero up to the target value which has been written in the corresponding RegCntX register(s). When the counter content is equal to the target value, an interrupt is generated at the next counter clock pulse and the counter is loaded again with the zero value as described in Figure 18. When in downcount mode, the counter will start counting down from the initial load value which has been written in the corresponding RegCntX register(s) down to the zero value. Once the counter content is equal to zero, an interrupt is generated at the next counter clock pulse and the counter is loaded again with the load value as described in Figure 18. The counter must be configured (capture, PWM, cascade, up/down counting mode) before writing any target value to RegCntX register(s). This ensures that the counter will start from the correct initial value. When counters are cascaded, both counter registers must be written to ensure that both cascaded counters will start from the correct initial values. Stopping and restarting a counter in counter mode without reloading a target or load value write can generate an unwanted interrupt if this counter has been stopped at the zero value (downcount) or at it is target value (upcount). This interrupt has already been generated when the counter has reached the zero or the target value. down counting clock counter X RegCntX_r XX RegCntX_w 3 XX 2 1 0 3 2 1 0 3 2 1 0 3 write RegCntX RegCntConfig1 (bit 4, 5, 6 or 7) IrqX RegCntOn (bit 0, 1, 2 or 3) up counting clock counter X XX RegCntX_r RegCntX_w 0 1 XX 2 3 0 1 2 3 0 1 2 3 3 write RegCntX RegCntConfig1 (bit 4, 5, 6 or 7) IrqX RegCntOn (bit 0, 1, 2 or 3) Figure 18 - Up and down count interrupt generation © Semtech 2006 www.semtech.com 42 XE1431 XE1431 Bluetooth® SoC 3.10.7 PWM mode The counters can generate PWM signals (Pulse Width Modulation) on port PB outputs PB[0] and PB[1]. The PWM mode is selected by setting RegCntConfig1[0] or RegCntConfig1[1]