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XC95288XL-10CSG280C Xilinx Flash PLD, 10ns, 288-Cell, CMOS, PBGA280, LEAD FREE, CSP-280 visit Digikey Buy
XC95288XL-10TQ144C Xilinx Flash PLD, 10ns, 288-Cell, CMOS, PQFP144, TQFP-144 visit Digikey Buy
XC95288XL-6PQ208C Xilinx Flash PLD, 6ns, 288-Cell, CMOS, PQFP208, PLASTIC, QFP-208 visit Digikey Buy
XC95288XL-7CSG280C Xilinx Flash PLD, 7.5ns, 288-Cell, CMOS, PBGA280, LEAD FREE, CSP-280 visit Digikey Buy
XC95288XL-7TQ144C Xilinx Flash PLD, 7.5ns, 288-Cell, CMOS, PQFP144, TQFP-144 visit Digikey Buy
XC95288XL-10FG256C Xilinx Flash PLD, 10ns, 288-Cell, CMOS, PBGA256, PLASTIC, FBGA-256 visit Digikey Buy

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XC95288 Datasheet

Part Manufacturer Description PDF Type
XC95288 Xilinx XC95288XL High Performance CPLD Original
XC95288 Xilinx The Programmable Logic Data Book Original
XC95288-10BG352C Xilinx 288 MACROCELL 5 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN Original
XC95288-10BG352C Xilinx In-System Programmable CPLD Original
XC95288-10BG352C Xilinx In-System Programmable CPLD Original
XC95288-10BG352C Xilinx Embedded - CPLDs (Complex Programmable Logic Devices), Integrated Circuits (ICs), IC CPLD 288MC 10NS 352BGA Original
XC95288-10BG352I Xilinx In-System Programmable CPLD Original
XC95288-10BGG352C Xilinx XC95288-10BGG352C - NEW PRODUCT Original
XC95288-10HQ208C Xilinx 288 MACROCELL 5 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN Original
XC95288-10HQ208C Xilinx In-System Programmable CPLD Original
XC95288-10HQ208C Xilinx In-System Programmable CPLD Original
XC95288-10HQ208C Xilinx Embedded - CPLDs (Complex Programmable Logic Devices), Integrated Circuits (ICs), IC CPLD 288MC 10NS 208HQFP Original
XC95288-10HQ208I Xilinx In-System Programmable CPLD Original
XC95288-15BG352C Xilinx In-System Programmable CPLD Original
XC95288-15BG352C Xilinx 288 MACROCELL 5 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN Original
XC95288-15BG352C Xilinx In-System Programmable CPLD Original
XC95288-15BG352C Xilinx Embedded - CPLDs (Complex Programmable Logic Devices), Integrated Circuits (ICs), IC CPLD 288MC 15NS 352BGA Original
XC95288-15BG352I Xilinx In-system programmable CPLD. Speed 15ns pin-to-pin delay. Original
XC95288-15BG352I Xilinx 288 MACROCELL 5 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN Original
XC95288-15BG352I Xilinx In-System Programmable CPLD Original
Showing first 20 results.

XC95288

Catalog Datasheet MFG & Type PDF Document Tags

BG352

Abstract: HQ208 XC95288-15 Symbol Parameter XC95288-20 Min Max Min Max Units - 15.0 - , XC95288-15BG352I 15 ns BG352 352-ball Ball Grid Array (BGA) I XC95288-20HQ208C 20 ns , Specification R XC95288 In-System Programmable CPLD Internal Timing Parameters XC95288-15 Symbol Parameter XC95288-20 Min Max Min Max Units Buffer Delays TIN Input buffer delay , (pin-to-pin delay) Pkg. Symbol No. of Pins Package Type Operating Range(1) XC95288-10HQ208C
Xilinx
Original
XC9500 HQ208 n439 DS069 36V18 XC9528 XC95288-15HQ208C

XC95288

Abstract: HQ208I Low) XC95288-15 XC95288-20 Min Min Max 15.0 8.0 0.0 20.0 10.0 0.0 8.0 , Allocator delay tSLEW Slew-rate limited delay XC95288-15 XC95288-20 Min Min Max Max , 1 XC95288 In-System Programmable CPLD ® December 4, 1998 (Version 3.0) 1 1 , dissipation can be reduced in the XC95288 by configuring macrocells to standard or low-power modes of , Description The XC95288 is a high-performance CPLD providing advanced in-system programming and test
Xilinx
Original
HQ208I X7131 X5906 208-P 352-P
Abstract: Figure 3: AC Load Circuit Internal Timing Parameters XC95288-15 Symbol XC95288-20 Parameter , AC Characteristics XC95288-15 Symbol Parameter Min IPD I/O to output valid isu I , I/O setup tim e before p-term clock input ipsu XC95288-20 Min 15.0 Max 20.0 10.0 , Iq q v s . Frequency For XC95288 Description The XC95288 is a high-performance CPLD providing , in the XC95288 by con­ figuring macrocells to standard or low-power modes of operation. Unused -
OCR Scan
XC95286

xc95288

Abstract: BG352 marking. Device Ordering and Part Marking Number XC95288-10HQ208C XC95288-10BG352C XC95288-15HQ208C XC95288-15BG352C XC95288-15HQ208I XC95288-15BG352I XC95288-20HQ208C XC95288-20BG352C XC95288-20HQ208I , AC Characteristics XC95288-15 Symbol TPD TSU TH TCO fCNT(1) fSYSTEM TPSU TPH TPCO TOE TOD TPOE TPOD TWLH (2) XC95288-20 Min 10.0 0 83.3 50.0 4.0 6.0 5.5 Max 20.0 10.0 16.0 16.0 16.0 18.0 18.0 Units , Programmable CPLD Internal Timing Parameters XC95288-15 Symbol Buffer Delays TIN TGCK TGSR TGTS TOUT TEN
Xilinx
Original
XC95288-20HQ208 TQ144 XC95288-20BG352I

10HQ

Abstract: 471 E25 enabled Product term OE to output disabled GCK pulse width (High or Low) XC95288-10 XC95288-15 XC95288-20 Min Min Max 10.0 6.0 0.0 111.1 66.7 2.0 4.0 Min 15.0 8.0 0.0 6.0 , Time Adders tPTA3 Incremental Product Term Allocator delay tSLEW Slew-rate limited delay XC95288-10 XC95288-15 XC95288-20 Min Min Max Max Min Max Units 3.5 2.5 6.0 6.0 3.0 0.0 , 0 XC95288 In-System Programmable CPLD ® September 15, 1999 (Version 4.0) 0 5
Xilinx
Original
10HQ 471 E25

XC95288

Abstract: Marking af1 Sample package with part marking. Device Ordering and Part Marking Number XC95288-10HQ208C XC95288-10BG352C XC95288-15HQ208C XC95288-15BG352C XC95288-15HQ208I XC95288-15BG352I XC95288-20HQ208C XC95288-20BG352C XC95288-20HQ208I XC95288-20BG352I Speed (pin-to-pin delay) 10 ns 10 ns 15 ns 15 ns 15 ns 15 ns 20 ns 20 , XC95288 In-System Programmable CPLD R AC Characteristics XC95288-15 Symbol TPD TSU TH TCO fCNT (1) (2) XC95288-20 Min 10.0 0 83.3 50.0 4.0 6.0 5.5 8.0 Max 20.0 10.0 16.0 16.0 16.0 18.0 18.0 Units
Xilinx
Original
Marking af1 AF24 marking

XC95288-15HQ208I

Abstract: part marking. Device Ordering and Part Marking Number XC95288-10HQ208C XC95288-10BG352C XC95288-15HQ208C XC95288-15BG352C XC95288-15HQ208I XC95288-15BG352I XC95288-20HQ208C XC95288-20BG352C XC95288-20HQ208I , In-System Programmable CPLD AC Characteristics XC95288-15 Symbol TPD TSU TH TCO fCNT(1) fSYSTEM(2) TPSU , ) Min 8.0 0 95.2 55.6 4.0 4.0 5.5 8.0 Max 15.0 8.0 12.0 11.0 11.0 14.0 14.0 XC95288-20 Min 10.0 0 83.3 , Programmable CPLD Internal Timing Parameters XC95288-15 Symbol Buffer Delays TIN TGCK TGSR TGTS TOUT TEN
Xilinx
Original
XCN11010

XC95288

Abstract: HQ208 ® XC95288 In-System Programmable CPLD June 1, 1996 (Version 1.0) Advance Product Specification Features Description · · · · · The XC95288 is a high-performance CPLD providing , Management Power dissipation can be reduced in the XC95288 by configuring macrocells to standard or , frequency (MHz) 3-57 XC95288 In-System Programmable CPLD 3 JTAG Port 1 JTAG Controller , Macrocells 1 to 18 X5924 Figure 1: XC95288 Architecture Note: Function Block outputs indicated by
Xilinx
Original

XC95288

Abstract: cpld xc9572 . 3-47 3-47 3-47 3-49 3-49 3-49 3-50 3-51 3-52 3-53 3-54 3-55 3-55 XC95288 In-System Programmable CPLD , . XC95288 I/O P in s. XC95288 I/O Pins (continued). XC95288 I/O Pins (con tinu ed). XC95288 I/O Pins (con tinu ed
-
OCR Scan
cpld xc9572 XC952 XC95432 XC95576

RES 364

Abstract: . 3-55 3-55 3-55 3-57 3-57 3-57 3-58 3-58 3-59 3-60 3-61 3-62 3-63 3-64 3-64 XC95288 In-System , . XC95288 I/O P in s. XC95288 I/O Pins (con tinu ed). XC95288 I/O Pins (continued). XC95288 I/O Pins (continued
-
OCR Scan
RES 364

471 E25

Abstract: XC95288-15HQ208I XC95288 In-System Programmable CPLD AC Characteristics XC95288-15 Symbol Parameter XC95288-20 , Programmable CPLD Internal Timing Parameters XC95288-15 Symbol Parameter XC95288-20 Min Max , ) XC95288-10HQ208C 10 ns HQ208 208-pin Heat Sink Quad Flat Pack (HQFP) C XC95288-10BG352C 10 ns BG352 352-ball Ball Grid Array (BGA) C XC95288-15HQ208C 15 ns HQ208 208 , ) I XC95288-15BG352I 15 ns BG352 352-ball Ball Grid Array (BGA) I XC95288-20HQ208C
Xilinx
Original
AD9318 h3144 A23 780-4
Abstract: XC95288-15 Symbol *PD ts u tH *0 0 fCNT1 Parameter Min I/O to output valid I/O setup time before GCK I/O , ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns XC95288-20 Units ^SYSTEM 2 Multiple FB internal , Figure 3: AC Load Circuit Internal Timing Parameters XC95288-15 Symbol Buffer Delays t|N ÎGCK teSR , 7.5 11.0 4.5 0.0 6.5 3.0 9.5 16.0 6.5 0.0 ns ns ns ns ns ns Parameter Min Max Min Max XC95288-20 Units , flXIUNX December 4, 1998 (Version 3.0) XC95288 In-System Programmable CPLD Product -
OCR Scan
Abstract: flX IU N X June 1, 1996 (Version 1.0) XC95288 In-System Programmable CPLD Advance Product , -pin HQFP packages Description The XC95288 is a high-performance CPLD providing advanced in-system , architec ture overview. Power Management Power dissipation can be reduced in the XC95288 by con , macrocells used f = Clock frequency (MHz) June 1, 1996 (Version 1.0) 3-57 XC95288 In-System Programmable CPLD X5924 Figure 1: XC95288 Architecture Note: Function Block outputs indicated by bold -
OCR Scan

BG352

Abstract: HQ208 Low) XC95288-10 XC95288-15 XC95288-20 Min Max 10.0 6.5 0.0 Min Max 15.0 8.0 0.0 , XC95288-10 XC95288-15 XC95288-20 Min Max Min Max Min Max Units 3.5 3.0 6.0 10.0 , ® XC95288 In-System Programmable CPLD January, 1997 (Version 1.0) Advanced Product , -pin HQFP and 352-pin BGA packages The XC95288 is a high-performance CPLD providing advanced in-system , the XC95288 by configuring macrocells to standard or low-power modes of operation. Unused macrocells
Xilinx
Original
Abstract: Internal Timing Parameters XC95288-15 Symbol XC95288-20 Parameter Units Min Max Min , , active) V, = GND, No load f = 1.0 MHz V OL 300 (Typ) ma AC Characteristics XC95288-15 , input ip s u I/O hold tim e after p-term clock input IpH XC95288-20 Min 15.0 Max 20.0 , used = Clock frequency (MHz) Figure 1 : Typical Iq q v s . Frequency For XC95288 Description The XC95288 is a high-performance CPLD providing advanced in-system programming and test -
OCR Scan

AC1284

Abstract: XC95288-15 Symbol Units Min tpD lSU tH I/O to output valid I/O setup time before GCK I/O , disable Product term OE to output enabled l OE XC95288-20 Parameter 16.0 20.0 ns ns , Parameter Symbol XC95288-15 Buffer Delays Input buffer delay % l GCK *GSR *GTS 'out »HI , {SUI XC95288-20 Units Min 2.5 3.0 15.5 ns ns ns 3.0 13.5 3.0 4.0 ns 0.5 , KXILINX XC95288 In-System Programmable CPLD April, 1997 (Version 1.0) Preliminary Product
-
OCR Scan
AC1284
Abstract: load f = 1.0 MHz 10.0 260 (Typ) pF ma AC Characteristics XC95288-10 Symbol (PD *SU Parameter , ultiple FBs. XC9528B-15 Min 8.0 0.0 8.0 Max 15.0 XC95288-20 Units Min 10.0 0.0 10.0 83 50 4.0 6.0 , Parameters XC95288-10 Sym bol Buffer Delays l IN l GCK *GSR `gts `out Input buffer delay GCK buffer delay , the span of the function as defined in the fam ily data sheet. XC95288-15 Min Max 4.5 3.0 7.5 15.0 4.5 0.0 2.5 3.0 13.5 3.0 3.5 4.5 0.5 8.0 XC95288-20 Units Min Max 6.5 3.0 9.5 20.0 6.5 0.0 2.5 3.0 -
OCR Scan

F25-F26

Abstract: 2.4 0.5 0.4 ±10.0 ±10.0 10.0 300 (Typ) V V uA HA pF ma AC Characteristics Parameter XC95288-15 Min , 15.0 10.0 0.0 10.0 XC95288-20 Min Max 20.0 Units ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns I/O to , 35 pF 35 pF Figure 3: AC Load Circuit Internal Timing Parameters Symbol Parameter XC95288-15 , 3.5 6.5 0.5 9.0 XC95288-20 Min Max 6.5 3.0 9.5 20.0 6.5 0.0 2.5 3.0 15.5 4.0 Units ns ns ns ns ns , flXILINX N o vem b er 12, 1997 (V ersion 2.0) XC95288 In-System Programmable CPLD Preliminary
-
OCR Scan
F25-F26

A23 780-4

Abstract: 471 E25 ) XC95288-15 XC95288-20 Min Max Min 15.0 8.0 0.0 Max 20.0 10.0 0.0 8.0 95 56 4.0 , Adders tPTA3 Incremental Product Term Allocator delay tSLEW Slew-rate limited delay XC95288-15 XC95288-20 Min Max Min Max Units 4.5 3.0 7.5 15.0 4.5 0.0 6.5 3.0 9.5 20.0 6.5 , 0 XC95288 In-System Programmable CPLD ® November 12, 1997 (Version 2.0) 0 3 , ) 100 X7131 Figure 1: Typical ICC vs. Frequency For XC95288 Description The XC95288 is a
Xilinx
Original
Abstract: HXILINX XC95288 In-System Programmable CPLD June 1,1 9 9 6 (Version 1.0) Advance Product Specification Features Description â'¢ â'¢ â'¢ â'¢ â'¢ The XC95288 is a high-performance CPLD , the XC95288 by con­ figuring macrocells to standard or low-power modes of operation. Unused , low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) 3-57 XC95288 In-System , : XC95288 Architecture Note: Function Block outputs indicated by bold line drive directly to I/O Blocks -
OCR Scan
Showing first 20 results.