XC95108 36V18 XC9500 X5898 X5897 XC95108-7 XC95108-10 XC95108-15 XC95108-20 - Datasheet Archive

 

XC95108 In-System Programmable CPLD ® October 28, 1997 (Version 2.0) 0 3* Product Specification Features Power Management

 

0 XC95108 XC95108 In-System Programmable CPLD ® October 28, 1997 (Version 2.0) 0 3* Product Specification Features Power Management · · · · · Power dissipation can be reduced in the XC95108 XC95108 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. · · · · · · · · · · · Description The XC95108 XC95108 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of six 36V18 36V18 Function Blocks, providing 2,400 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architecture overview. Operating current for each design can be approximated for specific operating conditions using the following equation: ICC (mA) = MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f Where: MCHP = Macrocells in high-performance mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC95108 XC95108 device. 300 (250) e rmanc erfo High P Typical ICC (mA) · · 7.5 ns pin-to-pin logic delays on all pins fCNT to 125 MHz 108 macrocells with 2400 usable gates Up to 108 user I/O pins 5 V in-system programmable (ISP) - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 36V18 Function Block - 90 product terms drive any or all of 18 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 1149.1 boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 mA outputs 3.3 V or 5 V I/O capability PCI compliant (-7, -10 speed grades) Advanced CMOS 5V FastFLASH technology Supports parallel programming of more than one XC9500 XC9500 concurrently Available in 84-pin PLCC, 100-pin PQFP, 100-pin TQFP and 160-pin PQFP packages 200 (180) (170) ower Low P 100 0 50 Clock Frequency (MHz) 100 X5898 X5898 Figure 1: Typical ICC vs. Frequency for XC95108 XC95108 October 28, 1997 (Version 2.0) 3-37 XC95108 XC95108 In-System Programmable CPLD 3 JTAG Port 1 JTAG Controller In-System Programming Controller 36 18 I/O Function Block 1 Macrocells 1 to 18 I/O I/O I/O Blocks I/O I/O I/O FastCONNECT Switch Matrix I/O 36 18 Function Block 2 Macrocells 1 to 18 36 18 Function Block 3 Macrocells 1 to 18 I/O 3 I/O/GCK 36 1 I/O/GSR I/O/GTS 18 2 36 18 36 18 Function Block 4 Macrocells 1 to 18 Function Block 5 Macrocells 1 to 18 Function Block 6 Macrocells 1 to 18 X5897 X5897 Figure 2: XC95108 XC95108 Architecture Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly 3-38 October 28, 1997 (Version 2.0) Absolute Maximum Ratings Symbol VCC VIN VTS TSTG TSOL Parameter Supply voltage relative to GND DC input voltage relative to GND Voltage applied to 3-state output with respect to GND Storage temperature Max soldering temperature (10 s @ 1/16 in = 1.5 mm) Value -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 -65 to +150 +260 Units V V V °C °C Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. Recommended Operation Conditions 1 Symbol VCCINT VCCIO VIL VIH VO Parameter Supply voltage for internal logic and input buffer Supply voltage for output drivers for 5 V operation Supply voltage for output drivers for 3.3 V operation Low-level input voltage High-level input voltage Output voltage Min 4.75 (4.5) 4.75 (4.5) 3.0 0 2.0 0 Max 5.25 (5.5) 5.25 (5.5) 3.6 0.80 VCCINT +0.5 VCCIO Units V Min Max Units 20 10,000 - Years Cycles V V V V V Note: 1. Numbers in parenthesis are for industrial-temperature range versions. Endurance Characteristics Symbol tDR NPE Parameter Data Retention Program/Erase Cycles October 28, 1997 (Version 2.0) 3-39 XC95108 XC95108 In-System Programmable CPLD DC Characteristics Over Recommended Operating Conditions Symbol VOH Parameter Output high voltage for 5 V operation Test Conditions IOH = -4.0 mA VCC = Min IOH = -3.2 mA VCC = Min IOL = 24 mA VCC = Min IOL = 10 mA VCC = Min VCC = Max VIN = GND or VCC VCC = Max VIN = GND or VCC VIN = GND f = 1.0 MHz VI = GND, No load f = 1.0 MHz Output high voltage for 3.3 V operation VOL Output low voltage for 5 V operation Output low voltage for 3.3 V operation IIL Input leakage current IIH I/O high-Z leakage current CIN I/O capacitance ICC Operating Supply Current (low power mode, active) Min 2.4 Max Units V V 2.4 0.5 V 0.4 V ±10.0 µA ±10.0 µA 10.0 pF 100 (Typ) ma AC Characteristics Symbol tPD tSU tH tCO fCNT1 fSYSTEM 2 tPSU tPH tPCO tOE tOD tPOE tPOD tWLH Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid 16-bit counter frequency Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock to output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GCK pulse width (High or Low) XC95108-7 XC95108-7 XC95108-10 XC95108-10 XC95108-15 XC95108-15 XC95108-20 XC95108-20 Min Min Max 7.5 5.5 0.0 Max 5.5 Min 15.0 8.0 0.0 Max 20.0 10.0 0.0 6.5 111 67 2.5 4.0 9.5 7.0 7.0 13.0 13.0 4.0 Max 10.0 6.5 0.0 125 83 1.5 4.0 Min 8.0 95 56 4.0 4.0 10.0 83 50 4.0 6.0 10.5 10.0 10.0 15.5 15.5 4.5 12.0 15.0 15.0 18.0 18.0 5.5 16.0 20.0 20.0 22.0 22.0 5.5 Units ns ns ns ns MHz MHz ns ns ns ns ns ns ns ns Note: 1. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable. fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG. 2. fSYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs. 3-40 October 28, 1997 (Version 2.0) VTEST R1 VTEST R1 R2 CL 5.0 V 160 120 35 pF 3.3 V R2 VCCIO 5.0 V Output Type Device Output 3.3 V 260 360 35 pF CL X5906 X5906 Figure 3: AC Load Circuit Internal Timing Parameters Symbol Parameter Buffer Delays tIN Input buffer delay tGCK GCK buffer delay tGSR GSR buffer delay tGTS GTS buffer delay tOUT Output buffer delay tEN Output buffer enable/disable delay Product Term Control Delays tPTCK Product term clock delay tPTSR Product term set/reset delay tPTTS Product term 3-state delay Internal Register and Combinatorial delays tPDI Combinatorial logic propagation delay Register setup time tSUI tHI Register hold time tCOI Register clock to output valid time tAOI Register async. S/R to output delay tRAI Register async. S/R recovery before clock tLOGI Internal logic delay tLOGILP Internal low power logic delay Feedback Delays tF FastCONNECT matrix feedback delay tLF Function Block local feeback delay Time Adders Incremental Product Term Allocator delay tPTA3 tSLEW Slew-rate limited delay XC95108-7 XC95108-7 XC95108-10 XC95108-10 XC95108-15 XC95108-15 XC95108-20 XC95108-20 Min Min Max Max Min Max Min Max Units 2.5 2.5 4.5 7.0 2.5 0.0 3.5 3.0 6.0 10.0 3.0 0.0 4.5 3.0 7.5 15.0 4.5 0.0 6.5 3.0 9.5 20.0 6.5 0.0 ns ns ns ns ns ns 4.0 2.0 10.5 3.5 2.5 12.0 2.5 3.0 13.5 2.5 3.0 15.5 ns ns ns 4.0 0.5 2.0 10.0 2.5 11.0 3.0 11.5 3.0 11.5 ns ns ns ns ns ns ns ns 6.0 2.0 8.5 2.5 11.0 3.5 13.0 5.0 ns ns 1.0 4.0 1.0 4.5 1.5 5.0 1.5 5.5 ns ns 3.5 2.0 1.0 3.5 3.0 0.5 6.5 7.5 3.0 3.5 4.5 0.5 7.0 10.0 3.5 6.5 0.5 8.0 15.0 0.5 9.0 20.0 Note: 3. tPTA is multiplied by the span of the function as defined in the family data sheet. October 28, 1997 (Version 2.0) 3-41 XC95108 XC95108 In-System Programmable CPLD XC95108 XC95108 I/O Pins Function Function BScan BScan Macrocell PC84 PQ100 PQ100 TQ100 TQ100 PQ160 PQ160 Macrocell PC84 PQ100 PQ100 TQ100 TQ100 PQ160 PQ160 Notes Notes Block Block Order Order 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 ­ 1 2 ­ 3 4 ­ 5 6 ­ 7 9 ­ 10 11 12 13 ­ ­ 71 72 ­ 74 75 ­ 76 77 ­ 79 80 ­ 81 82 83 84 ­ ­ 15 16 21 17 18 ­ 19 20 26 22 24 ­ 25 27 29 30 ­ ­ 98 99 4 1 3 ­ 5 6 9 8 10 ­ 11 12 13 14 ­ ­ 13 14 19 15 16 ­ 17 18 24 20 22 ­ 23 25 27 28 ­ ­ 96 97 2 99 1 ­ 3 4 7 6 8 ­ 9 10 11 12 ­ 25 21 22 29 23 24 27 26 28 36 30 33 34 35 37 42 44 43 158 154 156 4 159 2 9 6 8 12 11 13 14 15 17 18 19 16 321 318 315 312 309 306 303 300 297 294 291 288 285 282 279 276 273 270 267 264 261 258 255 252 249 246 243 240 237 234 231 228 225 222 219 216 [1] [1] [1] [1] [1] [1] 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 ­ 14 15 ­ 17 18 ­ 19 20 ­ 21 23 ­ 24 25 26 31 ­ ­ 57 58 ­ 61 62 ­ 63 65 ­ 66 67 ­ 68 69 ­ 70 ­ ­ 31 32 36 34 35 ­ 37 38 45 39 41 ­ 42 43 44 51 ­ ­ 83 84 82 87 88 ­ 89 91 ­ 92 93 ­ 95 96 94 97 ­ ­ 29 30 34 32 33 ­ 35 36 43 37 39 ­ 40 41 42 49 ­ ­ 81 82 80 85 86 ­ 87 89 ­ 90 91 ­ 93 94 92 95 ­ 45 47 49 57 54 56 50 58 59 69 60 62 52 63 64 68 77 74 123 134 135 133 138 139 128 140 142 147 143 144 153 146 148 145 152 155 213 210 207 204 201 198 195 192 189 186 183 180 177 174 171 168 165 162 159 156 153 150 147 144 141 138 135 132 129 126 123 120 117 114 111 108 Notes: [1] Global control pin 3-42 October 28, 1997 (Version 2.0) XC95108 XC95108 I/O Pins (continued) Function Function BScan BScan Macrocell PC84 PQ100 PQ100 TQ100 TQ100 PQ160 PQ160 Macrocell PC84 PQ100 PQ100 TQ100 TQ100 PQ160 PQ160 Notes Notes Block Block Order Order 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 ­ 32 33 ­ 34 35 ­ 36 37 ­ 39 40 ­ 41 43 ­ 44 ­ ­ 52 54 48 55 56 ­ 57 58 ­ 60 62 ­ 63 65 61 66 ­ ­ 50 52 46 53 54 ­ 55 56 ­ 58 60 ­ 61 63 59 64 ­ 76 79 82 72 86 88 78 90 92 84 95 97 87 98 101 96 102 89 105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 ­ 45 46 ­ 47 48 ­ 50 51 ­ 52 53 ­ 54 55 ­ 56 ­ ­ 67 68 75 69 70 ­ 72 73 ­ 74 76 ­ 78 79 81 80 ­ ­ 65 66 73 67 68 ­ 70 71 ­ 72 74 ­ 76 77 79 78 ­ 91 103 104 116 106 108 105 111 113 107 115 117 112 122 124 129 126 114 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0 XC95108 XC95108 Global, JTAG and Power Pins Pin Type PC84 PQ100 PQ100 I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GSR TCK TDI TDO TMS VCCINT 5 V VCCIO 3.3 V/5 V GND GND GND No connects 9 10 12 76 77 74 30 28 59 29 38,73,78 22,64 8,16,27,42,49,60 ­ ­ ­ 24 25 29 5 6 1 50 47 85 49 7,59,100 28,40,53,90 2,23,33,46,64,71,77,86 ­ ­ ­ October 28, 1997 (Version 2.0) TQ100 TQ100 PQ160 PQ160 22 33 23 35 27 42 3 6 4 8 99 159 48 75 45 71 83 136 47 73 5,57,98 10,46,94,157 26,38,51,88 1,41,61,81,121,141 100,21,31,44,62,69,75,84 20,31,40,51,70,80,99 ­ 100,110,120,127,137 ­ 160 ­ 3,5,7,32,38,39,48,53,55,6 5,66,67,83,85,93,109, 118,119,125,130,131, 132,149,150,151 3-43 XC95108 XC95108 In-System Programmable CPLD Ordering Information XC95108 XC95108 -7 PQ 160 C Device Type Temperature Range Number of Pins Speed Package Type Packaging Options Speed Options - 20 -15 -10 -7 PC84 PQ100 PQ100 TQ100 TQ100 PQ160 PQ160 20 ns pin-to-pin delay 15 ns pin-to-pin delay 10 ns pin-to-pin delay 7 ns pin-to-pin delay 84-Pin Plastic Leaded Chip Carrier (PLCC) 100-Pin Plastic Quad Flat Pack (PQFP) 100-Pin Very Thin Quad Flat Pack (TQFP) 160-Pin Plastic Quad Flat Pack (PQFP) Temperature Options C I Commercial Industrial 0°C to 70°C ­40°C to 85°C Component Availability Pins Type Code XC95108 XC95108 ­20 ­15 ­10 ­7 84 Plastic PLCC PC84 C,I C,I C,I C C = Commercial = 0° to +70°C 3-44 100 Plastic PQFP PQ100 PQ100 C,I C,I C,I C Plastic TQFP TQ100 TQ100 C,I C,I C,I C 160 Plastic PQFP PQ160 PQ160 C,I C,I C,I C I = Industrial = ­40° to 85°C October 28, 1997 (Version 2.0)