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XC9500 Datasheet

Part Manufacturer Description PDF Type Ordering
XC9500 Xilinx XC9500 In-System Programmable CPLD Family
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16 pages,
154.64 Kb

Original Buy
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XC9500 Xilinx XC9500: 5V ISP CPLD Family
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16 pages,
125.97 Kb

Original Buy
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XC9500 Xilinx The Programmable Logic Data Book
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909 pages,
12064.11 Kb

Original Buy
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XC9500XL Xilinx XC9500XL: 3.3V ISP CPLD Family
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16 pages,
126.54 Kb

Original Buy
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XC9500XV Xilinx XC9500XV: 2.5V ISP CPLD Family
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18 pages,
166.93 Kb

Original Buy
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XC9500

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: Device and Package Support Programming Socket Adapters · XC1700 XC1700 Serial PROMs · XC9500 CPLDs · , (Version 1.2) 9-1 HW-130 HW-130 Programmer Adapter Selection Table Product Family XC73001/XC9500 XC73001 XC73001 XC73001/XC9500 XC73001 XC73001 XC73001/XC9500 XC73001/XC9500 XC73001/XC9500 XC73001 XC73001 XC73001 XC73001, 2 CPLD (XC73001/XC9500)2 XC73001 XC73001 XC9500 XC9500 Package Types PLCC/CLCC 44 PQFP 44 VQFP 44 PLCC , versions of the HW-133-PQ160 HW-133-PQ160 adapter. The correct adapter for programming XC9500 devices has "CPLD" ... Xilinx
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2 pages,
13.62 Kb

XC9500 HQFP 208 HW-130 HW-133 HW-133-PG144 plcc 68 prom universal programmer XC1700 CLCC 44 HW-137-DIP8 HQFP-208 plcc20 socket CLCC 84 TEXT
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Abstract: KXILINX Jan ua ry, 1997 (V ersion 1.1) XC9500 In-System Programmable CPLD Family Preliminary , 0.6jxm CMOS 5V FastFLASH technology Supports parallel programming of multiple XC9500 devices · · · · Architecture Description Each XC9500 device is a subsystem consisting of multiple Function , signals drive directly to the lOBs. See Figure 1. · · · · · · · · · Family Overview The XC9500 CPLD , shown in Table 1, logic density of the XC9500 devices ranges from 800 to over 12,800 usable gates with ... OCR Scan
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15 pages,
524.83 Kb

XC9572F XC9500F 33vy xc9536 44 pin vqfp XC9500 TEXT
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Abstract: k 0 R XC9500 In-System Programmable CPLD Automotive IQ Family 0 0 DS120-1 DS120-1 (v1.1) February 3, 2003 Product Specification As shown in Table 1, logic density of the XC9500 devices ranges , associated I/O capacity are shown in Table 2. The XC9500 family is fully pin-compatible allowing easy design migration across multiple density options in a given package footprint. The XC9500 architectural features , be configured for 3.3V or 5V operation. All outputs provide 24 mA drive. Table 1: XC9500 Device ... Xilinx
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datasheet

3 pages,
27.48 Kb

xc9536 44 pin vqfp xc9536 44 pin TEXT
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Abstract: k 0 R XC9500 In-System Programmable CPLD Family 0 0 DS063 DS063 (v5.3) April 15, 2005 , XC9500 devices Features · High-performance · · 5 ns pin-to-pin logic delays on all pins fCNT to 125 , Program/erase over full commercial voltage and temperature range Family Overview The XC9500 CPLD , shown in Table 1, logic density of the XC9500 devices ranges from 800 to over 6,400 usable gates with 36 , Table 2. The XC9500 family is fully pin-compatible allowing easy design migration across multiple ... Xilinx
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16 pages,
319.1 Kb

TEXT
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Abstract: XILINX PROGRAMMER QUALIFICATION SPECIFICATION XC9500 FAMILY Introduction Signature String , QUALIFICATION SPECIFICATION XC9500 FAMILY Programming Sequence Device Blank Check The device , terminate the programming sequence. 2 XILINX PROGRAMMER QUALIFICATION SPECIFICATION XC9500 FAMILY , . 5/1/98 Rev. 2.6 3 XILINX PROGRAMMER QUALIFICATION SPECIFICATION XC9500 FAMILY Start , /98 Rev. 2.6 4 XILINX PROGRAMMER QUALIFICATION SPECIFICATION XC9500 FAMILY Program N ... Xilinx
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datasheet

31 pages,
172.54 Kb

xilinx xc9536 Fuse n25 XC9500 XC95108 XC95144 xc95144 pinout XC95216 XC95288 XC95288 Family XC9536 XC9572 XC9500 pinout TEXT
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Abstract: Benchmarks 1 1 1 10 Xilinx All XC9500-10 10 10 XC9572-10 XC9572-10 and larger 1 XC95108 XC95108 , , 1996 (Version 1.3) 1 1 1 10 10 10 Xilinx All XC9500-10 1 XC9572-10 XC9572-10 and larger , XC9500 Pin-Locking Capability and Benchmarks ® XBRF 009 October 1, 1996 (Version 1.3 , pin-locking capability of the Xilinx XC9500 CPLDs. These benchmarks are based on typical applications and , , proving that the Xilinx XC9500 family is the industry's best pin-locking CPLD. Xilinx Family XC9500 ... Xilinx
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8 pages,
43.48 Kb

XC9572 epm7192 epm7192 packages mach 1 family amd mach 1 to 5 from amd MAX7000 XC9500 XC9500 pinout EPM7000S m52561 EPM7000 AMD CPLD Mach 1 to 5 TEXT
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Abstract: Fall 1996 Seminar CPLDs Fall Seminar - CPLD - 1 XC9500 CPLDs DESIGN PROTOTYPING TEST XC9500 CPLDs MANUFACTURE FIELD UPGRADE Technology Fall Seminar - CPLD - 2 Designer's Needs , Significant expansion in industry capacity planned for late 90s Fall Seminar - CPLD - 5 XC9500 Uniform Architecture Identical I/Os Identical FBs Identical macrocells Fall Seminar - CPLD - 6 XC9500 Function Block Wide FB inputs Fall Seminar - CPLD - 7 XC9500 Macrocell To FastCONNECT Switch ... Xilinx
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33 pages,
1036.93 Kb

EPM7256S-10 EPM7160E-10 EPM7192S-10 epm7128s ispLSI1024 EPM7096-10 EPM7128S-10 9572F XC95108 44VQ 95144 xc95144 pinout xc9500 jtag cable XC9572 XC9500 XC9500F XC9500 XC95144 XC9500 304HQ XC9500 XC9500 XC9500 cpld 95108 XC9500 pinout TEXT
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Abstract: k 0 XC9500 In-System Programmable CPLD Family R DS063 DS063 (v5.5) June 25, 2007 0 0 , parallel programming of multiple XC9500 devices High-performance - · 5 ns pin-to-pin logic , High-drive 24 mA outputs - The XC9500 CPLD family provides advanced in-system programming and test , also included on all family members. As shown in Table 1, logic density of the XC9500 devices ranges , and associated I/O capacity are shown in Table 2. The XC9500 family is fully pin-compatible allowing ... Xilinx
Original
datasheet

17 pages,
150.34 Kb

xilinx cable 9536 XC9500 XC9500 pinout XC95108 xc95144 XC95216 XC95288 XC9536 xc9536 44 pin vqfp XC9572 XCN07010 DS06 TEXT
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Abstract: k 0 R XC9500 In-System Programmable CPLD Family 0 0 DS063 DS063 (v5.4) April 3, 2006 , XC9500 devices Features · High-performance · · 5 ns pin-to-pin logic delays on all pins fCNT to 125 , The XC9500 CPLD family provides advanced in-system programming and test capabilities for high , members. As shown in Table 1, logic density of the XC9500 devices ranges from 800 to over 6,400 usable , shown in Table 2. The XC9500 family is fully pin-compatible allowing easy design migration across ... Xilinx
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datasheet

17 pages,
254.47 Kb

XC9536 PIN CONNECTION xc9536 44 pin vqfp PLCC-48 footprint TEXT
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Abstract: , use XC9500. Has many 16x1 or 32x1 RAMs with synchronous write and dual-port capability. For , : Use XC9500. XC9500 achieves fast compilation through the simplicity of its PAL-like architecture. 5 , , and XC4000XL XC4000XL. Flash-based complex PLDs, the XC9500 family. XAPP 100 July 10, 1998 (Version 1.3 , families or the XC9500 CPLD family, may be an alternative. XC2000L XC2000L: 3.3V version of XC2000 XC2000; obsolete, do , (XC9500) XC4000XV XC4000XV: 2.5V FPGA SImilar architecture to XC4000EX XC4000EX (5V) and XC4000XL/T XC4000XL/T (3.3V). Together ... Xilinx
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6 pages,
31.32 Kb

XC9000 XC3000A XC3000L XC3100A XC4000 XC4000E XC4000EX XC5000 XC5200 XC3000 TEXT
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Abstract: XC9500/XL/XV CPLDs · Checksum calculation and comparison · XCR3000XL XCR3000XL CPLDs · Blank , www.xilinx.com 1 HW-130 HW-130 Programmer R Adapter Selection Package Types Adapter P/N XC9500/XL/XV Product Family PLCC 44 HW-133-PC44 HW-133-PC44 XC9500/XL/XV VQFP 44 HW-133-VQ44 HW-133-VQ44 XC9500/XL/XV CSP 48 HW-133-CS48 HW-133-CS48 XC9500XL/XV XC9500XL/XV VQFP 64 HW-133-VQ64 HW-133-VQ64 XC9500 PLCC 84 HW-133-PC84 HW-133-PC84 XC9500 PQFP 100 HW-133-PQ100 HW-133-PQ100 XC9500/XL/XV TQFP 100 HW-133-TQ100 HW-133-TQ100 XC9500XL/XV XC9500XL/XV CSP 144 ... Xilinx
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3 pages,
99.07 Kb

HW-136-VQ100 data sheet HW-136-CP56 HW-137-PC20 HW-130-J LCC44 SO8 DIP8 socket tqfp 64 socket vq44 HW-130 XC17S00 HW-133-BG256 HQFP HW-136-CS144 HW-136-VQ100 xc17v00 HW-137-PC44/VQ44 HW-137-DIP8 vqfp 44 XCR3000XL TEXT
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Abstract: APPLICATION NOTE 0 ® XC9500 CPLD Power Sequencing XAPP110 XAPP110 February 16, 1998 (Version 1.0 , can operate with two power supplies. Xilinx XC9500 CPLDs are designed to operate in either mixed 5V , in any particular sequence. This application note describes the underlying XC9500 circuitry to give designers the understanding they need to best use these powerful CPLDs. Application Note XC9500 CPLDs , pin VCCINT to FastCONNECT D2 Figure 1: Simplified XC9500 I/O Cell Structure Discussion ... Xilinx
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datasheet

3 pages,
29.33 Kb

XC9500 power-sequence XAPP110 TEXT
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Abstract: ® XBRF 018 July 1, 1997 (Version 1.0) Converting XC7200/XC7300 XC7200/XC7300 Designs to XC9500 Solutions Application Brief Summary Retargeting XC7200/XC7300 XC7200/XC7300 designs to the XC9500 CPLD family can be as simple as , XC9500 simplifies design translation. This document assumes a version 4.2 or later Xilinx design file for the original XC7200/XC7300 XC7200/XC7300 format. Xilinx M1 design software translation to the XC9500 is also , directory. 2. Invoke the Design Manager with the design file. Choose an XC9500 device to implement the ... Xilinx
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2 pages,
18.85 Kb

Xilinx XC73108 XC7236A XC7272A XC7300 XC73108 XC7336 XC7354 XC7372 XC9500 Family XC9572 Family XC7200 XC9500 XC9572 Family equivalent XC7200/XC7300 XC7200/XC7300 XC9500 TEXT
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Abstract: begun volume shipments of the newest member of the XC9500 family of aggressively-priced complex , now comprise the XC9500 CPLD family-the XC9536 XC9536, XC9572 XC9572, XC95108 XC95108, XC95216 XC95216 and the XC95288 XC95288 devices-and range in density from 36 to 288 macrocells in a variety of packages. The XC9500 family features , to take advantage of the XC9500 family's in-system programming (ISP) capability that enables easier , pricing and features of the XC9500 family," said Evert Wolsheimer, vice president and general manager of ... Xilinx
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datasheet

2 pages,
8.75 Kb

xc9572 data sheet HQ208 PC44 XC9500 XC95108 XC95216 XC95288 XC9536 XC9572 CPLD Complex Programmable Logic Devices XC9536-PC44 TEXT
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Abstract: XC9500 family. Attractive systems features include on-chip bidirectional busses and individual output , . The Spartan FPGA families or the XC9500 CPLD family, may be an alternative. XC2000L XC2000L: 3.3V version of , dedicated carry logic can speed up wide arithmetic and long counters. FLASH-Based CPLDs (XC9500) These , complex synchronous counters. The XC9500 in-system programmable family, based on FLASH technology , board testing. Overview of CPLD Families XC7200 XC7200: Obsoleted Do not use for new designs. Use XC9500 ... Xilinx
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6 pages,
45.19 Kb

XC9000 XC3000 XC3000A XC3000L XC3100A XC4000 XC4000E XC4000EX XC5000 XC5200 XAPP100 TEXT
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Abstract: programming of multiple XC9500 devices in a boundary-scan chain, and shows how to design systems that contain multiple XC9500 devices as well as other IEEE 1149.1-compatible devices. Xilinx Family XC9500 Introduction XC9500 TAP Characteristics The XC9500 family performs both in-system programming and IEEE , EZTagTM software that automatically programs and tests XC9500 devices from the standard test vector and , the XC9500 TAP are described as follows. TAP Timing Figure 1 shows the timing relationships of ... Xilinx
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datasheet

6 pages,
38.78 Kb

XC9500 XC3042 XAPP070 TDI timing 1.9 TDI dlc5 Xilinx DLC5 JTAG Parallel Cable III TEXT
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Abstract: Application Note: XC9500 CPLDs R Using In-System Programming in BoundaryScan Systems XAPP070 XAPP070 , for in-system programming (ISP) of multiple XC9500 devices in a Boundary-Scan chain and shows how to design systems that contain multiple XC9500 devices as well as other IEEE 1149.1-compatible devices , The XC9500 family performs both in-system programming and IEEE 1149.1 Boundary-Scan (JTAG) testing , and tests XC9500 devices. XC9500 TAP Characteristics The AC and DC characteristics of the ... Xilinx
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8 pages,
113.61 Kb

xilinx jtag cable XC9500 X07002 Signal path designer XAPP070 TEXT
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Archived Files

Abstract Saved from Date Saved File Size Type Download
for XC9500 devices   SAN JOSE, Calif., June 30, 1997-Reaffirming its commitment to be the price reductions of up to 30 percent for the company's XC9500 in-system programming (ISP) CPLDs. The new pricing manufacturing costs for the XC9500 devices, which are produced with a proven Flash process technology. Cost on speed and package. "Design wins for the XC9500 CPLDs are at an all-time high and have doubled business unit. "Customers are choosing the XC9500 devices over competing products because the Xilinx
/datasheets/files/xilinx/docs/wcd00001/wcd001db.htm
Xilinx 16/02/1999 7.09 Kb HTM wcd001db.htm
3-state control or Slow slew rate. By default, this option is on. XC9500 Only/XC9500XL Only - configuration data signature (usercode) of a programmed XC9500 or XC9500XL device. The default is Use XC9500 Implementation Template Dialog Box XC9500 Implementation Template Dialog Box Click the Basic, Advanced, Timing Reports, Interface, or for Speed) template. XC9500 Basic Tab Use the Basic tab, shown in the following figure
/datasheets/files/xilinx/docsan/dmf/dmf5_17.htm
Xilinx 12/11/1998 14.09 Kb HTM dmf5_17.htm
Spartan-II Application Notes XC9500 Product Information   XC9500 Product Overview   XC9500XL Product Overview   XC9500XV Product Overview   XC9500 Series Application Notes   XC9500 Series Datasheets   WebFITTER
/datasheets/files/xilinx/docs/rp00007/rp0079e.htm
Xilinx 19/03/2000 7.16 Kb HTM rp0079e.htm
(NASDAQ:XLNX) today announced further price reductions of up to 41 percent for selected XC9500 in-system months totaling up to 65 percent price reduction on XC9500 devices. The company said it has made significant strides in reducing manufacturing costs for the XC9500 devices with the aggressive Flash process customers. "Design wins for the XC9500 CPLDs are at an all-time high and have doubled from the last competition. The XC9500 family combined with the new Foundation and Alliance Series software is the most
/datasheets/files/xilinx/docs/wcd00001/wcd00167.htm
Xilinx 17/07/1998 6.19 Kb HTM wcd00167.htm
for XC9500 devices   SAN JOSE, Calif., June 30, 1997-Reaffirming its commitment to be the price reductions of up to 30 percent for the company's XC9500 in-system programming (ISP) CPLDs. The new pricing manufacturing costs for the XC9500 devices, which are produced with a proven Flash process technology. Cost on speed and package. "Design wins for the XC9500 CPLDs are at an all-time high and have doubled business unit. "Customers are choosing the XC9500 devices over competing products because the Xilinx
/datasheets/files/xilinx/docs/wcd00001/wcd0016a.htm
Xilinx 17/07/1998 7 Kb HTM wcd0016a.htm
Xilinx Answer #1050 : Designing with the XC9500 family in Mentor (XACT 5.2.x) The XC9500 software patch should be installed in a separate directory from any other Xilinx production software. When designing with XC9500 devices, this directory example, if you installed the XC9500 patch in /tools/xact9000, you would need to set:     set path = between the two technologies. To implement a design for an XC9500 device: 1. Prepare a Mentor
/datasheets/files/xilinx/docs/rp0000e/rp00e7c.htm
Xilinx 06/03/2000 8.51 Kb HTM rp00e7c.htm
Xilinx Answer #2029 : XC9500: Programming an XC9500 CPLD with a microcontroller (ISP)
/datasheets/files/xilinx/docs/wcd00006/wcd006e0.htm
Xilinx 17/07/1998 4.57 Kb HTM wcd006e0.htm
XC9500 In-System Programming Using an 8051 Microcontroller 250 KB XAPP058 XAPP058 XC9500 PC   SunOS Program XC9500 Devices In-System on Automatic Test Equipment and Third Party Tools 40 KB XAPP067 XAPP067 XC9500 In-System Programming Times 10 KB XAPP068 XAPP068 XC9500 Using the XC9500 JTAG Boundary Scan Interface 120 KB XAPP069 XAPP069 XC9500   Title Size  Summary XC9500 Using the XC9500 Timing Model 60 KB XAPP071 XAPP071 XC9500 XC9500 Design
/datasheets/files/xilinx/docs/wcd00002/wcd00206-v1.htm
Xilinx 16/02/1999 79.91 Kb HTM wcd00206-v1.htm
XC9500) ref.pdf 1,031KB 031KB XEPLD (For Windows) Reference Guide (for XC9500) sdg.pdf 513KB 513KB XEPLD Schematic Design Guide (for XC9500) xnf61_7k.pdf 21KB XNF XC7000 XC7000 Design Guide (for XC9500) xsi_epld.pdf 682KB 682KB Synopsys (XSI) For EPLDs Interface
/datasheets/files/xilinx/ftp/doc/cpld/00_index.htm
Xilinx 08/04/1997 4.12 Kb HTM 00_index.htm
: none lib.pdf 2,464KB 464KB Libraries Guide (for XC7000 XC7000 and XC9500) ref.pdf 1,031KB 031KB XEPLD (For Windows) Reference Guide (for XC9500) sdg.pdf 513KB 513KB XEPLD Schematic Design Guide (for XC9500) xnf61_7k.pdf 21KB XNF XC7000 XC7000 Design Guide (for XC9500) xsi_epld.pdf 682KB 682KB Synopsys (XSI) For EPLDs Interface
/datasheets/files/xilinx/docs/rp00021/rp02120.htm
Xilinx 06/03/2000 7 Kb HTM rp02120.htm