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XC9500 Datasheet

Part Manufacturer Description PDF Type Ordering
XC9500 Xilinx XC9500 In-System Programmable CPLD Family
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16 pages,
154.64 Kb

Original Buy
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XC9500 Xilinx XC9500: 5V ISP CPLD Family
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16 pages,
125.97 Kb

Original Buy
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XC9500 Xilinx The Programmable Logic Data Book
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909 pages,
12064.11 Kb

Original Buy
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XC9500XL Xilinx XC9500XL: 3.3V ISP CPLD Family
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16 pages,
126.54 Kb

Original Buy
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XC9500XV Xilinx XC9500XV: 2.5V ISP CPLD Family
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18 pages,
166.93 Kb

Original Buy
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XC9500

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: ® Designing with XC9500 CPLDs XAPP 073 - January, 1997 (Version 1.0) Application Note Summary This application note will help designers understand the XC9500 architecture and how to get the best performance from these devices. Xilinx Family XC9500 Introduction To get the best , successful designs. These design techniques apply to all XC9500 devices because the architecture is uniform across the family. Figure 1 shows the XC9500 architecture. Note the regular structure of high speed ... Xilinx
Original
datasheet

8 pages,
67.3 Kb

XC9572 x5878 xapp XC9500 XC95108 2-bit adder layout XC95180 XC95216 XC9536 XC95144 TEXT
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Abstract: is a 3.3 V-core derivative of the popular 5 V-core XC9500 family. Each XC9500XL device comprises , scalability. Development System Like the current XC9500 family, the XC9500XL family will be supported in all , ), announced today it will begin volume shipments this month of the newest member of the 5-volt XC9500 family , Semiconductor Corporation (USC), Taiwan. During 1998, all other members of the XC9500 family will be , to Xilinx and the XC9500 CPLD family an easy choice. We've completed one design, a complex board ... Xilinx
Original
datasheet

25 pages,
174.67 Kb

XC9500 XC9500XL XC95108 TQFP 144 PACKAGE DIMENSION footprint tqfp 208 CPLD PCMCIA cpld FOOTPRINT XC95216 XC95288 XC9536 XC9536XL Series XC95288XL pinout XC9500 pinout XC95144 XC95108XL xc95144 pin diagram XC95216XL xilinx xc9536 digital clock 100-PIN TQFP XILINX DIMENSION TEXT
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Abstract: ® XC9500 In-System Programmable CPLD Family January, 1997 (Version 1.1) Preliminary , technology Supports parallel programming of multiple XC9500 devices Advanced system features include , Each XC9500 device is a subsystem consisting of multiple Function Blocks (FBs) and I/O Blocks (IOBs , Figure 1. Family Overview The XC9500 CPLD family provides advanced in-system programming and test , also included on all family members. As shown in Table 1, logic density of the XC9500 devices ranges ... Xilinx
Original
datasheet

16 pages,
126.12 Kb

XC9572 XC9500 XC9500 pinout XC95108 XC95144 XC95180 XC95216 XC95288 XC9536 xc9536 44 pin vqfp X5880 TEXT
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Abstract: 0 XC9500 In-System Programmable CPLD Family R September 15, 1999 (Version 5.0) 0 1* Features Family Overview · The XC9500 CPLD family provides advanced in-system programming and , FastFLASH technology Supports parallel programming of multiple XC9500 devices As shown in Table 1, logic density of the XC9500 devices ranges from 800 to over 6,400 usable gates with 36 to 288 , XC9500 family is fully pin-compatible allowing easy design migration across multiple density options in ... Xilinx
Original
datasheet

16 pages,
125.97 Kb

XC9536 xc9536 44 pin vqfp XC9500 XC9572 XC95108 XC95288 XC95216 XC95144 XC9500 pinout xc95144 pinout TEXT
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Abstract: 0 XC9500 In-System Programmable CPLD Family R December 14, 1998 (Version 3.0) 0 1* Features Family Overview · The XC9500 CPLD family provides advanced in-system programming and , FastFLASH technology Supports parallel programming of multiple XC9500 devices As shown in Table 1, logic density of the XC9500 devices ranges from 800 to over 6,400 usable gates with 36 to 288 , XC9500 family is fully pin-compatible allowing easy design migration across multiple density options in ... Xilinx
Original
datasheet

16 pages,
183.74 Kb

XC9572 XC9536 XC95288 XC95216 XC95144 XC95108 XC9500 pinout XC9500 PLCC-48 footprint TEXT
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Abstract: ® XC9500 In-System Programmable CPLD Family August 1, 1996 (Version 1.1) Preliminary , mA drive. Architecture Description Each XC9500 device is a subsystem consisting of multiple , enable signals drive directly to the IOBs. See Figure 1. Description The XC9500 CPLD family provides , , the nine devices of the XC9500 family range in logic density from 800 to over 12,800 usable gates , in Table 2. The XC9500 family is fully pin-compatible allowing easy design migration across ... Xilinx
Original
datasheet

14 pages,
134.86 Kb

XC9572 XC9536 XC95288 XC95216 XC95180 XC95144 XC95108 XC9500 TEXT
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Abstract: k 0 XC9500 In-System Programmable CPLD Family R DS063 DS063 (v5.1) September 22, 2003 0 , Supports parallel programming of multiple XC9500 devices High-performance - · 5 ns pin-to-pin , High-drive 24 mA outputs - The XC9500 CPLD family provides advanced in-system programming and test , also included on all family members. As shown in Table 1, logic density of the XC9500 devices ranges , and associated I/O capacity are shown in Table 2. The XC9500 family is fully pin-compatible allowing ... Xilinx
Original
datasheet

16 pages,
154.64 Kb

XC9572 HW130 XC9500 XC9500 pinout XC95108 DS06 xc95144 pinout XC95216 XC95288 XC9536 XC95144 TEXT
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Abstract: 18 Figure 1: Simplified XC9500 I/O Architecture R DESIGN HINTS AND ISSUES Benchmarks Confirm XC9500 CPLD The Xilinx XC9500 CPLD family provides the , issues, Xilinx XC9500 CPLDs feature abundant routing resources, wide function block fanin and flexible product term allocation. The XC9500 fitter also optimizes the initial placement to maximize the design , /O pins. The XC9500 family provides the most routing resources of any available CPLD family. All ... Xilinx
Original
datasheet

4 pages,
432.11 Kb

XC9500 XC4005E test board XC3042-70 xilinx MTBF TEXT
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Abstract: ® Designing with XC9500 CPLDs XAPP073 XAPP073 January, 1998 (Version 1.3) Application Note Summary This application note will help designers understand the XC9500 architecture and how to get the best performance from these devices. Xilinx Family XC9500 Introduction To get the best , successful designs. These design techniques apply to all XC9500 devices because the architecture is uniform across the family. Figure 1 shows the XC9500 architecture. Note the regular structure of high speed ... Xilinx
Original
datasheet

8 pages,
69.07 Kb

DAT3 DIODE X5901 XAPP073 XC9500 XC95108 XC95144 XC95216 XC9536 XC9572 xc9572-44 pin TEXT
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Abstract: £ XILINX February 10, 1999 (Version 4.0) XC9500 In-System Programmable CPLD Family Features , 5V FastFLASH technology Supports parallel programming of multiple XC9500 devices Family Overview The XC9500 CPLD family provides advanced in-system programming and test capabilities for high , members. As shown in Table 1, logic density of the XC9500 devices ranges from 800 to over 6,400 usable , shown in Table 2. The XC9500 fam ily is fully pin-compatible allowing easy design migration across ... OCR Scan
datasheet

16 pages,
621.33 Kb

vqfp package pinout XC9500 TEXT
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Abstract: XC9500 In-System Programming Using an Embedded Microcontroller ® XAPP058 XAPP058 January, 1998 (Version 1.2) Application Note Summary The XC9500 high performance CPLD family provides in-system , Family XC9500 Introduction The XC9500 CPLD family combines superior performance with an advanced , information and generates the programming instructions, data, and control signals for the XC9500 CPLD , . Enables unique, customer-specific features. By using a simple IEEE 1149.1 (JTAG) interface, XC9500 ... Xilinx
Original
datasheet

32 pages,
131.98 Kb

8051 port timing diagram c-code intel 8051 40 pin datasheet intel 8051 copyright 1998 interfacing 8051 with eprom and ram 8051 microcontroller DATA SHEET 8051 microcontroller XC9500 XC95108 XC95216 XC95288 XC9536 XC9572 xc9572 pin diagram 8051 microcontroller pin configuration XSVF 0x00000fa0 XC95144 schematic eprom programing system XAPP058 TEXT
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Abstract: Application Note: XC9500/XL/XV Family R XAPP067 XAPP067 (v2.0) May 13, 2002 Using Serial Vector Format Files to Program XC9500/XL/XV Devices InSystem Summary This application note describes how , files. Introduction XC9500/XL/XV devices use a standard 4-wire Test Access Port (TAP) for both , . The XC9500/XL/XV Boundary Scan architecture is shown in Figure 1. The Xilinx iMPACT software helps , programming and test algorithms required by the XC9500/XL/XV devices. Most ATE platforms and Boundary Scan ... Xilinx
Original
datasheet

8 pages,
112.78 Kb

XC9500 XAPP067 x06701041102 3AFE 1000 XAPP0 XC9500/XL/XV TEXT
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Abstract: XILINX PROGRAMMER QUALIFICATION SPECIFICATION XC9500 FAMILY Introduction Signature String , QUALIFICATION SPECIFICATION XC9500 FAMILY Programming Sequence Device Blank Check The device , terminate the programming sequence. 2 XILINX PROGRAMMER QUALIFICATION SPECIFICATION XC9500 FAMILY , . 5/1/98 Rev. 2.6 3 XILINX PROGRAMMER QUALIFICATION SPECIFICATION XC9500 FAMILY Start , /98 Rev. 2.6 4 XILINX PROGRAMMER QUALIFICATION SPECIFICATION XC9500 FAMILY Program N ... Xilinx
Original
datasheet

31 pages,
172.54 Kb

xilinx xc9536 Fuse n25 XC9500 XC95108 XC95144 xc95144 pinout XC95216 XC95288 XC95288 Family XC9536 XC9572 XC9500 pinout TEXT
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Archived Files

Abstract Saved from Date Saved File Size Type Download
Xilinx XC9500 Software Design Flows XC9500 Software Flows with XC9500 Software v1.0 Introduction This application brief shows how to use XABEL to design with XC9500 CPLDs. System configuration issues and software flows are discussed for the PC, Sun and HP platforms. Software Required XACT-CPLD (DS-560 DS-560) XC9500 The XC9500 software should be installed in a separate directory from any other Xilinx production
/datasheets/files/xilinx/weblinx/appnotes/9500flow.htm
Xilinx 03/02/1997 26 Kb HTM 9500flow.htm
Xilinx CPLD Applications XC9500/XC7000 CPLD (35 kb) XAPP076 XAPP076 v1.0 Embedded Instrumentation Using XC9500 CPLDs (53 kb) XAPP075 XAPP075 v1.0 Using ABEL with Xilinx CPLDs (129 kb) XAPP074 XAPP074 v1.0 Pin Preassigning with XC9500 CPLDs (83 kb) XAPP073 XAPP073 v1.0 Designing with XC9500 CPLDs (107 kb) XAPP072 XAPP072 v1.0 XC9500 Design Optimization (72 kb) XAPP071 XAPP071 v1.0 Using the XC9500 Timing Model (65 kb) XAPP070 XAPP070 v1.0 Using In-System Programmability
/datasheets/files/xilinx/weblinx/apps/epld.htm
Xilinx 22/04/1997 8.89 Kb HTM epld.htm
Xilinx Product Spotlight : XC9500 ISP CPLDs New In-System Programmable XC9500 CPLDs - Leadership Speed, Architecture, Ease-Of-Use Advanced Family: From the leader of FPGA technology, the next generation of CPLDs is here! The XC9500 family needs. With fast pin-to-pin speed, performance predictability, and fast compile times, the XC9500 CPLDs are the perfect CPLD companions to Xilinx's leading edge FPGAs. All XC9500 CPLDs support
/datasheets/files/xilinx/weblinx/spot/xc9500.htm
Xilinx 14/04/1997 3.91 Kb HTM xc9500.htm
XC9500 Embedded System ISP Code for the application note : XC9500 In-System Porgramming Using an 8051 Microcontroller. HP-version eisp_pc.zip 121KB 121KB XC9500 Embedded System ISP Code for the application note : XC9500 In-System Porgramming Using an 8051 Microcontroller. PC-version eisp_sn.tar 759KB 759KB XC9500 Embedded System ISP Code for the application note : XC9500 In-System Porgramming Using an 8051 Microcontroller. Sun4-version eisp_sol.tar
/datasheets/files/xilinx/weblinx/support/techsup/ftp/htmindex/sw_cpld.htm
Xilinx 23/04/1997 6.16 Kb HTM sw_cpld.htm
XC9500 Embedded System ISP Code for the application note : XC9500 In-System Porgramming Using an 8051 Microcontroller. HP-version eisp_pc.zip 121KB 121KB XC9500 Embedded System ISP Code for the application note : XC9500 In-System Porgramming Using an 8051 Microcontroller. PC-version eisp_sn.tar.Z 759KB 759KB XC9500 Embedded System ISP Code for the application note : XC9500 In-System Porgramming Using an 8051
/datasheets/files/xilinx/ftp/swhelp/cpld/00_index
Xilinx 09/04/1997 4.2 Kb 00_index
Application Notes and Briefs   XC9500 Data Sheets   Packages and Thermal Characteristics   Debug Tool   1.0 1/98 130 KB XAPP102 XAPP102 XC9500 Remote Field Upgrade   Associated PC and UNIX design files 1.0 1/98 80 KB XAPP069 XAPP069 Using the XC9500 JTAG Boundary-Scan Systems   1.1 7/97 42 KB XAPP058 XAPP058 XC9500 In-System Programming Using an Embedded 1.2 1/98 130 KB XAPP067 XAPP067 Using Serial Vector Format Files to Program XC9500 Devices
/datasheets/files/xilinx/docs/wcd00000/wcd000d2.htm
Xilinx 17/07/1998 15.22 Kb HTM wcd000d2.htm
XC9500 Simulation Template Dialog Box XC9500 Simulation Template Dialog Box Click the General, VHDL/Verilog, or EDIF tab to access the click Help to obtain online help. XC9500 General Tab Use the XC9500 General tab, shown in the following figure, to set these options. Figure 5.61 XC9500 Simulation Template General Tab to avoid overwriting any files. The default name is time_sim. XC9500 VHDL/Verilog Tab Use the
/datasheets/files/xilinx/docsan/dmf/dmf5_18.htm
Xilinx 12/11/1998 3.22 Kb HTM dmf5_18.htm
XC9500 CPLD Available in Volume Quantities the new Xilinx XC9500 family-the XC9536 XC9536, XC9572 XC9572, XC95108 XC95108, and XC95216 XC95216 devices-offer densities competing CPLDs, the XC9500 family features an architecture optimized for pin-locking. Pin-locking is a necessity for digital designers who want to take advantage of the XC9500 family's in-system programming (ISP extremely excited about these new XC9500 products, which we consider highly strategic to the company's
/datasheets/files/xilinx/docs/wcd00001/wcd001eb.htm
Xilinx 16/02/1999 7.76 Kb HTM wcd001eb.htm
Title Ver. Date Size Programming Xilinx XC9500 CPLDs on GenRad Testers to Program XC9500 Devices In-System on Automatic Test Equipment and Third Party Tools (XAPP067 XAPP067) 1.1 7/97 40 KB Serial Vector Format (SVF) and JEDEC files for verifying blank XC9500 family.    Title Ver. Date Size Programming Xilinx XC9500 CPLDs on HP Using Serial Vector Format Files to Program XC9500 Devices In-System on Automatic Test Equipment and
/datasheets/files/xilinx/docs/wcd00010/wcd01014.htm
Xilinx 16/02/1999 13.49 Kb HTM wcd01014.htm
XC9500 CPLD Available in Volume Quantities Ann with in-system programming capability. The first four devices in the new Xilinx XC9500 family-the in a variety of packages. Priced at least 30 percent less than competing CPLDs, the XC9500 family want to take advantage of the XC9500 family's in-system programming (ISP) capability that enables about these new XC9500 products, which we consider highly strategic to the company's future growth
/datasheets/files/xilinx/weblinx/prs_rls/9500ship.htm
Xilinx 22/01/1997 7.16 Kb HTM 9500ship.htm