XC886/888CLM XC886/888 XC800 24K/32K PG-TQFP-48 PG-TQFP-64 XC886 XC888 - Datasheet Archive

 

XC886/888CLM P re li m in ar y 8-Bit Single-Chip Microcontroller Microcontrollers Edition 2006-02 Published by Infineon

 

Data Sheet, V0.1, Feb. 2006 XC886/888CLM XC886/888CLM P re li m in ar y 8-Bit Single-Chip Microcontroller Microcontrollers Edition 2006-02 Published by Infineon Technologies AG, 81726 München, Germany © Infineon Technologies AG 2006. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Data Sheet, V0.1, Feb. 2006 ar y XC886/888CLM XC886/888CLM P re li m in 8-Bit Single-Chip Microcontroller Microcontrollers XC886/888 XC886/888 Data Sheet Revision History: 2006-02 V0.1 Previous Version: Page Subjects (major changes since last revision) We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com 8-Bit Single-Chip Microcontroller 1 XC886/888 XC886/888 Summary of Features · High-performance XC800 XC800 Core ­ compatible with standard 8051 processor ­ two clocks per machine cycle architecture (for memory access without wait state) ­ two data pointers · On-chip memory ­ 12 Kbytes of Boot ROM ­ 256 bytes of RAM ­ 1.5 Kbytes of XRAM ­ 24/32 Kbytes of Flash; or 24/32 Kbytes of ROM, with additional 4 Kbytes of Flash (includes memory protection strategy) · I/O port supply at 3.3 V or 5.0 V and core logic supply at 2.5 V (generated by embedded voltage regulator) (more features on next page) Flash or ROM1) 24K/32K 24K/32K x 8 On-Chip Debug Support Port 0 8-bit Digital I/O Capture/Compare Unit 16-bit Port 1 8-bit Digital I/O Compare Unit 16-bit Boot ROM 12K x 8 UART SSC Port 2 8-bit Digital/ Analog Input XC800 XC800 Core . XRAM 1.5K x 8 RAM 256 x 8 Timer 0 16-bit Timer 1 16-bit Timer 2 16-bit Watchdog Timer ADC 10-bit 8-channel Port 3 8-bit Digital I/O MDU CORDIC MultiCAN Timer 21 16-bit UART1 Port 5 Port 4 8-bit Digital I/O 1) All ROM devices come with an additional 4K x 8 Flash Figure 1 Data Sheet Prelimary 8-bit Digital I/O XC886/888 XC886/888 Functional Units 1 V0.1, 2006-02 XC886/888CLM XC886/888CLM Summary of Features Features (continued): · Power-on reset generation · Brownout detection for core logic supply · On-chip OSC and PLL for clock generation ­ PLL loss-of-lock detection · Power saving modes ­ slow-down mode ­ idle mode ­ power-down mode with wake-up capability via RXD or EXINT0 ­ clock gating control to each peripheral · Programmable 16-bit Watchdog Timer (WDT) · Six ports ­ 34/48 pins as digital I/O ­ 8 pins as digital/analog input · 8-channel, 10-bit ADC · Four 16-bit timers ­ Timer 0 and Timer 1 (T0 and T1) ­ Timer 2 and Timer 21 · Multiplication/Division Unit for arithmetic operations (MDU) · CORDIC Coprocessor for computation of trigonometric, hyperbolic and linear functions · MultiCAN with 2 nodes, 32 message objects (MCAN) · Capture/compare unit for PWM signal generation (CCU6) · Two full-duplex serial interfaces (UART and UART1) · Synchronous serial channel (SSC) · On-chip debug support ­ 1 Kbyte of monitor ROM (part of the 12-Kbyte Boot ROM) ­ 64 bytes of monitor RAM · Packages: ­ PG-TQFP-48 PG-TQFP-48 ­ PG-TQFP-64 PG-TQFP-64 · Temperature range TA: ­ SAF (-40 to 85 °C) ­ SAK (-40 to 125 °C) Data Sheet Prelimary 2 V0.1, 2006-02 XC886/888CLM XC886/888CLM Summary of Features XC886/888 XC886/888 Variant Devices The XC886/888 XC886/888 product family features devices with different configurations, program memory sizes, package options, temperature and quality profiles (Automotive or Industrial), to offer cost-effective solutions for different application requirements. The list of XC886/888 XC886/888 device configurations are summarized in Table 1. For each configuration, 2 types of packages are available: · PG-TQFP-48 PG-TQFP-48, which is denoted by XC886 XC886 and; · PG-TQFP-64 PG-TQFP-64, which is denoted by XC888 XC888. Table 1 Device Configuration Device Name CAN Module LIN BSL Support MDU Module XC886/888 XC886/888 No No No XC886/888C XC886/888C Yes No No XC886/888CM XC886/888CM Yes No Yes XC886/888LM XC886/888LM No Yes Yes XC886/888CLM XC886/888CLM Yes Yes Yes From these 10 different combinations of configuration and package type, each are further made available in 6 sales types, which are grouped according to program memory sizes, temperature and quality profiles (Automotive or Industrial), as shown in Table 2. Table 2 Device Profile Sales Type Device Type Program Memory Temperature Quality Size (Kbytes) Profile (°C) Profile SAK-XC886 SAK-XC886*/888*-8FFA Flash 32 -40 to 125 Automotive SAK-XC886 SAK-XC886*/888*-6FFA Flash 24 -40 to 125 Automotive SAF-XC886 SAF-XC886*/888*-8FFA Flash 32 -40 to 85 Automotive SAF-XC886 SAF-XC886*/888*-6FFA Flash 24 -40 to 85 Automotive SAF-XC886 SAF-XC886*/888*-8FFI Flash 32 -40 to 85 Industrial SAF-XC886 SAF-XC886*/888*-6FFI Flash 24 -40 to 85 Industrial Note: The asterisk (*) above denotes the device configuration letters from Table 1. Corresponding ROM derivatives will be available on request. Data Sheet Prelimary 3 V0.1, 2006-02 XC886/888CLM XC886/888CLM Summary of Features Ordering Information The ordering code for Infineon Technologies microcontrollers provides an exact reference to the required product. This ordering code indentifies: · The derivative itself, i.e. its function set · the specified temperature range · the package and the type of delivery For the available ordering codes for the XC886/888 XC886/888, please refer to the "Product Catalog Microcontrollers" which summarizes all available microcontroller variants. Note: The ordering codes for the Mask-ROM versions are defined for each product after verification of the respective ROM code. Data Sheet Prelimary 4 V0.1, 2006-02 XC886/888CLM XC886/888CLM General Device Information 2 General Device Information 2.1 Block Diagram XC886/888 XC886/888 T0 & T1 UART CORDIC SSC WDT P2.0 - P2.7 Timer 2 1.5-Kbyte XRAM 24/32-Kbyte Flash or ROM 2) P1.0 - P1.7 UART1 MDU Port 0 TMS MBC RESET VDDP VSSP VDDC VSSC 256-byte RAM + 64-byte monitor RAM P0.0 - P0.7 Port 1 XC800 XC800 Core Port 2 Internal Bus 12-Kbyte Boot ROM1) ADC Timer 21 CCU6 P3.0 - P3.7 Port 4 9.6 MHz On-chip OSC Port 3 OCDS VAREF VAGND P4.0 - P4.7 Port 5 XTAL1 XTAL2 Clock Generator P5.0 - P5.7 PLL MCAN 1) Includes 1-Kbyte monitor ROM 2) The 24/32-Kbyte ROM has an additional 4-Kbyte Flash Figure 2 Data Sheet Prelimary XC886/888 XC886/888 Block Diagram 5 V0.1, 2006-02 XC886/888CLM XC886/888CLM General Device Information 2.2 Logic Symbol VDDP VDDP VSSP VSSP Port 0 8-Bit VAREF VAREF Port 0 7-Bit VAGND Port 1 8-Bit VAGND Port 1 8-Bit RESET XC886 XC886 MBC TMS Port 2 8-Bit RESET Port 2 8-Bit MBC Port 3 8-Bit Port 4 8-Bit XTAL1 Port 4 3-Bit XTAL2 VDDC Data Sheet Prelimary Port 3 8-Bit TMS XTAL1 Figure 3 XC888 XC888 XTAL2 VSSC Port 5 8-Bit VDDC VSSC XC886/888 XC886/888 Logic Symbol 6 V0.1, 2006-02 XC886/888CLM XC886/888CLM General Device Information P2.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P4.3 P3.6 P3.7 P3.0 Pin Configuration P3.1 2.3 36 35 34 33 32 31 30 29 28 27 26 25 P3.2 37 24 V AREF P3.3 38 23 V AGND P3.4 39 22 P2.6 P3.5 40 21 P2.5 RESET 41 20 P2.4 V SSP 42 19 P2.3 V DDP 43 18 V SSP MBC 44 17 V DDP P4.0 45 16 P2.2 XC886 XC886 P4.1 46 15 P2.1 P0.7 47 14 P2.0 P0.3 48 13 P0.1 VSSC VDDC 9 10 11 12 P0.2 XTAL1 8 P0.0 XTAL2 7 TMS 6 P1.7 5 P1.6 4 P0.5 Data Sheet Prelimary 3 P0.4 Figure 4 2 VDDP 1 XC886 XC886 Pin Configuration, PG-TQFP-48 PG-TQFP-48 Package (top view) 7 V0.1, 2006-02 XC886/888CLM XC886/888CLM P2.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P4.3 P3.6 P3.7 P3.0 P3.1 P4.4 P4.5 P4.6 P4.7 General Device Information 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P3.2 49 32 V AREF P3.3 50 31 V AGND P3.4 51 30 P2.6 P3.5 52 29 P2.5 RESET 53 28 P2.4 V SSP 54 27 P2.3 V DDP 55 26 V SSP NC 56 25 V DDP NC 57 MBC XC888 XC888 24 P2.2 58 23 P2.1 P4.0 59 22 P2.0 P4.1 60 21 P0.1 P4.2 61 20 P5.7 P0.7 62 19 P5.6 P0.3 63 18 P0.2 P0.4 64 17 P0.0 P0.5 P0.6 XTAL2 XTAL1 VSSC VDDC VDDP P5.0 9 10 11 12 13 14 15 16 TMS 8 P5.5 7 P5.4 6 P5.3 5 P5.2 4 P1.7 3 P1.6 2 P5.1 1 Note: The pins shaded in blue are not available in the PG-TQFP-48 PG-TQFP-48 package. Figure 5 Data Sheet Prelimary XC888 XC888 Pin Configuration, PG-TQFP-64 PG-TQFP-64 Package (top view) 8 V0.1, 2006-02 XC886/888CLM XC886/888CLM General Device Information 2.4 Pin Definitions and Functions Table 3 Pin Definitions and Functions Symbol Pin Number Type Reset Function (TQFP-48/64 TQFP-48/64) State P0 I/O Port 0 Port 0 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, UART1, Timer 2, Timer 21, MCAN and SSC. P0.0 11/17 Hi-Z TCK_0 T12HR T12HR_1 JTAG Clock Input CCU6 Timer 12 Hardware Run Input CC61_1 Input/Output of Capture/ Compare channel 1 CLKOUT_0 Clock Output RXDO_1 UART Transmit Data Output P0.1 13/21 Hi-Z TDI_0 T13HR T13HR_1 P0.2 12/18 PU CTRAP_2 TDO_0 TXD_1 JTAG Serial Data Input CCU6 Timer 13 Hardware Run Input RXD_1 UART Receive Data Input RXDC1_0 MCAN Node 1 Receiver Input COUT61 COUT61_1 Output of Capture/Compare channel 1 EXF2_1 Timer 2 External Flag Output TXDC1_0 P0.3 48/63 Data Sheet Prelimary Hi-Z CCU6 Trap Input JTAG Serial Data Output UART Transmit Data Output/ Clock Output MCAN Node 1 Transmitter Output SCK_1 SSC Clock Input/Output COUT63 COUT63_1 Output of Capture/Compare channel 3 RXDO1_0 UART1 Transmit Data Output 9 V0.1, 2006-02 XC886/888CLM XC886/888CLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number Type Reset Function (TQFP-48/64 TQFP-48/64) State P0.4 1/64 Hi-Z MTSR_1 CC62_1 TXD1_0 SSC Master Transmit Output/ Slave Receive Input Input/Output of Capture/ Compare channel 2 UART1 Transmit Data Output/ Clock Output P0.5 2/1 Hi-Z MRST_1 P0.6 ­/2 PU GPIO P0.7 47/62 PU CLKOUT_1 Clock Output Data Sheet Prelimary SSC Master Receive Input/ Slave Transmit Output EXINT0_0 External Interrupt Input 0 T2EX1_1 Timer 21 External Trigger Input RXD1_0 UART1 Receive Data Input COUT62 COUT62_1 Output of Capture/Compare channel 2 10 V0.1, 2006-02 XC886/888CLM XC886/888CLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number Type Reset Function (TQFP-48/64 TQFP-48/64) State P1 I/O Port 1 Port 1 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for the JTAG, CCU6, UART, Timer 0, Timer 1, Timer 2, Timer 21, MCAN and SSC. P1.0 26/34 PU RXD_0 T2EX RXDC0_0 UART Receive Data Input Timer 2 External Trigger Input MCAN Node 0 Receiver Input P1.1 27/35 PU EXINT3 T0_1 TDO_1 TXD_0 External Interrupt Input 3 Timer 0 Input JTAG Serial Data Output UART Transmit Data Output/ Clock Output MCAN Node 0 Transmitter Output TXDC0_0 P1.2 28/36 PU SCK_0 SSC Clock Input/Output P1.3 29/37 PU MTSR_0 SSC Master Transmit Output/ Slave Receive Input MCAN Node 1 Transmitter Output TXDC1_3 P1.4 EXINT0_1 RXDC1_3 P1.5 30/38 31/39 Data Sheet Prelimary PU PU MRST_0 SSC Master Receive Input/ Slave Transmit Output External Interrupt Input 6 MCAN Node 1 Receiver Input CCPOS0_1 EXINT5 T1_1 EXF2_0 RXDO_0 CCU6 Hall Input 0 External Interrupt Input 5 Timer 1 Input Timer 2 External Flag Output UART Transmit Data Output 11 V0.1, 2006-02 XC886/888CLM XC886/888CLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number Type Reset Function (TQFP-48/64 TQFP-48/64) State P1.6 8/10 PU CCPOS1_1 CCU6 Hall Input 1 T12HR T12HR_0 CCU6 Timer 12 Hardware Run Input EXINT6_0 External Interrupt Input 6 RXDC0_2 MCAN Node 0 Receiver Input T21_1 Timer 21 Input P1.7 9/11 PU CCPOS2_1 CCU6 Hall Input 2 T13HR T13HR_0 CCU6 Timer 13 Hardware Run Input T2_1 Timer 2 Input TXDC0_2 MCAN Node 0 Transmitter Output P1.5 and P1.6 can be used as a software chip select output for the SSC. Data Sheet Prelimary 12 V0.1, 2006-02 XC886/888CLM XC886/888CLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number Type Reset Function (TQFP-48/64 TQFP-48/64) State P2 I Port 2 Port 2 is an 8-bit general purpose input-only port. It can be used as alternate functions for the digital inputs of the JTAG and CCU6. It is also used as the analog inputs for the ADC. P2.0 14/22 Hi-Z CCPOS0_0 CCU6 Hall Input 0 EXINT1_0 External Interrupt Input 1 T12HR T12HR_2 CCU6 Timer 12 Hardware Run Input TCK_1 JTAG Clock Input CC61_3 Input of Capture/Compare channel 1 AN0 Analog Input 0 P2.1 15/23 Hi-Z CCPOS1_0 CCU6 Hall Input 1 EXINT2_0 External Interrupt Input 2 T13HR T13HR_2 CCU6 Timer 13 Hardware Run Input TDI_1 JTAG Serial Data Input CC62_3 Input of Capture/Compare channel 2 AN1 Analog Input 1 P2.2 16/24 Hi-Z CCPOS2_0 CCU6 Hall Input 2 CCU6 Trap Input CTRAP_1 CC60_3 Input of Capture/Compare channel 0 AN2 Analog Input 2 P2.3 19/27 Hi-Z AN3 Analog Input 3 P2.4 20/28 Hi-Z AN4 Analog Input 4 P2.5 21/29 Hi-Z AN5 Analog Input 5 P2.6 22/30 Hi-Z AN6 Analog Input 6 P2.7 25/33 Hi-Z AN7 Analog Input 7 Data Sheet Prelimary 13 V0.1, 2006-02 XC886/888CLM XC886/888CLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number Type Reset Function (TQFP-48/64 TQFP-48/64) State P3 I/O Port 3 Port 3 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for CCU6, UART1, Timer 21 and MCAN. P3.0 35/43 Hi-Z CCPOS1_2 CCU6 Hall Input 1 CC60_0 Input/Output of Capture/ Compare channel 0 RXDO1_1 UART1 Transmit Data Output P3.1 36/44 Hi-Z CCPOS0_2 CCU6 Hall Input 0 CC61_2 Input/Output of Capture/ Compare channel 1 COUT60 COUT60_0 Output of Capture/Compare channel 0 TXD1_1 UART1 Transmit Data Output/ Clock Output P3.2 37/49 Hi-Z CCPOS2_2 RXDC1_1 RXD1_1 CC61_0 P3.3 38/50 Hi-Z COUT61 COUT61_0 Output of Capture/Compare channel 1 TXDC1_1 MCAN Node 1 Transmitter Output P3.4 39/51 Hi-Z CC62_0 RXDC0_1 T2EX1_0 CCU6 Hall Input 2 MCAN Node 0 Receiver Input UART1 Receive Data Input Input/Output of Capture/ Compare channel 1 Input/Output of Capture/ Compare channel 2 MCAN Node 0 Receiver Input Timer 21 External Trigger Input P3.5 40/52 Hi-Z COUT62 COUT62_0 Output of Capture/Compare channel 2 EXF21 EXF21_0 Timer 21 External Flag Output TXDC0_1 MCAN Node 0 Transmitter Output P3.6 33/41 PD CTRAP_0 Data Sheet Prelimary 14 CCU6 Trap Input V0.1, 2006-02 XC886/888CLM XC886/888CLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number Type Reset Function (TQFP-48/64 TQFP-48/64) State P3.7 34/42 P4 Hi-Z I/O EXINT4 External Interrupt Input 4 COUT63 COUT63_0 Output of Capture/Compare channel 3 Port 4 Port 4 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for CCU6, Timer 0, Timer 1, Timer 21 and MCAN. P4.0 45/59 Hi-Z RXDC0_3 CC60_1 P4.1 46/60 Hi-Z TXDC0_3 P4.2 ­/61 PU EXINT6_1 T21_0 P4.3 32/40 Hi-Z EXF21 EXF21_1 Timer 21 External Flag Output COUT63 COUT63_2 Output of Capture/Compare channel 3 P4.4 ­/45 Hi-Z CCPOS0_3 CCU6 Hall Input 0 T0_0 Timer 0 Input CC61_4 Output of Capture/Compare channel 1 P4.5 ­/46 Hi-Z CCPOS1_3 CCU6 Hall Input 1 T1_0 Timer 1 Input COUT61 COUT61_2 Output of Capture/Compare channel 1 P4.6 ­/47 Hi-Z CCPOS2_3 CCU6 Hall Input 2 T2_0 Timer 2 Input CC62_2 Output of Capture/Compare channel 2 P4.7 ­/48 Hi-Z CCU6 Trap Input CTRAP_3 COUT62 COUT62_2 Output of Capture/Compare channel 2 Data Sheet Prelimary MCAN Node 0 Receiver Input Output of Capture/Compare channel 0 MCAN Node 0 Transmitter Output COUT60 COUT60_1 Output of Capture/Compare channel 0 15 External Interrupt Input 6 Timer 21 Input V0.1, 2006-02 XC886/888CLM XC886/888CLM General Device Information Table 3 Pin Definitions and Functions (cont'd) Symbol Pin Number Type Reset Function (TQFP-48/64 TQFP-48/64) State P5 I/O Port 5 Port 5 is an 8-bit bidirectional general purpose I/O port. It can be used as alternate functions for UART, UART1 and JTAG. P5.0 ­/8 PU EXINT1_1 External Interrupt Input 1 P5.1 ­/9 PU EXINT2_1 External Interrupt Input 2 P5.2 ­/12 PU RXD_2 UART Receive Data Input P5.3 ­/13 PU TXD_2 UART Transmit Data Output/ Clock Output P5.4 ­/14 PU RXDO_2 UART Transmit Data Output P5.5 ­/15 PU TDO_2 TXD1_2 JTAG Serial Data Output UART1 Transmit Data Output/ Clock Output P5.6 ­/19 PU TCK_2 RXDO1_2 JTAG Clock Input UART1 Transmit Data Output P5.7 ­/20 PU TDI_2 RXD1_2 JTAG Serial Data Input UART1 Receive Data Input VDDP 7, 17, 43/ 7, 25, 55 ­ I/O Port Supply (3.3 or 5.0 V) VSSP VDDC VSSC VAREF VAGND 18, 42/26, 54 ­ ­ I/O Port Ground 6/6 ­ ­ Core Supply Monitor (2.5 V) 5/5 ­ ­ Core Supply Ground 24/32 ­ ­ ADC Reference Voltage 23/31 ­ ­ ADC Reference Ground XTAL1 4/4 I Hi-Z External Oscillator Input (backup for on-chip OSC, normally NC) XTAL2 3/3 O Hi-Z External Oscillator Output (backup for on-chip OSC, normally NC) TMS ­ 10/16 I PD Test Mode Select RESET 41/53 I PU Reset Input MBC 44/58 I PU Monitor & BootStrap Loader Control NC ­/21, 59, 60 ­ ­ No Connection Data Sheet Prelimary 16 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description 3 Functional Description 3.1 Processor Architecture The XC886/888 XC886/888 is based on a high-performance 8-bit Central Processing Unit (CPU) that is compatible with the standard 8051 processor. While the standard 8051 processor is designed around a 12-clock machine cycle, the XC886/888 XC886/888 CPU uses a 2-clock machine cycle. This allows fast access to ROM or RAM memories without wait state. Access to the Flash memory, however, requires an additional wait state (one machine cycle). The instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte instructions. The XC886/888 XC886/888 CPU provides a range of debugging features, including basic stop/start, single-step execution, breakpoint support and read/write access to the data memory, program memory and SFRs. Figure 6 shows the CPU functional blocks. Data Sheet Prelimary 17 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description Internal Data Memory Core SFRs Register Interface External Data Memory External SFRs 16-bit Registers & Memory Interface ALU Opcode & Immediate Registers Multiplier / Divider Opcode Decoder Timer 0 / Timer 1 State Machine & Power Saving UART Program Memory fCCLK Memory Wait Reset Legacy External Interrupts (IEN0, IEN1) External Interrupts Non-Maskable Interrupt Figure 6 3.2 Interrupt Controller CPU Block Diagram Memory Organization The XC886/888 XC886/888 CPU operates in the following five address spaces: · 12 Kbytes of Boot ROM program memory · 256 bytes of internal RAM data memory · 1.5 Kbytes of XRAM memory (XRAM can be read/written as program memory or external data memory) · a 128-byte Special Function Register area · 24/32 Kbytes of Flash program memory (Flash devices); or 24/32 Kbytes of ROM program memory, with additional 4 Kbytes of Flash (ROM devices) Figure 7 illustrates the memory address spaces of the 32-Kbyte Flash devices. For the 24-Kbyte Flash devices, the shaded banks are not available. Data Sheet Prelimary 18 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description FFFFH FFFF H F600H F600H F600H F600H 1) In 24-Kbyte Flash devices, the upper 2Kbyte of Banks 4 and 5 are not available. XRAM 1.5 Kbytes XRAM 1.5 Kbytes F000H F000H F000H F000H Boot ROM 12 Kbytes C000H C000H D-Flash Bank 1 4 Kbytes B000H B000H D-Flash Bank 0 4 Kbytes A000H A000H 8000H 8000H D-Flash Bank 0 4 Kbytes 7000H 7000H D-Flash Bank 1 4 Kbytes 6000H 6000H P-Flash Banks 4 and 5 2 x 4 Kbytes 1) Indirect Address Direct Address Internal RAM 5000H 5000H Special Function Registers FF H 4000H 4000H P-Flash Banks 2 and 3 2 x 4 Kbytes 80H 2000H 2000H 7FH P-Flash Banks 0 and 1 2 x 4 Kbytes Internal RAM 0000H 0000H Program Space Figure 7 Data Sheet Prelimary 0000H 0000H 00H External Data Space Internal Data Space Memory Map of XC886/888 XC886/888 Flash Device 19 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description 3.2.1 Memory Protection Strategy The XC886/888 XC886/888 memory protection strategy includes: · Read-out protection: The user is able to protect the contents in the Flash (for Flash devices) and ROM (for ROM devices) memory from being read · Flash program and erase protection (for Flash devices only) Flash memory protection modes are available only for Flash devices: · Mode 0: Only the P-Flash is protected; the D-Flash is unprotected · Mode 1: Both the P-Flash and D-Flash are protected The selection of each protection mode and the restrictions imposed are summarized in Table 4. Table 4 Flash Protection Modes Mode 0 1 Activation Program a valid password via BSL mode 6 Selection MSB of password = 0 MSB of password = 1 P-Flash contents Read instructions in the can be read by P-Flash Read instructions in the P-Flash or D-Flash P-Flash program Not possible and erase Not possible D-Flash contents Read instructions in any program can be read by memory Read instructions in the P-Flash or D-Flash D-Flash program Possible Not possible D-Flash erase Not possible Possible, on the condition that bit DFLASHEN in register MISC_CON is set to 1 prior to each erase operation BSL mode 6, which is used for enabling Flash protection, can also be used for disabling Flash protection. Here, the programmed password must be provided by the user. A password match triggers an automatic erase of the protected P-Flash and D-Flash contents, including the programmed password. The Flash protection is then disabled upon the next reset. Although no protection scheme can be considered infallible, the XC886/888 XC886/888 memory protection strategy provides a very high level of protection for a general purpose microcontroller. Note: If ROM read-out protection is enabled, only read instructions in the ROM memory can target the ROM contents. Data Sheet Prelimary 20 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description 3.2.2 Special Function Register The Special Function Registers (SFRs) occupy direct internal data memory space in the range 80H to FFH. All registers, except the program counter, reside in the SFR area. The SFRs include pointers and registers that provide an interface between the CPU and the on-chip peripherals. As the 128-SFR 128-SFR range is less than the total number of registers required, address extension mechanisms are required to increase the number of addressable SFRs. The address extension mechanisms include: · Mapping · Paging 3.2.2.1 Address Extension by Mapping Address extension is performed at the system level by mapping. The SFR area is extended into two portions: the standard (non-mapped) SFR area and the mapped SFR area. Each portion supports the same address range 80H to FFH, bringing the number of addressable SFRs to 256. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bit RMAP in the system control register SYSCON0 at address 8FH. To access SFRs in the mapped area, bit RMAP in SFR SYSCON0 must be set. Alternatively, the SFRs in the standard area can be accessed by clearing bit RMAP. The SFR area can be selected as shown in Figure 8. SYSCON0 System Control Register 0 7 6 Reset Value: 00H 5 4 3 2 1 0 0 IMODE 0 RMAP r rw r rw The functions of the shaded bits are not described here Field Bits Type Description RMAP 0 rw Special Function Register Map Control 0 The access to the standard SFR area is enabled. 1 The access to the mapped SFR area is enabled. 0 [7:5], [3:1] r Reserved Returns 0 if read; should be written with 0. Data Sheet Prelimary 21 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description Note: The RMAP bit must be cleared/set by ANL or ORL instructions. The rest bits of SYSCON0 should not be modified. As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not cleared automatically by hardware. Thus, before standard/mapped registers are accessed, bit RMAP must be cleared/set, respectively, by software. Standard Area (RMAP = 0) FFH Module 1 SFRs Module 2 SFRs SYSCON0.RMAP rw . Module n SFRs 80H SFR Data (to/from CPU) Mapped Area (RMAP = 1) FFH Module (n+1) SFRs Module (n+2) SFRs . Module m SFRs 80H Direct Internal Data Memory Address Figure 8 Data Sheet Prelimary Address Extension by Mapping 22 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description 3.2.2.2 Address Extension by Paging Address extension is further performed at the module level by paging. With the address extension by mapping, the XC886/888 XC886/888 has a 256-SFR 256-SFR address range. However, this is still less than the total number of SFRs needed by the on-chip peripherals. To meet this requirement, some peripherals have a built-in local address extension mechanism for increasing the number of addressable SFRs. The extended address range is not directly controlled by the CPU instruction itself, but is derived from bit field PAGE in the module page register MOD_PAGE. Hence, the bit field PAGE must be programmed before accessing the SFR of the target module. Each module may contain a different number of pages and a different number of SFRs per page, depending on the specific requirement. Besides setting the correct RMAP bit value to select the SFR area, the user must also ensure that a valid PAGE is selected to target the desired SFR. A page inside the extended address range can be selected as shown in Figure 9. SFR Address (from CPU) PAGE 0 MOD_PAGE.PAGE SFR0 rw SFR1 . SFRx PAGE 1 SFR0 SFR Data (to/from CPU) SFR1 . SFRy . PAGE q SFR0 SFR1 . SFRz Module Figure 9 Data Sheet Prelimary Address Extension by Paging 23 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description In order to access a register located in a page different from the actual one, the current page must be left. This is done by reprogramming the bit field PAGE in the page register. Only then can the desired access be performed. If an interrupt routine is initiated between the page register access and the module register access, and the interrupt needs to access a register located in another page, the current page setting can be saved, the new one programmed and finally, the old page setting restored. This is possible with the storage fields STx (x = 0 - 3) for the save and restore action of the current page setting. By indicating which storage bit field should be used in parallel with the new page value, a single write operation can: · Save the contents of PAGE in STx before overwriting with the new value (this is done in the beginning of the interrupt routine to save the current page setting and program the new page number); or · Overwrite the contents of PAGE with the contents of STx, ignoring the value written to the bit positions of PAGE (this is done at the end of the interrupt routine to restore the previous page setting before the interrupt occurred) ST3 ST2 ST1 ST0 STNR PAGE value update from CPU Figure 10 Storage Elements for Paging With this mechanism, a certain number of interrupt routines (or other routines) can perform page changes without reading and storing the previously used page information. The use of only write operations makes the system simpler and faster. Consequently, this mechanism significantly improves the performance of short interrupt routines. The XC886/888 XC886/888 supports local address extension for: · · · · Parallel Ports Analog-to-Digital Converter (ADC) Capture/Compare Unit 6 (CCU6) System Control Registers Data Sheet Prelimary 24 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description The page register has the following definition: MOD_PAGE Page Register for module MOD 7 6 Reset Value: 00H 5 4 3 2 1 OP STNR 0 PAGE w w r 0 rw Field Bits Type Description PAGE [2:0] rw Page Bits When written, the value indicates the new page. When read, the value indicates the currently active page. STNR [5:4] w Storage Number This number indicates which storage bit field is the target of the operation defined by bit field OP. If OP = 10B, the contents of PAGE are saved in STx before being overwritten with the new value. If OP = 11B, the contents of PAGE are overwritten by the contents of STx. The value written to the bit positions of PAGE is ignored. 00 01 10 11 Data Sheet Prelimary ST0 is selected. ST1 is selected. ST2 is selected. ST3 is selected. 25 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description Field Bits Type Description OP [7:6] w Operation 0X Manual page mode. The value of STNR is ignored and PAGE is directly written. 10 New page programming with automatic page saving. The value written to the bit positions of PAGE is stored. In parallel, the previous contents of PAGE are saved in the storage bit field STx indicated by STNR. 11 Automatic restore page action. The value written to the bit positions PAGE is ignored and instead, PAGE is overwritten by the contents of the storage bit field STx indicated by STNR. 0 3 r Reserved Returns 0 if read; should be written with 0. Data Sheet Prelimary 26 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description 3.2.3 Bit Protection Scheme The bit protection scheme prevents direct software writing of selected bits (i.e., protected bits) using the PASSWD register. When the bit field MODE is 11B, writing 10011B 10011B to the bit field PASS opens access to writing of all protected bits, and writing 10101B 10101B to the bit field PASS closes access to writing of all protected bits. Note that access is opened for maximum 32 CCLKs if the "close access" password is not written. If "open access" password is written again before the end of 32 CCLK cycles, there will be a recount of 32 CCLK cycles. The protected bits include the N- and K-Divider bits, NDIV and KDIV; the Watchdog Timer enable bit, WDTEN; and the power-down and slow-down enable bits, PD and SD. PASSWD Password Register 7 Reset Value: 07H 6 5 4 3 2 1 0 PASS PROTECT _S MODE wh rh rw Field Bits Type Description MODE [1:0] rw Bit Protection Scheme Control bits 00 Scheme Disabled 11 Scheme Enabled (default) Others: Scheme Enabled These two bits cannot be written directly. To change the value between 11B and 00B, the bit field PASS must be written with 11000B 11000B; only then, will the MODE[1:0] be registered. PROTECT_S 2 rh Bit Protection Signal Status bit This bit shows the status of the protection. 0 Software is able to write to all protected bits. 1 Software is unable to write to any protected bits. PASS [7:3] wh Password bits The Bit Protection Scheme only recognizes three patterns. 11000B 11000B Enables writing of the bit field MODE. 10011B 10011B Opens access to writing of all protected bits. 10101B 10101B Closes access to writing of all protected bits. Data Sheet Prelimary 27 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description 3.2.4 XC886/888 XC886/888 Register Overview The SFRs of the XC886/888 XC886/888 are organized into groups according to their functional units. The contents (bits) of the SFRs are summarized in Table 5 to Table 18, with the addresses of the bitaddressable SFRs appearing in bold typeface. The CPU SFRs can be accessed in both the standard and mapped memory areas (RMAP = 0 or 1). Table 5 Addr CPU Register Overview Register Name RMAP = 0 or 1 SP 81H Stack Pointer Register Bit Reset: 07H DPL Reset: 00H Data Pointer Register Low Bit Field Type 83H DPH Reset: 00H Data Pointer Register High Bit Field Type 87H PCON Power Control Register Reset: 00H Bit Field Type 88H TCON Timer Control Register Reset: 00H Bit Field Type 89H TMOD Timer Mode Register Reset: 00H Bit Field Type 8AH TL0 Timer 0 Register Low Reset: 00H Bit Field Type 8BH TL1 Timer 1 Register Low Reset: 00H Bit Field Type 8CH TH0 Timer 0 Register High Reset: 00H Bit Field Type 8DH TH1 Timer 1 Register High Reset: 00H Bit Field Type 98H SCON Reset: 00H Serial Channel Control Register Bit Field Type 99H SBUF Reset: 00H Serial Data Buffer Register Bit Field Type A2H EO Reset: 00H Extended Operation Register Bit Field A8H IEN0 Reset: 00H Interrupt Enable Register 0 B8H IP Reset: 00H Interrupt Priority Register B9H IPH Reset: 00H Interrupt Priority Register High D0H PSW Reset: 00H Program Status Word Register E0H ACC Accumulator Register E8H IEN1 Reset: 00H Interrupt Enable Register 1 6 5 4 Bit Field Type 82H 7 Reset: 00H Bit Field Type Bit Field Type Bit Field Type Data Sheet Prelimary 2 1 0 SP rw DPL7 DPL6 rw rw DPH7 DPH6 rw rw SMOD rw TF1 TR1 rwh rw GATE1 0 rw r SM0 rw SM1 rw 0 Type Bit Field Type Bit Field Type Bit Field Type 3 r EA rw 0 r DPL5 DPL4 DPL3 DPL2 rw rw rw rw DPH5 DPH4 DPH3 DPH2 rw rw rw rw 0 GF1 GF0 r rw rw TF0 TR0 IE1 IT1 rwh rw rwh rw T1M GATE0 0 rw rw r VAL rwh VAL rwh VAL rwh VAL rwh SM2 REN TB8 RB8 rw rw rw rwh VAL rwh TRAP_ 0 EN rw r DPL1 DPL0 rw rw DPH1 DPH0 rw rw 0 IDLE r rw IE0 IT0 rwh rw T0M rw ET2 rw PT2 rw PT2H rw RI rwh DPSEL 0 rw ET1 rw PT1 rw PT1H rw EX1 rw PX1 rw PX1H rw ET0 rw PT0 rw PT0H rw EX0 rw PX0 rw PX0H rw CY AC F0 RS1 RS0 rwh rwh rw rw rw ACC7 ACC6 ACC5 ACC4 ACC3 rw rw rw rw rw ECCIP ECCIP ECCIP ECCIP EXM 3 2 1 0 rw rw rw rw rw OV rwh ACC2 rw EX2 F1 rw ACC1 rw ESSC P rh ACC0 rw EADC rw rw rw 0 r 0 r 28 ES rw PS rw PSH rw TI rwh V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description Table 5 CPU Register Overview (cont'd) Addr Register Name F0H B B Register Bit F8H IP1 Reset: 00H Interrupt Priority Register 1 F9H IPH1 Reset: 00H Interrupt Priority Register 1 High Reset: 00H Bit Field Type Bit Field Type Bit Field Type 7 6 5 4 3 B7 B6 B5 B4 B3 rw rw rw rw rw PCCIP PCCIP PCCIP PCCIP PXM 3 2 1 0 rw rw rw rw rw PCCIP PCCIP PCCIP PCCIP PXMH 3H 2H 1H 0H rw rw rw rw rw 2 1 0 B2 rw PX2 B1 rw PSSC B0 rw PADC rw rw rw PX2H PSSCH PADC H rw rw rw The MDU SFRs can be accessed in the mapped memory area (RMAP = 1). Table 6 Addr MDU Register Overview Register Name RMAP = 1 MDUSTAT B0H MDU Status Register Bit Reset: 00H Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field B1H MDUCON MDU Control Register Reset: 00H B2H MD0 MDU Data Register 0 Reset: 00H MR0 MDU Data Register 0 Reset: 00H MD1 MDU Data Register 1 Reset: 00H MR1 MDU Data Register 1 Reset: 00H MD2 MDU Data Register 2 Reset: 00H MR2 MDU Data Register 2 Reset: 00H MD3 MDU Data Register 3 Reset: 00H MR3 MDU Data Register 3 Reset: 00H MD4 MDU Data Register 4 Multiplication/Division Shift/Normalization Reset: 00H MR4 MDU Data Register 4 Multiplication/Division Shift/Normalization Reset: 00H MD5 MDU Data Register 5 Reset: 00H Bit Field MR5 MDU Data Register 5 Reset: 00H 7 Type Bit Field B3H B4H B5H B6H B7H Data Sheet Prelimary 6 IE rw IR rw 5 4 3 0 r RSEL START rw rwh DATA rw DATA rh DATA rw DATA rh DATA rw DATA rh DATA rw DATA rh DATA Type 2 1 BSY IERR rh rwh OPCODE rw 0 IRDY rwh rw 0 rw SLR rw Bit Field SCTR rw DATA Type rh 0 rh SCTR rh DATA rw DATA rh Type 29 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description The CORDIC SFRs can be accessed in the mapped memory area (RMAP = 1). Table 7 Addr CORDIC Register Overview Register Name Bit RMAP = 1 CD_CORDXL Reset: 00H 9AH CORDIC X Data Low Byte 9BH CD_CORDXH Reset: 00H CORDIC X Data High Byte 9CH CD_CORDYL Reset: 00H CORDIC Y Data Low Byte 9DH CD_CORDYH Reset: 00H CORDIC Y Data High Byte CD_CORDZL Reset: 00H CORDIC Z Data Low Byte CD_CORDZH Reset: 00H CORDIC Z Data High Byte A0H CD_STATC Reset: 00H CORDIC Status and Data Control Register Bit Field Type Bit Field A1H CD_CON Reset: 00H CORDIC Control Register 5 4 Bit Field Type 9FH 6 Bit Field Type Bit Field Type Bit Field Type Bit Field Type 9EH 7 Type Bit Field Type 3 2 1 0 DATAL rw DATAH rw DATAL rw DATAH rw DATAL rw DATAH rw KEEPZ KEEPY KEEPX DMAP INT_E EOC ERRO N R rw rw rw rw rw rwh rh MPS X_USI ST_MO ROTVE MODE GN DE C rw w rw rw rw BSY rh ST rwh The system control SFRs can be accessed in the standard memory area (RMAP = 0). Table 8 Addr System Control Register Overview Register Name Bit RMAP = 0 or 1 SYSCON0 Reset: 00H 8FH System Control Register 0 Bit Field Type 6 Bit Field Type RMAP = 0 SCU_PAGE BFH Page Register 7 Reset: 00H RMAP = 0, PAGE 0 MODPISEL Reset: 00H B3H Peripheral Input Select Register IRCON0 Reset: 00H Interrupt Request Register 0 B5H IRCON1 Reset: 00H Interrupt Request Register 1 B6H IRCON2 Reset: 00H Interrupt Request Register 2 B7H EXICON0 Reset: F0H External Interrupt Control Register 0 OP w BAH EXICON1 Reset: 3FH External Interrupt Control Register 1 Data Sheet Prelimary Bit Field 0 Type Bit Field 0 Type Bit Field r 0 r r Bit Field Type Bit Field Type Bit Field Type 4 0 r Type B4H 5 IMODE rw STNR w 2 1 0 r 0 r 0 RMAP rw PAGE rw URRIS JTAGT JTAGT EXINT EXINT EXINT URRIS H DIS CKS 2IS 1IS 0IS rw rw rw rw rw rw rw EXINT EXINT EXINT EXINT EXINT EXINT EXINT 6 5 4 3 2 1 0 rwh rwh rwh rwh rwh rwh rwh CANS CANS ADCS ADCS RIR TIR EIR RC2 RC1 RC1 RC0 rwh 0 r EXINT3 rw 0 r 30 3 rwh rwh CANS RC3 rwh EXINT2 rw EXINT6 rw rwh rwh 0 r EXINT1 rw EXINT5 rw rwh rwh CANS RC0 rwh EXINT0 rw EXINT4 rw V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description Table 8 System Control Register Overview (cont'd) Addr Register Name BBH NMICON NMI Control Register Reset: 00H Bit BCH NMISR NMI Status Register Reset: 00H BDH BCON Reset: 00H Baud Rate Control Register BEH BG Reset: 00H Baud Rate Timer/Reload Register E9H FDCON Reset: 00H Fractional Divider Control Register EAH FDSTEP Reset: 00H Fractional Divider Reload Register EBH FDRES Reset: 00H Fractional Divider Result Register 7 Bit Field 0 Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type RMAP = 0, PAGE 1 ID B3H Identity Register Reset: 09H Bit Field Type Bit Field Type r r 0 Type r PMCON1 Reset: 00H Power Mode Control Register 1 B6H OSC_CON OSC Control Register Reset: 08H Bit Field B7H PLL_CON PLL Control Register Reset: 90H CMCON Clock Control Register Reset: 10H Type Bit Field BBH PASSWD Password Register Reset: 07H Type Bit Field BCH FEAL Reset: 00H Flash Error Address Register Low BDH FEAH Reset: 00H Flash Error Address Register High BEH COCON Reset: 00H Clock Output Control Register E9H MISC_CON Reset: 00H Miscellaneous Control Register PRODID r WDT WKRS RST rwh rwh CDC_D CAN_D IS IS rw rw 0 Bit Field BAH 3 Type r NDIV rw VCO SEL rw KDIV 0 rw Type 0 NMI WDT rw FNMI WDT rwh R rw r PASS 0 r FDEN rw WK SD PD SEL rw rw rwh rw MDU_ T2_DIS CCU SSC ADC DIS _DIS _DIS _DIS rw rw rw rw rw OSC XPD OSC ORDR OSCR PD SS ES rw rw rw rwh rh VCOB OSC RESLD LOCK YP DISC rw rw rwh rh FCCFG CLKREL rw rw PROTE CT_S rh ECCERRADDR rh ECCERRADDR rh TLEN COUT S rw rw Bit Field 0 Type Data Sheet Prelimary 1 NMI PLL VERID r WS wh Bit Field Type Bit Field Type Bit Field Type RMAP = 0, PAGE 3 XADDRH Reset: F0H B3H On-chip XRAM Address Higher Order 2 NMI NMI OCDS FLASH rw rw rw FNMI FNMI FNMI FNMI FNMI VDDP VDD OCDS FLASH PLL rwh rwh rwh rwh rwh 0 BRDIS BRPRE r rw rw BR_VALUE rwh BGS SYNEN ERRSY EOFSY BRK NDOV FDM N N rw rw rwh rwh rwh rwh rw STEP rw RESULT rh Type Bit Field B5H 4 NMI VDD rw FNMI ECC r rwh BGSEL rw 0 PMCON0 Reset: 00H Power Mode Control Register 0 5 NMI VDDP rw 0 Bit Field Type Bit Field B4H 6 NMI ECC rw r Bit Field Type MODE rw COREL rw ADDRH rw 31 DFLAS HEN rwh V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description Table 8 System Control Register Overview (cont'd) Addr Register Name Bit B4H IRCON3 Reset: 00H Interrupt Request Register 3 Bit Field B5H IRCON4 Reset: 00H Interrupt Request Register 4 B7H MODPISEL1 Reset: 00H Peripheral Input Select Register 1 BAH MODPISEL2 Reset: 00H Peripheral Input Select Register 2 BBH PMCON2 Reset: 00H Power Mode Control Register 2 BDH MODSUSP Reset: 00H Module Suspend Control Register 7 6 0 Type r Bit Field 0 Type Bit Field Type Bit Field Type 5 4 3 CANS CCU6S RC5 R1 rwh rwh CANS CCU6S RC7 R3 rwh rwh 0 UR1RIS r EXINT 6IS rw 0 Type r Bit Field 0 Type r 1 0 CANS CCU6S RC4 R0 rwh rwh CANS CCU6S RC6 R2 r rwh rwh T21EXI T21EXI JTAGT JTAGT S DIS1 CKS1 rw rw rw rw T21IS T21IS T2IS T1IS T0IS rw rw rw rw UART1 T21 _DIS _DIS r 0 r Bit Field 2 0 r 0 rw rw T21SU T21SU T2SUS T13SU T13SU T12SU T12SU WDTS SP P SP SP USP rw rw rw rw rw The WDT SFRs can be accessed in the mapped memory area (RMAP = 1). Table 9 Addr WDT Register Overview Register Name Bit RMAP = 1 WDTCON Reset: 00H BBH Watchdog Timer Control Register 7 6 WDTREL Reset: 00H Watchdog Timer Reload Register BDH WDTWINB Reset: 00H Watchdog Window-Boundary Count Register BEH WDTL Reset: 00H Watchdog Timer Register Low BFH WDTH Reset: 00H Watchdog Timer Register High r 4 3 2 1 0 WINB EN rw 0 Type BCH Bit Field 5 WDT PR rh 0 WDT EN WDT RS WDT IN rw rwh rw 1 0 Bit Field Type Bit Field r WDTREL rw WDTWINB Type Bit Field rw WDT[7:0] rh WDT[15:8] rh Type Bit Field Type The Port SFRs can be accessed in the standard memory area (RMAP = 0). Table 10 Addr Port Register Overview Register Name Bit RMAP = 0 PORT_PAGE Reset: 00H B2H Page Register for PORT Bit Field Type RMAP = 0, Page 0 P0_DATA 80H P0 Data Register Reset: 00H Bit Field Type 7 OP w 86H P0_DIR P0 Direction Register Reset: 00H Bit Field Type P7 rw P7 rw 90H P1_DATA P1 Data Register Reset: 00H Bit Field Type P7 rw Data Sheet Prelimary 6 32 5 4 STNR w P6 rw P6 rw P5 rw P5 rw P4 rw P4 rw P6 rw P5 rw P4 rw 3 2 0 r PAGE rw P3 rw P3 P2 rw P2 P1 rw P1 P0 rw P0 rw P3 rw rw P2 rw rw P1 rw rw P0 rw V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description Table 10 Port Register Overview (cont'd) Addr Register Name Bit 7 6 5 4 3 2 1 0 91H P1_DIR P1 Direction Register Reset: 00H Bit Field 92H P5_DATA P5 Data Register Reset: 00H Type Bit Field 93H P5_DIR P5 Direction Register Reset: 00H Type Bit Field A0H P2_DATA P2 Data Register Reset: 00H Type Bit Field Type Bit Field P0 rw P0 rw P0 rw P0 rw B0H P3_DATA P3 Data Register Reset: 00H Type Bit Field B1H P3_DIR P3 Direction Register Reset: 00H Bit Field Type C8H P4_DATA P4 Data Register Reset: 00H Bit Field Type C9H P4_DIR P4 Direction Register Reset: 00H Bit Field Type P4 rw P4 rw P4 rw P4 rw P4 rw P4 rw P4 rw P4 rw P4 rw P1 rw P1 rw P1 rw P1 rw Reset: 00H P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P2 rw P2 rw P2 rw P2 rw P2_DIR P2 Direction Register P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P3 rw P3 rw P3 rw P3 rw A1H P7 rw P7 rw P7 rw P7 rw P7 rw P7 rw P7 rw P7 rw P7 rw P3 rw P3 rw P3 rw P3 rw P3 rw P2 rw P2 rw P2 rw P2 rw P2 rw P1 rw P1 rw P1 rw P1 rw P1 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0_PUDEN Reset: C4H Bit Field P0 Pull-Up/Pull-Down Enable Register Type P1_PUDSEL Reset: FFH Bit Field P1 Pull-Up/Pull-Down Select Register Type P1_PUDEN Reset: FFH Bit Field P1 Pull-Up/Pull-Down Enable Register Type P5_PUDSEL Reset: FFH Bit Field P5 Pull-Up/Pull-Down Select Register Type P5_PUDEN Reset: FFH Bit Field P5 Pull-Up/Pull-Down Enable Register Type P2_PUDSEL Reset: FFH Bit Field P2 Pull-Up/Pull-Down Select Register Type P2_PUDEN Reset: 00H Bit Field P2 Pull-Up/Pull-Down Enable Register Type P3_PUDSEL Reset: BFH Bit Field P3 Pull-Up/Pull-Down Select Register Type P3_PUDEN Reset: 40H Bit Field P3 Pull-Up/Pull-Down Enable Register Type P4_PUDSEL Reset: FFH Bit Field P4 Pull-Up/Pull-Down Select Register Type P7 rw P7 rw P7 rw P7 rw P7 rw P7 rw P7 rw P7 rw P7 rw P7 rw P7 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P4 rw P4 rw P4 rw P4 rw P4 rw P4 rw P4 rw P4 rw P4 rw P4 rw P4 rw P3 rw P3 rw P3 rw P3 rw P3 rw P3 rw P3 rw P3 rw P3 rw P3 rw P3 P2 rw P2 rw P2 rw P2 rw P2 rw P2 rw P2 rw P2 rw P2 rw P2 rw P2 P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 rw P1 P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 rw P0 P4_PUDEN Reset: 04H Bit Field P4 Pull-Up/Pull-Down Enable Register Type P7 rw P6 rw P5 rw P4 rw rw P3 rw rw P2 rw rw P1 rw rw P0 rw P7 rw P7 rw P7 rw P6 rw P6 rw P6 rw P5 rw P5 rw P5 rw P4 rw P4 rw P4 rw P3 rw P3 rw P3 rw P2 rw P2 rw P2 rw P1 rw P1 rw P1 rw P0 rw P0 rw P0 rw Type RMAP = 0, Page 1 P0_PUDSEL Reset: FFH 80H P0 Pull-Up/Pull-Down Select Register 86H 90H 91H 92H 93H A0H A1H B0H B1H C8H C9H RMAP = 0, Page 2 P0_ALTSEL0 Reset: 00H 80H P0 Alternate Select 0 Register 86H P0_ALTSEL1 Reset: 00H P0 Alternate Select 1 Register 90H P1_ALTSEL0 Reset: 00H P1 Alternate Select 0 Register Data Sheet Prelimary Bit Field Type Bit Field Type Bit Field Type Bit Field Type 33 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description Table 10 Port Register Overview (cont'd) Addr Register Name Bit 7 6 5 4 3 2 1 0 91H P1_ALTSEL1 Reset: 00H P1 Alternate Select 1 Register Bit Field 92H P5_ALTSEL0 Reset: 00H P5 Alternate Select 0 Register 93H P5_ALTSEL1 Reset: 00H P5 Alternate Select 1 Register B0H P3_ALTSEL0 Reset: 00H P3 Alternate Select 0 Register P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P5 rw P4 rw P4 rw P4 rw P4 rw P4 rw P4 rw P4 rw P2 rw P2 rw P2 rw P2 rw P1 rw P1 rw P1 rw P1 rw P0 rw P0 rw P0 rw P0 rw P3_ALTSEL1 Reset: 00H P3 Alternate Select 1 Register P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P6 rw P3 rw P3 rw P3 rw P3 rw B1H P7 rw P7 rw P7 rw P7 rw P7 rw P7 rw P7 rw P3 rw P3 rw P3 rw P2 rw P2 rw P2 rw P1 rw P1 rw P1 rw P0 rw P0 rw P0 rw P7 rw P7 rw P7 rw P7 rw P7 rw P6 rw P6 rw P6 rw P6 rw P6 rw P5 rw P5 rw P5 rw P5 rw P5 rw P4 rw P4 rw P4 rw P4 rw P4 rw P3 rw P3 rw P3 rw P3 rw P3 rw P2 rw P2 rw P2 rw P2 rw P2 rw P1 rw P1 rw P1 rw P1 rw P1 rw P0 rw P0 rw P0 rw P0 rw P0 rw 1 0 Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field C8H P4_ALTSEL0 Reset: 00H P4 Alternate Select 0 Register C9H P4_ALTSEL1 Reset: 00H P4 Alternate Select 1 Register Bit Field Type RMAP = 0, Page 3 P0_OD Reset: 00H 80H P0 Open Drain Control Register Bit Field Type 90H P1_OD Reset: 00H P1 Open Drain Control Register Bit Field Type 92H P5_OD Reset: 00H P5 Open Drain Control Register Bit Field Type B0H P3_OD Reset: 00H P3 Open Drain Control Register Bit Field Type C8H P4_OD Reset: 00H P4 Open Drain Control Register Bit Field Type Type The ADC SFRs can be accessed in the standard memory area (RMAP = 0). Table 11 Addr ADC Register Overview Register Name Bit RMAP = 0 ADC_PAGE D1H Page Register for ADC Reset: 00H RMAP = 0, Page 0 CAH ADC_GLOBCTR Global Control Register Reset: 30H Bit Field CBH ADC_GLOBSTR Global Status Register Reset: 00H Type Bit Field CCH ADC_PRAR Reset: 00H Priority and Arbitration Register Type Bit Field Type CDH ADC_LCBR Reset: B7H Limit Check Boundary Register Bit Field Type CEH ADC_INPCR0 Input Class Register 0 Reset: 00H ADC_ETRCR Reset: 00H External Trigger Control Register Bit Field 6 Bit Field Type CFH 7 Bit Field Type Type 5 OP w ANON rw 4 STNR w DW rw 0 r ASEN1 ASEN0 0 rw rw r BOUND1 rw SYNEN SYNEN 1 0 rw rw CTC rw CHNR 3 2 0 r PAGE rw 0 r SAM BUSY PLE r rh rh rh ARBM CSM1 PRIO1 CSM0 PRIO0 rw rw rw rw rw BOUND0 rw STC rw ETRSEL1 ETRSEL0 rw 0 rw RMAP = 0, Page 1 Data Sheet Prelimary 34 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description Table 11 ADC Register Overview (cont'd) Addr Register Name Bit 7 CAH ADC_CHCTR0 Reset: 00H Channel Control Register 0 Bit Field CBH ADC_CHCTR1 Reset: 00H Channel Control Register 1 CCH ADC_CHCTR2 Reset: 00H Channel Control Register 2 CDH ADC_CHCTR3 Reset: 00H Channel Control Register 3 CEH ADC_CHCTR4 Reset: 00H Channel Control Register 4 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field CFH ADC_CHCTR5 Reset: 00H Channel Control Register 5 D2H ADC_CHCTR6 Reset: 00H Channel Control Register 6 Bit Field Type D3H ADC_CHCTR7 Reset: 00H Channel Control Register 7 Bit Field Type Type RMAP = 0, Page 2 ADC_RESR0L CAH Result Register 0 Low Reset: 00H Bit Field Type CBH ADC_RESR0H Result Register 0 High Reset: 00H ADC_RESR1L Result Register 1 Low Reset: 00H Bit Field Type CDH ADC_RESR1H Result Register 1 High Reset: 00H Bit Field Type CEH ADC_RESR2L Result Register 2 Low Reset: 00H Bit Field Type CFH ADC_RESR2H Result Register 2 High Reset: 00H Bit Field Type D2H ADC_RESR3L Result Register 3 Low Reset: 00H Bit Field Type D3H ADC_RESR3H Result Register 3 High Reset: 00H 5 Bit Field Type RMAP = 0, Page 3 ADC_RESRA0L Reset: 00H CAH Result Register 0, View A Low CBH ADC_RESRA0H Reset: 00H Result Register 0, View A High ADC_RESRA1L Reset: 00H Result Register 1, View A Low ADC_RESRA1H Reset: 00H Result Register 1, View A High CEH ADC_RESRA2L Reset: 00H Result Register 2, View A Low CFH ADC_RESRA2H Reset: 00H Result Register 2, View A High D2H ADC_RESRA3L Reset: 00H Result Register 3, View A Low D3H ADC_RESRA3H Reset: 00H Result Register 3, View A High RESULT[1:0] rh 0 r RESULT[1:0] rh 0 r RESULT[1:0] rh 0 r Bit Field Type CDH 0 r Bit Field Type CCH RESULT[1:0] rh Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Data Sheet Prelimary RESULT[2:0] rh RESULT[2:0] rh RESULT[2:0] rh RESULT[2:0] rh 35 4 3 LCC rw LCC rw LCC rw LCC rw LCC rw LCC rw LCC rw LCC rw Bit Field Type CCH 6 2 1 0 0 r 0 r 0 r 0 r RESRSEL rw RESRSEL rw RESRSEL rw RESRSEL rw 0 r 0 r 0 r 0 r RESRSEL rw RESRSEL rw RESRSEL rw RESRSEL rw VF DRC rh rh RESULT[9:2] rh VF DRC rh rh RESULT[9:2] rh VF DRC rh rh RESULT[9:2] rh VF DRC rh rh RESULT[9:2] rh CHNR rh VF DRC rh rh RESULT[10:3] rh VF DRC rh rh CHNR rh RESULT[10:3] rh VF DRC rh rh RESULT[10:3] rh VF DRC rh rh RESULT[10:3] rh CHNR rh CHNR rh CHNR rh CHNR rh CHNR rh CHNR rh V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description Table 11 Addr ADC Register Overview (cont'd) Register Name RMAP = 0, Page 4 ADC_RCR0 Reset: 00H CAH Result Control Register 0 Bit 7 6 IEN Type Bit Field rw rw VFCTR WFR rw FEN rw IEN rw rw VFCTR WFR rw FEN rw IEN r 0 Type Bit Field rw rw VFCTR WFR rw FEN rw IEN r 0 rw rw CDH ADC_RCR3 Reset: 00H Result Control Register 3 CEH ADC_VFCR Reset: 00H Valid Flag Clear Register Bit Field Type RMAP = 0, Page 5 ADC_CHINFR Reset: 00H CAH Channel Interrupt Flag Register Bit Field Type Type CDH ADC_CHINPR Reset: 00H Channel Interrupt Node Pointer Register CEH ADC_EVINFR Reset: 00H Event Interrupt Flag Register CFH ADC_EVINCR Reset: 00H Event Interrupt Clear Flag Register D2H ADC_EVINSR Reset: 00H Event Interrupt Set Flag Register D3H ADC_EVINPR Reset: 00H Event Interrupt Node Pointer Register Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type Bit Field Type RMAP = 0, Page 6 ADC_CRCR1 Reset: 00H Bit Field CAH Conversion Request Control Register 1 Type CBH ADC_CRPR1 Reset: 00H Bit Field Conversion Request Pending Register 1 Type CCH ADC_CRMR1 Reset: 00H Conversion Request Mode Register 1 CDH ADC_QMR0 Reset: 00H Queue Mode Register 0 Bit Field Type Data Sheet Prelimary 0 r 0 Type Bit Field 1 0 ADC_RCR2 Reset: 00H Result Control Register 2 ADC_CHINSR Reset: 00H Channel Interrupt Set Register 2 FEN CCH CCH 3 VFCTR WFR ADC_RCR1 Reset: 00H Result Control Register 1 ADC_CHINCR Reset: 00H Channel Interrupt Clear Register 4 Bit Field CBH CBH 5 Bit Field Type rw rw 0 r r VFC2 w VFC3 w CHINF CHINF CHINF CHINF CHINF 7 6 5 4 3 rh rh rh rh rh CHINC CHINC CHINC CHINC CHINC 7 6 5 4 3 w w w w w CHINS CHINS CHINS CHINS CHINS 7 6 5 4 3 w w w w w CHINP CHINP CHINP CHINP CHINP 7 6 5 4 3 rw rw rw rw rw EVINF EVINF EVINF EVINF 7 6 5 4 rh rh rh rh EVINC EVINC EVINC EVINC 7 6 5 4 w w w w CH6 CH5 rh rh rh CHINC CHINC CHINC 2 1 0 w w w CHINS CHINS CHINS 2 1 0 w w w CHINP CHINP CHINP 2 1 0 rw rw rw EVINF EVINF 1 0 rh rh EVINC EVINC 1 0 r 0 r 0 w w EVINS EVINS 1 0 w w EVINP EVINP 1 0 rw rw r 0 r 0 r 0 rwh rwh rwh rwh CHP6 CHP5 CHP4 rwh Rsv rwh LDEV rwh CLR PND w rwh SCAN r 36 w rw VFC0 w CHINF CHINF CHINF 2 1 0 CH4 CHP7 CEV w VFC1 w 0 EVINS EVINS EVINS EVINS 7 6 5 4 w w w w EVINP EVINP EVINP EVINP 7 6 5 4 rw rw rw rw CH7 DRCT R rw DRCT R rw DRCT R rw DRCT R rw TREV FLUSH CLRV w w w r ENSI ENTR ENGT rw 0 r rw ENTR rw rw ENGT rw V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description Table 11 ADC Register Overview (cont'd) Addr Register Name Bit CEH ADC_QSR0 Reset: 20H Queue Status Register 0 Bit Field CFH ADC_Q0R0 Queue 0 Register 0 Reset: 00H D2H ADC_QBUR0 Reset: 00H Queue Backup Register 0 D2H ADC_QINR0 Queue Input Register 0 Reset: 00H Type Bit Field Type Bit Field Type Bit Field Type 7 Rsv r EXTR rh EXTR rh EXTR w 6 5 4 0 EMPTY r rh ENSI RF rh rh ENSI RF rh rh ENSI RF w w 3 EV rh V rh V rh 2 0 r 1 0 FILL rh REQCHNR rh REQCHNR rh REQCHNR w 0 r 0 r 0 r The Timer 2 SFRs can be accessed in the standard memory area (RMAP = 0). Table 12 Timer 2 Register Overview Addr Register Name Bit C0H T2_T2CON Reset: 00H Timer 2 Control Register Bit Field C1H T2_T2MOD Timer 2 Mode Register C2H T2_RC2L Reset: 00H Timer 2 Reload/Capture Register Low C3H T2_RC2H Reset: 00H Bit Field Timer 2 Reload/Capture Register High Type T2_T2L Reset: 00H Bit Field Timer 2 Register Low Type T2_T2H Reset: 00H Bit Field Timer 2 Register High Type Reset: 00H Type Bit Field Type C4H C5H Bit Field Type 7 6 TF2 EXF2 5 4 3 2 1 0 EXEN2 0 TR2 0 rwh T2PRE r CP/ RL2 rw DCEN rwh rwh r rw T2 T2 EDGE PREN REGS RHEN SEL rw rw rw rw RC2 rwh RC2 rwh THL2 rwh THL2 rwh rw rw The Timer 21 SFRs can be accessed in the standard memory area (RMAP = 1). Table 13 Addr T21 Register Overview Register Name Bit RMAP = 1 T2CON Reset: 00H C0H Timer 2 Control Register Bit Field C1H T2MOD Timer 2 Mode Register Reset: 00H Type Bit Field C2H RC2L Reset: 00H Timer 2 Reload/Capture Register Low Type Bit Field Type C3H 7 TF2 RC2H Reset: 00H Bit Field Timer 2 Reload/Capture Register High Type T2L Reset: 00H Bit Field Timer 2 Register Low Type C4H C5H T2H Timer 2 Register High Data Sheet Prelimary Reset: 00H 6 5 4 3 2 1 0 EXF2 0 0 EXEN2 TR2 C/T2 rwh T2PRE rw CP/ RL2 rw DCEN rwh rwh r r rw T2 T2 EDGE PREN REGS RHEN SEL rw rw rw rw RC2 rwh rw rw RC2 rwh THL2 rwh THL2 rwh Bit Field Type 37 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description The CCU6 SFRs can be accessed in the standard memory area (RMAP = 0). Table 14 Addr CCU6 Register Overview Register Name RMAP = 0 CCU6_PAGE Reset: 00H A3H Page Register for CCU6 Bit 7 6 OP w Bit Field Type 5 4 3 STNR w 2 1 0 r 0 PAGE rw RMAP = 0, Page 0 9AH 9BH CCU6_CC63SRL CC63SRL Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC63 Low Type CCU6_CC63SRH CC63SRH Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC63 High Type 9CH CCU6_TCTR4L Reset: 00H Timer Control Register 4 Low Bit Field 9DH CCU6_TCTR4H Reset: 00H Timer Control Register 4 High 9EH CCU6_MCMOUTSL Reset: 00H Multi-Channel Mode Output Shadow Register Low 9FH CCU6_MCMOUTSH Reset: 00H Multi-Channel Mode Output Shadow Register High CCU6_ISRL Reset: 00H Capture/Compare Interrupt Status Reset Register Low A5H CCU6_ISRH Reset: 00H Capture/Compare Interrupt Status Reset Register High Bit Field A6H CCU6_CMPMODIFL Reset: 00H Compare State Modification Register Low A7H CCU6_CMPMODIFH Reset: 00H Compare State Modification Register High FAH FBH FCH FDH FEH FFH rw CC63SH CC63SH T12 STR w T13 STR w 0 Type Bit Field Type STRHP w 0 r Bit Field RT12P RT12P RT12O RT12O RCC62 RCC62 RCC62 RCC62 RCC61 RCC61 RCC61 RCC61 RCC60 RCC60 M M F R F R F w w w w w w w RSTR RIDLE RWHE RCHE 0 RTRPF RT13 PM w w w w r w w 0 MCC63 MCC63 0 MCC62 MCC62 MCC61 MCC61 S S S r w r w w 0 MCC63 MCC63 0 MCC62 MCC62 MCC61 MCC61 R R R r w r w w CC60SL CC60SL Type Bit Field Bit Field Type Type Bit Field Type Bit Field Type CCU6_CC60SRL CC60SRL Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC60 Low Type CCU6_CC60SRH CC60SRH Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC60 High Type 0 T12 RES w w T13 RES w MCMPS r 0 r r T12RS T12RS T12RR T12RR w w T13RS T13RS T13RR T13RR w w rw CURHS rw EXPHS rw RCC60 RCC60 R w RT13 CM w MCC60 MCC60 S w MCC60 MCC60 R w rwh CC60SH CC60SH rwh CCU6_CC61SRL CC61SRL Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC61 Low Type CCU6_CC61SRH CC61SRH Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC61 High Type CCU6_CC62SRL CC62SRL Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC62 Low Type CCU6_CC62SRH CC62SRH Reset: 00H Bit Field Capture/Compare Shadow Register for Channel CC62 High Type Data Sheet Prelimary rw DTRES T12 STD w T13 STD w STRM CM w Type A4H CC63SL CC63SL CC61SL CC61SL rwh CC61SH CC61SH rwh CC62SL CC62SL rwh CC62SH CC62SH rwh 38 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description Table 14 Addr CCU6 Register Overview (cont'd) Register Name Bit 7 6 5 RMAP = 0, Page 1 CCU6_CC63RL CC63RL Reset: 00H Bit Field 9AH Capture/Compare Register for Channel CC63 Low Type CCU6_CC63RH CC63RH Reset: 00H Bit Field 9BH Capture/Compare Register for Channel CC63 High Type CCU6_T12PRL T12PRL Reset: 00H Bit Field 9CH Timer T12 Period Register Low Type 9DH CCU6_T12PRH T12PRH Reset: 00H Timer T12 Period Register High 9EH CCU6_T13PRL T13PRL Reset: 00H Timer T13 Period Register Low 9FH CCU6_T13PRH T13PRH Reset: 00H Timer T13 Period Register High A4H CCU6_T12DTCL T12DTCL Reset: 00H Dead-Time Control Register for Timer T12 Low 4 0 rh CC63VH CC63VH Type Bit Field Type Bit Field Type Bit Field T13PVH T13PVH rwh DTM Type A6H CCU6_TCTR0L Reset: 00H Timer Control Register 0 Low A7H CCU6_TCTR0H Reset: 00H Timer Control Register 0 High FAH rw Bit Field 0 DTR2 DTR1 DTR0 0 DTE2 DTE1 DTE0 Type Bit Field r CTM rh CDIR rh STE12 STE12 rh T12R rw rw T12CLK T12CLK rw rh r T12 PRE rw T13 PRE CCU6_CC60RL CC60RL Reset: 00H Bit Field Capture/Compare Register for Channel CC60 Low Type CCU6_CC60RH CC60RH Reset: 00H Bit Field Capture/Compare Register for Channel CC60 High Type Type Bit Field 0 rh STE13 STE13 rh T13R Type r rh rh FCH FDH rw rw T13CLK T13CLK rw CC60VL CC60VL rw rh CC60VH CC60VH rh CC61VL CC61VL CCU6_CC61RL CC61RL Reset: 00H Bit Field Capture/Compare Register for Channel CC61 Low Type CCU6_CC61RH CC61RH Reset: 00H Bit Field Capture/Compare Register for Channel CC61 High Type CCU6_CC62RL CC62RL Reset: 00H Bit Field Capture/Compare Register for Channel CC62 Low Type FFH 1 CC63VL CC63VL Bit Field CCU6_T12DTCH T12DTCH Reset: 00H Dead-Time Control Register for Timer T12 High FEH 2 rh T12PVL T12PVL rwh T12PVH T12PVH rwh T13PVL T13PVL rwh A5H FBH 3 rh CC61VH CC61VH rh CC62VL CC62VL rh CC62VH CC62VH CCU6_CC62RH CC62RH Reset: 00H Bit Field Capture/Compare Register for Channel CC62 High Type rh RMAP = 0, Page 2 9AH CCU6_T12MSELL T12MSELL Reset: 00H T12 Capture/Compare Mode Select Register Low 9BH CCU6_T12MSELH T12MSELH Reset: 00H T12 Capture/Compare Mode Select Register High Data Sheet Prelimary Bit Field Type Bit Field Type MSEL61 MSEL61 DBYP rw 39 rw HSYNC rw MSEL60 MSEL60 rw MSEL62 MSEL62 rw V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description Table 14 CCU6 Register Overview (cont'd) Addr Register Name Bit 9CH CCU6_IENL Reset: 00H Capture/Compare Interrupt Enable Register Low Bit Field 9DH CCU6_IENH Reset: 00H Capture/Compare Interrupt Enable Register High 9EH CCU6_INPL Reset: 40H Capture/Compare Interrupt Node Pointer Register Low 9FH CCU6_INPH Reset: 39H Capture/Compare Interrupt Node Pointer Register High A4H CCU6_ISSL Reset: 00H Bit Field Capture/Compare Interrupt Status Set Register Low Type CCU6_ISSH Reset: 00H Bit Field Capture/Compare Interrupt Status Set Register High Type CCU6_PSLR Reset: 00H Bit Field Passive State Level Register Type CCU6_MCMCTR Reset: 00H Bit Field Multi-Channel Mode Control Register Type CCU6_TCTR2L Reset: 00H Bit Field Timer Control Register 2 Low Type A5H A6H A7H FAH Type Bit Field Type Bit Field 7 Type Bit Field CCU6_TCTR2H Reset: 00H Timer Control Register 2 High Bit Field Type Bit Field FCH CCU6_MODCTRL Reset: 00H Modulation Control Register Low FDH CCU6_MODCTRH Reset: 00H Modulation Control Register High FEH CCU6_TRPCTRL Reset: 00H Trap Control Register Low Bit Field Type FFH CCU6_TRPCTRH Reset: 00H Trap Control Register High Bit Field Type Bit Field Type Type 5 4 3 2 1 0 rw 0 rw INPT13 INPT13 rw INPT12 INPT12 rw INPERR r Type FBH 6 ENT12 ENT12 ENT12 ENT12 ENCC ENCC ENCC ENCC ENCC ENCC PM OM 62F 62R 61F 61R 60F 60R rw rw rw rw rw rw rw rw ENSTR EN EN EN 0 EN ENT13 ENT13 ENT13 ENT13 IDLE WHE CHE TRPF PM CM rw rw rw rw r rw rw rw INPCHE INPCC62 INPCC62 INPCC61 INPCC61 INPCC60 INPCC60 rw rw rw ST12P ST12P ST12O ST12O SCC62 SCC62 SCC62 SCC62 SCC61 SCC61 SCC61 SCC61 SCC60 SCC60 SCC60 SCC60 M M F R F R F R w w w w w w w w SSTR SIDLE SWHE SCHE SWHC STRPF ST13 ST13 PM CM w w w w w w w w PSL63 PSL63 0 PSL rwh r rwh 0 SWSYN 0 SWSEL r rw r rw 0 T13TED T13TED T13TEC T13TEC T13 T12 SSC SSC r rw rw rw rw 0 T13RSEL T13RSEL T12RSEL T12RSEL r rw rw MC 0 T12MODEN T12MODEN MEN rw r rw ECT13 ECT13 0 T13MODEN T13MODEN O rw r rw 0 TRPM2 TRPM1 TRPM0 r rw rw rw TRPPE TRPEN TRPEN N 13 rw rw rw RMAP = 0, Page 3 9AH CCU6_MCMOUTL Reset: 00H Multi-Channel Mode Output Register Low 9BH CCU6_MCMOUTH Reset: 00H Multi-Channel Mode Output Register High 9CH CCU6_ISL Reset: 00H Capture/Compare Interrupt Status Register Low 9DH CCU6_ISH Reset: 00H Capture/Compare Interrupt Status Register High 9EH CCU6_PISEL0L Reset: 00H Port Input Select Register 0 Low Data Sheet Prelimary Bit Field 0 Type Bit Field r Type Bit Field Type Bit Field Type Bit Field Type R MCMP rh 0 rh CURH EXPH r rh rh T12PM T12PM T12OM T12OM ICC62F ICC62F ICC62 ICC62 ICC61F ICC61F ICC61 ICC61 ICC60F ICC60F ICC60 ICC60 R R R rh rh rh rh rh rh rh rh STR IDLE WHE CHE TRPS TRPF T13PM T13PM T13CM T13CM rh rh ISTRP rw 40 rh rh ISCC62 ISCC62 rw rh rh ISCC61 ISCC61 rw rh rh ISCC60 ISCC60 rw V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description Table 14 CCU6 Register Overview (cont'd) Addr Register Name Bit 7 9FH CCU6_PISEL0H Reset: 00H Port Input Select Register 0 High Bit Field IST12HR IST12HR ISPOS2 ISPOS1 ISPOS0 rw 0 r rw CCU6_PISEL2 Reset: 00H Port Input Select Register 2 Type Bit Field Type rw A4H rw IST13HR IST13HR rw FAH CCU6_T12L Reset: 00H Timer T12 Counter Register Low Bit Field Type FBH CCU6_T12H Reset: 00H Timer T12 Counter Register High Bit Field Type FCH CCU6_T13L Reset: 00H Timer T13 Counter Register Low Bit Field Type FDH CCU6_T13H Reset: 00H Timer T13 Counter Register High Bit Field Type FEH CCU6_CMPSTATL Reset: 00H Compare State Register Low Bit Field FFH CCU6_CMPSTATH Reset: 00H Compare State Register High Type Bit Field Type 6 5 4 3 2 1 0 T12CVL T12CVL rwh T12CVH T12CVH rwh T13CVL T13CVL rwh T13CVH T13CVH rwh 0 CC63 CCPO CCPO CCPO ST S2 S1 S0 r rh rh rh rh T13IM T13IM COUT COUT CC62 COUT 63PS 62PS PS 61PS rwh rwh rwh rwh rwh CC62 ST rh CC61 PS rwh CC61 ST rh COUT 60PS rwh CC60 ST rh CC60 PS rwh The UART1 SFRs can be accessed in the mapped memory area (RMAP = 1). Table 15 Addr UART1 Register Overview Register Name RMAP = 1 C8H SCON Reset: 00H Serial Channel Control Register C9H SBUF Reset: 00H Serial Data Buffer Register CAH BCON Reset: 00H Baud Rate Control Register CBH CCH CDH CEH BG Reset: 00H Baud Rate Timer/Reload Register FDCON Reset: 00H Fractional Divider Control Register FDSTEP Reset: 00H Fractional Divider Reload Register FDRES Reset: 00H Fractional Divider Result Register Bit Bit Field Type Bit Field Type Bit Field 7 SM0 rw 6 5 SM1 rw SM2 rw 4 3 REN TB8 rw rw VAL rwh 0 r Type Bit Field 2 1 0 RB8 rwh TI rwh RI rwh BRPRE rw R rw BR_VALUE rwh Type Bit Field 0 r Type Bit Field NDOV rwh FDM rw FDEN rw 2 1 0 CIS rw SIS rw MIS rw STEP rw RESULT rh Type Bit Field Type The SSC SFRs can be accessed in the standard memory area (RMAP = 0). Table 16 Addr SSC Register Overview Register Name RMAP = 0 SSC_PISEL Reset: 00H A9H Port Input Select Register Data Sheet Prelimary Bit 7 Bit Field Type 6 5 0 r 41 4 3 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description Table 16 AAH SSC Register Overview SSC_CONL Control Register Low Programming Mode Operating Mode Reset: 00H Bit Field Type LB rw PO rw Bit Field PH rw BC rh EN MS 0 Operating Mode Type Bit Field Type rw EN rw rw MS rw r 0 r ACH SSC_TBL Reset: 00H Transmitter Buffer Register Low Bit Field Type ADH SSC_RBL Reset: 00H Receiver Buffer Register Low AEH SSC_BRL Reset: 00H Baudrate Timer Reload Register Low AFH SSC_BRH Reset: 00H Baudrate Timer Reload Register High SSC_CONH Control Register High Programming Mode Reset: 00H BM rw 0 r Type Bit Field ABH HB rw AREN BEN PEN REN TEN rw PE rwh rw RE rwh rw TE rwh Bit Field Type rw rw BSY BE rh rwh TB_VALUE rw RB_VALUE rh Bit Field Type Bit Field Type BR_VALUE rw BR_VALUE rw The MultiCAN SFRs can be accessed in the standard memory area (RMAP = 0). Table 17 Addr MultiCAN Register Overview Register Name Bit RMAP = 0 ADCON Reset: 00H D8H CAN Address/Data Control Register Bit Field Type D9H ADL Reset: 00H CAN Address Low Register Bit Field Type DAH ADH Reset: 00H CAN Address High Register DATA0 CAN Data Register 0 Reset: 00H DATA1 CAN Data Register 1 Reset: 00H DATA2 CAN Data Register 2 Reset: 00H DATA3 CAN Data Register 3 Reset: 00H V2 rw CA8 rwh V1 rw CA7 rwh V0 rw CA6 rwh Bit Field Type DEH 4 Bit Field Type DDH 5 Bit Field Type DCH 6 Bit Field Type DBH 7 Bit Field Type V3 rw CA9 rwh 0 r 3 2 1 AUAD rw CA5 CA4 rwh rwh CA13 CA12 rwh rwh CD rwh CD rwh CD rwh CD rwh 0 BSY rh CA3 rwh CA11 rwh RWEN rw CA2 rwh CA10 rwh The OCDS SFRs can be accessed in the mapped memory area (RMAP = 1). Table 18 Addr OCDS Register Overview Register Name RMAP = 1 MMCR2 Reset: 1UH E9H Monitor Mode Control 2 Register F1H MMCR Reset: 00H Monitor Mode Control Register Bit Bit Field Type Bit Field Type Data Sheet Prelimary 7 6 5 4 3 2 1 0 STMO EXBC DSUSP MBCO ALTDI MMEP MMOD JENA DE N E rw rw rw rwh rw rwh rh rh MEXIT MEXIT 0 MSTEP MRAM MRAM TRF RRF _P S_P S w hw r rw w rwh rh rh 42 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description Table 18 OCDS Register Overview (cont'd) Addr Register Name Bit F2H MMSR Reset: 00H Monitor Mode Status Register Bit Field Type MBCA MBCIN EXBF M rw rwh rwh F3H MMBPCR Reset: 00H BreakPoints Control Register Bit Field SWBC F4H Type MMICR Reset: 00H Bit Field Monitor Mode Interrupt Control Register F5H MMDR Reset: 00H Monitor Mode Data Transfer Register Receive Transmit Type Bit Field 7 6 HWB3C rw rw DVECT DRETR COM RST rwh rwh rwh Type Bit Field F6H HWBPDR Reset: 00H Hardware Breakpoints Data Register EBH MMWR1 Reset: 00H Monitor Work Register 1 ECH MMWR2 Reset: 00H Monitor Work Register 2 4 3 1 0 rh 0 r w BPSEL _P w Bit Field Type Bit Field BPSEL rw HWBPxx rw MMWR1 Type rw MMWR2 Bit Field Type Data Sheet Prelimary 2 SWBF HWB3 HWB2 HWB1 HWB0 F F F F rwh rwh rwh rwh rwh HWB2C HWB1 HWB0C C rw rw rw MST MMUIE MMUIE RRIE_ RRIE SEL _P P w rw w rw rh MMRR MMTR Type HWBPSR Reset: 00H Bit Field Hardware Breakpoints Select Register Type F7H 5 rw 43 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description 3.3 Flash Memory The Flash memory provides an embedded user-programmable non-volatile memory, allowing fast and reliable storage of user code and data. It is operated from a single 2.5 V supply from the Embedded Voltage Regulator (EVR) and does not require additional programming or erasing voltage. The sectorization of the Flash memory allows each sector to be erased independently. Features: · · · · · · · · · · · · In-System Programming (ISP) via UART In-Application Programming (IAP) Error Correction Code (ECC) for dynamic correction of single-bit errors Background program and erase operations for CPU load minimization Support for aborting erase operation Minimum program width1) of 32-byte for D-Flash and 64-byte for P-Flash 1-sector minimum erase width 1-byte read access 135.1 ns minimum read access time (3 × tCCLK @ fCCLK = 24 MHz ± 7.5 %2) Operating supply voltage: 2.5 V ± 7.5 % Program time: 2.3 ms3) Erase time: 120 ms3) Table 19 shows the Flash data retention and endurance targets4). Table 19 Flash Data Retention and Endurance Targets Retention up to Endurance up to Programming Temperature Size 20 years 1,000 cycles 0 ­ 100°C 15 Kbytes 5 years 10,000 cycles -40 ­ 125°C 896 bytes 2 years 70,000 cycles -40 ­ 125°C 512 bytes 2 years 100,000 cycles -40 ­ 125°C 128 bytes 1) P-Flash: 64-byte wordline can only be programmed once, i.e., one gate disturb allowed. D-Flash: 32-byte wordline can be programmed twice, i.e., two gate disturbs allowed. fsys = 96 MHz ± 7.5% (fCCLK = 24 MHz ± 7.5 %) is the maximum frequency range for Flash read access. fsys = 96 MHz ± 7.5% is the only frequency range for Flash programming and erasing. fsysmin is used for obtaining the worst case timing. 4) Specification according to operating temperature profile with 0.2ppm error rate. 2) 3) Data Sheet Prelimary 44 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description 3.3.1 Flash Bank Sectorization The XC886/888 XC886/888 product family offers Flash devices with either 24 Kbytes or 32 Kbytes of embedded Flash memory. Each Flash device consists of Program Flash (P-Flash) bank(s) and a single Data Flash (D-Flash) bank with different sectorization shown in Figure 11. Both types can be used for code and data storage. The label "Data" neither implies that the D-Flash is mapped to the data memory region, nor that it can only be used for data storage. It is used to distinguish the different Flash bank sectorizations. The XC886/888 XC886/888 ROM devices offer a single 4-Kbyte D-Flash bank. Sector 2: 128-byte Sector 1: 128-byte Sector 9: Sector 8: Sector 7: Sector 6: 128-byte 128-byte 128-byte 128-byte Sector 5: 256-byte Sector 4: 256-byte Sector 3: 512-byte Sector 0: 3.75-Kbyte Sector 2: 512-byte Sector 1: 1-Kbyte Sector 0: 1-Kbyte P-Flash Figure 11 D-Flash Flash Bank Sectorization The internal structure of each Flash bank represents a sector architecture for flexible erase capability. The minimum erase width is always a complete sector, and sectors can be erased separately or in parallel. Contrary to standard EPROMs, erased Flash memory cells contain 0s. The D-Flash bank is divided into more physical sectors for extended erasing and reprogramming capability; even numbers for each sector size are provided to allow greater flexibility and the ability to adapt to a wide range of application requirements. Data Sheet Prelimary 45 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description 3.3.2 Flash Programming Width For the P-Flash banks, a programmed wordline (WL) must be erased before it can be reprogrammed as the Flash cells can only withstand one gate disturb. This means that the entire sector containing the WL must be erased since it is impossible to erase a single WL. For the D-Flash bank, the same WL can be programmed twice before erasing is required as the Flash cells are able to withstand two gate disturbs. Hence, it is possible to program the same WL, for example, with 16 bytes of data in two times (see Figure 12). 16 bytes 16 bytes 0000 . 0000 H 32 bytes (1 WL) 0000 . 0000 H Program 1 0000 . 0000 H 1111 . 1111 H 0000 . 0000 H 1111 . 1111 H Program 2 1111 . 0000 H 0000 . 0000 H 1111 . 0000 H 1111 . 1111 H Note: A Flash memory cell can be programmed from 0 to 1, but not from 1 to 0. Flash memory cells Figure 12 32-byte write buffers D-Flash Programming Note: When programming a D-Flash WL the second time, the previously programmed Flash memory cells (whether 0s or 1s) should be reprogrammed with 0s to retain its original contents and to prevent "over-programming". Data Sheet Prelimary 46 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description 3.4 Interrupt System The XC800 XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt requests. In addition to the standard interrupt functions supported by the core, e.g., configurable interrupt priority and interrupt masking, the XC886/888 XC886/888 interrupt system provides extended interrupt support capabilities such as the mapping of each interrupt vector to several interrupt sources to increase the number of interrupt sources supported, and additional status registers for detecting and determining the interrupt source. 3.4.1 Interrupt Source Figure 13 to Figure 17 give a general overview of the interrupt sources and illustrates the request and control flags. WDT Overflow FNMIWDT NMIISR.0 NMIWDT NMICON.0 PLL Loss of Lock FNMIPLL NMIISR.1 NMIPLL NMICON.1 Flash Operation Complete FNMIFLASH NMIISR.2 NMIFLASH >=1 VDD Pre-Warning 0073 FNMIVDD NMIISR.4 H Non Maskable Interrupt NMIVDD NMICON.4 VDDP Pre-Warning FNMIVDDP NMIISR.5 NMIVDDP NMICON.5 Flash ECC Error FNMIECC NMIISR.6 NMIECC NMICON.6 Figure 13 Data Sheet Prelimary Non-Maskable Interrupt Request Sources 47 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description Highest Timer 0 Overflow TF0 TCON.5 ET0 000B Lowest Priority Level H IEN0.1 Timer 1 Overflow IP.1/ IPH.1 TF1 TCON.7 ET1 001B H IEN0.3 IP.3/ IPH.3 RI SCON.0 UART >=1 TI ES SCON.1 EINT0 0023 IEN0.4 EXINT0 TCON.1 H IP.4/ IPH.4 IE0 IRCON0.0 EX0 IT0 0003 H IEN0.0 EXINT0 P o l l i n g TCON.0 S e q u e n c e IP.0/ IPH.0 EXICON0.0/1 EINT1 EXINT1 IE1 IRCON0.1 TCON.3 EX1 IT1 0013 H IEN0.2 EXINT1 TCON.2 IP.2/ IPH.2 EXICON0.2/3 EA IEN0.7 Bit-addressable Request flag is cleared by hardware Figure 14 Data Sheet Prelimary Interrupt Request Sources (Part 1) 48 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description Highest Timer 2 Overflow TF2 Lowest Priority Level T2_T2CON.7 >=1 T2EX EXF2 T2_T2CON.6 EXEN2 EDGES EL T2_T2MOD.5 T2_T2CON.3 Normal Divider Overflow NDOV >=1 FDCON.2 End of Syn Byte ET2 EOFSYN Syn Byte Error ERRSYN 002B H IEN0.5 SYNEN FDCON.6 FDCON.4 IP.5/ IPH.5 FDCON.5 MCAN_0 CANSRC0 IRCON2.0 ADC_0 ADCSRC0 IRCON1.3 ADC_1 ADCSRC1 MCAN_1 CANSRC1 IRCON1.4 >=1 EADC IRCON1.5 MCAN_2 0033 H IEN1.0 IP1.0/ IPH1.0 P o l l i n g S e q u e n c e CANSRC2 EA IEN0.7 IRCON1.6 Bit-addressable Request flag is cleared by hardware Figure 15 Data Sheet Prelimary Interrupt Request Sources (Part 2) 49 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description Highest Lowest Priority Level SSC_EIR EIR IRCON1.0 SSC_TIR TIR >=1 IRCON1.1 SSC_RIR ESSC 003B H IEN1.1 RIR IP1.1/ IPH1.1 IRCON1.2 P o l l i n g EXINT2 EINT2 IRCON0.2 EXINT2 EXICON0.4/5 RI UART1_SCON.0 UART1 >=1 TI UART1_SCON.1 Timer 21 Overflow TF2 >=1 EX2 T21_T2CON.7 T21EX T21EX 0043 H IEN1.2 EXF2 EXEN2 EDGES EL T21_T2MOD.5 >=1 IP1.2/ IPH1.2 S e q u e n c e T21_T2CON.6 T21_T2CON.3 Normal Divider Overflow NDOV UART1_FDCON.2 Cordic EOC CDSTATC.2 MDU_0 IRDY MDUSTAT.0 MDU_1 EA IERR MDUSTAT.1 IEN0.7 Bit-addressable Request flag is cleared by hardware Figure 16 Data Sheet Prelimary Interrupt Request Sources (Part 3) 50 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description Highest Lowest Priority Level EXINT3 EINT3 IRCON0.3 EXINT3 EXICON0.6/7 EXINT4 EINT4 P o l l i n g IRCON0.4 EXINT3 EXICON1.0/1 >=1 EXINT5 EINT5 IRCON0.5 EXM 004B H IEN1.3 EXINT5 EXICON1.2/3 EXINT6 EINT6 IP1.3/ IPH1.3 S e q u e n c e IRCON0.6 EXINT6 EXICON1.4/5 MCAN_3 CANSRC3 EA IEN0.7 IRCON2.4 Bit-addressable Request flag is cleared by hardware Figure 17 Data Sheet Prelimary Interrupt Request Sources (Part 4) 51 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description Highest Lowest CCU6 interrupt node 0 CCU6SR0 IRCON3.0 MCAN_4 Priority Level >=1 MCANSRC4 ECCIP0 IRCON3.1 0053 H IEN1.4 CCU6 interrupt node 1 CCU6SR1 IRCON3.4 MCAN_5 >=1 MCANSRC5 ECCIP1 IRCON3.5 CCU6 interrupt node 2 >=1 ECCIP2 MCANSRC6 IP1.5/ IPH1.5 0063 H IP1.6/ IPH1.6 P o l l i n g S e q u e n c e CCU6SRC3 IRCON4.4 MCAN_7 H IEN1.6 IRCON4.1 CCU6 interrupt node 3 005B IEN1.5 CCU6SR2 IRCON4.0 MCAN_6 IP1.4/ IPH1.4 >=1 MCANSRC7 ECCIP3 IRCON4.5 006B H IEN1.7 IP1.7/ IPH1.7 EA IEN0.7 Bit-addressable Request flag is cleared by hardware Figure 18 Data Sheet Prelimary Interrupt Request Sources (Part 5) 52 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description ICC60R ICC60R CC60 ISL.0 ENCC60R ENCC60R IENL.0 >=1 ICC60F ICC60F ISL.1 ENCC60F ENCC60F IENL.1 INPL.1 INPL.0 INPL.3 INPL.2 INPL.5 INPL.4 INPH.3 INPH.2 INPH.5 INPH.4 INPH.1 INPH.0 INPL.7 INPL.6 ICC61R ICC61R CC61 ISL.2 ENCC61R ENCC61R IENL.2 >=1 ICC61F ICC61F ISL.3 ENCC61F ENCC61F IENL.3 ICC62R ICC62R CC62 ISL.4 ENCC62R ENCC62R IENL.4 >=1 ICC62F ICC62F ISL.5 T12 One match T12OM T12OM T12 Period match T12PM T12PM T13 Compare match T13CM T13CM T13 Period match ENCC62F ENCC62F IENL.5 T13PM T13PM ISL.6 ISL.7 ISH.0 ISH.1 CTRAP Correct Hall Event ENT12PM ENT12PM IENL.7 ENT13CM ENT13CM IENH.0 >=1 ENT13PM ENT13PM IENH.1 ENTRPF IENH.2 >=1 WHE ISH.5 ENWHE IENH.5 CHE ISH.4 Multi-Channel Shadow Transfer >=1 TRPF ISH.2 Wrong Hall Event ENT12OM ENT12OM IENL.6 ENCHE IENH.4 >=1 STR ISH.7 ENSTR IENH.7 CCU6 Interrupt node 0 CCU6 Interrupt node 1 . CCU6 Interrupt node 2 CCU6 Interrupt node 3 Figure 19 Data Sheet Prelimary Interrupt Request Sources (Part 6) 53 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description 3.4.2 Interrupt Source and Vector Each interrupt source has an associated interrupt vector address. This vector is accessed to service the corresponding interrupt source request. The interrupt service of each interrupt source can be individually enabled or disabled via an enable bit. The assignment of the XC886/888 XC886/888 interrupt sources to the interrupt vector addresses and the corresponding interrupt source enable bits are summarized in Table 20. Table 20 Interrupt Source Interrupt Vector Addresses Assignment for XC886/ XC886/ 888 Enable Bit SFR 0073H 0073H Watchdog Timer NMI NMIWDT NMICON PLL NMI NMI Vector Address NMIPLL Flash NMI NMIFLASH VDDC Prewarning NMI NMIVDD VDDP Prewarning NMI NMIVDDP Flash ECC NMI NMIECC XINTR0 0003H 0003H External Interrupt 0 EX0 XINTR1 000BH 000BH Timer 0 ET0 XINTR2 0013H 0013H External Interrupt 1 EX1 XINTR3 001BH 001BH Timer 1 ET1 XINTR4 0023H 0023H UART ES XINTR5 002BH 002BH T2 ET2 IEN0 UART Fractional Divider (Normal Divider Overflow) MultiCAN Node 0 LIN Data Sheet Prelimary 54 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description Table 20 XINTR6 Interrupt Vector Addresses (cont'd) 0033H 0033H MultiCAN Nodes 1 and 2 EADC IEN1 ADC[1:0] XINTR7 003BH 003BH SSC ESSC XINTR8 0043H 0043H External Interrupt 2 EX2 T21 CORDIC UART1 UART1 Fractional Divider (Normal Divider Overflow) MDU[1:0] XINTR9 004BH 004BH External Interrupt 3 EXM External Interrupt 4 External Interrupt 5 External Interrupt 6 MultiCAN Node 3 XINTR10 XINTR10 0053H 0053H XINTR11 XINTR11 005BH 005BH XINTR12 XINTR12 0063H 0063H CCU6 INP0 ECCIP0 MultiCAN Node 4 CCU6 INP1 ECCIP1 MultiCAN Node 5 CCU6 INP2 ECCIP2 MultiCAN Node 6 XINTR13 XINTR13 006BH 006BH CCU6 INP3 ECCIP3 MultiCAN Node 7 Data Sheet Prelimary 55 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description 3.4.3 Interrupt Priority Each interrupt source, except for NMI, can be individually programmed to one of the four possible priority levels. The NMI has the highest priority and supersedes all other interrupts. Two pairs of interrupt priority registers (IP and IPH, IP1 and IPH1) are available to program the priority level of each non-NMI interrupt vector. A low-priority interrupt can be interrupted by a high-priority interrupt, but not by another interrupt of the same or lower priority. Further, an interrupt of the highest priority cannot be interrupted by any other interrupt source. If two or more requests of different priority levels are received simultaneously, the request of the highest priority is serviced first. If requests of the same priority are received simultaneously, then an internal polling sequence determines which request is serviced first. Thus, within each priority level, there is a second priority structure determined by the polling sequence shown in Table 21. Table 21 Priority Structure within Interrupt Level Source Level Non-Maskable Interrupt (NMI) (highest) External Interrupt 0 1 Timer 0 Interrupt 2 External Interrupt 1 3 Timer 1 Interrupt 4 UART Interrupt 5 Timer 2,UART Fractional Divider, MCAN, LIN Interrupt 6 ADC, MCAN Interrupt 7 SSC Interrupt 8 External Interrupt 2, Timer 21, UART1, UART1 9 Fractional Divider, MDU, CORDIC Interrupt External Interrupt [6:3], MCAN Interrupt 10 CCU6 Interrupt Node Pointer 0, MCAN interrupt 11 CCU6 Interrupt Node Pointer 1, MCAN Interrupt 12 CCU6 Interrupt Node Pointer 2, MCAN Interrupt 13 CCU6 Interrupt Node Pointer 3, MCAN Interrupt 14 Data Sheet Prelimary 56 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description 3.5 Parallel Ports The XC886 XC886 has 34 port pins organized into five parallel ports, Port 0 (P0) to Port 4 (P4), while the XC888 XC888 has 48 port pins organized into six parallel ports, Port 0 (P0) to Port 6 (P6). Each pin has a pair of internal pull-up and pull-down devices that can be individually enabled or disabled. Ports P0, P1, P3, P4 and P5 are bidirectional and can be used as general purpose input/output (GPIO) or to perform alternate input/output functions for the on-chip peripherals. When configured as an output, the open drain mode can be selected. Port P2 is an input-only port, providing general purpose input functions, alternate input functions for the on-chip peripherals, and also analog inputs for the Analog-to-Digital Converter (ADC). Bidirectional Port Features: · · · · · Configurable pin direction Configurable pull-up/pull-down devices Configurable open drain mode Transfer of data through digital inputs and outputs (general purpose I/O) Alternate input/output for on-chip peripherals Input Port Features: · · · · · Configurable input driver Configurable pull-up/pull-down devices Receive of data through digital input (general purpose input) Alternate input for on-chip peripherals Analog input for ADC module Data Sheet Prelimary 57 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description Internal Bus Px_PUDSEL Pull-up/Pull-down Select Register Px_PUDEN Pull-up/Pull-down Enable Register Px_OD Open Drain Control Register Px_DIR Direction Register Px_ALTSEL0 Alternate Select Register 0 VDDP Px_ALTSEL1 Alternate Select Register 1 enable AltDataOut 3 AltDataOut 2 AltDataOut1 enable 11 10 Pull Up Device Output Driver Pin 01 00 Px_Data Data Register enable Out In Input Driver Schmitt Trigger AltDataIn enable Pull Down Device Pad Figure 20 Data Sheet Prelimary General Structure of Bidirectional Port 58 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description Internal Bus Px_PUDSEL Pull-up/Pull-down Select Register Px_PUDEN Pull-up/Pull-down Enable Register Px_DIR Direction Register VDDP enable enable Px_DATA Data Register In Input Driver Pull Up Device Pin Schmitt Trigger AltDataIn AnalogIn enable Pull Down Device Pad Figure 21 Data Sheet Prelimary General Structure of Input Port 59 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description 3.6 Power Supply System with Embedded Voltage Regulator The XC886/888 XC886/888 microcontroller requires two different levels of power supply: · 3.3 V or 5.0 V for the Embedded Voltage Regulator (EVR) and Ports · 2.5 V for the core, memory, on-chip oscillator, and peripherals Figure 22 shows the XC886/888 XC886/888 power supply system. A power supply of 3.3 V or 5.0 V must be provided from the external power supply pin. The 2.5 V power supply for the logic is generated by the EVR. The EVR helps to reduce the power consumption of the whole chip and the complexity of the application board design. The EVR consists of a main voltage regulator and a low power voltage regulator. In active mode, both voltage regulators are enabled. In power-down mode, the main voltage regulator is switched off, while the low power voltage regulator continues to function and provide power supply to the system with low power consumption. CPU & Memory On-chip OSC Peripheral logic ADC V DDC (2.5V) FLASH PLL GPIO Ports (P0-P5) XTAL1& XTAL2 EVR VDDP (3.3V/5.0V) VSSP Figure 22 XC886/888 XC886/888 Power Supply System EVR Features: · · · · · Input voltage (VDDP): 3.3 V/5.0 V Output voltage (VDDC): 2.5 V ± 7.5% Low power voltage regulator provided in power-down mode VDDC and VDDP prewarning detection VDDC brownout detection Data Sheet Prelimary 60 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description 3.7 Reset Control The XC886/888 XC886/888 has five types of reset: power-on reset, hardware reset, watchdog timer reset, power-down wake-up reset, and brownout reset. When the XC886/888 XC886/888 is first powered up, the status of certain pins (see Table 23) must be defined to ensure proper start operation of the device. At the end of a reset sequence, the sampled values are latched to select the desired boot option, which cannot be modified until the next power-on reset or hardware reset. This guarantees stable conditions during the normal operation of the device. In order to power up the system properly, the external reset pin RESET must be asserted until VDDC reaches 0.9*VDDC. The delay of external reset can be realized by an external capacitor at RESET pin. This capacitor value must be selected so that VRESET reaches 0.4 V, but not before VDDC reaches 0.9* VDDC. A typical application example is shown in Figure 23. For a voltage regulator with IDDmax = 100 mA, the VDDP capacitor value is 10 µF. VDDC capacitor value is 220 nF. The capacitor connected to RESET pin is 100 nF. Typically, the time taken for VDDC to reach 0.9*VDDC is less than 50 µs once VDDP reaches 2.3V. Hence, based on the condition that 10% to 90% VDDP (slew rate) is less than 500 µs, the RESET pin should be held low for 500 µs typically. See Figure 24. Vin VR 3 - 5V / e.g. 100mA e.g. 10uF VSSP typ. 100nF VDDP 220nF VDDC VSSC RESET EVR 30k XC886/888 XC886/888 Figure 23 Data Sheet Prelimary Reset Circuitry 61 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description Voltage 5V VDDP 2.5V 2.3V 0.9*VDDC VDDC Time Voltage RESET with capacitor 5V < 0.4V 0V Time typ. < 50 u s Figure 24 VDDP, VDDC and VRESET during Power-on Reset The second type of reset in XC886/888 XC886/888 is the hardware reset. This reset function can be used during normal operation or when the chip is in power-down mode. A reset input pin RESET is provided for the hardware reset. The Watchdog Timer (WDT) module is also capable of resetting the device if it detects a malfunction in the system. Another type of reset that needs to be detected is a reset while the device is in power-down mode (wake-up reset). While the contents of the static RAM are undefined after a power-on reset, they are well defined after a wake-up reset from power-down mode. Data Sheet Prelimary 62 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description 3.7.1 Module Reset Behavior Table 22 shows how the functions of the XC886/888 XC886/888 are affected by the various reset types. A " " means that this function is reset to its default state. Table 22 Effect of Reset on Device Functions Module/ Function Wake-Up Reset Watchdog Reset Hardware Reset Power-On Reset Brownout Reset CPU Core Peripherals On-Chip Static RAM Not affected, Not affected, Not affected, Affected, un- Affected, unreliable reliable reliable reliable reliable Oscillator, PLL Not affected Port Pins EVR The voltage Not affected regulator is switched on FLASH NMI Disabled 3.7.2 Disabled Booting Scheme When the XC886/888 XC886/888 is reset, it must identify the type of configuration with which to start the different modes once the reset sequence is complete. Thus, boot configuration information that is required for activation of special modes and conditions needs to be applied by the external world through input pins. After power-on reset or hardware reset, the pins MBC, TMS and P0.0 collectively select the different boot options. Table 23 shows the available boot options in the XC886/888 XC886/888. Table 23 MBC XC886/888 XC886/888 Boot Selection TMS P0.0 Type of Mode PC Start Value 1 0 x User Mode; on-chip OSC/PLL non-bypassed 0000H 0000H 0 0 x BSL Mode; on-chip OSC/PLL non-bypassed 0000H 0000H 0 1 0 OCDS Mode; on-chip OSC/PLL nonbypassed 0000H 0000H 1 1 0 User (JTAG) Mode1); on-chip OSC/PLL nonbypassed (normal) 0000H 0000H 1) Normal user mode with standard JTAG (TCK,TDI,TDO) pins for hot-attach purpose. Data Sheet Prelimary 63 V0.1, 2006-02 XC886/888CLM XC886/888CLM Functional Description 3.8 Clock Generation Unit The Clock Generation Unit (CGU) allows great flexibility in the clock generation for the XC886/888 XC886/888. The power consumption is indirectly proportional to the frequency, whereas the performance of the m